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14#ifndef __RTL871X_MP_H_
15#define __RTL871X_MP_H_
16
17#define MPT_NOOP 0
18#define MPT_READ_MAC_1BYTE 1
19#define MPT_READ_MAC_2BYTE 2
20#define MPT_READ_MAC_4BYTE 3
21#define MPT_WRITE_MAC_1BYTE 4
22#define MPT_WRITE_MAC_2BYTE 5
23#define MPT_WRITE_MAC_4BYTE 6
24#define MPT_READ_BB_CCK 7
25#define MPT_WRITE_BB_CCK 8
26#define MPT_READ_BB_OFDM 9
27#define MPT_WRITE_BB_OFDM 10
28#define MPT_READ_RF 11
29#define MPT_WRITE_RF 12
30#define MPT_READ_EEPROM_1BYTE 13
31#define MPT_WRITE_EEPROM_1BYTE 14
32#define MPT_READ_EEPROM_2BYTE 15
33#define MPT_WRITE_EEPROM_2BYTE 16
34#define MPT_SET_CSTHRESHOLD 21
35#define MPT_SET_INITGAIN 22
36#define MPT_SWITCH_BAND 23
37#define MPT_SWITCH_CHANNEL 24
38#define MPT_SET_DATARATE 25
39#define MPT_SWITCH_ANTENNA 26
40#define MPT_SET_TX_POWER 27
41#define MPT_SET_CONT_TX 28
42#define MPT_SET_SINGLE_CARRIER 29
43#define MPT_SET_CARRIER_SUPPRESSION 30
44#define MPT_GET_RATE_TABLE 31
45#define MPT_READ_TSSI 32
46#define MPT_GET_THERMAL_METER 33
47#define MAX_MP_XMITBUF_SZ 2048
48#define NR_MP_XMITFRAME 8
49
50struct mp_xmit_frame {
51 struct list_head list;
52 struct pkt_attrib attrib;
53 _pkt *pkt;
54 int frame_tag;
55 struct _adapter *padapter;
56 u8 *mem_addr;
57 u16 sz[8];
58 struct urb *pxmit_urb[8];
59 u8 bpending[8];
60 u8 last[8];
61};
62
63struct mp_wiparam {
64 u32 bcompleted;
65 u32 act_type;
66 u32 io_offset;
67 u32 io_value;
68};
69
70struct mp_priv {
71 struct _adapter *papdater;
72
73 struct mp_wiparam workparam;
74 u8 act_in_progress;
75
76 u8 TID;
77 u32 tx_pktcount;
78
79 u32 rx_pktcount;
80 u32 rx_crcerrpktcount;
81 u32 rx_pktloss;
82 struct recv_stat rxstat;
83
84 u32 curr_ch;
85 u32 curr_rateidx;
86 u8 curr_bandwidth;
87 u8 curr_modem;
88 u8 curr_txpoweridx;
89 u32 curr_crystalcap;
90 u16 antenna_tx;
91 u16 antenna_rx;
92 u8 curr_rfpath;
93 u8 check_mp_pkt;
94 uint ForcedDataRate;
95 struct wlan_network mp_network;
96 unsigned char network_macaddr[6];
97
98 u32 mode;
99
100
101 sint prev_fw_state;
102 u8 *pallocated_mp_xmitframe_buf;
103 u8 *pmp_xmtframe_buf;
104 struct __queue free_mp_xmitqueue;
105 u32 free_mp_xmitframe_cnt;
106};
107
108struct IOCMD_STRUCT {
109 u8 cmdclass;
110 u16 value;
111 u8 index;
112};
113
114struct rf_reg_param {
115 u32 path;
116 u32 offset;
117 u32 value;
118};
119
120struct bb_reg_param {
121 u32 offset;
122 u32 value;
123};
124
125
126#define LOWER true
127#define RAISE false
128#define IOCMD_CTRL_REG 0x10250370
129#define IOCMD_DATA_REG 0x10250374
130#define IOCMD_GET_THERMAL_METER 0xFD000028
131#define IOCMD_CLASS_BB_RF 0xF0
132#define IOCMD_BB_READ_IDX 0x00
133#define IOCMD_BB_WRITE_IDX 0x01
134#define IOCMD_RF_READ_IDX 0x02
135#define IOCMD_RF_WRIT_IDX 0x03
136#define BB_REG_BASE_ADDR 0x800
137#define RF_PATH_A 0
138#define RF_PATH_B 1
139#define RF_PATH_C 2
140#define RF_PATH_D 3
141#define MAX_RF_PATH_NUMS 2
142#define _2MAC_MODE_ 0
143#define _LOOPBOOK_MODE_ 1
144
145
146enum {
147
148 MPT_RATE_1M,
149 MPT_RATE_2M,
150 MPT_RATE_55M,
151 MPT_RATE_11M,
152
153
154 MPT_RATE_6M,
155 MPT_RATE_9M,
156 MPT_RATE_12M,
157 MPT_RATE_18M,
158 MPT_RATE_24M,
159 MPT_RATE_36M,
160 MPT_RATE_48M,
161 MPT_RATE_54M,
162
163
164 MPT_RATE_MCS0,
165 MPT_RATE_MCS1,
166 MPT_RATE_MCS2,
167 MPT_RATE_MCS3,
168 MPT_RATE_MCS4,
169 MPT_RATE_MCS5,
170 MPT_RATE_MCS6,
171 MPT_RATE_MCS7,
172 MPT_RATE_MCS8,
173 MPT_RATE_MCS9,
174 MPT_RATE_MCS10,
175 MPT_RATE_MCS11,
176 MPT_RATE_MCS12,
177 MPT_RATE_MCS13,
178 MPT_RATE_MCS14,
179 MPT_RATE_MCS15,
180 MPT_RATE_LAST
181};
182
183
184enum HT_CHANNEL_WIDTH {
185 HT_CHANNEL_WIDTH_20 = 0,
186 HT_CHANNEL_WIDTH_40 = 1,
187};
188
189#define MAX_TX_PWR_INDEX_N_MODE 64
190
191enum POWER_MODE {
192 POWER_LOW = 0,
193 POWER_NORMAL
194};
195
196#define RX_PKT_BROADCAST 1
197#define RX_PKT_DEST_ADDR 2
198#define RX_PKT_PHY_MATCH 3
199
200#define RPTMaxCount 0x000FFFFF
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217
218enum RXPHY_BITMASK {
219 OFDM_PPDU_BIT = 0,
220 OFDM_MPDU_OK_BIT,
221 OFDM_MPDU_FAIL_BIT,
222 CCK_PPDU_BIT,
223 CCK_MPDU_OK_BIT,
224 CCK_MPDU_FAIL_BIT,
225 HT_PPDU_BIT,
226 HT_MPDU_BIT,
227 HT_MPDU_OK_BIT,
228 HT_MPDU_FAIL_BIT,
229};
230
231enum ENCRY_CTRL_STATE {
232 HW_CONTROL,
233 SW_CONTROL,
234 HW_ENCRY_SW_DECRY,
235 SW_ENCRY_HW_DECRY
236};
237
238
239#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
240#define HAL_PRIME_CHNL_OFFSET_LOWER 1
241#define HAL_PRIME_CHNL_OFFSET_UPPER 2
242
243void mp871xinit(struct _adapter *padapter);
244void mp871xdeinit(struct _adapter *padapter);
245u32 r8712_bb_reg_read(struct _adapter *Adapter, u16 offset);
246u8 r8712_bb_reg_write(struct _adapter *Adapter, u16 offset, u32 value);
247u32 r8712_rf_reg_read(struct _adapter *Adapter, u8 path, u8 offset);
248u8 r8712_rf_reg_write(struct _adapter *Adapter, u8 path,
249 u8 offset, u32 value);
250u32 r8712_get_bb_reg(struct _adapter *Adapter, u16 offset, u32 bitmask);
251u8 r8712_set_bb_reg(struct _adapter *Adapter, u16 offset,
252 u32 bitmask, u32 value);
253u32 r8712_get_rf_reg(struct _adapter *Adapter, u8 path, u8 offset,
254 u32 bitmask);
255u8 r8712_set_rf_reg(struct _adapter *Adapter, u8 path, u8 offset,
256 u32 bitmask, u32 value);
257
258void r8712_SetChannel(struct _adapter *pAdapter);
259void r8712_SetTxPower(struct _adapter *pAdapte);
260void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset);
261void r8712_SetDataRate(struct _adapter *pAdapter);
262void r8712_SwitchBandwidth(struct _adapter *pAdapter);
263void r8712_SwitchAntenna(struct _adapter *pAdapter);
264void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value);
265void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart);
266void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart);
267void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart);
268void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart);
269void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter);
270u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter);
271u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter);
272
273#endif
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