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11#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/clk.h>
16#include <linux/device.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/serial_8250.h>
20#include <linux/serial_reg.h>
21#include <linux/tty_flip.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/of_gpio.h>
27#include <linux/of_irq.h>
28#include <linux/delay.h>
29#include <linux/pm_runtime.h>
30#include <linux/console.h>
31#include <linux/pm_qos.h>
32#include <linux/pm_wakeirq.h>
33#include <linux/dma-mapping.h>
34
35#include "8250.h"
36
37#define DEFAULT_CLK_SPEED 48000000
38
39#define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
40#define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
41#define OMAP_DMA_TX_KICK (1 << 2)
42
43
44
45
46#define UART_ERRATA_CLOCK_DISABLE (1 << 3)
47
48#define OMAP_UART_FCR_RX_TRIG 6
49#define OMAP_UART_FCR_TX_TRIG 4
50
51
52#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
53#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
54#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
55#define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
56#define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
57#define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
58
59
60#define OMAP_UART_MVR_SCHEME_SHIFT 30
61#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
62#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
63#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
64#define OMAP_UART_MVR_MAJ_MASK 0x700
65#define OMAP_UART_MVR_MAJ_SHIFT 8
66#define OMAP_UART_MVR_MIN_MASK 0x3f
67
68
69#define OMAP_UART_SYSC_SOFTRESET (1 << 1)
70
71
72#define OMAP_UART_SYSS_RESETDONE (1 << 0)
73
74#define UART_TI752_TLR_TX 0
75#define UART_TI752_TLR_RX 4
76
77#define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
78#define TRIGGER_FCR_MASK(x) (x & 3)
79
80
81#define OMAP_UART_SW_TX 0x08
82
83#define OMAP_UART_SW_RX 0x02
84
85#define OMAP_UART_WER_MOD_WKUP 0x7f
86#define OMAP_UART_TX_WAKEUP_EN (1 << 7)
87
88#define TX_TRIGGER 1
89#define RX_TRIGGER 48
90
91#define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
92#define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
93
94#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
95
96#define OMAP_UART_REV_46 0x0406
97#define OMAP_UART_REV_52 0x0502
98#define OMAP_UART_REV_63 0x0603
99
100struct omap8250_priv {
101 int line;
102 u8 habit;
103 u8 mdr1;
104 u8 efr;
105 u8 scr;
106 u8 wer;
107 u8 xon;
108 u8 xoff;
109 u8 delayed_restore;
110 u16 quot;
111
112 bool is_suspending;
113 int wakeirq;
114 int wakeups_enabled;
115 u32 latency;
116 u32 calc_latency;
117 struct pm_qos_request pm_qos_request;
118 struct work_struct qos_work;
119 struct uart_8250_dma omap8250_dma;
120 spinlock_t rx_dma_lock;
121 bool rx_dma_broken;
122 bool throttled;
123};
124
125#ifdef CONFIG_SERIAL_8250_DMA
126static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
127#else
128static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
129#endif
130
131static u32 uart_read(struct uart_8250_port *up, u32 reg)
132{
133 return readl(up->port.membase + (reg << up->port.regshift));
134}
135
136static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
137{
138 struct uart_8250_port *up = up_to_u8250p(port);
139 struct omap8250_priv *priv = up->port.private_data;
140 u8 lcr;
141
142 serial8250_do_set_mctrl(port, mctrl);
143
144 if (!up->gpios) {
145
146
147
148
149 lcr = serial_in(up, UART_LCR);
150 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
151 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
152 priv->efr |= UART_EFR_RTS;
153 else
154 priv->efr &= ~UART_EFR_RTS;
155 serial_out(up, UART_EFR, priv->efr);
156 serial_out(up, UART_LCR, lcr);
157 }
158}
159
160
161
162
163
164
165
166
167
168
169static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
170 struct omap8250_priv *priv)
171{
172 u8 timeout = 255;
173 u8 old_mdr1;
174
175 old_mdr1 = serial_in(up, UART_OMAP_MDR1);
176 if (old_mdr1 == priv->mdr1)
177 return;
178
179 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
180 udelay(2);
181 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
182 UART_FCR_CLEAR_RCVR);
183
184
185
186
187 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
188 (UART_LSR_THRE | UART_LSR_DR))) {
189 timeout--;
190 if (!timeout) {
191
192 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
193 serial_in(up, UART_LSR));
194 break;
195 }
196 udelay(1);
197 }
198}
199
200static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
201 struct omap8250_priv *priv)
202{
203 unsigned int uartclk = port->uartclk;
204 unsigned int div_13, div_16;
205 unsigned int abs_d13, abs_d16;
206
207
208
209
210 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
211 priv->quot = port->custom_divisor & UART_DIV_MAX;
212
213
214
215
216
217 if (port->custom_divisor & (1 << 16))
218 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
219 else
220 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
221 return;
222 }
223 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
224 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
225
226 if (!div_13)
227 div_13 = 1;
228 if (!div_16)
229 div_16 = 1;
230
231 abs_d13 = abs(baud - uartclk / 13 / div_13);
232 abs_d16 = abs(baud - uartclk / 16 / div_16);
233
234 if (abs_d13 >= abs_d16) {
235 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
236 priv->quot = div_16;
237 } else {
238 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
239 priv->quot = div_13;
240 }
241}
242
243static void omap8250_update_scr(struct uart_8250_port *up,
244 struct omap8250_priv *priv)
245{
246 u8 old_scr;
247
248 old_scr = serial_in(up, UART_OMAP_SCR);
249 if (old_scr == priv->scr)
250 return;
251
252
253
254
255
256
257 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
258 serial_out(up, UART_OMAP_SCR,
259 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
260 serial_out(up, UART_OMAP_SCR, priv->scr);
261}
262
263static void omap8250_update_mdr1(struct uart_8250_port *up,
264 struct omap8250_priv *priv)
265{
266 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
267 omap_8250_mdr1_errataset(up, priv);
268 else
269 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
270}
271
272static void omap8250_restore_regs(struct uart_8250_port *up)
273{
274 struct omap8250_priv *priv = up->port.private_data;
275 struct uart_8250_dma *dma = up->dma;
276
277 if (dma && dma->tx_running) {
278
279
280
281
282
283
284 priv->delayed_restore = 1;
285 return;
286 }
287
288 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
289 serial_out(up, UART_EFR, UART_EFR_ECB);
290
291 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
292 serial8250_out_MCR(up, UART_MCR_TCRTLR);
293 serial_out(up, UART_FCR, up->fcr);
294
295 omap8250_update_scr(up, priv);
296
297 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
298
299 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
300 OMAP_UART_TCR_HALT(52));
301 serial_out(up, UART_TI752_TLR,
302 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
303 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
304
305 serial_out(up, UART_LCR, 0);
306
307
308 serial8250_out_MCR(up, up->mcr);
309 serial_out(up, UART_IER, up->ier);
310
311 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
312 serial_dl_write(up, priv->quot);
313
314 serial_out(up, UART_EFR, priv->efr);
315
316
317 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
318 serial_out(up, UART_XON1, priv->xon);
319 serial_out(up, UART_XOFF1, priv->xoff);
320
321 serial_out(up, UART_LCR, up->lcr);
322
323 omap8250_update_mdr1(up, priv);
324
325 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
326}
327
328
329
330
331
332static void omap_8250_set_termios(struct uart_port *port,
333 struct ktermios *termios,
334 struct ktermios *old)
335{
336 struct uart_8250_port *up = up_to_u8250p(port);
337 struct omap8250_priv *priv = up->port.private_data;
338 unsigned char cval = 0;
339 unsigned int baud;
340
341 switch (termios->c_cflag & CSIZE) {
342 case CS5:
343 cval = UART_LCR_WLEN5;
344 break;
345 case CS6:
346 cval = UART_LCR_WLEN6;
347 break;
348 case CS7:
349 cval = UART_LCR_WLEN7;
350 break;
351 default:
352 case CS8:
353 cval = UART_LCR_WLEN8;
354 break;
355 }
356
357 if (termios->c_cflag & CSTOPB)
358 cval |= UART_LCR_STOP;
359 if (termios->c_cflag & PARENB)
360 cval |= UART_LCR_PARITY;
361 if (!(termios->c_cflag & PARODD))
362 cval |= UART_LCR_EPAR;
363 if (termios->c_cflag & CMSPAR)
364 cval |= UART_LCR_SPAR;
365
366
367
368
369 baud = uart_get_baud_rate(port, termios, old,
370 port->uartclk / 16 / UART_DIV_MAX,
371 port->uartclk / 13);
372 omap_8250_get_divisor(port, baud, priv);
373
374
375
376
377
378 pm_runtime_get_sync(port->dev);
379 spin_lock_irq(&port->lock);
380
381
382
383
384 uart_update_timeout(port, termios->c_cflag, baud);
385
386 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
387 if (termios->c_iflag & INPCK)
388 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
389 if (termios->c_iflag & (IGNBRK | PARMRK))
390 up->port.read_status_mask |= UART_LSR_BI;
391
392
393
394
395 up->port.ignore_status_mask = 0;
396 if (termios->c_iflag & IGNPAR)
397 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
398 if (termios->c_iflag & IGNBRK) {
399 up->port.ignore_status_mask |= UART_LSR_BI;
400
401
402
403
404 if (termios->c_iflag & IGNPAR)
405 up->port.ignore_status_mask |= UART_LSR_OE;
406 }
407
408
409
410
411 if ((termios->c_cflag & CREAD) == 0)
412 up->port.ignore_status_mask |= UART_LSR_DR;
413
414
415
416
417 up->ier &= ~UART_IER_MSI;
418 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
419 up->ier |= UART_IER_MSI;
420
421 up->lcr = cval;
422
423
424
425
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427
428
429
430
431
432
433
434
435
436
437
438
439
440
441 up->fcr = UART_FCR_ENABLE_FIFO;
442 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
443 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
444
445 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
446 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
447
448 if (up->dma)
449 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
450 OMAP_UART_SCR_DMAMODE_CTL;
451
452 priv->xon = termios->c_cc[VSTART];
453 priv->xoff = termios->c_cc[VSTOP];
454
455 priv->efr = 0;
456 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
457
458 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
459 !up->gpios) {
460
461 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
462 priv->efr |= UART_EFR_CTS;
463 } else if (up->port.flags & UPF_SOFT_FLOW) {
464
465
466
467
468
469
470
471
472
473
474 if (termios->c_iflag & IXOFF) {
475 up->port.status |= UPSTAT_AUTOXOFF;
476 priv->efr |= OMAP_UART_SW_TX;
477 }
478 }
479 omap8250_restore_regs(up);
480
481 spin_unlock_irq(&up->port.lock);
482 pm_runtime_mark_last_busy(port->dev);
483 pm_runtime_put_autosuspend(port->dev);
484
485
486 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
487 priv->latency = priv->calc_latency;
488
489 schedule_work(&priv->qos_work);
490
491
492 if (tty_termios_baud_rate(termios))
493 tty_termios_encode_baud_rate(termios, baud, baud);
494}
495
496
497static void omap_8250_pm(struct uart_port *port, unsigned int state,
498 unsigned int oldstate)
499{
500 struct uart_8250_port *up = up_to_u8250p(port);
501 u8 efr;
502
503 pm_runtime_get_sync(port->dev);
504 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
505 efr = serial_in(up, UART_EFR);
506 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
507 serial_out(up, UART_LCR, 0);
508
509 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
510 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
511 serial_out(up, UART_EFR, efr);
512 serial_out(up, UART_LCR, 0);
513
514 pm_runtime_mark_last_busy(port->dev);
515 pm_runtime_put_autosuspend(port->dev);
516}
517
518static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
519 struct omap8250_priv *priv)
520{
521 u32 mvr, scheme;
522 u16 revision, major, minor;
523
524 mvr = uart_read(up, UART_OMAP_MVER);
525
526
527 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
528
529 switch (scheme) {
530 case 0:
531
532 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
533 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
534 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
535 break;
536 case 1:
537
538
539 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
540 OMAP_UART_MVR_MAJ_SHIFT;
541 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
542 break;
543 default:
544 dev_warn(up->port.dev,
545 "Unknown revision, defaulting to highest\n");
546
547 major = 0xff;
548 minor = 0xff;
549 }
550
551 revision = UART_BUILD_REVISION(major, minor);
552
553 switch (revision) {
554 case OMAP_UART_REV_46:
555 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
556 break;
557 case OMAP_UART_REV_52:
558 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
559 OMAP_UART_WER_HAS_TX_WAKEUP;
560 break;
561 case OMAP_UART_REV_63:
562 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
563 OMAP_UART_WER_HAS_TX_WAKEUP;
564 break;
565 default:
566 break;
567 }
568}
569
570static void omap8250_uart_qos_work(struct work_struct *work)
571{
572 struct omap8250_priv *priv;
573
574 priv = container_of(work, struct omap8250_priv, qos_work);
575 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
576}
577
578#ifdef CONFIG_SERIAL_8250_DMA
579static int omap_8250_dma_handle_irq(struct uart_port *port);
580#endif
581
582static irqreturn_t omap8250_irq(int irq, void *dev_id)
583{
584 struct uart_port *port = dev_id;
585 struct uart_8250_port *up = up_to_u8250p(port);
586 unsigned int iir;
587 int ret;
588
589#ifdef CONFIG_SERIAL_8250_DMA
590 if (up->dma) {
591 ret = omap_8250_dma_handle_irq(port);
592 return IRQ_RETVAL(ret);
593 }
594#endif
595
596 serial8250_rpm_get(up);
597 iir = serial_port_in(port, UART_IIR);
598 ret = serial8250_handle_irq(port, iir);
599 serial8250_rpm_put(up);
600
601 return IRQ_RETVAL(ret);
602}
603
604static int omap_8250_startup(struct uart_port *port)
605{
606 struct uart_8250_port *up = up_to_u8250p(port);
607 struct omap8250_priv *priv = port->private_data;
608 int ret;
609
610 if (priv->wakeirq) {
611 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
612 if (ret)
613 return ret;
614 }
615
616 pm_runtime_get_sync(port->dev);
617
618 up->mcr = 0;
619 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
620
621 serial_out(up, UART_LCR, UART_LCR_WLEN8);
622
623 up->lsr_saved_flags = 0;
624 up->msr_saved_flags = 0;
625
626
627 if (uart_console(port))
628 up->dma = NULL;
629
630 if (up->dma) {
631 ret = serial8250_request_dma(up);
632 if (ret) {
633 dev_warn_ratelimited(port->dev,
634 "failed to request DMA\n");
635 up->dma = NULL;
636 }
637 }
638
639 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
640 dev_name(port->dev), port);
641 if (ret < 0)
642 goto err;
643
644 up->ier = UART_IER_RLSI | UART_IER_RDI;
645 serial_out(up, UART_IER, up->ier);
646
647#ifdef CONFIG_PM
648 up->capabilities |= UART_CAP_RPM;
649#endif
650
651
652 priv->wer = OMAP_UART_WER_MOD_WKUP;
653 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
654 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
655 serial_out(up, UART_OMAP_WER, priv->wer);
656
657 if (up->dma)
658 up->dma->rx_dma(up);
659
660 pm_runtime_mark_last_busy(port->dev);
661 pm_runtime_put_autosuspend(port->dev);
662 return 0;
663err:
664 pm_runtime_mark_last_busy(port->dev);
665 pm_runtime_put_autosuspend(port->dev);
666 dev_pm_clear_wake_irq(port->dev);
667 return ret;
668}
669
670static void omap_8250_shutdown(struct uart_port *port)
671{
672 struct uart_8250_port *up = up_to_u8250p(port);
673 struct omap8250_priv *priv = port->private_data;
674
675 flush_work(&priv->qos_work);
676 if (up->dma)
677 omap_8250_rx_dma_flush(up);
678
679 pm_runtime_get_sync(port->dev);
680
681 serial_out(up, UART_OMAP_WER, 0);
682
683 up->ier = 0;
684 serial_out(up, UART_IER, 0);
685
686 if (up->dma)
687 serial8250_release_dma(up);
688
689
690
691
692 if (up->lcr & UART_LCR_SBC)
693 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
694 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
695
696 pm_runtime_mark_last_busy(port->dev);
697 pm_runtime_put_autosuspend(port->dev);
698 free_irq(port->irq, port);
699 dev_pm_clear_wake_irq(port->dev);
700}
701
702static void omap_8250_throttle(struct uart_port *port)
703{
704 struct omap8250_priv *priv = port->private_data;
705 struct uart_8250_port *up = up_to_u8250p(port);
706 unsigned long flags;
707
708 pm_runtime_get_sync(port->dev);
709
710 spin_lock_irqsave(&port->lock, flags);
711 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
712 serial_out(up, UART_IER, up->ier);
713 priv->throttled = true;
714 spin_unlock_irqrestore(&port->lock, flags);
715
716 pm_runtime_mark_last_busy(port->dev);
717 pm_runtime_put_autosuspend(port->dev);
718}
719
720static int omap_8250_rs485_config(struct uart_port *port,
721 struct serial_rs485 *rs485)
722{
723 struct uart_8250_port *up = up_to_u8250p(port);
724
725
726 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
727 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
728
729 port->rs485 = *rs485;
730
731
732
733
734
735 if (rs485->flags & SER_RS485_ENABLED) {
736 int ret = serial8250_em485_init(up);
737
738 if (ret) {
739 rs485->flags &= ~SER_RS485_ENABLED;
740 port->rs485.flags &= ~SER_RS485_ENABLED;
741 }
742 return ret;
743 }
744
745 serial8250_em485_destroy(up);
746
747 return 0;
748}
749
750static void omap_8250_unthrottle(struct uart_port *port)
751{
752 struct omap8250_priv *priv = port->private_data;
753 struct uart_8250_port *up = up_to_u8250p(port);
754 unsigned long flags;
755
756 pm_runtime_get_sync(port->dev);
757
758 spin_lock_irqsave(&port->lock, flags);
759 priv->throttled = false;
760 if (up->dma)
761 up->dma->rx_dma(up);
762 up->ier |= UART_IER_RLSI | UART_IER_RDI;
763 serial_out(up, UART_IER, up->ier);
764 spin_unlock_irqrestore(&port->lock, flags);
765
766 pm_runtime_mark_last_busy(port->dev);
767 pm_runtime_put_autosuspend(port->dev);
768}
769
770#ifdef CONFIG_SERIAL_8250_DMA
771static int omap_8250_rx_dma(struct uart_8250_port *p);
772
773static void __dma_rx_do_complete(struct uart_8250_port *p)
774{
775 struct omap8250_priv *priv = p->port.private_data;
776 struct uart_8250_dma *dma = p->dma;
777 struct tty_port *tty_port = &p->port.state->port;
778 struct dma_tx_state state;
779 int count;
780 unsigned long flags;
781 int ret;
782
783 spin_lock_irqsave(&priv->rx_dma_lock, flags);
784
785 if (!dma->rx_running)
786 goto unlock;
787
788 dma->rx_running = 0;
789 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
790
791 count = dma->rx_size - state.residue;
792
793 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
794
795 p->port.icount.rx += ret;
796 p->port.icount.buf_overrun += count - ret;
797unlock:
798 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
799
800 tty_flip_buffer_push(tty_port);
801}
802
803static void __dma_rx_complete(void *param)
804{
805 struct uart_8250_port *p = param;
806 struct omap8250_priv *priv = p->port.private_data;
807 struct uart_8250_dma *dma = p->dma;
808 struct dma_tx_state state;
809 unsigned long flags;
810
811 spin_lock_irqsave(&p->port.lock, flags);
812
813
814
815
816
817
818 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
819 DMA_COMPLETE) {
820 spin_unlock_irqrestore(&p->port.lock, flags);
821 return;
822 }
823 __dma_rx_do_complete(p);
824 if (!priv->throttled)
825 omap_8250_rx_dma(p);
826
827 spin_unlock_irqrestore(&p->port.lock, flags);
828}
829
830static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
831{
832 struct omap8250_priv *priv = p->port.private_data;
833 struct uart_8250_dma *dma = p->dma;
834 struct dma_tx_state state;
835 unsigned long flags;
836 int ret;
837
838 spin_lock_irqsave(&priv->rx_dma_lock, flags);
839
840 if (!dma->rx_running) {
841 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
842 return;
843 }
844
845 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
846 if (ret == DMA_IN_PROGRESS) {
847 ret = dmaengine_pause(dma->rxchan);
848 if (WARN_ON_ONCE(ret))
849 priv->rx_dma_broken = true;
850 }
851 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
852
853 __dma_rx_do_complete(p);
854 dmaengine_terminate_all(dma->rxchan);
855}
856
857static int omap_8250_rx_dma(struct uart_8250_port *p)
858{
859 struct omap8250_priv *priv = p->port.private_data;
860 struct uart_8250_dma *dma = p->dma;
861 int err = 0;
862 struct dma_async_tx_descriptor *desc;
863 unsigned long flags;
864
865 if (priv->rx_dma_broken)
866 return -EINVAL;
867
868 spin_lock_irqsave(&priv->rx_dma_lock, flags);
869
870 if (dma->rx_running)
871 goto out;
872
873 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
874 dma->rx_size, DMA_DEV_TO_MEM,
875 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
876 if (!desc) {
877 err = -EBUSY;
878 goto out;
879 }
880
881 dma->rx_running = 1;
882 desc->callback = __dma_rx_complete;
883 desc->callback_param = p;
884
885 dma->rx_cookie = dmaengine_submit(desc);
886
887 dma_async_issue_pending(dma->rxchan);
888out:
889 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
890 return err;
891}
892
893static int omap_8250_tx_dma(struct uart_8250_port *p);
894
895static void omap_8250_dma_tx_complete(void *param)
896{
897 struct uart_8250_port *p = param;
898 struct uart_8250_dma *dma = p->dma;
899 struct circ_buf *xmit = &p->port.state->xmit;
900 unsigned long flags;
901 bool en_thri = false;
902 struct omap8250_priv *priv = p->port.private_data;
903
904 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
905 UART_XMIT_SIZE, DMA_TO_DEVICE);
906
907 spin_lock_irqsave(&p->port.lock, flags);
908
909 dma->tx_running = 0;
910
911 xmit->tail += dma->tx_size;
912 xmit->tail &= UART_XMIT_SIZE - 1;
913 p->port.icount.tx += dma->tx_size;
914
915 if (priv->delayed_restore) {
916 priv->delayed_restore = 0;
917 omap8250_restore_regs(p);
918 }
919
920 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
921 uart_write_wakeup(&p->port);
922
923 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
924 int ret;
925
926 ret = omap_8250_tx_dma(p);
927 if (ret)
928 en_thri = true;
929 } else if (p->capabilities & UART_CAP_RPM) {
930 en_thri = true;
931 }
932
933 if (en_thri) {
934 dma->tx_err = 1;
935 serial8250_set_THRI(p);
936 }
937
938 spin_unlock_irqrestore(&p->port.lock, flags);
939}
940
941static int omap_8250_tx_dma(struct uart_8250_port *p)
942{
943 struct uart_8250_dma *dma = p->dma;
944 struct omap8250_priv *priv = p->port.private_data;
945 struct circ_buf *xmit = &p->port.state->xmit;
946 struct dma_async_tx_descriptor *desc;
947 unsigned int skip_byte = 0;
948 int ret;
949
950 if (dma->tx_running)
951 return 0;
952 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
953
954
955
956
957
958
959 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
960 ret = -EBUSY;
961 goto err;
962 }
963 serial8250_clear_THRI(p);
964 return 0;
965 }
966
967 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
968 if (priv->habit & OMAP_DMA_TX_KICK) {
969 u8 tx_lvl;
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
987 if (tx_lvl == p->tx_loadsz) {
988 ret = -EBUSY;
989 goto err;
990 }
991 if (dma->tx_size < 4) {
992 ret = -EINVAL;
993 goto err;
994 }
995 skip_byte = 1;
996 }
997
998 desc = dmaengine_prep_slave_single(dma->txchan,
999 dma->tx_addr + xmit->tail + skip_byte,
1000 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1001 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1002 if (!desc) {
1003 ret = -EBUSY;
1004 goto err;
1005 }
1006
1007 dma->tx_running = 1;
1008
1009 desc->callback = omap_8250_dma_tx_complete;
1010 desc->callback_param = p;
1011
1012 dma->tx_cookie = dmaengine_submit(desc);
1013
1014 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1015 UART_XMIT_SIZE, DMA_TO_DEVICE);
1016
1017 dma_async_issue_pending(dma->txchan);
1018 if (dma->tx_err)
1019 dma->tx_err = 0;
1020
1021 serial8250_clear_THRI(p);
1022 if (skip_byte)
1023 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1024 return 0;
1025err:
1026 dma->tx_err = 1;
1027 return ret;
1028}
1029
1030static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1031{
1032 switch (iir & 0x3f) {
1033 case UART_IIR_RLSI:
1034 case UART_IIR_RX_TIMEOUT:
1035 case UART_IIR_RDI:
1036 omap_8250_rx_dma_flush(up);
1037 return true;
1038 }
1039 return omap_8250_rx_dma(up);
1040}
1041
1042
1043
1044
1045
1046
1047static int omap_8250_dma_handle_irq(struct uart_port *port)
1048{
1049 struct uart_8250_port *up = up_to_u8250p(port);
1050 unsigned char status;
1051 unsigned long flags;
1052 u8 iir;
1053
1054 serial8250_rpm_get(up);
1055
1056 iir = serial_port_in(port, UART_IIR);
1057 if (iir & UART_IIR_NO_INT) {
1058 serial8250_rpm_put(up);
1059 return 0;
1060 }
1061
1062 spin_lock_irqsave(&port->lock, flags);
1063
1064 status = serial_port_in(port, UART_LSR);
1065
1066 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1067 if (handle_rx_dma(up, iir)) {
1068 status = serial8250_rx_chars(up, status);
1069 omap_8250_rx_dma(up);
1070 }
1071 }
1072 serial8250_modem_status(up);
1073 if (status & UART_LSR_THRE && up->dma->tx_err) {
1074 if (uart_tx_stopped(&up->port) ||
1075 uart_circ_empty(&up->port.state->xmit)) {
1076 up->dma->tx_err = 0;
1077 serial8250_tx_chars(up);
1078 } else {
1079
1080
1081
1082
1083 if (omap_8250_tx_dma(up))
1084 serial8250_tx_chars(up);
1085 }
1086 }
1087
1088 uart_unlock_and_check_sysrq(port, flags);
1089 serial8250_rpm_put(up);
1090 return 1;
1091}
1092
1093static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1094{
1095 return false;
1096}
1097
1098#else
1099
1100static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1101{
1102 return -EINVAL;
1103}
1104#endif
1105
1106static int omap8250_no_handle_irq(struct uart_port *port)
1107{
1108
1109 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1110 return 0;
1111}
1112
1113static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE;
1114static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1115static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1116
1117static const struct of_device_id omap8250_dt_ids[] = {
1118 { .compatible = "ti,am654-uart" },
1119 { .compatible = "ti,omap2-uart" },
1120 { .compatible = "ti,omap3-uart" },
1121 { .compatible = "ti,omap4-uart", .data = &omap4_habit, },
1122 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1123 { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1124 { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1125 {},
1126};
1127MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1128
1129static int omap8250_probe(struct platform_device *pdev)
1130{
1131 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1132 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1133 struct device_node *np = pdev->dev.of_node;
1134 struct omap8250_priv *priv;
1135 struct uart_8250_port up;
1136 int ret;
1137 void __iomem *membase;
1138 const struct of_device_id *id;
1139
1140 if (!regs || !irq) {
1141 dev_err(&pdev->dev, "missing registers or irq\n");
1142 return -EINVAL;
1143 }
1144
1145 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1146 if (!priv)
1147 return -ENOMEM;
1148
1149 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1150 resource_size(regs));
1151 if (!membase)
1152 return -ENODEV;
1153
1154 memset(&up, 0, sizeof(up));
1155 up.port.dev = &pdev->dev;
1156 up.port.mapbase = regs->start;
1157 up.port.membase = membase;
1158 up.port.irq = irq->start;
1159
1160
1161
1162
1163
1164
1165
1166
1167 up.port.type = PORT_8250;
1168 up.port.iotype = UPIO_MEM;
1169 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1170 UPF_HARD_FLOW;
1171 up.port.private_data = priv;
1172
1173 up.port.regshift = 2;
1174 up.port.fifosize = 64;
1175 up.tx_loadsz = 64;
1176 up.capabilities = UART_CAP_FIFO;
1177#ifdef CONFIG_PM
1178
1179
1180
1181
1182
1183
1184 up.capabilities |= UART_CAP_RPM;
1185#endif
1186 up.port.set_termios = omap_8250_set_termios;
1187 up.port.set_mctrl = omap8250_set_mctrl;
1188 up.port.pm = omap_8250_pm;
1189 up.port.startup = omap_8250_startup;
1190 up.port.shutdown = omap_8250_shutdown;
1191 up.port.throttle = omap_8250_throttle;
1192 up.port.unthrottle = omap_8250_unthrottle;
1193 up.port.rs485_config = omap_8250_rs485_config;
1194
1195 ret = of_alias_get_id(np, "serial");
1196 if (ret < 0) {
1197 dev_err(&pdev->dev, "failed to get alias\n");
1198 return ret;
1199 }
1200 up.port.line = ret;
1201
1202 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1203 struct clk *clk;
1204
1205 clk = devm_clk_get(&pdev->dev, NULL);
1206 if (IS_ERR(clk)) {
1207 if (PTR_ERR(clk) == -EPROBE_DEFER)
1208 return -EPROBE_DEFER;
1209 } else {
1210 up.port.uartclk = clk_get_rate(clk);
1211 }
1212 }
1213
1214 priv->wakeirq = irq_of_parse_and_map(np, 1);
1215
1216 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1217 if (id && id->data)
1218 priv->habit |= *(u8 *)id->data;
1219
1220 if (!up.port.uartclk) {
1221 up.port.uartclk = DEFAULT_CLK_SPEED;
1222 dev_warn(&pdev->dev,
1223 "No clock speed specified: using default: %d\n",
1224 DEFAULT_CLK_SPEED);
1225 }
1226
1227 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1228 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1229 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1230 priv->latency);
1231 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1232
1233 spin_lock_init(&priv->rx_dma_lock);
1234
1235 device_init_wakeup(&pdev->dev, true);
1236 pm_runtime_use_autosuspend(&pdev->dev);
1237 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1238
1239 pm_runtime_irq_safe(&pdev->dev);
1240 pm_runtime_enable(&pdev->dev);
1241
1242 pm_runtime_get_sync(&pdev->dev);
1243
1244 omap_serial_fill_features_erratas(&up, priv);
1245 up.port.handle_irq = omap8250_no_handle_irq;
1246#ifdef CONFIG_SERIAL_8250_DMA
1247
1248
1249
1250
1251
1252
1253
1254
1255 ret = of_property_count_strings(np, "dma-names");
1256 if (ret == 2) {
1257 up.dma = &priv->omap8250_dma;
1258 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1259 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1260 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1261 priv->omap8250_dma.rx_size = RX_TRIGGER;
1262 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1263 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1264 }
1265#endif
1266 ret = serial8250_register_8250_port(&up);
1267 if (ret < 0) {
1268 dev_err(&pdev->dev, "unable to register 8250 port\n");
1269 goto err;
1270 }
1271 priv->line = ret;
1272 platform_set_drvdata(pdev, priv);
1273 pm_runtime_mark_last_busy(&pdev->dev);
1274 pm_runtime_put_autosuspend(&pdev->dev);
1275 return 0;
1276err:
1277 pm_runtime_dont_use_autosuspend(&pdev->dev);
1278 pm_runtime_put_sync(&pdev->dev);
1279 pm_runtime_disable(&pdev->dev);
1280 return ret;
1281}
1282
1283static int omap8250_remove(struct platform_device *pdev)
1284{
1285 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1286
1287 pm_runtime_dont_use_autosuspend(&pdev->dev);
1288 pm_runtime_put_sync(&pdev->dev);
1289 pm_runtime_disable(&pdev->dev);
1290 serial8250_unregister_port(priv->line);
1291 pm_qos_remove_request(&priv->pm_qos_request);
1292 device_init_wakeup(&pdev->dev, false);
1293 return 0;
1294}
1295
1296#ifdef CONFIG_PM_SLEEP
1297static int omap8250_prepare(struct device *dev)
1298{
1299 struct omap8250_priv *priv = dev_get_drvdata(dev);
1300
1301 if (!priv)
1302 return 0;
1303 priv->is_suspending = true;
1304 return 0;
1305}
1306
1307static void omap8250_complete(struct device *dev)
1308{
1309 struct omap8250_priv *priv = dev_get_drvdata(dev);
1310
1311 if (!priv)
1312 return;
1313 priv->is_suspending = false;
1314}
1315
1316static int omap8250_suspend(struct device *dev)
1317{
1318 struct omap8250_priv *priv = dev_get_drvdata(dev);
1319 struct uart_8250_port *up = serial8250_get_port(priv->line);
1320
1321 serial8250_suspend_port(priv->line);
1322
1323 pm_runtime_get_sync(dev);
1324 if (!device_may_wakeup(dev))
1325 priv->wer = 0;
1326 serial_out(up, UART_OMAP_WER, priv->wer);
1327 pm_runtime_mark_last_busy(dev);
1328 pm_runtime_put_autosuspend(dev);
1329
1330 flush_work(&priv->qos_work);
1331 return 0;
1332}
1333
1334static int omap8250_resume(struct device *dev)
1335{
1336 struct omap8250_priv *priv = dev_get_drvdata(dev);
1337
1338 serial8250_resume_port(priv->line);
1339 return 0;
1340}
1341#else
1342#define omap8250_prepare NULL
1343#define omap8250_complete NULL
1344#endif
1345
1346#ifdef CONFIG_PM
1347static int omap8250_lost_context(struct uart_8250_port *up)
1348{
1349 u32 val;
1350
1351 val = serial_in(up, UART_OMAP_SCR);
1352
1353
1354
1355
1356
1357 if (!val)
1358 return 1;
1359 return 0;
1360}
1361
1362
1363static int omap8250_soft_reset(struct device *dev)
1364{
1365 struct omap8250_priv *priv = dev_get_drvdata(dev);
1366 struct uart_8250_port *up = serial8250_get_port(priv->line);
1367 int timeout = 100;
1368 int sysc;
1369 int syss;
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1381 serial_out(up, UART_OMAP_SCR,
1382 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1383
1384 sysc = serial_in(up, UART_OMAP_SYSC);
1385
1386
1387 sysc |= OMAP_UART_SYSC_SOFTRESET;
1388 serial_out(up, UART_OMAP_SYSC, sysc);
1389
1390
1391 do {
1392 udelay(1);
1393 syss = serial_in(up, UART_OMAP_SYSS);
1394 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1395
1396 if (!timeout) {
1397 dev_err(dev, "timed out waiting for reset done\n");
1398 return -ETIMEDOUT;
1399 }
1400
1401 return 0;
1402}
1403
1404static int omap8250_runtime_suspend(struct device *dev)
1405{
1406 struct omap8250_priv *priv = dev_get_drvdata(dev);
1407 struct uart_8250_port *up;
1408
1409
1410 if (!priv)
1411 return 0;
1412
1413 up = serial8250_get_port(priv->line);
1414
1415
1416
1417
1418
1419
1420 if (priv->is_suspending && !console_suspend_enabled) {
1421 if (uart_console(&up->port))
1422 return -EBUSY;
1423 }
1424
1425 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1426 int ret;
1427
1428 ret = omap8250_soft_reset(dev);
1429 if (ret)
1430 return ret;
1431
1432
1433 omap8250_update_mdr1(up, priv);
1434
1435 serial_out(up, UART_OMAP_WER, priv->wer);
1436 }
1437
1438 if (up->dma && up->dma->rxchan)
1439 omap_8250_rx_dma_flush(up);
1440
1441 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1442 schedule_work(&priv->qos_work);
1443
1444 return 0;
1445}
1446
1447static int omap8250_runtime_resume(struct device *dev)
1448{
1449 struct omap8250_priv *priv = dev_get_drvdata(dev);
1450 struct uart_8250_port *up;
1451
1452
1453 if (!priv)
1454 return 0;
1455
1456 up = serial8250_get_port(priv->line);
1457
1458 if (omap8250_lost_context(up))
1459 omap8250_restore_regs(up);
1460
1461 if (up->dma && up->dma->rxchan)
1462 omap_8250_rx_dma(up);
1463
1464 priv->latency = priv->calc_latency;
1465 schedule_work(&priv->qos_work);
1466 return 0;
1467}
1468#endif
1469
1470#ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1471static int __init omap8250_console_fixup(void)
1472{
1473 char *omap_str;
1474 char *options;
1475 u8 idx;
1476
1477 if (strstr(boot_command_line, "console=ttyS"))
1478
1479 return 0;
1480
1481 omap_str = strstr(boot_command_line, "console=ttyO");
1482 if (!omap_str)
1483
1484 return 0;
1485
1486 omap_str += 12;
1487 if ('0' <= *omap_str && *omap_str <= '9')
1488 idx = *omap_str - '0';
1489 else
1490 return 0;
1491
1492 omap_str++;
1493 if (omap_str[0] == ',') {
1494 omap_str++;
1495 options = omap_str;
1496 } else {
1497 options = NULL;
1498 }
1499
1500 add_preferred_console("ttyS", idx, options);
1501 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1502 idx, idx);
1503 pr_err("This ensures that you still see kernel messages. Please\n");
1504 pr_err("update your kernel commandline.\n");
1505 return 0;
1506}
1507console_initcall(omap8250_console_fixup);
1508#endif
1509
1510static const struct dev_pm_ops omap8250_dev_pm_ops = {
1511 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1512 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1513 omap8250_runtime_resume, NULL)
1514 .prepare = omap8250_prepare,
1515 .complete = omap8250_complete,
1516};
1517
1518static struct platform_driver omap8250_platform_driver = {
1519 .driver = {
1520 .name = "omap8250",
1521 .pm = &omap8250_dev_pm_ops,
1522 .of_match_table = omap8250_dt_ids,
1523 },
1524 .probe = omap8250_probe,
1525 .remove = omap8250_remove,
1526};
1527module_platform_driver(omap8250_platform_driver);
1528
1529MODULE_AUTHOR("Sebastian Andrzej Siewior");
1530MODULE_DESCRIPTION("OMAP 8250 Driver");
1531MODULE_LICENSE("GPL v2");
1532