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14#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15#define SUPPORT_SYSRQ
16#endif
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/ioport.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/sysrq.h>
24#include <linux/delay.h>
25#include <linux/platform_device.h>
26#include <linux/tty.h>
27#include <linux/ratelimit.h>
28#include <linux/tty_flip.h>
29#include <linux/serial.h>
30#include <linux/serial_8250.h>
31#include <linux/nmi.h>
32#include <linux/mutex.h>
33#include <linux/slab.h>
34#include <linux/uaccess.h>
35#include <linux/pm_runtime.h>
36#include <linux/ktime.h>
37
38#include <asm/io.h>
39#include <asm/irq.h>
40
41#include "8250.h"
42
43
44
45
46#define UART_EXAR_INT0 0x80
47#define UART_EXAR_SLEEP 0x8b
48#define UART_EXAR_DVID 0x8d
49
50
51#define UART_NPCM_TOR 7
52#define UART_NPCM_TOIE BIT(7)
53
54
55
56
57#if 0
58#define DEBUG_AUTOCONF(fmt...) printk(fmt)
59#else
60#define DEBUG_AUTOCONF(fmt...) do { } while (0)
61#endif
62
63#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
64
65
66
67
68static const struct serial8250_config uart_config[] = {
69 [PORT_UNKNOWN] = {
70 .name = "unknown",
71 .fifo_size = 1,
72 .tx_loadsz = 1,
73 },
74 [PORT_8250] = {
75 .name = "8250",
76 .fifo_size = 1,
77 .tx_loadsz = 1,
78 },
79 [PORT_16450] = {
80 .name = "16450",
81 .fifo_size = 1,
82 .tx_loadsz = 1,
83 },
84 [PORT_16550] = {
85 .name = "16550",
86 .fifo_size = 1,
87 .tx_loadsz = 1,
88 },
89 [PORT_16550A] = {
90 .name = "16550A",
91 .fifo_size = 16,
92 .tx_loadsz = 16,
93 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
94 .rxtrig_bytes = {1, 4, 8, 14},
95 .flags = UART_CAP_FIFO,
96 },
97 [PORT_CIRRUS] = {
98 .name = "Cirrus",
99 .fifo_size = 1,
100 .tx_loadsz = 1,
101 },
102 [PORT_16650] = {
103 .name = "ST16650",
104 .fifo_size = 1,
105 .tx_loadsz = 1,
106 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
107 },
108 [PORT_16650V2] = {
109 .name = "ST16650V2",
110 .fifo_size = 32,
111 .tx_loadsz = 16,
112 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
113 UART_FCR_T_TRIG_00,
114 .rxtrig_bytes = {8, 16, 24, 28},
115 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
116 },
117 [PORT_16750] = {
118 .name = "TI16750",
119 .fifo_size = 64,
120 .tx_loadsz = 64,
121 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
122 UART_FCR7_64BYTE,
123 .rxtrig_bytes = {1, 16, 32, 56},
124 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
125 },
126 [PORT_STARTECH] = {
127 .name = "Startech",
128 .fifo_size = 1,
129 .tx_loadsz = 1,
130 },
131 [PORT_16C950] = {
132 .name = "16C950/954",
133 .fifo_size = 128,
134 .tx_loadsz = 128,
135 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
136
137 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
138 },
139 [PORT_16654] = {
140 .name = "ST16654",
141 .fifo_size = 64,
142 .tx_loadsz = 32,
143 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
144 UART_FCR_T_TRIG_10,
145 .rxtrig_bytes = {8, 16, 56, 60},
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
147 },
148 [PORT_16850] = {
149 .name = "XR16850",
150 .fifo_size = 128,
151 .tx_loadsz = 128,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
153 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
154 },
155 [PORT_RSA] = {
156 .name = "RSA",
157 .fifo_size = 2048,
158 .tx_loadsz = 2048,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
160 .flags = UART_CAP_FIFO,
161 },
162 [PORT_NS16550A] = {
163 .name = "NS16550A",
164 .fifo_size = 16,
165 .tx_loadsz = 16,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_NATSEMI,
168 },
169 [PORT_XSCALE] = {
170 .name = "XScale",
171 .fifo_size = 32,
172 .tx_loadsz = 32,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
175 },
176 [PORT_OCTEON] = {
177 .name = "OCTEON",
178 .fifo_size = 64,
179 .tx_loadsz = 64,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
181 .flags = UART_CAP_FIFO,
182 },
183 [PORT_AR7] = {
184 .name = "AR7",
185 .fifo_size = 16,
186 .tx_loadsz = 16,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
188 .flags = UART_CAP_FIFO ,
189 },
190 [PORT_U6_16550A] = {
191 .name = "U6_16550A",
192 .fifo_size = 64,
193 .tx_loadsz = 64,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
195 .flags = UART_CAP_FIFO | UART_CAP_AFE,
196 },
197 [PORT_TEGRA] = {
198 .name = "Tegra",
199 .fifo_size = 32,
200 .tx_loadsz = 8,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
202 UART_FCR_T_TRIG_01,
203 .rxtrig_bytes = {1, 4, 8, 14},
204 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
205 },
206 [PORT_XR17D15X] = {
207 .name = "XR17D15X",
208 .fifo_size = 64,
209 .tx_loadsz = 64,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
211 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
212 UART_CAP_SLEEP,
213 },
214 [PORT_XR17V35X] = {
215 .name = "XR17V35X",
216 .fifo_size = 256,
217 .tx_loadsz = 256,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
219 UART_FCR_T_TRIG_11,
220 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
221 UART_CAP_SLEEP,
222 },
223 [PORT_LPC3220] = {
224 .name = "LPC3220",
225 .fifo_size = 64,
226 .tx_loadsz = 32,
227 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
228 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
229 .flags = UART_CAP_FIFO,
230 },
231 [PORT_BRCM_TRUMANAGE] = {
232 .name = "TruManage",
233 .fifo_size = 1,
234 .tx_loadsz = 1024,
235 .flags = UART_CAP_HFIFO,
236 },
237 [PORT_8250_CIR] = {
238 .name = "CIR port"
239 },
240 [PORT_ALTR_16550_F32] = {
241 .name = "Altera 16550 FIFO32",
242 .fifo_size = 32,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .rxtrig_bytes = {1, 8, 16, 30},
246 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 },
248 [PORT_ALTR_16550_F64] = {
249 .name = "Altera 16550 FIFO64",
250 .fifo_size = 64,
251 .tx_loadsz = 64,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .rxtrig_bytes = {1, 16, 32, 62},
254 .flags = UART_CAP_FIFO | UART_CAP_AFE,
255 },
256 [PORT_ALTR_16550_F128] = {
257 .name = "Altera 16550 FIFO128",
258 .fifo_size = 128,
259 .tx_loadsz = 128,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261 .rxtrig_bytes = {1, 32, 64, 126},
262 .flags = UART_CAP_FIFO | UART_CAP_AFE,
263 },
264
265
266
267
268
269 [PORT_16550A_FSL64] = {
270 .name = "16550A_FSL64",
271 .fifo_size = 64,
272 .tx_loadsz = 63,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
274 UART_FCR7_64BYTE,
275 .flags = UART_CAP_FIFO,
276 },
277 [PORT_RT2880] = {
278 .name = "Palmchip BK-3103",
279 .fifo_size = 16,
280 .tx_loadsz = 16,
281 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
282 .rxtrig_bytes = {1, 4, 8, 14},
283 .flags = UART_CAP_FIFO,
284 },
285 [PORT_DA830] = {
286 .name = "TI DA8xx/66AK2x",
287 .fifo_size = 16,
288 .tx_loadsz = 16,
289 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
290 UART_FCR_R_TRIG_10,
291 .rxtrig_bytes = {1, 4, 8, 14},
292 .flags = UART_CAP_FIFO | UART_CAP_AFE,
293 },
294 [PORT_MTK_BTIF] = {
295 .name = "MediaTek BTIF",
296 .fifo_size = 16,
297 .tx_loadsz = 16,
298 .fcr = UART_FCR_ENABLE_FIFO |
299 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
300 .flags = UART_CAP_FIFO,
301 },
302 [PORT_NPCM] = {
303 .name = "Nuvoton 16550",
304 .fifo_size = 16,
305 .tx_loadsz = 16,
306 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
307 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
308 .rxtrig_bytes = {1, 4, 8, 14},
309 .flags = UART_CAP_FIFO,
310 },
311};
312
313
314static int default_serial_dl_read(struct uart_8250_port *up)
315{
316 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
317}
318
319
320static void default_serial_dl_write(struct uart_8250_port *up, int value)
321{
322 serial_out(up, UART_DLL, value & 0xff);
323 serial_out(up, UART_DLM, value >> 8 & 0xff);
324}
325
326#ifdef CONFIG_SERIAL_8250_RT288X
327
328
329static const s8 au_io_in_map[8] = {
330 0,
331 2,
332 3,
333 5,
334 6,
335 7,
336 8,
337 -1,
338};
339
340static const s8 au_io_out_map[8] = {
341 1,
342 2,
343 4,
344 5,
345 6,
346 -1,
347 -1,
348 -1,
349};
350
351unsigned int au_serial_in(struct uart_port *p, int offset)
352{
353 if (offset >= ARRAY_SIZE(au_io_in_map))
354 return UINT_MAX;
355 offset = au_io_in_map[offset];
356 if (offset < 0)
357 return UINT_MAX;
358 return __raw_readl(p->membase + (offset << p->regshift));
359}
360
361void au_serial_out(struct uart_port *p, int offset, int value)
362{
363 if (offset >= ARRAY_SIZE(au_io_out_map))
364 return;
365 offset = au_io_out_map[offset];
366 if (offset < 0)
367 return;
368 __raw_writel(value, p->membase + (offset << p->regshift));
369}
370
371
372static int au_serial_dl_read(struct uart_8250_port *up)
373{
374 return __raw_readl(up->port.membase + 0x28);
375}
376
377static void au_serial_dl_write(struct uart_8250_port *up, int value)
378{
379 __raw_writel(value, up->port.membase + 0x28);
380}
381
382#endif
383
384static unsigned int hub6_serial_in(struct uart_port *p, int offset)
385{
386 offset = offset << p->regshift;
387 outb(p->hub6 - 1 + offset, p->iobase);
388 return inb(p->iobase + 1);
389}
390
391static void hub6_serial_out(struct uart_port *p, int offset, int value)
392{
393 offset = offset << p->regshift;
394 outb(p->hub6 - 1 + offset, p->iobase);
395 outb(value, p->iobase + 1);
396}
397
398static unsigned int mem_serial_in(struct uart_port *p, int offset)
399{
400 offset = offset << p->regshift;
401 return readb(p->membase + offset);
402}
403
404static void mem_serial_out(struct uart_port *p, int offset, int value)
405{
406 offset = offset << p->regshift;
407 writeb(value, p->membase + offset);
408}
409
410static void mem16_serial_out(struct uart_port *p, int offset, int value)
411{
412 offset = offset << p->regshift;
413 writew(value, p->membase + offset);
414}
415
416static unsigned int mem16_serial_in(struct uart_port *p, int offset)
417{
418 offset = offset << p->regshift;
419 return readw(p->membase + offset);
420}
421
422static void mem32_serial_out(struct uart_port *p, int offset, int value)
423{
424 offset = offset << p->regshift;
425 writel(value, p->membase + offset);
426}
427
428static unsigned int mem32_serial_in(struct uart_port *p, int offset)
429{
430 offset = offset << p->regshift;
431 return readl(p->membase + offset);
432}
433
434static void mem32be_serial_out(struct uart_port *p, int offset, int value)
435{
436 offset = offset << p->regshift;
437 iowrite32be(value, p->membase + offset);
438}
439
440static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
441{
442 offset = offset << p->regshift;
443 return ioread32be(p->membase + offset);
444}
445
446static unsigned int io_serial_in(struct uart_port *p, int offset)
447{
448 offset = offset << p->regshift;
449 return inb(p->iobase + offset);
450}
451
452static void io_serial_out(struct uart_port *p, int offset, int value)
453{
454 offset = offset << p->regshift;
455 outb(value, p->iobase + offset);
456}
457
458static int serial8250_default_handle_irq(struct uart_port *port);
459
460static void set_io_from_upio(struct uart_port *p)
461{
462 struct uart_8250_port *up = up_to_u8250p(p);
463
464 up->dl_read = default_serial_dl_read;
465 up->dl_write = default_serial_dl_write;
466
467 switch (p->iotype) {
468 case UPIO_HUB6:
469 p->serial_in = hub6_serial_in;
470 p->serial_out = hub6_serial_out;
471 break;
472
473 case UPIO_MEM:
474 p->serial_in = mem_serial_in;
475 p->serial_out = mem_serial_out;
476 break;
477
478 case UPIO_MEM16:
479 p->serial_in = mem16_serial_in;
480 p->serial_out = mem16_serial_out;
481 break;
482
483 case UPIO_MEM32:
484 p->serial_in = mem32_serial_in;
485 p->serial_out = mem32_serial_out;
486 break;
487
488 case UPIO_MEM32BE:
489 p->serial_in = mem32be_serial_in;
490 p->serial_out = mem32be_serial_out;
491 break;
492
493#ifdef CONFIG_SERIAL_8250_RT288X
494 case UPIO_AU:
495 p->serial_in = au_serial_in;
496 p->serial_out = au_serial_out;
497 up->dl_read = au_serial_dl_read;
498 up->dl_write = au_serial_dl_write;
499 break;
500#endif
501
502 default:
503 p->serial_in = io_serial_in;
504 p->serial_out = io_serial_out;
505 break;
506 }
507
508 up->cur_iotype = p->iotype;
509 p->handle_irq = serial8250_default_handle_irq;
510}
511
512static void
513serial_port_out_sync(struct uart_port *p, int offset, int value)
514{
515 switch (p->iotype) {
516 case UPIO_MEM:
517 case UPIO_MEM16:
518 case UPIO_MEM32:
519 case UPIO_MEM32BE:
520 case UPIO_AU:
521 p->serial_out(p, offset, value);
522 p->serial_in(p, UART_LCR);
523 break;
524 default:
525 p->serial_out(p, offset, value);
526 }
527}
528
529
530
531
532static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
533{
534 serial_out(up, UART_SCR, offset);
535 serial_out(up, UART_ICR, value);
536}
537
538static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
539{
540 unsigned int value;
541
542 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
543 serial_out(up, UART_SCR, offset);
544 value = serial_in(up, UART_ICR);
545 serial_icr_write(up, UART_ACR, up->acr);
546
547 return value;
548}
549
550
551
552
553static void serial8250_clear_fifos(struct uart_8250_port *p)
554{
555 if (p->capabilities & UART_CAP_FIFO) {
556 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
557 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
558 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
559 serial_out(p, UART_FCR, 0);
560 }
561}
562
563static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
564{
565 unsigned char mcr = serial8250_in_MCR(p);
566
567 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
568 mcr |= UART_MCR_RTS;
569 else
570 mcr &= ~UART_MCR_RTS;
571 serial8250_out_MCR(p, mcr);
572}
573
574static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
575static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
576
577void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
578{
579 serial8250_clear_fifos(p);
580 serial_out(p, UART_FCR, p->fcr);
581}
582EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
583
584void serial8250_rpm_get(struct uart_8250_port *p)
585{
586 if (!(p->capabilities & UART_CAP_RPM))
587 return;
588 pm_runtime_get_sync(p->port.dev);
589}
590EXPORT_SYMBOL_GPL(serial8250_rpm_get);
591
592void serial8250_rpm_put(struct uart_8250_port *p)
593{
594 if (!(p->capabilities & UART_CAP_RPM))
595 return;
596 pm_runtime_mark_last_busy(p->port.dev);
597 pm_runtime_put_autosuspend(p->port.dev);
598}
599EXPORT_SYMBOL_GPL(serial8250_rpm_put);
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621int serial8250_em485_init(struct uart_8250_port *p)
622{
623 if (p->em485)
624 return 0;
625
626 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
627 if (!p->em485)
628 return -ENOMEM;
629
630 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
631 HRTIMER_MODE_REL);
632 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
633 HRTIMER_MODE_REL);
634 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
635 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
636 p->em485->port = p;
637 p->em485->active_timer = NULL;
638 serial8250_em485_rts_after_send(p);
639
640 return 0;
641}
642EXPORT_SYMBOL_GPL(serial8250_em485_init);
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657void serial8250_em485_destroy(struct uart_8250_port *p)
658{
659 if (!p->em485)
660 return;
661
662 hrtimer_cancel(&p->em485->start_tx_timer);
663 hrtimer_cancel(&p->em485->stop_tx_timer);
664
665 kfree(p->em485);
666 p->em485 = NULL;
667}
668EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
669
670
671
672
673
674
675void serial8250_rpm_get_tx(struct uart_8250_port *p)
676{
677 unsigned char rpm_active;
678
679 if (!(p->capabilities & UART_CAP_RPM))
680 return;
681
682 rpm_active = xchg(&p->rpm_tx_active, 1);
683 if (rpm_active)
684 return;
685 pm_runtime_get_sync(p->port.dev);
686}
687EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
688
689void serial8250_rpm_put_tx(struct uart_8250_port *p)
690{
691 unsigned char rpm_active;
692
693 if (!(p->capabilities & UART_CAP_RPM))
694 return;
695
696 rpm_active = xchg(&p->rpm_tx_active, 0);
697 if (!rpm_active)
698 return;
699 pm_runtime_mark_last_busy(p->port.dev);
700 pm_runtime_put_autosuspend(p->port.dev);
701}
702EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
703
704
705
706
707
708
709static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
710{
711 unsigned char lcr = 0, efr = 0;
712
713
714
715
716
717
718
719 serial8250_rpm_get(p);
720 if ((p->port.type == PORT_XR17V35X) ||
721 (p->port.type == PORT_XR17D15X)) {
722 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
723 goto out;
724 }
725
726 if (p->capabilities & UART_CAP_SLEEP) {
727 if (p->capabilities & UART_CAP_EFR) {
728 lcr = serial_in(p, UART_LCR);
729 efr = serial_in(p, UART_EFR);
730 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
731 serial_out(p, UART_EFR, UART_EFR_ECB);
732 serial_out(p, UART_LCR, 0);
733 }
734 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
735 if (p->capabilities & UART_CAP_EFR) {
736 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
737 serial_out(p, UART_EFR, efr);
738 serial_out(p, UART_LCR, lcr);
739 }
740 }
741out:
742 serial8250_rpm_put(p);
743}
744
745#ifdef CONFIG_SERIAL_8250_RSA
746
747
748
749
750static int __enable_rsa(struct uart_8250_port *up)
751{
752 unsigned char mode;
753 int result;
754
755 mode = serial_in(up, UART_RSA_MSR);
756 result = mode & UART_RSA_MSR_FIFO;
757
758 if (!result) {
759 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
760 mode = serial_in(up, UART_RSA_MSR);
761 result = mode & UART_RSA_MSR_FIFO;
762 }
763
764 if (result)
765 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
766
767 return result;
768}
769
770static void enable_rsa(struct uart_8250_port *up)
771{
772 if (up->port.type == PORT_RSA) {
773 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
774 spin_lock_irq(&up->port.lock);
775 __enable_rsa(up);
776 spin_unlock_irq(&up->port.lock);
777 }
778 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
779 serial_out(up, UART_RSA_FRR, 0);
780 }
781}
782
783
784
785
786
787
788
789static void disable_rsa(struct uart_8250_port *up)
790{
791 unsigned char mode;
792 int result;
793
794 if (up->port.type == PORT_RSA &&
795 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
796 spin_lock_irq(&up->port.lock);
797
798 mode = serial_in(up, UART_RSA_MSR);
799 result = !(mode & UART_RSA_MSR_FIFO);
800
801 if (!result) {
802 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
803 mode = serial_in(up, UART_RSA_MSR);
804 result = !(mode & UART_RSA_MSR_FIFO);
805 }
806
807 if (result)
808 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
809 spin_unlock_irq(&up->port.lock);
810 }
811}
812#endif
813
814
815
816
817
818static int size_fifo(struct uart_8250_port *up)
819{
820 unsigned char old_fcr, old_mcr, old_lcr;
821 unsigned short old_dl;
822 int count;
823
824 old_lcr = serial_in(up, UART_LCR);
825 serial_out(up, UART_LCR, 0);
826 old_fcr = serial_in(up, UART_FCR);
827 old_mcr = serial8250_in_MCR(up);
828 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
829 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
830 serial8250_out_MCR(up, UART_MCR_LOOP);
831 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
832 old_dl = serial_dl_read(up);
833 serial_dl_write(up, 0x0001);
834 serial_out(up, UART_LCR, 0x03);
835 for (count = 0; count < 256; count++)
836 serial_out(up, UART_TX, count);
837 mdelay(20);
838 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
839 (count < 256); count++)
840 serial_in(up, UART_RX);
841 serial_out(up, UART_FCR, old_fcr);
842 serial8250_out_MCR(up, old_mcr);
843 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
844 serial_dl_write(up, old_dl);
845 serial_out(up, UART_LCR, old_lcr);
846
847 return count;
848}
849
850
851
852
853
854
855static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
856{
857 unsigned char old_lcr;
858 unsigned int id, old_dl;
859
860 old_lcr = serial_in(p, UART_LCR);
861 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
862 old_dl = serial_dl_read(p);
863 serial_dl_write(p, 0);
864 id = serial_dl_read(p);
865 serial_dl_write(p, old_dl);
866
867 serial_out(p, UART_LCR, old_lcr);
868
869 return id;
870}
871
872
873
874
875
876
877
878
879
880
881
882static void autoconfig_has_efr(struct uart_8250_port *up)
883{
884 unsigned int id1, id2, id3, rev;
885
886
887
888
889 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908 up->acr = 0;
909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
910 serial_out(up, UART_EFR, UART_EFR_ECB);
911 serial_out(up, UART_LCR, 0x00);
912 id1 = serial_icr_read(up, UART_ID1);
913 id2 = serial_icr_read(up, UART_ID2);
914 id3 = serial_icr_read(up, UART_ID3);
915 rev = serial_icr_read(up, UART_REV);
916
917 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
918
919 if (id1 == 0x16 && id2 == 0xC9 &&
920 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
921 up->port.type = PORT_16C950;
922
923
924
925
926
927
928 if (id3 == 0x52 && rev == 0x01)
929 up->bugs |= UART_BUG_QUOT;
930 return;
931 }
932
933
934
935
936
937
938
939
940
941 id1 = autoconfig_read_divisor_id(up);
942 DEBUG_AUTOCONF("850id=%04x ", id1);
943
944 id2 = id1 >> 8;
945 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
946 up->port.type = PORT_16850;
947 return;
948 }
949
950
951
952
953
954
955
956
957
958
959 if (size_fifo(up) == 64)
960 up->port.type = PORT_16654;
961 else
962 up->port.type = PORT_16650V2;
963}
964
965
966
967
968
969
970static void autoconfig_8250(struct uart_8250_port *up)
971{
972 unsigned char scratch, status1, status2;
973
974 up->port.type = PORT_8250;
975
976 scratch = serial_in(up, UART_SCR);
977 serial_out(up, UART_SCR, 0xa5);
978 status1 = serial_in(up, UART_SCR);
979 serial_out(up, UART_SCR, 0x5a);
980 status2 = serial_in(up, UART_SCR);
981 serial_out(up, UART_SCR, scratch);
982
983 if (status1 == 0xa5 && status2 == 0x5a)
984 up->port.type = PORT_16450;
985}
986
987static int broken_efr(struct uart_8250_port *up)
988{
989
990
991
992
993
994 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
995 return 1;
996
997 return 0;
998}
999
1000
1001
1002
1003
1004
1005
1006static void autoconfig_16550a(struct uart_8250_port *up)
1007{
1008 unsigned char status1, status2;
1009 unsigned int iersave;
1010
1011 up->port.type = PORT_16550A;
1012 up->capabilities |= UART_CAP_FIFO;
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022 if (up->port.flags & UPF_EXAR_EFR) {
1023 status1 = serial_in(up, UART_EXAR_DVID);
1024 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
1025 DEBUG_AUTOCONF("Exar XR17V35x ");
1026 up->port.type = PORT_XR17V35X;
1027 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1028 UART_CAP_SLEEP;
1029
1030 return;
1031 }
1032
1033 }
1034
1035
1036
1037
1038
1039 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1040 if (serial_in(up, UART_EFR) == 0) {
1041 serial_out(up, UART_EFR, 0xA8);
1042 if (serial_in(up, UART_EFR) != 0) {
1043 DEBUG_AUTOCONF("EFRv1 ");
1044 up->port.type = PORT_16650;
1045 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1046 } else {
1047 serial_out(up, UART_LCR, 0);
1048 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1049 UART_FCR7_64BYTE);
1050 status1 = serial_in(up, UART_IIR) >> 5;
1051 serial_out(up, UART_FCR, 0);
1052 serial_out(up, UART_LCR, 0);
1053
1054 if (status1 == 7)
1055 up->port.type = PORT_16550A_FSL64;
1056 else
1057 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1058 }
1059 serial_out(up, UART_EFR, 0);
1060 return;
1061 }
1062
1063
1064
1065
1066
1067 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1068 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1069 DEBUG_AUTOCONF("EFRv2 ");
1070 autoconfig_has_efr(up);
1071 return;
1072 }
1073
1074
1075
1076
1077
1078
1079
1080
1081 serial_out(up, UART_LCR, 0);
1082 status1 = serial8250_in_MCR(up);
1083 serial_out(up, UART_LCR, 0xE0);
1084 status2 = serial_in(up, 0x02);
1085
1086 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1087 serial_out(up, UART_LCR, 0);
1088 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1089 serial_out(up, UART_LCR, 0xE0);
1090 status2 = serial_in(up, 0x02);
1091 serial_out(up, UART_LCR, 0);
1092 serial8250_out_MCR(up, status1);
1093
1094 if ((status2 ^ status1) & UART_MCR_LOOP) {
1095 unsigned short quot;
1096
1097 serial_out(up, UART_LCR, 0xE0);
1098
1099 quot = serial_dl_read(up);
1100 quot <<= 3;
1101
1102 if (ns16550a_goto_highspeed(up))
1103 serial_dl_write(up, quot);
1104
1105 serial_out(up, UART_LCR, 0);
1106
1107 up->port.uartclk = 921600*16;
1108 up->port.type = PORT_NS16550A;
1109 up->capabilities |= UART_NATSEMI;
1110 return;
1111 }
1112 }
1113
1114
1115
1116
1117
1118
1119
1120 serial_out(up, UART_LCR, 0);
1121 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1122 status1 = serial_in(up, UART_IIR) >> 5;
1123 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1124 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1125 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1126 status2 = serial_in(up, UART_IIR) >> 5;
1127 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1128 serial_out(up, UART_LCR, 0);
1129
1130 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1131
1132 if (status1 == 6 && status2 == 7) {
1133 up->port.type = PORT_16750;
1134 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1135 return;
1136 }
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146 iersave = serial_in(up, UART_IER);
1147 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1148 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1149
1150
1151
1152
1153 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1154 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1155
1156
1157
1158
1159 DEBUG_AUTOCONF("Xscale ");
1160 up->port.type = PORT_XSCALE;
1161 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1162 return;
1163 }
1164 } else {
1165
1166
1167
1168
1169 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1170 }
1171 serial_out(up, UART_IER, iersave);
1172
1173
1174
1175
1176 if (up->port.flags & UPF_EXAR_EFR) {
1177 DEBUG_AUTOCONF("Exar XR17D15x ");
1178 up->port.type = PORT_XR17D15X;
1179 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1180 UART_CAP_SLEEP;
1181
1182 return;
1183 }
1184
1185
1186
1187
1188
1189 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1190 up->port.type = PORT_U6_16550A;
1191 up->capabilities |= UART_CAP_AFE;
1192 }
1193}
1194
1195
1196
1197
1198
1199
1200
1201
1202static void autoconfig(struct uart_8250_port *up)
1203{
1204 unsigned char status1, scratch, scratch2, scratch3;
1205 unsigned char save_lcr, save_mcr;
1206 struct uart_port *port = &up->port;
1207 unsigned long flags;
1208 unsigned int old_capabilities;
1209
1210 if (!port->iobase && !port->mapbase && !port->membase)
1211 return;
1212
1213 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1214 port->name, port->iobase, port->membase);
1215
1216
1217
1218
1219
1220 spin_lock_irqsave(&port->lock, flags);
1221
1222 up->capabilities = 0;
1223 up->bugs = 0;
1224
1225 if (!(port->flags & UPF_BUGGY_UART)) {
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239 scratch = serial_in(up, UART_IER);
1240 serial_out(up, UART_IER, 0);
1241#ifdef __i386__
1242 outb(0xff, 0x080);
1243#endif
1244
1245
1246
1247
1248 scratch2 = serial_in(up, UART_IER) & 0x0f;
1249 serial_out(up, UART_IER, 0x0F);
1250#ifdef __i386__
1251 outb(0, 0x080);
1252#endif
1253 scratch3 = serial_in(up, UART_IER) & 0x0f;
1254 serial_out(up, UART_IER, scratch);
1255 if (scratch2 != 0 || scratch3 != 0x0F) {
1256
1257
1258
1259 spin_unlock_irqrestore(&port->lock, flags);
1260 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1261 scratch2, scratch3);
1262 goto out;
1263 }
1264 }
1265
1266 save_mcr = serial8250_in_MCR(up);
1267 save_lcr = serial_in(up, UART_LCR);
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278 if (!(port->flags & UPF_SKIP_TEST)) {
1279 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1280 status1 = serial_in(up, UART_MSR) & 0xF0;
1281 serial8250_out_MCR(up, save_mcr);
1282 if (status1 != 0x90) {
1283 spin_unlock_irqrestore(&port->lock, flags);
1284 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1285 status1);
1286 goto out;
1287 }
1288 }
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1300 serial_out(up, UART_EFR, 0);
1301 serial_out(up, UART_LCR, 0);
1302
1303 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1304 scratch = serial_in(up, UART_IIR) >> 6;
1305
1306 switch (scratch) {
1307 case 0:
1308 autoconfig_8250(up);
1309 break;
1310 case 1:
1311 port->type = PORT_UNKNOWN;
1312 break;
1313 case 2:
1314 port->type = PORT_16550;
1315 break;
1316 case 3:
1317 autoconfig_16550a(up);
1318 break;
1319 }
1320
1321#ifdef CONFIG_SERIAL_8250_RSA
1322
1323
1324
1325 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1326 __enable_rsa(up))
1327 port->type = PORT_RSA;
1328#endif
1329
1330 serial_out(up, UART_LCR, save_lcr);
1331
1332 port->fifosize = uart_config[up->port.type].fifo_size;
1333 old_capabilities = up->capabilities;
1334 up->capabilities = uart_config[port->type].flags;
1335 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1336
1337 if (port->type == PORT_UNKNOWN)
1338 goto out_lock;
1339
1340
1341
1342
1343#ifdef CONFIG_SERIAL_8250_RSA
1344 if (port->type == PORT_RSA)
1345 serial_out(up, UART_RSA_FRR, 0);
1346#endif
1347 serial8250_out_MCR(up, save_mcr);
1348 serial8250_clear_fifos(up);
1349 serial_in(up, UART_RX);
1350 if (up->capabilities & UART_CAP_UUE)
1351 serial_out(up, UART_IER, UART_IER_UUE);
1352 else
1353 serial_out(up, UART_IER, 0);
1354
1355out_lock:
1356 spin_unlock_irqrestore(&port->lock, flags);
1357
1358
1359
1360
1361 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1362 fintek_8250_probe(up);
1363
1364 if (up->capabilities != old_capabilities) {
1365 pr_warn("%s: detected caps %08x should be %08x\n",
1366 port->name, old_capabilities, up->capabilities);
1367 }
1368out:
1369 DEBUG_AUTOCONF("iir=%d ", scratch);
1370 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1371}
1372
1373static void autoconfig_irq(struct uart_8250_port *up)
1374{
1375 struct uart_port *port = &up->port;
1376 unsigned char save_mcr, save_ier;
1377 unsigned char save_ICP = 0;
1378 unsigned int ICP = 0;
1379 unsigned long irqs;
1380 int irq;
1381
1382 if (port->flags & UPF_FOURPORT) {
1383 ICP = (port->iobase & 0xfe0) | 0x1f;
1384 save_ICP = inb_p(ICP);
1385 outb_p(0x80, ICP);
1386 inb_p(ICP);
1387 }
1388
1389 if (uart_console(port))
1390 console_lock();
1391
1392
1393 probe_irq_off(probe_irq_on());
1394 save_mcr = serial8250_in_MCR(up);
1395 save_ier = serial_in(up, UART_IER);
1396 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1397
1398 irqs = probe_irq_on();
1399 serial8250_out_MCR(up, 0);
1400 udelay(10);
1401 if (port->flags & UPF_FOURPORT) {
1402 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1403 } else {
1404 serial8250_out_MCR(up,
1405 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1406 }
1407 serial_out(up, UART_IER, 0x0f);
1408 serial_in(up, UART_LSR);
1409 serial_in(up, UART_RX);
1410 serial_in(up, UART_IIR);
1411 serial_in(up, UART_MSR);
1412 serial_out(up, UART_TX, 0xFF);
1413 udelay(20);
1414 irq = probe_irq_off(irqs);
1415
1416 serial8250_out_MCR(up, save_mcr);
1417 serial_out(up, UART_IER, save_ier);
1418
1419 if (port->flags & UPF_FOURPORT)
1420 outb_p(save_ICP, ICP);
1421
1422 if (uart_console(port))
1423 console_unlock();
1424
1425 port->irq = (irq > 0) ? irq : 0;
1426}
1427
1428static void serial8250_stop_rx(struct uart_port *port)
1429{
1430 struct uart_8250_port *up = up_to_u8250p(port);
1431
1432 serial8250_rpm_get(up);
1433
1434 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1435 up->port.read_status_mask &= ~UART_LSR_DR;
1436 serial_port_out(port, UART_IER, up->ier);
1437
1438 serial8250_rpm_put(up);
1439}
1440
1441static void __do_stop_tx_rs485(struct uart_8250_port *p)
1442{
1443 serial8250_em485_rts_after_send(p);
1444
1445
1446
1447
1448
1449
1450 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1451 serial8250_clear_and_reinit_fifos(p);
1452
1453 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1454 serial_port_out(&p->port, UART_IER, p->ier);
1455 }
1456}
1457static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1458{
1459 struct uart_8250_em485 *em485;
1460 struct uart_8250_port *p;
1461 unsigned long flags;
1462
1463 em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1464 p = em485->port;
1465
1466 serial8250_rpm_get(p);
1467 spin_lock_irqsave(&p->port.lock, flags);
1468 if (em485->active_timer == &em485->stop_tx_timer) {
1469 __do_stop_tx_rs485(p);
1470 em485->active_timer = NULL;
1471 }
1472 spin_unlock_irqrestore(&p->port.lock, flags);
1473 serial8250_rpm_put(p);
1474 return HRTIMER_NORESTART;
1475}
1476
1477static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1478{
1479 long sec = msec / 1000;
1480 long nsec = (msec % 1000) * 1000000;
1481 ktime_t t = ktime_set(sec, nsec);
1482
1483 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1484}
1485
1486static void __stop_tx_rs485(struct uart_8250_port *p)
1487{
1488 struct uart_8250_em485 *em485 = p->em485;
1489
1490
1491
1492
1493
1494 if (p->port.rs485.delay_rts_after_send > 0) {
1495 em485->active_timer = &em485->stop_tx_timer;
1496 start_hrtimer_ms(&em485->stop_tx_timer,
1497 p->port.rs485.delay_rts_after_send);
1498 } else {
1499 __do_stop_tx_rs485(p);
1500 }
1501}
1502
1503static inline void __do_stop_tx(struct uart_8250_port *p)
1504{
1505 if (serial8250_clear_THRI(p))
1506 serial8250_rpm_put_tx(p);
1507}
1508
1509static inline void __stop_tx(struct uart_8250_port *p)
1510{
1511 struct uart_8250_em485 *em485 = p->em485;
1512
1513 if (em485) {
1514 unsigned char lsr = serial_in(p, UART_LSR);
1515
1516
1517
1518
1519
1520
1521 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1522 return;
1523
1524 em485->active_timer = NULL;
1525
1526 __stop_tx_rs485(p);
1527 }
1528 __do_stop_tx(p);
1529}
1530
1531static void serial8250_stop_tx(struct uart_port *port)
1532{
1533 struct uart_8250_port *up = up_to_u8250p(port);
1534
1535 serial8250_rpm_get(up);
1536 __stop_tx(up);
1537
1538
1539
1540
1541 if (port->type == PORT_16C950) {
1542 up->acr |= UART_ACR_TXDIS;
1543 serial_icr_write(up, UART_ACR, up->acr);
1544 }
1545 serial8250_rpm_put(up);
1546}
1547
1548static inline void __start_tx(struct uart_port *port)
1549{
1550 struct uart_8250_port *up = up_to_u8250p(port);
1551
1552 if (up->dma && !up->dma->tx_dma(up))
1553 return;
1554
1555 if (serial8250_set_THRI(up)) {
1556 if (up->bugs & UART_BUG_TXEN) {
1557 unsigned char lsr;
1558
1559 lsr = serial_in(up, UART_LSR);
1560 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1561 if (lsr & UART_LSR_THRE)
1562 serial8250_tx_chars(up);
1563 }
1564 }
1565
1566
1567
1568
1569 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1570 up->acr &= ~UART_ACR_TXDIS;
1571 serial_icr_write(up, UART_ACR, up->acr);
1572 }
1573}
1574
1575static inline void start_tx_rs485(struct uart_port *port)
1576{
1577 struct uart_8250_port *up = up_to_u8250p(port);
1578 struct uart_8250_em485 *em485 = up->em485;
1579 unsigned char mcr;
1580
1581 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1582 serial8250_stop_rx(&up->port);
1583
1584 em485->active_timer = NULL;
1585
1586 mcr = serial8250_in_MCR(up);
1587 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1588 !!(mcr & UART_MCR_RTS)) {
1589 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1590 mcr |= UART_MCR_RTS;
1591 else
1592 mcr &= ~UART_MCR_RTS;
1593 serial8250_out_MCR(up, mcr);
1594
1595 if (up->port.rs485.delay_rts_before_send > 0) {
1596 em485->active_timer = &em485->start_tx_timer;
1597 start_hrtimer_ms(&em485->start_tx_timer,
1598 up->port.rs485.delay_rts_before_send);
1599 return;
1600 }
1601 }
1602
1603 __start_tx(port);
1604}
1605
1606static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1607{
1608 struct uart_8250_em485 *em485;
1609 struct uart_8250_port *p;
1610 unsigned long flags;
1611
1612 em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1613 p = em485->port;
1614
1615 spin_lock_irqsave(&p->port.lock, flags);
1616 if (em485->active_timer == &em485->start_tx_timer) {
1617 __start_tx(&p->port);
1618 em485->active_timer = NULL;
1619 }
1620 spin_unlock_irqrestore(&p->port.lock, flags);
1621 return HRTIMER_NORESTART;
1622}
1623
1624static void serial8250_start_tx(struct uart_port *port)
1625{
1626 struct uart_8250_port *up = up_to_u8250p(port);
1627 struct uart_8250_em485 *em485 = up->em485;
1628
1629 serial8250_rpm_get_tx(up);
1630
1631 if (em485 &&
1632 em485->active_timer == &em485->start_tx_timer)
1633 return;
1634
1635 if (em485)
1636 start_tx_rs485(port);
1637 else
1638 __start_tx(port);
1639}
1640
1641static void serial8250_throttle(struct uart_port *port)
1642{
1643 port->throttle(port);
1644}
1645
1646static void serial8250_unthrottle(struct uart_port *port)
1647{
1648 port->unthrottle(port);
1649}
1650
1651static void serial8250_disable_ms(struct uart_port *port)
1652{
1653 struct uart_8250_port *up = up_to_u8250p(port);
1654
1655
1656 if (up->bugs & UART_BUG_NOMSR)
1657 return;
1658
1659 mctrl_gpio_disable_ms(up->gpios);
1660
1661 up->ier &= ~UART_IER_MSI;
1662 serial_port_out(port, UART_IER, up->ier);
1663}
1664
1665static void serial8250_enable_ms(struct uart_port *port)
1666{
1667 struct uart_8250_port *up = up_to_u8250p(port);
1668
1669
1670 if (up->bugs & UART_BUG_NOMSR)
1671 return;
1672
1673 mctrl_gpio_enable_ms(up->gpios);
1674
1675 up->ier |= UART_IER_MSI;
1676
1677 serial8250_rpm_get(up);
1678 serial_port_out(port, UART_IER, up->ier);
1679 serial8250_rpm_put(up);
1680}
1681
1682void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1683{
1684 struct uart_port *port = &up->port;
1685 unsigned char ch;
1686 char flag = TTY_NORMAL;
1687
1688 if (likely(lsr & UART_LSR_DR))
1689 ch = serial_in(up, UART_RX);
1690 else
1691
1692
1693
1694
1695
1696
1697
1698 ch = 0;
1699
1700 port->icount.rx++;
1701
1702 lsr |= up->lsr_saved_flags;
1703 up->lsr_saved_flags = 0;
1704
1705 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1706 if (lsr & UART_LSR_BI) {
1707 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1708 port->icount.brk++;
1709
1710
1711
1712
1713
1714
1715 if (uart_handle_break(port))
1716 return;
1717 } else if (lsr & UART_LSR_PE)
1718 port->icount.parity++;
1719 else if (lsr & UART_LSR_FE)
1720 port->icount.frame++;
1721 if (lsr & UART_LSR_OE)
1722 port->icount.overrun++;
1723
1724
1725
1726
1727 lsr &= port->read_status_mask;
1728
1729 if (lsr & UART_LSR_BI) {
1730 pr_debug("%s: handling break\n", __func__);
1731 flag = TTY_BREAK;
1732 } else if (lsr & UART_LSR_PE)
1733 flag = TTY_PARITY;
1734 else if (lsr & UART_LSR_FE)
1735 flag = TTY_FRAME;
1736 }
1737 if (uart_prepare_sysrq_char(port, ch))
1738 return;
1739
1740 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1741}
1742EXPORT_SYMBOL_GPL(serial8250_read_char);
1743
1744
1745
1746
1747
1748
1749unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1750{
1751 struct uart_port *port = &up->port;
1752 int max_count = 256;
1753
1754 do {
1755 serial8250_read_char(up, lsr);
1756 if (--max_count == 0)
1757 break;
1758 lsr = serial_in(up, UART_LSR);
1759 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1760
1761 tty_flip_buffer_push(&port->state->port);
1762 return lsr;
1763}
1764EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1765
1766void serial8250_tx_chars(struct uart_8250_port *up)
1767{
1768 struct uart_port *port = &up->port;
1769 struct circ_buf *xmit = &port->state->xmit;
1770 int count;
1771
1772 if (port->x_char) {
1773 serial_out(up, UART_TX, port->x_char);
1774 port->icount.tx++;
1775 port->x_char = 0;
1776 return;
1777 }
1778 if (uart_tx_stopped(port)) {
1779 serial8250_stop_tx(port);
1780 return;
1781 }
1782 if (uart_circ_empty(xmit)) {
1783 __stop_tx(up);
1784 return;
1785 }
1786
1787 count = up->tx_loadsz;
1788 do {
1789 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1790 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1791 port->icount.tx++;
1792 if (uart_circ_empty(xmit))
1793 break;
1794 if ((up->capabilities & UART_CAP_HFIFO) &&
1795 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1796 break;
1797
1798 if ((up->capabilities & UART_CAP_MINI) &&
1799 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1800 break;
1801 } while (--count > 0);
1802
1803 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1804 uart_write_wakeup(port);
1805
1806
1807
1808
1809
1810
1811 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1812 __stop_tx(up);
1813}
1814EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1815
1816
1817unsigned int serial8250_modem_status(struct uart_8250_port *up)
1818{
1819 struct uart_port *port = &up->port;
1820 unsigned int status = serial_in(up, UART_MSR);
1821
1822 status |= up->msr_saved_flags;
1823 up->msr_saved_flags = 0;
1824 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1825 port->state != NULL) {
1826 if (status & UART_MSR_TERI)
1827 port->icount.rng++;
1828 if (status & UART_MSR_DDSR)
1829 port->icount.dsr++;
1830 if (status & UART_MSR_DDCD)
1831 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1832 if (status & UART_MSR_DCTS)
1833 uart_handle_cts_change(port, status & UART_MSR_CTS);
1834
1835 wake_up_interruptible(&port->state->port.delta_msr_wait);
1836 }
1837
1838 return status;
1839}
1840EXPORT_SYMBOL_GPL(serial8250_modem_status);
1841
1842static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1843{
1844 switch (iir & 0x3f) {
1845 case UART_IIR_RX_TIMEOUT:
1846 serial8250_rx_dma_flush(up);
1847
1848 case UART_IIR_RLSI:
1849 return true;
1850 }
1851 return up->dma->rx_dma(up);
1852}
1853
1854
1855
1856
1857int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1858{
1859 unsigned char status;
1860 unsigned long flags;
1861 struct uart_8250_port *up = up_to_u8250p(port);
1862
1863 if (iir & UART_IIR_NO_INT)
1864 return 0;
1865
1866 spin_lock_irqsave(&port->lock, flags);
1867
1868 status = serial_port_in(port, UART_LSR);
1869
1870 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1871 if (!up->dma || handle_rx_dma(up, iir))
1872 status = serial8250_rx_chars(up, status);
1873 }
1874 serial8250_modem_status(up);
1875 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1876 (up->ier & UART_IER_THRI))
1877 serial8250_tx_chars(up);
1878
1879 uart_unlock_and_check_sysrq(port, flags);
1880 return 1;
1881}
1882EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1883
1884static int serial8250_default_handle_irq(struct uart_port *port)
1885{
1886 struct uart_8250_port *up = up_to_u8250p(port);
1887 unsigned int iir;
1888 int ret;
1889
1890 serial8250_rpm_get(up);
1891
1892 iir = serial_port_in(port, UART_IIR);
1893 ret = serial8250_handle_irq(port, iir);
1894
1895 serial8250_rpm_put(up);
1896 return ret;
1897}
1898
1899
1900
1901
1902
1903
1904
1905static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1906{
1907 unsigned long flags;
1908 unsigned int iir = serial_port_in(port, UART_IIR);
1909
1910
1911 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1912 struct uart_8250_port *up = up_to_u8250p(port);
1913
1914 spin_lock_irqsave(&port->lock, flags);
1915 serial8250_tx_chars(up);
1916 spin_unlock_irqrestore(&port->lock, flags);
1917 }
1918
1919 iir = serial_port_in(port, UART_IIR);
1920 return serial8250_handle_irq(port, iir);
1921}
1922
1923static unsigned int serial8250_tx_empty(struct uart_port *port)
1924{
1925 struct uart_8250_port *up = up_to_u8250p(port);
1926 unsigned long flags;
1927 unsigned int lsr;
1928
1929 serial8250_rpm_get(up);
1930
1931 spin_lock_irqsave(&port->lock, flags);
1932 lsr = serial_port_in(port, UART_LSR);
1933 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1934 spin_unlock_irqrestore(&port->lock, flags);
1935
1936 serial8250_rpm_put(up);
1937
1938 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1939}
1940
1941unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1942{
1943 struct uart_8250_port *up = up_to_u8250p(port);
1944 unsigned int status;
1945 unsigned int val;
1946
1947 serial8250_rpm_get(up);
1948 status = serial8250_modem_status(up);
1949 serial8250_rpm_put(up);
1950
1951 val = serial8250_MSR_to_TIOCM(status);
1952 if (up->gpios)
1953 return mctrl_gpio_get(up->gpios, &val);
1954
1955 return val;
1956}
1957EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1958
1959static unsigned int serial8250_get_mctrl(struct uart_port *port)
1960{
1961 if (port->get_mctrl)
1962 return port->get_mctrl(port);
1963 return serial8250_do_get_mctrl(port);
1964}
1965
1966void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1967{
1968 struct uart_8250_port *up = up_to_u8250p(port);
1969 unsigned char mcr;
1970
1971 mcr = serial8250_TIOCM_to_MCR(mctrl);
1972
1973 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1974
1975 serial8250_out_MCR(up, mcr);
1976}
1977EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1978
1979static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1980{
1981 if (port->set_mctrl)
1982 port->set_mctrl(port, mctrl);
1983 else
1984 serial8250_do_set_mctrl(port, mctrl);
1985}
1986
1987static void serial8250_break_ctl(struct uart_port *port, int break_state)
1988{
1989 struct uart_8250_port *up = up_to_u8250p(port);
1990 unsigned long flags;
1991
1992 serial8250_rpm_get(up);
1993 spin_lock_irqsave(&port->lock, flags);
1994 if (break_state == -1)
1995 up->lcr |= UART_LCR_SBC;
1996 else
1997 up->lcr &= ~UART_LCR_SBC;
1998 serial_port_out(port, UART_LCR, up->lcr);
1999 spin_unlock_irqrestore(&port->lock, flags);
2000 serial8250_rpm_put(up);
2001}
2002
2003
2004
2005
2006static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2007{
2008 unsigned int status, tmout = 10000;
2009
2010
2011 for (;;) {
2012 status = serial_in(up, UART_LSR);
2013
2014 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2015
2016 if ((status & bits) == bits)
2017 break;
2018 if (--tmout == 0)
2019 break;
2020 udelay(1);
2021 touch_nmi_watchdog();
2022 }
2023
2024
2025 if (up->port.flags & UPF_CONS_FLOW) {
2026 for (tmout = 1000000; tmout; tmout--) {
2027 unsigned int msr = serial_in(up, UART_MSR);
2028 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2029 if (msr & UART_MSR_CTS)
2030 break;
2031 udelay(1);
2032 touch_nmi_watchdog();
2033 }
2034 }
2035}
2036
2037#ifdef CONFIG_CONSOLE_POLL
2038
2039
2040
2041
2042
2043static int serial8250_get_poll_char(struct uart_port *port)
2044{
2045 struct uart_8250_port *up = up_to_u8250p(port);
2046 unsigned char lsr;
2047 int status;
2048
2049 serial8250_rpm_get(up);
2050
2051 lsr = serial_port_in(port, UART_LSR);
2052
2053 if (!(lsr & UART_LSR_DR)) {
2054 status = NO_POLL_CHAR;
2055 goto out;
2056 }
2057
2058 status = serial_port_in(port, UART_RX);
2059out:
2060 serial8250_rpm_put(up);
2061 return status;
2062}
2063
2064
2065static void serial8250_put_poll_char(struct uart_port *port,
2066 unsigned char c)
2067{
2068 unsigned int ier;
2069 struct uart_8250_port *up = up_to_u8250p(port);
2070
2071 serial8250_rpm_get(up);
2072
2073
2074
2075 ier = serial_port_in(port, UART_IER);
2076 if (up->capabilities & UART_CAP_UUE)
2077 serial_port_out(port, UART_IER, UART_IER_UUE);
2078 else
2079 serial_port_out(port, UART_IER, 0);
2080
2081 wait_for_xmitr(up, BOTH_EMPTY);
2082
2083
2084
2085 serial_port_out(port, UART_TX, c);
2086
2087
2088
2089
2090
2091 wait_for_xmitr(up, BOTH_EMPTY);
2092 serial_port_out(port, UART_IER, ier);
2093 serial8250_rpm_put(up);
2094}
2095
2096#endif
2097
2098int serial8250_do_startup(struct uart_port *port)
2099{
2100 struct uart_8250_port *up = up_to_u8250p(port);
2101 unsigned long flags;
2102 unsigned char lsr, iir;
2103 int retval;
2104
2105 if (!port->fifosize)
2106 port->fifosize = uart_config[port->type].fifo_size;
2107 if (!up->tx_loadsz)
2108 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2109 if (!up->capabilities)
2110 up->capabilities = uart_config[port->type].flags;
2111 up->mcr = 0;
2112
2113 if (port->iotype != up->cur_iotype)
2114 set_io_from_upio(port);
2115
2116 serial8250_rpm_get(up);
2117 if (port->type == PORT_16C950) {
2118
2119 up->acr = 0;
2120 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2121 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2122 serial_port_out(port, UART_IER, 0);
2123 serial_port_out(port, UART_LCR, 0);
2124 serial_icr_write(up, UART_CSR, 0);
2125 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2126 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2127 serial_port_out(port, UART_LCR, 0);
2128 }
2129
2130 if (port->type == PORT_DA830) {
2131
2132 serial_port_out(port, UART_IER, 0);
2133 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2134 mdelay(10);
2135
2136
2137 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2138 UART_DA830_PWREMU_MGMT_UTRST |
2139 UART_DA830_PWREMU_MGMT_URRST |
2140 UART_DA830_PWREMU_MGMT_FREE);
2141 }
2142
2143 if (port->type == PORT_NPCM) {
2144
2145
2146
2147
2148
2149 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2150 }
2151
2152#ifdef CONFIG_SERIAL_8250_RSA
2153
2154
2155
2156
2157 enable_rsa(up);
2158#endif
2159
2160 if (port->type == PORT_XR17V35X) {
2161
2162
2163
2164
2165 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2166
2167
2168
2169
2170
2171 serial_port_out(port, UART_IER, 0);
2172 }
2173
2174
2175
2176
2177
2178 serial8250_clear_fifos(up);
2179
2180
2181
2182
2183 serial_port_in(port, UART_LSR);
2184 serial_port_in(port, UART_RX);
2185 serial_port_in(port, UART_IIR);
2186 serial_port_in(port, UART_MSR);
2187 if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2188 serial_port_in(port, UART_EXAR_INT0);
2189
2190
2191
2192
2193
2194
2195 if (!(port->flags & UPF_BUGGY_UART) &&
2196 (serial_port_in(port, UART_LSR) == 0xff)) {
2197 pr_info_ratelimited("%s: LSR safety check engaged!\n", port->name);
2198 retval = -ENODEV;
2199 goto out;
2200 }
2201
2202
2203
2204
2205 if (port->type == PORT_16850) {
2206 unsigned char fctr;
2207
2208 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2209
2210 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2211 serial_port_out(port, UART_FCTR,
2212 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2213 serial_port_out(port, UART_TRG, UART_TRG_96);
2214 serial_port_out(port, UART_FCTR,
2215 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2216 serial_port_out(port, UART_TRG, UART_TRG_96);
2217
2218 serial_port_out(port, UART_LCR, 0);
2219 }
2220
2221
2222
2223
2224 if (((port->type == PORT_ALTR_16550_F32) ||
2225 (port->type == PORT_ALTR_16550_F64) ||
2226 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2227
2228 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2229 pr_err("%s TX FIFO Threshold errors, skipping\n",
2230 port->name);
2231 } else {
2232 serial_port_out(port, UART_ALTR_AFR,
2233 UART_ALTR_EN_TXFIFO_LW);
2234 serial_port_out(port, UART_ALTR_TX_LOW,
2235 port->fifosize - up->tx_loadsz);
2236 port->handle_irq = serial8250_tx_threshold_handle_irq;
2237 }
2238 }
2239
2240 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2241 unsigned char iir1;
2242
2243
2244
2245
2246
2247
2248
2249
2250 spin_lock_irqsave(&port->lock, flags);
2251 if (up->port.irqflags & IRQF_SHARED)
2252 disable_irq_nosync(port->irq);
2253
2254 wait_for_xmitr(up, UART_LSR_THRE);
2255 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2256 udelay(1);
2257 iir1 = serial_port_in(port, UART_IIR);
2258 serial_port_out(port, UART_IER, 0);
2259 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2260 udelay(1);
2261 iir = serial_port_in(port, UART_IIR);
2262 serial_port_out(port, UART_IER, 0);
2263
2264 if (port->irqflags & IRQF_SHARED)
2265 enable_irq(port->irq);
2266 spin_unlock_irqrestore(&port->lock, flags);
2267
2268
2269
2270
2271
2272
2273 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2274 up->port.flags & UPF_BUG_THRE) {
2275 up->bugs |= UART_BUG_THRE;
2276 }
2277 }
2278
2279 retval = up->ops->setup_irq(up);
2280 if (retval)
2281 goto out;
2282
2283
2284
2285
2286 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2287
2288 spin_lock_irqsave(&port->lock, flags);
2289 if (up->port.flags & UPF_FOURPORT) {
2290 if (!up->port.irq)
2291 up->port.mctrl |= TIOCM_OUT1;
2292 } else
2293
2294
2295
2296 if (port->irq)
2297 up->port.mctrl |= TIOCM_OUT2;
2298
2299 serial8250_set_mctrl(port, port->mctrl);
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2313 goto dont_test_tx_en;
2314
2315
2316
2317
2318
2319 serial_port_out(port, UART_IER, UART_IER_THRI);
2320 lsr = serial_port_in(port, UART_LSR);
2321 iir = serial_port_in(port, UART_IIR);
2322 serial_port_out(port, UART_IER, 0);
2323
2324 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2325 if (!(up->bugs & UART_BUG_TXEN)) {
2326 up->bugs |= UART_BUG_TXEN;
2327 pr_debug("%s - enabling bad tx status workarounds\n",
2328 port->name);
2329 }
2330 } else {
2331 up->bugs &= ~UART_BUG_TXEN;
2332 }
2333
2334dont_test_tx_en:
2335 spin_unlock_irqrestore(&port->lock, flags);
2336
2337
2338
2339
2340
2341
2342 serial_port_in(port, UART_LSR);
2343 serial_port_in(port, UART_RX);
2344 serial_port_in(port, UART_IIR);
2345 serial_port_in(port, UART_MSR);
2346 if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2347 serial_port_in(port, UART_EXAR_INT0);
2348 up->lsr_saved_flags = 0;
2349 up->msr_saved_flags = 0;
2350
2351
2352
2353
2354 if (up->dma) {
2355 retval = serial8250_request_dma(up);
2356 if (retval) {
2357 pr_warn_ratelimited("%s - failed to request DMA\n",
2358 port->name);
2359 up->dma = NULL;
2360 }
2361 }
2362
2363
2364
2365
2366
2367
2368 up->ier = UART_IER_RLSI | UART_IER_RDI;
2369
2370 if (port->flags & UPF_FOURPORT) {
2371 unsigned int icp;
2372
2373
2374
2375 icp = (port->iobase & 0xfe0) | 0x01f;
2376 outb_p(0x80, icp);
2377 inb_p(icp);
2378 }
2379 retval = 0;
2380out:
2381 serial8250_rpm_put(up);
2382 return retval;
2383}
2384EXPORT_SYMBOL_GPL(serial8250_do_startup);
2385
2386static int serial8250_startup(struct uart_port *port)
2387{
2388 if (port->startup)
2389 return port->startup(port);
2390 return serial8250_do_startup(port);
2391}
2392
2393void serial8250_do_shutdown(struct uart_port *port)
2394{
2395 struct uart_8250_port *up = up_to_u8250p(port);
2396 unsigned long flags;
2397
2398 serial8250_rpm_get(up);
2399
2400
2401
2402 spin_lock_irqsave(&port->lock, flags);
2403 up->ier = 0;
2404 serial_port_out(port, UART_IER, 0);
2405 spin_unlock_irqrestore(&port->lock, flags);
2406
2407 synchronize_irq(port->irq);
2408
2409 if (up->dma)
2410 serial8250_release_dma(up);
2411
2412 spin_lock_irqsave(&port->lock, flags);
2413 if (port->flags & UPF_FOURPORT) {
2414
2415 inb((port->iobase & 0xfe0) | 0x1f);
2416 port->mctrl |= TIOCM_OUT1;
2417 } else
2418 port->mctrl &= ~TIOCM_OUT2;
2419
2420 serial8250_set_mctrl(port, port->mctrl);
2421 spin_unlock_irqrestore(&port->lock, flags);
2422
2423
2424
2425
2426 serial_port_out(port, UART_LCR,
2427 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2428 serial8250_clear_fifos(up);
2429
2430#ifdef CONFIG_SERIAL_8250_RSA
2431
2432
2433
2434 disable_rsa(up);
2435#endif
2436
2437
2438
2439
2440
2441 serial_port_in(port, UART_RX);
2442 serial8250_rpm_put(up);
2443
2444 up->ops->release_irq(up);
2445}
2446EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2447
2448static void serial8250_shutdown(struct uart_port *port)
2449{
2450 if (port->shutdown)
2451 port->shutdown(port);
2452 else
2453 serial8250_do_shutdown(port);
2454}
2455
2456
2457
2458
2459
2460static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2461 unsigned int baud,
2462 unsigned int *frac)
2463{
2464 struct uart_port *port = &up->port;
2465 unsigned int quot_16;
2466
2467 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2468 *frac = quot_16 & 0x0f;
2469
2470 return quot_16 >> 4;
2471}
2472
2473
2474static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2475 unsigned int baud)
2476{
2477 struct uart_port *port = &up->port;
2478
2479 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2480}
2481
2482static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2483 unsigned int baud,
2484 unsigned int *frac)
2485{
2486 struct uart_8250_port *up = up_to_u8250p(port);
2487 unsigned int quot;
2488
2489
2490
2491
2492
2493
2494 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2495 baud == (port->uartclk/4))
2496 quot = 0x8001;
2497 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2498 baud == (port->uartclk/8))
2499 quot = 0x8002;
2500 else if (up->port.type == PORT_XR17V35X)
2501 quot = xr17v35x_get_divisor(up, baud, frac);
2502 else if (up->port.type == PORT_NPCM)
2503 quot = npcm_get_divisor(up, baud);
2504 else
2505 quot = uart_get_divisor(port, baud);
2506
2507
2508
2509
2510 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2511 quot++;
2512
2513 return quot;
2514}
2515
2516static unsigned int serial8250_get_divisor(struct uart_port *port,
2517 unsigned int baud,
2518 unsigned int *frac)
2519{
2520 if (port->get_divisor)
2521 return port->get_divisor(port, baud, frac);
2522
2523 return serial8250_do_get_divisor(port, baud, frac);
2524}
2525
2526static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2527 tcflag_t c_cflag)
2528{
2529 unsigned char cval;
2530
2531 switch (c_cflag & CSIZE) {
2532 case CS5:
2533 cval = UART_LCR_WLEN5;
2534 break;
2535 case CS6:
2536 cval = UART_LCR_WLEN6;
2537 break;
2538 case CS7:
2539 cval = UART_LCR_WLEN7;
2540 break;
2541 default:
2542 case CS8:
2543 cval = UART_LCR_WLEN8;
2544 break;
2545 }
2546
2547 if (c_cflag & CSTOPB)
2548 cval |= UART_LCR_STOP;
2549 if (c_cflag & PARENB) {
2550 cval |= UART_LCR_PARITY;
2551 if (up->bugs & UART_BUG_PARITY)
2552 up->fifo_bug = true;
2553 }
2554 if (!(c_cflag & PARODD))
2555 cval |= UART_LCR_EPAR;
2556#ifdef CMSPAR
2557 if (c_cflag & CMSPAR)
2558 cval |= UART_LCR_SPAR;
2559#endif
2560
2561 return cval;
2562}
2563
2564void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2565 unsigned int quot, unsigned int quot_frac)
2566{
2567 struct uart_8250_port *up = up_to_u8250p(port);
2568
2569
2570 if (is_omap1510_8250(up)) {
2571 if (baud == 115200) {
2572 quot = 1;
2573 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2574 } else
2575 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2576 }
2577
2578
2579
2580
2581
2582 if (up->capabilities & UART_NATSEMI)
2583 serial_port_out(port, UART_LCR, 0xe0);
2584 else
2585 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2586
2587 serial_dl_write(up, quot);
2588
2589
2590 if (up->port.type == PORT_XR17V35X) {
2591
2592 quot_frac |= serial_port_in(port, 0x2) & 0xf0;
2593 serial_port_out(port, 0x2, quot_frac);
2594 }
2595}
2596EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2597
2598static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2599 unsigned int quot, unsigned int quot_frac)
2600{
2601 if (port->set_divisor)
2602 port->set_divisor(port, baud, quot, quot_frac);
2603 else
2604 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2605}
2606
2607static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2608 struct ktermios *termios,
2609 struct ktermios *old)
2610{
2611
2612
2613
2614
2615
2616
2617 return uart_get_baud_rate(port, termios, old,
2618 port->uartclk / 16 / UART_DIV_MAX,
2619 port->uartclk);
2620}
2621
2622void
2623serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2624 struct ktermios *old)
2625{
2626 struct uart_8250_port *up = up_to_u8250p(port);
2627 unsigned char cval;
2628 unsigned long flags;
2629 unsigned int baud, quot, frac = 0;
2630
2631 if (up->capabilities & UART_CAP_MINI) {
2632 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2633 if ((termios->c_cflag & CSIZE) == CS5 ||
2634 (termios->c_cflag & CSIZE) == CS6)
2635 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2636 }
2637 cval = serial8250_compute_lcr(up, termios->c_cflag);
2638
2639 baud = serial8250_get_baud_rate(port, termios, old);
2640 quot = serial8250_get_divisor(port, baud, &frac);
2641
2642
2643
2644
2645
2646 serial8250_rpm_get(up);
2647 spin_lock_irqsave(&port->lock, flags);
2648
2649 up->lcr = cval;
2650
2651 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2652
2653 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2654 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2655 up->fcr |= UART_FCR_TRIGGER_1;
2656 }
2657 }
2658
2659
2660
2661
2662
2663
2664 if (up->capabilities & UART_CAP_AFE) {
2665 up->mcr &= ~UART_MCR_AFE;
2666 if (termios->c_cflag & CRTSCTS)
2667 up->mcr |= UART_MCR_AFE;
2668 }
2669
2670
2671
2672
2673 uart_update_timeout(port, termios->c_cflag, baud);
2674
2675 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2676 if (termios->c_iflag & INPCK)
2677 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2678 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2679 port->read_status_mask |= UART_LSR_BI;
2680
2681
2682
2683
2684 port->ignore_status_mask = 0;
2685 if (termios->c_iflag & IGNPAR)
2686 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2687 if (termios->c_iflag & IGNBRK) {
2688 port->ignore_status_mask |= UART_LSR_BI;
2689
2690
2691
2692
2693 if (termios->c_iflag & IGNPAR)
2694 port->ignore_status_mask |= UART_LSR_OE;
2695 }
2696
2697
2698
2699
2700 if ((termios->c_cflag & CREAD) == 0)
2701 port->ignore_status_mask |= UART_LSR_DR;
2702
2703
2704
2705
2706 up->ier &= ~UART_IER_MSI;
2707 if (!(up->bugs & UART_BUG_NOMSR) &&
2708 UART_ENABLE_MS(&up->port, termios->c_cflag))
2709 up->ier |= UART_IER_MSI;
2710 if (up->capabilities & UART_CAP_UUE)
2711 up->ier |= UART_IER_UUE;
2712 if (up->capabilities & UART_CAP_RTOIE)
2713 up->ier |= UART_IER_RTOIE;
2714
2715 serial_port_out(port, UART_IER, up->ier);
2716
2717 if (up->capabilities & UART_CAP_EFR) {
2718 unsigned char efr = 0;
2719
2720
2721
2722
2723
2724 if (termios->c_cflag & CRTSCTS)
2725 efr |= UART_EFR_CTS;
2726
2727 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2728 if (port->flags & UPF_EXAR_EFR)
2729 serial_port_out(port, UART_XR_EFR, efr);
2730 else
2731 serial_port_out(port, UART_EFR, efr);
2732 }
2733
2734 serial8250_set_divisor(port, baud, quot, frac);
2735
2736
2737
2738
2739
2740 if (port->type == PORT_16750)
2741 serial_port_out(port, UART_FCR, up->fcr);
2742
2743 serial_port_out(port, UART_LCR, up->lcr);
2744 if (port->type != PORT_16750) {
2745
2746 if (up->fcr & UART_FCR_ENABLE_FIFO)
2747 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2748 serial_port_out(port, UART_FCR, up->fcr);
2749 }
2750 serial8250_set_mctrl(port, port->mctrl);
2751 spin_unlock_irqrestore(&port->lock, flags);
2752 serial8250_rpm_put(up);
2753
2754
2755 if (tty_termios_baud_rate(termios))
2756 tty_termios_encode_baud_rate(termios, baud, baud);
2757}
2758EXPORT_SYMBOL(serial8250_do_set_termios);
2759
2760static void
2761serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2762 struct ktermios *old)
2763{
2764 if (port->set_termios)
2765 port->set_termios(port, termios, old);
2766 else
2767 serial8250_do_set_termios(port, termios, old);
2768}
2769
2770void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2771{
2772 if (termios->c_line == N_PPS) {
2773 port->flags |= UPF_HARDPPS_CD;
2774 spin_lock_irq(&port->lock);
2775 serial8250_enable_ms(port);
2776 spin_unlock_irq(&port->lock);
2777 } else {
2778 port->flags &= ~UPF_HARDPPS_CD;
2779 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2780 spin_lock_irq(&port->lock);
2781 serial8250_disable_ms(port);
2782 spin_unlock_irq(&port->lock);
2783 }
2784 }
2785}
2786EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2787
2788static void
2789serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2790{
2791 if (port->set_ldisc)
2792 port->set_ldisc(port, termios);
2793 else
2794 serial8250_do_set_ldisc(port, termios);
2795}
2796
2797void serial8250_do_pm(struct uart_port *port, unsigned int state,
2798 unsigned int oldstate)
2799{
2800 struct uart_8250_port *p = up_to_u8250p(port);
2801
2802 serial8250_set_sleep(p, state != 0);
2803}
2804EXPORT_SYMBOL(serial8250_do_pm);
2805
2806static void
2807serial8250_pm(struct uart_port *port, unsigned int state,
2808 unsigned int oldstate)
2809{
2810 if (port->pm)
2811 port->pm(port, state, oldstate);
2812 else
2813 serial8250_do_pm(port, state, oldstate);
2814}
2815
2816static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2817{
2818 if (pt->port.mapsize)
2819 return pt->port.mapsize;
2820 if (pt->port.iotype == UPIO_AU) {
2821 if (pt->port.type == PORT_RT2880)
2822 return 0x100;
2823 return 0x1000;
2824 }
2825 if (is_omap1_8250(pt))
2826 return 0x16 << pt->port.regshift;
2827
2828 return 8 << pt->port.regshift;
2829}
2830
2831
2832
2833
2834static int serial8250_request_std_resource(struct uart_8250_port *up)
2835{
2836 unsigned int size = serial8250_port_size(up);
2837 struct uart_port *port = &up->port;
2838 int ret = 0;
2839
2840 switch (port->iotype) {
2841 case UPIO_AU:
2842 case UPIO_TSI:
2843 case UPIO_MEM32:
2844 case UPIO_MEM32BE:
2845 case UPIO_MEM16:
2846 case UPIO_MEM:
2847 if (!port->mapbase)
2848 break;
2849
2850 if (!request_mem_region(port->mapbase, size, "serial")) {
2851 ret = -EBUSY;
2852 break;
2853 }
2854
2855 if (port->flags & UPF_IOREMAP) {
2856 port->membase = ioremap_nocache(port->mapbase, size);
2857 if (!port->membase) {
2858 release_mem_region(port->mapbase, size);
2859 ret = -ENOMEM;
2860 }
2861 }
2862 break;
2863
2864 case UPIO_HUB6:
2865 case UPIO_PORT:
2866 if (!request_region(port->iobase, size, "serial"))
2867 ret = -EBUSY;
2868 break;
2869 }
2870 return ret;
2871}
2872
2873static void serial8250_release_std_resource(struct uart_8250_port *up)
2874{
2875 unsigned int size = serial8250_port_size(up);
2876 struct uart_port *port = &up->port;
2877
2878 switch (port->iotype) {
2879 case UPIO_AU:
2880 case UPIO_TSI:
2881 case UPIO_MEM32:
2882 case UPIO_MEM32BE:
2883 case UPIO_MEM16:
2884 case UPIO_MEM:
2885 if (!port->mapbase)
2886 break;
2887
2888 if (port->flags & UPF_IOREMAP) {
2889 iounmap(port->membase);
2890 port->membase = NULL;
2891 }
2892
2893 release_mem_region(port->mapbase, size);
2894 break;
2895
2896 case UPIO_HUB6:
2897 case UPIO_PORT:
2898 release_region(port->iobase, size);
2899 break;
2900 }
2901}
2902
2903static void serial8250_release_port(struct uart_port *port)
2904{
2905 struct uart_8250_port *up = up_to_u8250p(port);
2906
2907 serial8250_release_std_resource(up);
2908}
2909
2910static int serial8250_request_port(struct uart_port *port)
2911{
2912 struct uart_8250_port *up = up_to_u8250p(port);
2913
2914 return serial8250_request_std_resource(up);
2915}
2916
2917static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2918{
2919 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2920 unsigned char bytes;
2921
2922 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2923
2924 return bytes ? bytes : -EOPNOTSUPP;
2925}
2926
2927static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2928{
2929 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2930 int i;
2931
2932 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2933 return -EOPNOTSUPP;
2934
2935 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2936 if (bytes < conf_type->rxtrig_bytes[i])
2937
2938 return (--i) << UART_FCR_R_TRIG_SHIFT;
2939 }
2940
2941 return UART_FCR_R_TRIG_11;
2942}
2943
2944static int do_get_rxtrig(struct tty_port *port)
2945{
2946 struct uart_state *state = container_of(port, struct uart_state, port);
2947 struct uart_port *uport = state->uart_port;
2948 struct uart_8250_port *up = up_to_u8250p(uport);
2949
2950 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2951 return -EINVAL;
2952
2953 return fcr_get_rxtrig_bytes(up);
2954}
2955
2956static int do_serial8250_get_rxtrig(struct tty_port *port)
2957{
2958 int rxtrig_bytes;
2959
2960 mutex_lock(&port->mutex);
2961 rxtrig_bytes = do_get_rxtrig(port);
2962 mutex_unlock(&port->mutex);
2963
2964 return rxtrig_bytes;
2965}
2966
2967static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2968 struct device_attribute *attr, char *buf)
2969{
2970 struct tty_port *port = dev_get_drvdata(dev);
2971 int rxtrig_bytes;
2972
2973 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2974 if (rxtrig_bytes < 0)
2975 return rxtrig_bytes;
2976
2977 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2978}
2979
2980static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2981{
2982 struct uart_state *state = container_of(port, struct uart_state, port);
2983 struct uart_port *uport = state->uart_port;
2984 struct uart_8250_port *up = up_to_u8250p(uport);
2985 int rxtrig;
2986
2987 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2988 up->fifo_bug)
2989 return -EINVAL;
2990
2991 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2992 if (rxtrig < 0)
2993 return rxtrig;
2994
2995 serial8250_clear_fifos(up);
2996 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2997 up->fcr |= (unsigned char)rxtrig;
2998 serial_out(up, UART_FCR, up->fcr);
2999 return 0;
3000}
3001
3002static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3003{
3004 int ret;
3005
3006 mutex_lock(&port->mutex);
3007 ret = do_set_rxtrig(port, bytes);
3008 mutex_unlock(&port->mutex);
3009
3010 return ret;
3011}
3012
3013static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
3014 struct device_attribute *attr, const char *buf, size_t count)
3015{
3016 struct tty_port *port = dev_get_drvdata(dev);
3017 unsigned char bytes;
3018 int ret;
3019
3020 if (!count)
3021 return -EINVAL;
3022
3023 ret = kstrtou8(buf, 10, &bytes);
3024 if (ret < 0)
3025 return ret;
3026
3027 ret = do_serial8250_set_rxtrig(port, bytes);
3028 if (ret < 0)
3029 return ret;
3030
3031 return count;
3032}
3033
3034static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
3035 serial8250_get_attr_rx_trig_bytes,
3036 serial8250_set_attr_rx_trig_bytes);
3037
3038static struct attribute *serial8250_dev_attrs[] = {
3039 &dev_attr_rx_trig_bytes.attr,
3040 NULL,
3041 };
3042
3043static struct attribute_group serial8250_dev_attr_group = {
3044 .attrs = serial8250_dev_attrs,
3045 };
3046
3047static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3048{
3049 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3050
3051 if (conf_type->rxtrig_bytes[0])
3052 up->port.attr_group = &serial8250_dev_attr_group;
3053}
3054
3055static void serial8250_config_port(struct uart_port *port, int flags)
3056{
3057 struct uart_8250_port *up = up_to_u8250p(port);
3058 int ret;
3059
3060
3061
3062
3063
3064 ret = serial8250_request_std_resource(up);
3065 if (ret < 0)
3066 return;
3067
3068 if (port->iotype != up->cur_iotype)
3069 set_io_from_upio(port);
3070
3071 if (flags & UART_CONFIG_TYPE)
3072 autoconfig(up);
3073
3074
3075 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3076 up->bugs |= UART_BUG_NOMSR;
3077
3078
3079 if (port->type == PORT_TEGRA)
3080 up->bugs |= UART_BUG_NOMSR;
3081
3082 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3083 autoconfig_irq(up);
3084
3085 if (port->type == PORT_UNKNOWN)
3086 serial8250_release_std_resource(up);
3087
3088 register_dev_spec_attr_grp(up);
3089 up->fcr = uart_config[up->port.type].fcr;
3090}
3091
3092static int
3093serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3094{
3095 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3096 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3097 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3098 ser->type == PORT_STARTECH)
3099 return -EINVAL;
3100 return 0;
3101}
3102
3103static const char *serial8250_type(struct uart_port *port)
3104{
3105 int type = port->type;
3106
3107 if (type >= ARRAY_SIZE(uart_config))
3108 type = 0;
3109 return uart_config[type].name;
3110}
3111
3112static const struct uart_ops serial8250_pops = {
3113 .tx_empty = serial8250_tx_empty,
3114 .set_mctrl = serial8250_set_mctrl,
3115 .get_mctrl = serial8250_get_mctrl,
3116 .stop_tx = serial8250_stop_tx,
3117 .start_tx = serial8250_start_tx,
3118 .throttle = serial8250_throttle,
3119 .unthrottle = serial8250_unthrottle,
3120 .stop_rx = serial8250_stop_rx,
3121 .enable_ms = serial8250_enable_ms,
3122 .break_ctl = serial8250_break_ctl,
3123 .startup = serial8250_startup,
3124 .shutdown = serial8250_shutdown,
3125 .set_termios = serial8250_set_termios,
3126 .set_ldisc = serial8250_set_ldisc,
3127 .pm = serial8250_pm,
3128 .type = serial8250_type,
3129 .release_port = serial8250_release_port,
3130 .request_port = serial8250_request_port,
3131 .config_port = serial8250_config_port,
3132 .verify_port = serial8250_verify_port,
3133#ifdef CONFIG_CONSOLE_POLL
3134 .poll_get_char = serial8250_get_poll_char,
3135 .poll_put_char = serial8250_put_poll_char,
3136#endif
3137};
3138
3139void serial8250_init_port(struct uart_8250_port *up)
3140{
3141 struct uart_port *port = &up->port;
3142
3143 spin_lock_init(&port->lock);
3144 port->ops = &serial8250_pops;
3145
3146 up->cur_iotype = 0xFF;
3147}
3148EXPORT_SYMBOL_GPL(serial8250_init_port);
3149
3150void serial8250_set_defaults(struct uart_8250_port *up)
3151{
3152 struct uart_port *port = &up->port;
3153
3154 if (up->port.flags & UPF_FIXED_TYPE) {
3155 unsigned int type = up->port.type;
3156
3157 if (!up->port.fifosize)
3158 up->port.fifosize = uart_config[type].fifo_size;
3159 if (!up->tx_loadsz)
3160 up->tx_loadsz = uart_config[type].tx_loadsz;
3161 if (!up->capabilities)
3162 up->capabilities = uart_config[type].flags;
3163 }
3164
3165 set_io_from_upio(port);
3166
3167
3168 if (up->dma) {
3169 if (!up->dma->tx_dma)
3170 up->dma->tx_dma = serial8250_tx_dma;
3171 if (!up->dma->rx_dma)
3172 up->dma->rx_dma = serial8250_rx_dma;
3173 }
3174}
3175EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3176
3177#ifdef CONFIG_SERIAL_8250_CONSOLE
3178
3179static void serial8250_console_putchar(struct uart_port *port, int ch)
3180{
3181 struct uart_8250_port *up = up_to_u8250p(port);
3182
3183 wait_for_xmitr(up, UART_LSR_THRE);
3184 serial_port_out(port, UART_TX, ch);
3185}
3186
3187
3188
3189
3190static void serial8250_console_restore(struct uart_8250_port *up)
3191{
3192 struct uart_port *port = &up->port;
3193 struct ktermios termios;
3194 unsigned int baud, quot, frac = 0;
3195
3196 termios.c_cflag = port->cons->cflag;
3197 if (port->state->port.tty && termios.c_cflag == 0)
3198 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3199
3200 baud = serial8250_get_baud_rate(port, &termios, NULL);
3201 quot = serial8250_get_divisor(port, baud, &frac);
3202
3203 serial8250_set_divisor(port, baud, quot, frac);
3204 serial_port_out(port, UART_LCR, up->lcr);
3205 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3206}
3207
3208
3209
3210
3211
3212
3213
3214void serial8250_console_write(struct uart_8250_port *up, const char *s,
3215 unsigned int count)
3216{
3217 struct uart_port *port = &up->port;
3218 unsigned long flags;
3219 unsigned int ier;
3220 int locked = 1;
3221
3222 touch_nmi_watchdog();
3223
3224 serial8250_rpm_get(up);
3225
3226 if (oops_in_progress)
3227 locked = spin_trylock_irqsave(&port->lock, flags);
3228 else
3229 spin_lock_irqsave(&port->lock, flags);
3230
3231
3232
3233
3234 ier = serial_port_in(port, UART_IER);
3235
3236 if (up->capabilities & UART_CAP_UUE)
3237 serial_port_out(port, UART_IER, UART_IER_UUE);
3238 else
3239 serial_port_out(port, UART_IER, 0);
3240
3241
3242 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3243 serial8250_console_restore(up);
3244 up->canary = 0;
3245 }
3246
3247 uart_console_write(port, s, count, serial8250_console_putchar);
3248
3249
3250
3251
3252
3253 wait_for_xmitr(up, BOTH_EMPTY);
3254 serial_port_out(port, UART_IER, ier);
3255
3256
3257
3258
3259
3260
3261
3262
3263 if (up->msr_saved_flags)
3264 serial8250_modem_status(up);
3265
3266 if (locked)
3267 spin_unlock_irqrestore(&port->lock, flags);
3268 serial8250_rpm_put(up);
3269}
3270
3271static unsigned int probe_baud(struct uart_port *port)
3272{
3273 unsigned char lcr, dll, dlm;
3274 unsigned int quot;
3275
3276 lcr = serial_port_in(port, UART_LCR);
3277 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3278 dll = serial_port_in(port, UART_DLL);
3279 dlm = serial_port_in(port, UART_DLM);
3280 serial_port_out(port, UART_LCR, lcr);
3281
3282 quot = (dlm << 8) | dll;
3283 return (port->uartclk / 16) / quot;
3284}
3285
3286int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3287{
3288 int baud = 9600;
3289 int bits = 8;
3290 int parity = 'n';
3291 int flow = 'n';
3292
3293 if (!port->iobase && !port->membase)
3294 return -ENODEV;
3295
3296 if (options)
3297 uart_parse_options(options, &baud, &parity, &bits, &flow);
3298 else if (probe)
3299 baud = probe_baud(port);
3300
3301 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3302}
3303
3304#endif
3305
3306MODULE_LICENSE("GPL");
3307