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43#include <linux/delay.h>
44#include <linux/device.h>
45#include <linux/dma-mapping.h>
46#include <linux/extcon.h>
47#include <linux/phy/phy.h>
48#include <linux/platform_device.h>
49#include <linux/module.h>
50#include <linux/idr.h>
51#include <linux/interrupt.h>
52#include <linux/io.h>
53#include <linux/kernel.h>
54#include <linux/slab.h>
55#include <linux/pm_runtime.h>
56#include <linux/pinctrl/consumer.h>
57#include <linux/usb/ch9.h>
58#include <linux/usb/gadget.h>
59#include <linux/usb/otg.h>
60#include <linux/usb/chipidea.h>
61#include <linux/usb/of.h>
62#include <linux/of.h>
63#include <linux/regulator/consumer.h>
64#include <linux/usb/ehci_def.h>
65
66#include "ci.h"
67#include "udc.h"
68#include "bits.h"
69#include "host.h"
70#include "otg.h"
71#include "otg_fsm.h"
72
73
74static const u8 ci_regs_nolpm[] = {
75 [CAP_CAPLENGTH] = 0x00U,
76 [CAP_HCCPARAMS] = 0x08U,
77 [CAP_DCCPARAMS] = 0x24U,
78 [CAP_TESTMODE] = 0x38U,
79 [OP_USBCMD] = 0x00U,
80 [OP_USBSTS] = 0x04U,
81 [OP_USBINTR] = 0x08U,
82 [OP_DEVICEADDR] = 0x14U,
83 [OP_ENDPTLISTADDR] = 0x18U,
84 [OP_TTCTRL] = 0x1CU,
85 [OP_BURSTSIZE] = 0x20U,
86 [OP_ULPI_VIEWPORT] = 0x30U,
87 [OP_PORTSC] = 0x44U,
88 [OP_DEVLC] = 0x84U,
89 [OP_OTGSC] = 0x64U,
90 [OP_USBMODE] = 0x68U,
91 [OP_ENDPTSETUPSTAT] = 0x6CU,
92 [OP_ENDPTPRIME] = 0x70U,
93 [OP_ENDPTFLUSH] = 0x74U,
94 [OP_ENDPTSTAT] = 0x78U,
95 [OP_ENDPTCOMPLETE] = 0x7CU,
96 [OP_ENDPTCTRL] = 0x80U,
97};
98
99static const u8 ci_regs_lpm[] = {
100 [CAP_CAPLENGTH] = 0x00U,
101 [CAP_HCCPARAMS] = 0x08U,
102 [CAP_DCCPARAMS] = 0x24U,
103 [CAP_TESTMODE] = 0xFCU,
104 [OP_USBCMD] = 0x00U,
105 [OP_USBSTS] = 0x04U,
106 [OP_USBINTR] = 0x08U,
107 [OP_DEVICEADDR] = 0x14U,
108 [OP_ENDPTLISTADDR] = 0x18U,
109 [OP_TTCTRL] = 0x1CU,
110 [OP_BURSTSIZE] = 0x20U,
111 [OP_ULPI_VIEWPORT] = 0x30U,
112 [OP_PORTSC] = 0x44U,
113 [OP_DEVLC] = 0x84U,
114 [OP_OTGSC] = 0xC4U,
115 [OP_USBMODE] = 0xC8U,
116 [OP_ENDPTSETUPSTAT] = 0xD8U,
117 [OP_ENDPTPRIME] = 0xDCU,
118 [OP_ENDPTFLUSH] = 0xE0U,
119 [OP_ENDPTSTAT] = 0xE4U,
120 [OP_ENDPTCOMPLETE] = 0xE8U,
121 [OP_ENDPTCTRL] = 0xECU,
122};
123
124static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
125{
126 int i;
127
128 for (i = 0; i < OP_ENDPTCTRL; i++)
129 ci->hw_bank.regmap[i] =
130 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
131 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
132
133 for (; i <= OP_LAST; i++)
134 ci->hw_bank.regmap[i] = ci->hw_bank.op +
135 4 * (i - OP_ENDPTCTRL) +
136 (is_lpm
137 ? ci_regs_lpm[OP_ENDPTCTRL]
138 : ci_regs_nolpm[OP_ENDPTCTRL]);
139
140}
141
142static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
143{
144 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
145 enum ci_revision rev = CI_REVISION_UNKNOWN;
146
147 if (ver == 0x2) {
148 rev = hw_read_id_reg(ci, ID_ID, REVISION)
149 >> __ffs(REVISION);
150 rev += CI_REVISION_20;
151 } else if (ver == 0x0) {
152 rev = CI_REVISION_1X;
153 }
154
155 return rev;
156}
157
158
159
160
161
162
163
164
165u32 hw_read_intr_enable(struct ci_hdrc *ci)
166{
167 return hw_read(ci, OP_USBINTR, ~0);
168}
169
170
171
172
173
174
175
176
177u32 hw_read_intr_status(struct ci_hdrc *ci)
178{
179 return hw_read(ci, OP_USBSTS, ~0);
180}
181
182
183
184
185
186
187
188int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
189{
190 const u8 TEST_MODE_MAX = 7;
191
192 if (mode > TEST_MODE_MAX)
193 return -EINVAL;
194
195 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
196 return 0;
197}
198
199
200
201
202
203
204
205
206u8 hw_port_test_get(struct ci_hdrc *ci)
207{
208 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
209}
210
211static void hw_wait_phy_stable(void)
212{
213
214
215
216
217
218
219 usleep_range(2000, 2500);
220}
221
222
223static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
224{
225 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
226 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
227
228 if (enable && !lpm)
229 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
230 PORTSC_PHCD(ci->hw_bank.lpm));
231 else if (!enable && lpm)
232 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
233 0);
234}
235
236static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
237{
238 u32 reg;
239
240
241 ci->hw_bank.abs = base;
242
243 ci->hw_bank.cap = ci->hw_bank.abs;
244 ci->hw_bank.cap += ci->platdata->capoffset;
245 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
246
247 hw_alloc_regmap(ci, false);
248 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
249 __ffs(HCCPARAMS_LEN);
250 ci->hw_bank.lpm = reg;
251 if (reg)
252 hw_alloc_regmap(ci, !!reg);
253 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
254 ci->hw_bank.size += OP_LAST;
255 ci->hw_bank.size /= sizeof(u32);
256
257 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
258 __ffs(DCCPARAMS_DEN);
259 ci->hw_ep_max = reg * 2;
260
261 if (ci->hw_ep_max > ENDPT_MAX)
262 return -ENODEV;
263
264 ci_hdrc_enter_lpm(ci, false);
265
266
267 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
268
269
270 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
271
272 ci->rev = ci_get_revision(ci);
273
274 dev_dbg(ci->dev,
275 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
276 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
277
278
279
280
281
282
283
284 return 0;
285}
286
287void hw_phymode_configure(struct ci_hdrc *ci)
288{
289 u32 portsc, lpm, sts = 0;
290
291 switch (ci->platdata->phy_mode) {
292 case USBPHY_INTERFACE_MODE_UTMI:
293 portsc = PORTSC_PTS(PTS_UTMI);
294 lpm = DEVLC_PTS(PTS_UTMI);
295 break;
296 case USBPHY_INTERFACE_MODE_UTMIW:
297 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
298 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
299 break;
300 case USBPHY_INTERFACE_MODE_ULPI:
301 portsc = PORTSC_PTS(PTS_ULPI);
302 lpm = DEVLC_PTS(PTS_ULPI);
303 break;
304 case USBPHY_INTERFACE_MODE_SERIAL:
305 portsc = PORTSC_PTS(PTS_SERIAL);
306 lpm = DEVLC_PTS(PTS_SERIAL);
307 sts = 1;
308 break;
309 case USBPHY_INTERFACE_MODE_HSIC:
310 portsc = PORTSC_PTS(PTS_HSIC);
311 lpm = DEVLC_PTS(PTS_HSIC);
312 break;
313 default:
314 return;
315 }
316
317 if (ci->hw_bank.lpm) {
318 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
319 if (sts)
320 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
321 } else {
322 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
323 if (sts)
324 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
325 }
326}
327EXPORT_SYMBOL_GPL(hw_phymode_configure);
328
329
330
331
332
333
334
335
336static int _ci_usb_phy_init(struct ci_hdrc *ci)
337{
338 int ret;
339
340 if (ci->phy) {
341 ret = phy_init(ci->phy);
342 if (ret)
343 return ret;
344
345 ret = phy_power_on(ci->phy);
346 if (ret) {
347 phy_exit(ci->phy);
348 return ret;
349 }
350 } else {
351 ret = usb_phy_init(ci->usb_phy);
352 }
353
354 return ret;
355}
356
357
358
359
360
361
362static void ci_usb_phy_exit(struct ci_hdrc *ci)
363{
364 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
365 return;
366
367 if (ci->phy) {
368 phy_power_off(ci->phy);
369 phy_exit(ci->phy);
370 } else {
371 usb_phy_shutdown(ci->usb_phy);
372 }
373}
374
375
376
377
378
379
380
381static int ci_usb_phy_init(struct ci_hdrc *ci)
382{
383 int ret;
384
385 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
386 return 0;
387
388 switch (ci->platdata->phy_mode) {
389 case USBPHY_INTERFACE_MODE_UTMI:
390 case USBPHY_INTERFACE_MODE_UTMIW:
391 case USBPHY_INTERFACE_MODE_HSIC:
392 ret = _ci_usb_phy_init(ci);
393 if (!ret)
394 hw_wait_phy_stable();
395 else
396 return ret;
397 hw_phymode_configure(ci);
398 break;
399 case USBPHY_INTERFACE_MODE_ULPI:
400 case USBPHY_INTERFACE_MODE_SERIAL:
401 hw_phymode_configure(ci);
402 ret = _ci_usb_phy_init(ci);
403 if (ret)
404 return ret;
405 break;
406 default:
407 ret = _ci_usb_phy_init(ci);
408 if (!ret)
409 hw_wait_phy_stable();
410 }
411
412 return ret;
413}
414
415
416
417
418
419
420
421void ci_platform_configure(struct ci_hdrc *ci)
422{
423 bool is_device_mode, is_host_mode;
424
425 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
426 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
427
428 if (is_device_mode) {
429 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
430
431 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
432 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
433 USBMODE_CI_SDIS);
434 }
435
436 if (is_host_mode) {
437 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
438
439 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
440 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
441 USBMODE_CI_SDIS);
442 }
443
444 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
445 if (ci->hw_bank.lpm)
446 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
447 else
448 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
449 }
450
451 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
452 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
453
454 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
455
456 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
457 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
458 ci->platdata->ahb_burst_config);
459
460
461 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
462 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
463 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
464 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
465
466 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
467 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
468 ci->platdata->rx_burst_size);
469 }
470}
471
472
473
474
475
476
477
478static int hw_controller_reset(struct ci_hdrc *ci)
479{
480 int count = 0;
481
482 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
483 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
484 udelay(10);
485 if (count++ > 1000)
486 return -ETIMEDOUT;
487 }
488
489 return 0;
490}
491
492
493
494
495
496
497
498int hw_device_reset(struct ci_hdrc *ci)
499{
500 int ret;
501
502
503 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
504 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
505
506 ret = hw_controller_reset(ci);
507 if (ret) {
508 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
509 return ret;
510 }
511
512 if (ci->platdata->notify_event) {
513 ret = ci->platdata->notify_event(ci,
514 CI_HDRC_CONTROLLER_RESET_EVENT);
515 if (ret)
516 return ret;
517 }
518
519
520 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
521 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
522
523 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
524
525 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
526 dev_err(ci->dev, "cannot enter in %s device mode\n",
527 ci_role(ci)->name);
528 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
529 return -ENODEV;
530 }
531
532 ci_platform_configure(ci);
533
534 return 0;
535}
536
537static irqreturn_t ci_irq(int irq, void *data)
538{
539 struct ci_hdrc *ci = data;
540 irqreturn_t ret = IRQ_NONE;
541 u32 otgsc = 0;
542
543 if (ci->in_lpm) {
544 disable_irq_nosync(irq);
545 ci->wakeup_int = true;
546 pm_runtime_get(ci->dev);
547 return IRQ_HANDLED;
548 }
549
550 if (ci->is_otg) {
551 otgsc = hw_read_otgsc(ci, ~0);
552 if (ci_otg_is_fsm_mode(ci)) {
553 ret = ci_otg_fsm_irq(ci);
554 if (ret == IRQ_HANDLED)
555 return ret;
556 }
557 }
558
559
560
561
562
563 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
564 ci->id_event = true;
565
566 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
567 ci_otg_queue_work(ci);
568 return IRQ_HANDLED;
569 }
570
571
572
573
574
575 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
576 ci->b_sess_valid_event = true;
577
578 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
579 ci_otg_queue_work(ci);
580 return IRQ_HANDLED;
581 }
582
583
584 if (ci->role != CI_ROLE_END)
585 ret = ci_role(ci)->irq(ci);
586
587 return ret;
588}
589
590static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
591 void *ptr)
592{
593 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
594 struct ci_hdrc *ci = cbl->ci;
595
596 cbl->connected = event;
597 cbl->changed = true;
598
599 ci_irq(ci->irq, ci);
600 return NOTIFY_DONE;
601}
602
603static int ci_get_platdata(struct device *dev,
604 struct ci_hdrc_platform_data *platdata)
605{
606 struct extcon_dev *ext_vbus, *ext_id;
607 struct ci_hdrc_cable *cable;
608 int ret;
609
610 if (!platdata->phy_mode)
611 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
612
613 if (!platdata->dr_mode)
614 platdata->dr_mode = usb_get_dr_mode(dev);
615
616 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
617 platdata->dr_mode = USB_DR_MODE_OTG;
618
619 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
620
621 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
622 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
623 return -EPROBE_DEFER;
624 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
625
626 platdata->reg_vbus = NULL;
627 } else if (IS_ERR(platdata->reg_vbus)) {
628 dev_err(dev, "Getting regulator error: %ld\n",
629 PTR_ERR(platdata->reg_vbus));
630 return PTR_ERR(platdata->reg_vbus);
631 }
632
633 if (!platdata->tpl_support)
634 platdata->tpl_support =
635 of_usb_host_tpl_support(dev->of_node);
636 }
637
638 if (platdata->dr_mode == USB_DR_MODE_OTG) {
639
640 platdata->ci_otg_caps.otg_rev = 0x0200;
641 platdata->ci_otg_caps.hnp_support = true;
642 platdata->ci_otg_caps.srp_support = true;
643
644
645 ret = of_usb_update_otg_caps(dev->of_node,
646 &platdata->ci_otg_caps);
647 if (ret)
648 return ret;
649 }
650
651 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
652 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
653
654 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
655 &platdata->phy_clkgate_delay_us);
656
657 platdata->itc_setting = 1;
658
659 of_property_read_u32(dev->of_node, "itc-setting",
660 &platdata->itc_setting);
661
662 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
663 &platdata->ahb_burst_config);
664 if (!ret) {
665 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
666 } else if (ret != -EINVAL) {
667 dev_err(dev, "failed to get ahb-burst-config\n");
668 return ret;
669 }
670
671 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
672 &platdata->tx_burst_size);
673 if (!ret) {
674 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
675 } else if (ret != -EINVAL) {
676 dev_err(dev, "failed to get tx-burst-size-dword\n");
677 return ret;
678 }
679
680 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
681 &platdata->rx_burst_size);
682 if (!ret) {
683 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
684 } else if (ret != -EINVAL) {
685 dev_err(dev, "failed to get rx-burst-size-dword\n");
686 return ret;
687 }
688
689 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
690 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
691
692 ext_id = ERR_PTR(-ENODEV);
693 ext_vbus = ERR_PTR(-ENODEV);
694 if (of_property_read_bool(dev->of_node, "extcon")) {
695
696 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
697 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
698 return PTR_ERR(ext_vbus);
699
700 ext_id = extcon_get_edev_by_phandle(dev, 1);
701 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
702 return PTR_ERR(ext_id);
703 }
704
705 cable = &platdata->vbus_extcon;
706 cable->nb.notifier_call = ci_cable_notifier;
707 cable->edev = ext_vbus;
708
709 if (!IS_ERR(ext_vbus)) {
710 ret = extcon_get_state(cable->edev, EXTCON_USB);
711 if (ret)
712 cable->connected = true;
713 else
714 cable->connected = false;
715 }
716
717 cable = &platdata->id_extcon;
718 cable->nb.notifier_call = ci_cable_notifier;
719 cable->edev = ext_id;
720
721 if (!IS_ERR(ext_id)) {
722 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
723 if (ret)
724 cable->connected = true;
725 else
726 cable->connected = false;
727 }
728
729 platdata->pctl = devm_pinctrl_get(dev);
730 if (!IS_ERR(platdata->pctl)) {
731 struct pinctrl_state *p;
732
733 p = pinctrl_lookup_state(platdata->pctl, "default");
734 if (!IS_ERR(p))
735 platdata->pins_default = p;
736
737 p = pinctrl_lookup_state(platdata->pctl, "host");
738 if (!IS_ERR(p))
739 platdata->pins_host = p;
740
741 p = pinctrl_lookup_state(platdata->pctl, "device");
742 if (!IS_ERR(p))
743 platdata->pins_device = p;
744 }
745
746 return 0;
747}
748
749static int ci_extcon_register(struct ci_hdrc *ci)
750{
751 struct ci_hdrc_cable *id, *vbus;
752 int ret;
753
754 id = &ci->platdata->id_extcon;
755 id->ci = ci;
756 if (!IS_ERR_OR_NULL(id->edev)) {
757 ret = devm_extcon_register_notifier(ci->dev, id->edev,
758 EXTCON_USB_HOST, &id->nb);
759 if (ret < 0) {
760 dev_err(ci->dev, "register ID failed\n");
761 return ret;
762 }
763 }
764
765 vbus = &ci->platdata->vbus_extcon;
766 vbus->ci = ci;
767 if (!IS_ERR_OR_NULL(vbus->edev)) {
768 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
769 EXTCON_USB, &vbus->nb);
770 if (ret < 0) {
771 dev_err(ci->dev, "register VBUS failed\n");
772 return ret;
773 }
774 }
775
776 return 0;
777}
778
779static DEFINE_IDA(ci_ida);
780
781struct platform_device *ci_hdrc_add_device(struct device *dev,
782 struct resource *res, int nres,
783 struct ci_hdrc_platform_data *platdata)
784{
785 struct platform_device *pdev;
786 int id, ret;
787
788 ret = ci_get_platdata(dev, platdata);
789 if (ret)
790 return ERR_PTR(ret);
791
792 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
793 if (id < 0)
794 return ERR_PTR(id);
795
796 pdev = platform_device_alloc("ci_hdrc", id);
797 if (!pdev) {
798 ret = -ENOMEM;
799 goto put_id;
800 }
801
802 pdev->dev.parent = dev;
803
804 ret = platform_device_add_resources(pdev, res, nres);
805 if (ret)
806 goto err;
807
808 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
809 if (ret)
810 goto err;
811
812 ret = platform_device_add(pdev);
813 if (ret)
814 goto err;
815
816 return pdev;
817
818err:
819 platform_device_put(pdev);
820put_id:
821 ida_simple_remove(&ci_ida, id);
822 return ERR_PTR(ret);
823}
824EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
825
826void ci_hdrc_remove_device(struct platform_device *pdev)
827{
828 int id = pdev->id;
829 platform_device_unregister(pdev);
830 ida_simple_remove(&ci_ida, id);
831}
832EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
833
834static inline void ci_role_destroy(struct ci_hdrc *ci)
835{
836 ci_hdrc_gadget_destroy(ci);
837 ci_hdrc_host_destroy(ci);
838 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
839 ci_hdrc_otg_destroy(ci);
840}
841
842static void ci_get_otg_capable(struct ci_hdrc *ci)
843{
844 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
845 ci->is_otg = false;
846 else
847 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
848 DCCPARAMS_DC | DCCPARAMS_HC)
849 == (DCCPARAMS_DC | DCCPARAMS_HC));
850 if (ci->is_otg) {
851 dev_dbg(ci->dev, "It is OTG capable controller\n");
852
853 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
854 OTGSC_INT_STATUS_BITS);
855 }
856}
857
858static ssize_t role_show(struct device *dev, struct device_attribute *attr,
859 char *buf)
860{
861 struct ci_hdrc *ci = dev_get_drvdata(dev);
862
863 if (ci->role != CI_ROLE_END)
864 return sprintf(buf, "%s\n", ci_role(ci)->name);
865
866 return 0;
867}
868
869static ssize_t role_store(struct device *dev,
870 struct device_attribute *attr, const char *buf, size_t n)
871{
872 struct ci_hdrc *ci = dev_get_drvdata(dev);
873 enum ci_role role;
874 int ret;
875
876 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
877 dev_warn(dev, "Current configuration is not dual-role, quit\n");
878 return -EPERM;
879 }
880
881 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
882 if (!strncmp(buf, ci->roles[role]->name,
883 strlen(ci->roles[role]->name)))
884 break;
885
886 if (role == CI_ROLE_END || role == ci->role)
887 return -EINVAL;
888
889 pm_runtime_get_sync(dev);
890 disable_irq(ci->irq);
891 ci_role_stop(ci);
892 ret = ci_role_start(ci, role);
893 if (!ret && ci->role == CI_ROLE_GADGET)
894 ci_handle_vbus_change(ci);
895 enable_irq(ci->irq);
896 pm_runtime_put_sync(dev);
897
898 return (ret == 0) ? n : ret;
899}
900static DEVICE_ATTR_RW(role);
901
902static struct attribute *ci_attrs[] = {
903 &dev_attr_role.attr,
904 NULL,
905};
906
907static const struct attribute_group ci_attr_group = {
908 .attrs = ci_attrs,
909};
910
911static int ci_hdrc_probe(struct platform_device *pdev)
912{
913 struct device *dev = &pdev->dev;
914 struct ci_hdrc *ci;
915 struct resource *res;
916 void __iomem *base;
917 int ret;
918 enum usb_dr_mode dr_mode;
919
920 if (!dev_get_platdata(dev)) {
921 dev_err(dev, "platform data missing\n");
922 return -ENODEV;
923 }
924
925 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
926 base = devm_ioremap_resource(dev, res);
927 if (IS_ERR(base))
928 return PTR_ERR(base);
929
930 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
931 if (!ci)
932 return -ENOMEM;
933
934 spin_lock_init(&ci->lock);
935 ci->dev = dev;
936 ci->platdata = dev_get_platdata(dev);
937 ci->imx28_write_fix = !!(ci->platdata->flags &
938 CI_HDRC_IMX28_WRITE_FIX);
939 ci->supports_runtime_pm = !!(ci->platdata->flags &
940 CI_HDRC_SUPPORTS_RUNTIME_PM);
941 platform_set_drvdata(pdev, ci);
942
943 ret = hw_device_init(ci, base);
944 if (ret < 0) {
945 dev_err(dev, "can't initialize hardware\n");
946 return -ENODEV;
947 }
948
949 ret = ci_ulpi_init(ci);
950 if (ret)
951 return ret;
952
953 if (ci->platdata->phy) {
954 ci->phy = ci->platdata->phy;
955 } else if (ci->platdata->usb_phy) {
956 ci->usb_phy = ci->platdata->usb_phy;
957 } else {
958
959 ci->phy = devm_phy_get(dev->parent, "usb-phy");
960
961 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
962 ret = -EPROBE_DEFER;
963 goto ulpi_exit;
964 } else if (IS_ERR(ci->phy)) {
965 ci->phy = NULL;
966 }
967
968
969 if (!ci->phy) {
970 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
971 "phys", 0);
972
973 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
974 ret = -EPROBE_DEFER;
975 goto ulpi_exit;
976 } else if (IS_ERR(ci->usb_phy)) {
977 ci->usb_phy = NULL;
978 }
979 }
980
981
982 if (!ci->phy && !ci->usb_phy) {
983 ci->usb_phy = devm_usb_get_phy(dev->parent,
984 USB_PHY_TYPE_USB2);
985
986 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
987 ret = -EPROBE_DEFER;
988 goto ulpi_exit;
989 } else if (IS_ERR(ci->usb_phy)) {
990 ci->usb_phy = NULL;
991 }
992 }
993
994
995 if (!ci->phy && !ci->usb_phy) {
996 ret = -ENXIO;
997 goto ulpi_exit;
998 }
999 }
1000
1001 ret = ci_usb_phy_init(ci);
1002 if (ret) {
1003 dev_err(dev, "unable to init phy: %d\n", ret);
1004 return ret;
1005 }
1006
1007 ci->hw_bank.phys = res->start;
1008
1009 ci->irq = platform_get_irq(pdev, 0);
1010 if (ci->irq < 0) {
1011 dev_err(dev, "missing IRQ\n");
1012 ret = ci->irq;
1013 goto deinit_phy;
1014 }
1015
1016 ci_get_otg_capable(ci);
1017
1018 dr_mode = ci->platdata->dr_mode;
1019
1020 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1021 ret = ci_hdrc_host_init(ci);
1022 if (ret) {
1023 if (ret == -ENXIO)
1024 dev_info(dev, "doesn't support host\n");
1025 else
1026 goto deinit_phy;
1027 }
1028 }
1029
1030 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1031 ret = ci_hdrc_gadget_init(ci);
1032 if (ret) {
1033 if (ret == -ENXIO)
1034 dev_info(dev, "doesn't support gadget\n");
1035 else
1036 goto deinit_host;
1037 }
1038 }
1039
1040 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1041 dev_err(dev, "no supported roles\n");
1042 ret = -ENODEV;
1043 goto deinit_gadget;
1044 }
1045
1046 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1047 ret = ci_hdrc_otg_init(ci);
1048 if (ret) {
1049 dev_err(dev, "init otg fails, ret = %d\n", ret);
1050 goto deinit_gadget;
1051 }
1052 }
1053
1054 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1055 if (ci->is_otg) {
1056 ci->role = ci_otg_role(ci);
1057
1058 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1059 } else {
1060
1061
1062
1063
1064
1065 ci->role = CI_ROLE_GADGET;
1066 }
1067 } else {
1068 ci->role = ci->roles[CI_ROLE_HOST]
1069 ? CI_ROLE_HOST
1070 : CI_ROLE_GADGET;
1071 }
1072
1073 if (!ci_otg_is_fsm_mode(ci)) {
1074
1075 if (ci->role == CI_ROLE_GADGET)
1076 ci_handle_vbus_change(ci);
1077
1078 ret = ci_role_start(ci, ci->role);
1079 if (ret) {
1080 dev_err(dev, "can't start %s role\n",
1081 ci_role(ci)->name);
1082 goto stop;
1083 }
1084 }
1085
1086 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1087 ci->platdata->name, ci);
1088 if (ret)
1089 goto stop;
1090
1091 ret = ci_extcon_register(ci);
1092 if (ret)
1093 goto stop;
1094
1095 if (ci->supports_runtime_pm) {
1096 pm_runtime_set_active(&pdev->dev);
1097 pm_runtime_enable(&pdev->dev);
1098 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1099 pm_runtime_mark_last_busy(ci->dev);
1100 pm_runtime_use_autosuspend(&pdev->dev);
1101 }
1102
1103 if (ci_otg_is_fsm_mode(ci))
1104 ci_hdrc_otg_fsm_start(ci);
1105
1106 device_set_wakeup_capable(&pdev->dev, true);
1107 dbg_create_files(ci);
1108
1109 ret = sysfs_create_group(&dev->kobj, &ci_attr_group);
1110 if (ret)
1111 goto remove_debug;
1112
1113 return 0;
1114
1115remove_debug:
1116 dbg_remove_files(ci);
1117stop:
1118 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1119 ci_hdrc_otg_destroy(ci);
1120deinit_gadget:
1121 ci_hdrc_gadget_destroy(ci);
1122deinit_host:
1123 ci_hdrc_host_destroy(ci);
1124deinit_phy:
1125 ci_usb_phy_exit(ci);
1126ulpi_exit:
1127 ci_ulpi_exit(ci);
1128
1129 return ret;
1130}
1131
1132static int ci_hdrc_remove(struct platform_device *pdev)
1133{
1134 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1135
1136 if (ci->supports_runtime_pm) {
1137 pm_runtime_get_sync(&pdev->dev);
1138 pm_runtime_disable(&pdev->dev);
1139 pm_runtime_put_noidle(&pdev->dev);
1140 }
1141
1142 dbg_remove_files(ci);
1143 sysfs_remove_group(&ci->dev->kobj, &ci_attr_group);
1144 ci_role_destroy(ci);
1145 ci_hdrc_enter_lpm(ci, true);
1146 ci_usb_phy_exit(ci);
1147 ci_ulpi_exit(ci);
1148
1149 return 0;
1150}
1151
1152#ifdef CONFIG_PM
1153
1154static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1155{
1156 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1157 !hw_read_otgsc(ci, OTGSC_ID)) {
1158 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1159 PORTSC_PP);
1160 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1161 PORTSC_WKCN);
1162 }
1163}
1164
1165
1166static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1167{
1168 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1169 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1170 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1171 ci->fsm.a_srp_det = 1;
1172 ci->fsm.a_bus_drop = 0;
1173 } else {
1174 ci->fsm.id = 1;
1175 }
1176 ci_otg_queue_work(ci);
1177 }
1178}
1179
1180static void ci_controller_suspend(struct ci_hdrc *ci)
1181{
1182 disable_irq(ci->irq);
1183 ci_hdrc_enter_lpm(ci, true);
1184 if (ci->platdata->phy_clkgate_delay_us)
1185 usleep_range(ci->platdata->phy_clkgate_delay_us,
1186 ci->platdata->phy_clkgate_delay_us + 50);
1187 usb_phy_set_suspend(ci->usb_phy, 1);
1188 ci->in_lpm = true;
1189 enable_irq(ci->irq);
1190}
1191
1192static int ci_controller_resume(struct device *dev)
1193{
1194 struct ci_hdrc *ci = dev_get_drvdata(dev);
1195 int ret;
1196
1197 dev_dbg(dev, "at %s\n", __func__);
1198
1199 if (!ci->in_lpm) {
1200 WARN_ON(1);
1201 return 0;
1202 }
1203
1204 ci_hdrc_enter_lpm(ci, false);
1205
1206 ret = ci_ulpi_resume(ci);
1207 if (ret)
1208 return ret;
1209
1210 if (ci->usb_phy) {
1211 usb_phy_set_suspend(ci->usb_phy, 0);
1212 usb_phy_set_wakeup(ci->usb_phy, false);
1213 hw_wait_phy_stable();
1214 }
1215
1216 ci->in_lpm = false;
1217 if (ci->wakeup_int) {
1218 ci->wakeup_int = false;
1219 pm_runtime_mark_last_busy(ci->dev);
1220 pm_runtime_put_autosuspend(ci->dev);
1221 enable_irq(ci->irq);
1222 if (ci_otg_is_fsm_mode(ci))
1223 ci_otg_fsm_wakeup_by_srp(ci);
1224 }
1225
1226 return 0;
1227}
1228
1229#ifdef CONFIG_PM_SLEEP
1230static int ci_suspend(struct device *dev)
1231{
1232 struct ci_hdrc *ci = dev_get_drvdata(dev);
1233
1234 if (ci->wq)
1235 flush_workqueue(ci->wq);
1236
1237
1238
1239
1240
1241
1242 if (ci->in_lpm)
1243 pm_runtime_resume(dev);
1244
1245 if (ci->in_lpm) {
1246 WARN_ON(1);
1247 return 0;
1248 }
1249
1250 if (device_may_wakeup(dev)) {
1251 if (ci_otg_is_fsm_mode(ci))
1252 ci_otg_fsm_suspend_for_srp(ci);
1253
1254 usb_phy_set_wakeup(ci->usb_phy, true);
1255 enable_irq_wake(ci->irq);
1256 }
1257
1258 ci_controller_suspend(ci);
1259
1260 return 0;
1261}
1262
1263static int ci_resume(struct device *dev)
1264{
1265 struct ci_hdrc *ci = dev_get_drvdata(dev);
1266 int ret;
1267
1268 if (device_may_wakeup(dev))
1269 disable_irq_wake(ci->irq);
1270
1271 ret = ci_controller_resume(dev);
1272 if (ret)
1273 return ret;
1274
1275 if (ci->supports_runtime_pm) {
1276 pm_runtime_disable(dev);
1277 pm_runtime_set_active(dev);
1278 pm_runtime_enable(dev);
1279 }
1280
1281 return ret;
1282}
1283#endif
1284
1285static int ci_runtime_suspend(struct device *dev)
1286{
1287 struct ci_hdrc *ci = dev_get_drvdata(dev);
1288
1289 dev_dbg(dev, "at %s\n", __func__);
1290
1291 if (ci->in_lpm) {
1292 WARN_ON(1);
1293 return 0;
1294 }
1295
1296 if (ci_otg_is_fsm_mode(ci))
1297 ci_otg_fsm_suspend_for_srp(ci);
1298
1299 usb_phy_set_wakeup(ci->usb_phy, true);
1300 ci_controller_suspend(ci);
1301
1302 return 0;
1303}
1304
1305static int ci_runtime_resume(struct device *dev)
1306{
1307 return ci_controller_resume(dev);
1308}
1309
1310#endif
1311static const struct dev_pm_ops ci_pm_ops = {
1312 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1313 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1314};
1315
1316static struct platform_driver ci_hdrc_driver = {
1317 .probe = ci_hdrc_probe,
1318 .remove = ci_hdrc_remove,
1319 .driver = {
1320 .name = "ci_hdrc",
1321 .pm = &ci_pm_ops,
1322 },
1323};
1324
1325static int __init ci_hdrc_platform_register(void)
1326{
1327 ci_hdrc_host_driver_init();
1328 return platform_driver_register(&ci_hdrc_driver);
1329}
1330module_init(ci_hdrc_platform_register);
1331
1332static void __exit ci_hdrc_platform_unregister(void)
1333{
1334 platform_driver_unregister(&ci_hdrc_driver);
1335}
1336module_exit(ci_hdrc_platform_unregister);
1337
1338MODULE_ALIAS("platform:ci_hdrc");
1339MODULE_LICENSE("GPL v2");
1340MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1341MODULE_DESCRIPTION("ChipIdea HDRC Driver");
1342
