LXR linux/drivers/usb/host/ehci-pci.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   4 *
   5 * Copyright (c) 2000-2004 by David Brownell
   6 */
   7
   8#include <linux/kernel.h>
   9#include <linux/module.h>
  10#include <linux/pci.h>
  11#include <linux/usb.h>
  12#include <linux/usb/hcd.h>
  13
  14#include "ehci.h"
  15#include "pci-quirks.h"
  16
  17#define DRIVER_DESC "EHCI PCI platform driver"
  18
  19static const char hcd_name[] = "ehci-pci";
  20
  21/* defined here to avoid adding to pci_ids.h for single instance use */
  22#define PCI_DEVICE_ID_INTEL_CE4100_USB  0x2e70
  23
  24/*-------------------------------------------------------------------------*/
  25#define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC             0x0939
  26static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
  27{
  28        return pdev->vendor == PCI_VENDOR_ID_INTEL &&
  29                pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
  30}
  31
  32/*
  33 * This is the list of PCI IDs for the devices that have EHCI USB class and
  34 * specific drivers for that. One of the example is a ChipIdea device installed
  35 * on some Intel MID platforms.
  36 */
  37static const struct pci_device_id bypass_pci_id_table[] = {
  38        /* ChipIdea on Intel MID platform */
  39        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
  40        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
  41        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
  42        {}
  43};
  44
  45static inline bool is_bypassed_id(struct pci_dev *pdev)
  46{
  47        return !!pci_match_id(bypass_pci_id_table, pdev);
  48}
  49
  50/*
  51 * 0x84 is the offset of in/out threshold register,
  52 * and it is the same offset as the register of 'hostpc'.
  53 */
  54#define intel_quark_x1000_insnreg01     hostpc
  55
  56/* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
  57#define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD    0x007f007f
  58
  59/* called after powerup, by probe or system-pm "wakeup" */
  60static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  61{
  62        int                     retval;
  63
  64        /* we expect static quirk code to handle the "extended capabilities"
  65         * (currently just BIOS handoff) allowed starting with EHCI 0.96
  66         */
  67
  68        /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  69        retval = pci_set_mwi(pdev);
  70        if (!retval)
  71                ehci_dbg(ehci, "MWI active\n");
  72
  73        /* Reset the threshold limit */
  74        if (is_intel_quark_x1000(pdev)) {
  75                /*
  76                 * For the Intel QUARK X1000, raise the I/O threshold to the
  77                 * maximum usable value in order to improve performance.
  78                 */
  79                ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
  80                        ehci->regs->intel_quark_x1000_insnreg01);
  81        }
  82
  83        return 0;
  84}
  85
  86/* called during probe() after chip reset completes */
  87static int ehci_pci_setup(struct usb_hcd *hcd)
  88{
  89        struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  90        struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  91        u32                     temp;
  92        int                     retval;
  93
  94        ehci->caps = hcd->regs;
  95
  96        /*
  97         * ehci_init() causes memory for DMA transfers to be
  98         * allocated.  Thus, any vendor-specific workarounds based on
  99         * limiting the type of memory used for DMA transfers must
 100         * happen before ehci_setup() is called.
 101         *
 102         * Most other workarounds can be done either before or after
 103         * init and reset; they are located here too.
 104         */
 105        switch (pdev->vendor) {
 106        case PCI_VENDOR_ID_TOSHIBA_2:
 107                /* celleb's companion chip */
 108                if (pdev->device == 0x01b5) {
 109#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 110                        ehci->big_endian_mmio = 1;
 111#else
 112                        ehci_warn(ehci,
 113                                  "unsupported big endian Toshiba quirk\n");
 114#endif
 115                }
 116                break;
 117        case PCI_VENDOR_ID_NVIDIA:
 118                /* NVidia reports that certain chips don't handle
 119                 * QH, ITD, or SITD addresses above 2GB.  (But TD,
 120                 * data buffer, and periodic schedule are normal.)
 121                 */
 122                switch (pdev->device) {
 123                case 0x003c:    /* MCP04 */
 124                case 0x005b:    /* CK804 */
 125                case 0x00d8:    /* CK8 */
 126                case 0x00e8:    /* CK8S */
 127                        if (pci_set_consistent_dma_mask(pdev,
 128                                                DMA_BIT_MASK(31)) < 0)
 129                                ehci_warn(ehci, "can't enable NVidia "
 130                                        "workaround for >2GB RAM\n");
 131                        break;
 132
 133                /* Some NForce2 chips have problems with selective suspend;
 134                 * fixed in newer silicon.
 135                 */
 136                case 0x0068:
 137                        if (pdev->revision < 0xa4)
 138                                ehci->no_selective_suspend = 1;
 139                        break;
 140                }
 141                break;
 142        case PCI_VENDOR_ID_INTEL:
 143                if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
 144                        hcd->has_tt = 1;
 145                break;
 146        case PCI_VENDOR_ID_TDI:
 147                if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
 148                        hcd->has_tt = 1;
 149                break;
 150        case PCI_VENDOR_ID_AMD:
 151                /* AMD PLL quirk */
 152                if (usb_amd_quirk_pll_check())
 153                        ehci->amd_pll_fix = 1;
 154                /* AMD8111 EHCI doesn't work, according to AMD errata */
 155                if (pdev->device == 0x7463) {
 156                        ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 157                        retval = -EIO;
 158                        goto done;
 159                }
 160
 161                /*
 162                 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 163                 * read/write memory space which does not belong to it when
 164                 * there is NULL pointer with T-bit set to 1 in the frame list
 165                 * table. To avoid the issue, the frame list link pointer
 166                 * should always contain a valid pointer to a inactive qh.
 167                 */
 168                if (pdev->device == 0x7808) {
 169                        ehci->use_dummy_qh = 1;
 170                        ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
 171                }
 172                break;
 173        case PCI_VENDOR_ID_VIA:
 174                if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 175                        u8 tmp;
 176
 177                        /* The VT6212 defaults to a 1 usec EHCI sleep time which
 178                         * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 179                         * that sleep time use the conventional 10 usec.
 180                         */
 181                        pci_read_config_byte(pdev, 0x4b, &tmp);
 182                        if (tmp & 0x20)
 183                                break;
 184                        pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 185                }
 186                break;
 187        case PCI_VENDOR_ID_ATI:
 188                /* AMD PLL quirk */
 189                if (usb_amd_quirk_pll_check())
 190                        ehci->amd_pll_fix = 1;
 191
 192                /*
 193                 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 194                 * read/write memory space which does not belong to it when
 195                 * there is NULL pointer with T-bit set to 1 in the frame list
 196                 * table. To avoid the issue, the frame list link pointer
 197                 * should always contain a valid pointer to a inactive qh.
 198                 */
 199                if (pdev->device == 0x4396) {
 200                        ehci->use_dummy_qh = 1;
 201                        ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
 202                }
 203                /* SB600 and old version of SB700 have a bug in EHCI controller,
 204                 * which causes usb devices lose response in some cases.
 205                 */
 206                if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
 207                                usb_amd_hang_symptom_quirk()) {
 208                        u8 tmp;
 209                        ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
 210                        pci_read_config_byte(pdev, 0x53, &tmp);
 211                        pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 212                }
 213                break;
 214        case PCI_VENDOR_ID_NETMOS:
 215                /* MosChip frame-index-register bug */
 216                ehci_info(ehci, "applying MosChip frame-index workaround\n");
 217                ehci->frame_index_bug = 1;
 218                break;
 219        }
 220
 221        /* optional debug port, normally in the first BAR */
 222        temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
 223        if (temp) {
 224                pci_read_config_dword(pdev, temp, &temp);
 225                temp >>= 16;
 226                if (((temp >> 13) & 7) == 1) {
 227                        u32 hcs_params = ehci_readl(ehci,
 228                                                    &ehci->caps->hcs_params);
 229
 230                        temp &= 0x1fff;
 231                        ehci->debug = hcd->regs + temp;
 232                        temp = ehci_readl(ehci, &ehci->debug->control);
 233                        ehci_info(ehci, "debug port %d%s\n",
 234                                  HCS_DEBUG_PORT(hcs_params),
 235                                  (temp & DBGP_ENABLED) ? " IN USE" : "");
 236                        if (!(temp & DBGP_ENABLED))
 237                                ehci->debug = NULL;
 238                }
 239        }
 240
 241        retval = ehci_setup(hcd);
 242        if (retval)
 243                return retval;
 244
 245        /* These workarounds need to be applied after ehci_setup() */
 246        switch (pdev->vendor) {
 247        case PCI_VENDOR_ID_NEC:
 248        case PCI_VENDOR_ID_INTEL:
 249        case PCI_VENDOR_ID_AMD:
 250                ehci->need_io_watchdog = 0;
 251                break;
 252        case PCI_VENDOR_ID_NVIDIA:
 253                switch (pdev->device) {
 254                /* MCP89 chips on the MacBookAir3,1 give EPROTO when
 255                 * fetching device descriptors unless LPM is disabled.
 256                 * There are also intermittent problems enumerating
 257                 * devices with PPCD enabled.
 258                 */
 259                case 0x0d9d:
 260                        ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
 261                        ehci->has_ppcd = 0;
 262                        ehci->command &= ~CMD_PPCEE;
 263                        break;
 264                }
 265                break;
 266        }
 267
 268        /* at least the Genesys GL880S needs fixup here */
 269        temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 270        temp &= 0x0f;
 271        if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 272                ehci_dbg(ehci, "bogus port configuration: "
 273                        "cc=%d x pcc=%d < ports=%d\n",
 274                        HCS_N_CC(ehci->hcs_params),
 275                        HCS_N_PCC(ehci->hcs_params),
 276                        HCS_N_PORTS(ehci->hcs_params));
 277
 278                switch (pdev->vendor) {
 279                case 0x17a0:            /* GENESYS */
 280                        /* GL880S: should be PORTS=2 */
 281                        temp |= (ehci->hcs_params & ~0xf);
 282                        ehci->hcs_params = temp;
 283                        break;
 284                case PCI_VENDOR_ID_NVIDIA:
 285                        /* NF4: should be PCC=10 */
 286                        break;
 287                }
 288        }
 289
 290        /* Serial Bus Release Number is at PCI 0x60 offset */
 291        if (pdev->vendor == PCI_VENDOR_ID_STMICRO
 292            && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
 293                ;       /* ConneXT has no sbrn register */
 294        else
 295                pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 296
 297        /* Keep this around for a while just in case some EHCI
 298         * implementation uses legacy PCI PM support.  This test
 299         * can be removed on 17 Dec 2009 if the dev_warn() hasn't
 300         * been triggered by then.
 301         */
 302        if (!device_can_wakeup(&pdev->dev)) {
 303                u16     port_wake;
 304
 305                pci_read_config_word(pdev, 0x62, &port_wake);
 306                if (port_wake & 0x0001) {
 307                        dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
 308                        device_set_wakeup_capable(&pdev->dev, 1);
 309                }
 310        }
 311
 312#ifdef  CONFIG_PM
 313        if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 314                ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 315#endif
 316
 317        retval = ehci_pci_reinit(ehci, pdev);
 318done:
 319        return retval;
 320}
 321
 322/*-------------------------------------------------------------------------*/
 323
 324#ifdef  CONFIG_PM
 325
 326/* suspend/resume, section 4.3 */
 327
 328/* These routines rely on the PCI bus glue
 329 * to handle powerdown and wakeup, and currently also on
 330 * transceivers that don't need any software attention to set up
 331 * the right sort of wakeup.
 332 * Also they depend on separate root hub suspend/resume.
 333 */
 334
 335static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 336{
 337        struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 338        struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 339
 340        if (ehci_resume(hcd, hibernated) != 0)
 341                (void) ehci_pci_reinit(ehci, pdev);
 342        return 0;
 343}
 344
 345#else
 346
 347#define ehci_suspend            NULL
 348#define ehci_pci_resume         NULL
 349#endif  /* CONFIG_PM */
 350
 351static struct hc_driver __read_mostly ehci_pci_hc_driver;
 352
 353static const struct ehci_driver_overrides pci_overrides __initconst = {
 354        .reset =                ehci_pci_setup,
 355};
 356
 357/*-------------------------------------------------------------------------*/
 358
 359static int ehci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 360{
 361        if (is_bypassed_id(pdev))
 362                return -ENODEV;
 363        return usb_hcd_pci_probe(pdev, id);
 364}
 365
 366static void ehci_pci_remove(struct pci_dev *pdev)
 367{
 368        pci_clear_mwi(pdev);
 369        usb_hcd_pci_remove(pdev);       
 370}
 371
 372/* PCI driver selection metadata; PCI hotplugging uses this */
 373static const struct pci_device_id pci_ids [] = { {
 374        /* handle any USB 2.0 EHCI controller */
 375        PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 376        .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 377        }, {
 378        PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
 379        .driver_data = (unsigned long) &ehci_pci_hc_driver,
 380        },
 381        { /* end: all zeroes */ }
 382};
 383MODULE_DEVICE_TABLE(pci, pci_ids);
 384
 385/* pci driver glue; this is a "new style" PCI driver module */
 386static struct pci_driver ehci_pci_driver = {
 387        .name =         (char *) hcd_name,
 388        .id_table =     pci_ids,
 389
 390        .probe =        ehci_pci_probe,
 391        .remove =       ehci_pci_remove,
 392        .shutdown =     usb_hcd_pci_shutdown,
 393
 394#ifdef CONFIG_PM
 395        .driver =       {
 396                .pm =   &usb_hcd_pci_pm_ops
 397        },
 398#endif
 399};
 400
 401static int __init ehci_pci_init(void)
 402{
 403        if (usb_disabled())
 404                return -ENODEV;
 405
 406        pr_info("%s: " DRIVER_DESC "\n", hcd_name);
 407
 408        ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
 409
 410        /* Entries for the PCI suspend/resume callbacks are special */
 411        ehci_pci_hc_driver.pci_suspend = ehci_suspend;
 412        ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
 413
 414        return pci_register_driver(&ehci_pci_driver);
 415}
 416module_init(ehci_pci_init);
 417
 418static void __exit ehci_pci_cleanup(void)
 419{
 420        pci_unregister_driver(&ehci_pci_driver);
 421}
 422module_exit(ehci_pci_cleanup);
 423
 424MODULE_DESCRIPTION(DRIVER_DESC);
 425MODULE_AUTHOR("David Brownell");
 426MODULE_AUTHOR("Alan Stern");
 427MODULE_LICENSE("GPL");
 428