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11
12#include <linux/slab.h>
13#include <asm/unaligned.h>
14
15#include "xhci.h"
16#include "xhci-trace.h"
17
18#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
19#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
20 PORT_RC | PORT_PLC | PORT_PE)
21
22
23
24
25static u8 usb_bos_descriptor [] = {
26 USB_DT_BOS_SIZE,
27 USB_DT_BOS,
28 0x0F, 0x00,
29 0x1,
30
31 USB_DT_USB_SS_CAP_SIZE,
32 USB_DT_DEVICE_CAPABILITY,
33 USB_SS_CAP_TYPE,
34 0x00,
35 USB_5GBPS_OPERATION, 0x00,
36 0x03,
37
38 0x00,
39 0x00, 0x00,
40
41 0x1c,
42 USB_DT_DEVICE_CAPABILITY,
43 USB_SSP_CAP_TYPE,
44 0x00,
45 0x23, 0x00, 0x00, 0x00,
46 0x01, 0x00,
47 0x00, 0x00,
48
49 0x34, 0x00, 0x05, 0x00,
50 0xb4, 0x00, 0x05, 0x00,
51 0x35, 0x40, 0x0a, 0x00,
52 0xb5, 0x40, 0x0a, 0x00,
53};
54
55static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
56 u16 wLength)
57{
58 int i, ssa_count;
59 u32 temp;
60 u16 desc_size, ssp_cap_size, ssa_size = 0;
61 bool usb3_1 = false;
62
63 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
64 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
65
66
67 if (xhci->usb3_rhub.min_rev >= 0x01) {
68
69 if (xhci->usb3_rhub.psi_count) {
70
71 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
72 ssa_size = ssa_count * sizeof(u32);
73 ssp_cap_size -= 16;
74 }
75 desc_size += ssp_cap_size;
76 usb3_1 = true;
77 }
78 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
79
80 if (usb3_1) {
81
82 buf[4] += 1;
83 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
84 }
85
86 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
87 return wLength;
88
89
90 temp = readl(&xhci->cap_regs->hcc_params);
91 if (HCC_LTC(temp))
92 buf[8] |= USB_LTM_SUPPORT;
93
94
95 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
96 temp = readl(&xhci->cap_regs->hcs_params3);
97 buf[12] = HCS_U1_LATENCY(temp);
98 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
99 }
100
101
102 if (usb3_1 && xhci->usb3_rhub.psi_count) {
103 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
104 int offset;
105
106 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
107
108 if (wLength < desc_size)
109 return wLength;
110 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
111
112
113 bm_attrib = (ssa_count - 1) & 0x1f;
114 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
115 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
116
117 if (wLength < desc_size + ssa_size)
118 return wLength;
119
120
121
122
123
124
125
126 offset = desc_size;
127 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
128 psi = xhci->usb3_rhub.psi[i];
129 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
130 psi_exp = XHCI_EXT_PORT_PSIE(psi);
131 psi_mant = XHCI_EXT_PORT_PSIM(psi);
132
133
134 for (; psi_exp < 3; psi_exp++)
135 psi_mant /= 1000;
136 if (psi_mant >= 10)
137 psi |= BIT(14);
138
139 if ((psi & PLT_MASK) == PLT_SYM) {
140
141 put_unaligned_le32(psi, &buf[offset]);
142 psi |= 1 << 7;
143 offset += 4;
144 if (offset >= desc_size + ssa_size)
145 return desc_size + ssa_size;
146 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
147
148 psi ^= PLT_MASK;
149 }
150 put_unaligned_le32(psi, &buf[offset]);
151 offset += 4;
152 if (offset >= desc_size + ssa_size)
153 return desc_size + ssa_size;
154 }
155 }
156
157 return desc_size + ssa_size;
158}
159
160static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
161 struct usb_hub_descriptor *desc, int ports)
162{
163 u16 temp;
164
165 desc->bPwrOn2PwrGood = 10;
166 desc->bHubContrCurrent = 0;
167
168 desc->bNbrPorts = ports;
169 temp = 0;
170
171 if (HCC_PPC(xhci->hcc_params))
172 temp |= HUB_CHAR_INDV_PORT_LPSM;
173 else
174 temp |= HUB_CHAR_NO_LPSM;
175
176
177 temp |= HUB_CHAR_INDV_PORT_OCPM;
178
179
180 desc->wHubCharacteristics = cpu_to_le16(temp);
181}
182
183
184static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
185 struct usb_hub_descriptor *desc)
186{
187 int ports;
188 u16 temp;
189 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
190 u32 portsc;
191 unsigned int i;
192 struct xhci_hub *rhub;
193
194 rhub = &xhci->usb2_rhub;
195 ports = rhub->num_ports;
196 xhci_common_hub_descriptor(xhci, desc, ports);
197 desc->bDescriptorType = USB_DT_HUB;
198 temp = 1 + (ports / 8);
199 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
200
201
202
203
204 memset(port_removable, 0, sizeof(port_removable));
205 for (i = 0; i < ports; i++) {
206 portsc = readl(rhub->ports[i]->addr);
207
208
209
210 if (portsc & PORT_DEV_REMOVE)
211
212
213
214 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
215 }
216
217
218
219
220
221
222
223
224
225
226
227 memset(desc->u.hs.DeviceRemovable, 0xff,
228 sizeof(desc->u.hs.DeviceRemovable));
229 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
230 sizeof(desc->u.hs.PortPwrCtrlMask));
231
232 for (i = 0; i < (ports + 1 + 7) / 8; i++)
233 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
234 sizeof(__u8));
235}
236
237
238static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
239 struct usb_hub_descriptor *desc)
240{
241 int ports;
242 u16 port_removable;
243 u32 portsc;
244 unsigned int i;
245 struct xhci_hub *rhub;
246
247 rhub = &xhci->usb3_rhub;
248 ports = rhub->num_ports;
249 xhci_common_hub_descriptor(xhci, desc, ports);
250 desc->bDescriptorType = USB_DT_SS_HUB;
251 desc->bDescLength = USB_DT_SS_HUB_SIZE;
252
253
254
255
256 desc->u.ss.bHubHdrDecLat = 0;
257 desc->u.ss.wHubDelay = 0;
258
259 port_removable = 0;
260
261 for (i = 0; i < ports; i++) {
262 portsc = readl(rhub->ports[i]->addr);
263 if (portsc & PORT_DEV_REMOVE)
264 port_removable |= 1 << (i + 1);
265 }
266
267 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
268}
269
270static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
271 struct usb_hub_descriptor *desc)
272{
273
274 if (hcd->speed >= HCD_USB3)
275 xhci_usb3_hub_descriptor(hcd, xhci, desc);
276 else
277 xhci_usb2_hub_descriptor(hcd, xhci, desc);
278
279}
280
281static unsigned int xhci_port_speed(unsigned int port_status)
282{
283 if (DEV_LOWSPEED(port_status))
284 return USB_PORT_STAT_LOW_SPEED;
285 if (DEV_HIGHSPEED(port_status))
286 return USB_PORT_STAT_HIGH_SPEED;
287
288
289
290
291
292 return 0;
293}
294
295
296
297
298
299
300
301
302#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
303
304
305
306
307
308#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
309
310
311
312
313#define XHCI_PORT_RW1S ((1<<4))
314
315
316
317
318
319
320
321#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
322
323
324
325
326#define XHCI_PORT_RW ((1<<16))
327
328
329
330
331#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
332
333
334
335
336
337
338
339
340
341u32 xhci_port_state_to_neutral(u32 state)
342{
343
344 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
345}
346
347
348
349
350
351int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
352 u16 port)
353{
354 int slot_id;
355 int i;
356 enum usb_device_speed speed;
357
358 slot_id = 0;
359 for (i = 0; i < MAX_HC_SLOTS; i++) {
360 if (!xhci->devs[i] || !xhci->devs[i]->udev)
361 continue;
362 speed = xhci->devs[i]->udev->speed;
363 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
364 && xhci->devs[i]->fake_port == port) {
365 slot_id = i;
366 break;
367 }
368 }
369
370 return slot_id;
371}
372
373
374
375
376
377
378
379static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
380{
381 struct xhci_virt_device *virt_dev;
382 struct xhci_command *cmd;
383 unsigned long flags;
384 int ret;
385 int i;
386
387 ret = 0;
388 virt_dev = xhci->devs[slot_id];
389 if (!virt_dev)
390 return -ENODEV;
391
392 trace_xhci_stop_device(virt_dev);
393
394 cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
395 if (!cmd)
396 return -ENOMEM;
397
398 spin_lock_irqsave(&xhci->lock, flags);
399 for (i = LAST_EP_INDEX; i > 0; i--) {
400 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
401 struct xhci_ep_ctx *ep_ctx;
402 struct xhci_command *command;
403
404 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
405
406
407 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
408 continue;
409
410 command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
411 if (!command) {
412 spin_unlock_irqrestore(&xhci->lock, flags);
413 ret = -ENOMEM;
414 goto cmd_cleanup;
415 }
416
417 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
418 i, suspend);
419 if (ret) {
420 spin_unlock_irqrestore(&xhci->lock, flags);
421 xhci_free_command(xhci, command);
422 goto cmd_cleanup;
423 }
424 }
425 }
426 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
427 if (ret) {
428 spin_unlock_irqrestore(&xhci->lock, flags);
429 goto cmd_cleanup;
430 }
431
432 xhci_ring_cmd_db(xhci);
433 spin_unlock_irqrestore(&xhci->lock, flags);
434
435
436 wait_for_completion(cmd->completion);
437
438 if (cmd->status == COMP_COMMAND_ABORTED ||
439 cmd->status == COMP_COMMAND_RING_STOPPED) {
440 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
441 ret = -ETIME;
442 }
443
444cmd_cleanup:
445 xhci_free_command(xhci, cmd);
446 return ret;
447}
448
449
450
451
452void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
453{
454 int i, s;
455 struct xhci_virt_ep *ep;
456
457 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
458 ep = &xhci->devs[slot_id]->eps[i];
459
460 if (ep->ep_state & EP_HAS_STREAMS) {
461 for (s = 1; s < ep->stream_info->num_streams; s++)
462 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
463 } else if (ep->ring && ep->ring->dequeue) {
464 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
465 }
466 }
467
468 return;
469}
470
471static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
472 u16 wIndex, __le32 __iomem *addr, u32 port_status)
473{
474
475 if (hcd->speed >= HCD_USB3) {
476 xhci_dbg(xhci, "Ignoring request to disable "
477 "SuperSpeed port.\n");
478 return;
479 }
480
481 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
482 xhci_dbg(xhci,
483 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
484 return;
485 }
486
487
488 writel(port_status | PORT_PE, addr);
489 port_status = readl(addr);
490 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
491 hcd->self.busnum, wIndex + 1, port_status);
492}
493
494static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
495 u16 wIndex, __le32 __iomem *addr, u32 port_status)
496{
497 char *port_change_bit;
498 u32 status;
499
500 switch (wValue) {
501 case USB_PORT_FEAT_C_RESET:
502 status = PORT_RC;
503 port_change_bit = "reset";
504 break;
505 case USB_PORT_FEAT_C_BH_PORT_RESET:
506 status = PORT_WRC;
507 port_change_bit = "warm(BH) reset";
508 break;
509 case USB_PORT_FEAT_C_CONNECTION:
510 status = PORT_CSC;
511 port_change_bit = "connect";
512 break;
513 case USB_PORT_FEAT_C_OVER_CURRENT:
514 status = PORT_OCC;
515 port_change_bit = "over-current";
516 break;
517 case USB_PORT_FEAT_C_ENABLE:
518 status = PORT_PEC;
519 port_change_bit = "enable/disable";
520 break;
521 case USB_PORT_FEAT_C_SUSPEND:
522 status = PORT_PLC;
523 port_change_bit = "suspend/resume";
524 break;
525 case USB_PORT_FEAT_C_PORT_LINK_STATE:
526 status = PORT_PLC;
527 port_change_bit = "link state";
528 break;
529 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
530 status = PORT_CEC;
531 port_change_bit = "config error";
532 break;
533 default:
534
535 return;
536 }
537
538 writel(port_status | status, addr);
539 port_status = readl(addr);
540
541 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
542 wIndex + 1, port_change_bit, port_status);
543}
544
545struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
546{
547 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
548
549 if (hcd->speed >= HCD_USB3)
550 return &xhci->usb3_rhub;
551 return &xhci->usb2_rhub;
552}
553
554
555
556
557
558
559static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
560 u16 index, bool on, unsigned long *flags)
561{
562 struct xhci_hub *rhub;
563 struct xhci_port *port;
564 u32 temp;
565
566 rhub = xhci_get_rhub(hcd);
567 port = rhub->ports[index];
568 temp = readl(port->addr);
569
570 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
571 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
572
573 temp = xhci_port_state_to_neutral(temp);
574
575 if (on) {
576
577 writel(temp | PORT_POWER, port->addr);
578 readl(port->addr);
579 } else {
580
581 writel(temp & ~PORT_POWER, port->addr);
582 }
583
584 spin_unlock_irqrestore(&xhci->lock, *flags);
585 temp = usb_acpi_power_manageable(hcd->self.root_hub,
586 index);
587 if (temp)
588 usb_acpi_set_power_state(hcd->self.root_hub,
589 index, on);
590 spin_lock_irqsave(&xhci->lock, *flags);
591}
592
593static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
594 u16 test_mode, u16 wIndex)
595{
596 u32 temp;
597 struct xhci_port *port;
598
599
600 port = xhci->usb2_rhub.ports[wIndex];
601 temp = readl(port->addr + PORTPMSC);
602 temp |= test_mode << PORT_TEST_MODE_SHIFT;
603 writel(temp, port->addr + PORTPMSC);
604 xhci->test_mode = test_mode;
605 if (test_mode == TEST_FORCE_EN)
606 xhci_start(xhci);
607}
608
609static int xhci_enter_test_mode(struct xhci_hcd *xhci,
610 u16 test_mode, u16 wIndex, unsigned long *flags)
611{
612 int i, retval;
613
614
615 xhci_dbg(xhci, "Disable all slots\n");
616 spin_unlock_irqrestore(&xhci->lock, *flags);
617 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
618 if (!xhci->devs[i])
619 continue;
620
621 retval = xhci_disable_slot(xhci, i);
622 if (retval)
623 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
624 i, retval);
625 }
626 spin_lock_irqsave(&xhci->lock, *flags);
627
628 xhci_dbg(xhci, "Disable all port (PP = 0)\n");
629
630 for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
631 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
632
633 for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
634 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
635
636 xhci_dbg(xhci, "Stop controller\n");
637 retval = xhci_halt(xhci);
638 if (retval)
639 return retval;
640
641 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
642
643
644 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
645 test_mode, wIndex + 1);
646 xhci_port_set_test_mode(xhci, test_mode, wIndex);
647 return retval;
648}
649
650static int xhci_exit_test_mode(struct xhci_hcd *xhci)
651{
652 int retval;
653
654 if (!xhci->test_mode) {
655 xhci_err(xhci, "Not in test mode, do nothing.\n");
656 return 0;
657 }
658 if (xhci->test_mode == TEST_FORCE_EN &&
659 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
660 retval = xhci_halt(xhci);
661 if (retval)
662 return retval;
663 }
664 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
665 xhci->test_mode = 0;
666 return xhci_reset(xhci);
667}
668
669void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
670 u32 link_state)
671{
672 u32 temp;
673 u32 portsc;
674
675 portsc = readl(port->addr);
676 temp = xhci_port_state_to_neutral(portsc);
677 temp &= ~PORT_PLS_MASK;
678 temp |= PORT_LINK_STROBE | link_state;
679 writel(temp, port->addr);
680
681 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
682 port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
683 portsc, temp);
684}
685
686static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
687 struct xhci_port *port, u16 wake_mask)
688{
689 u32 temp;
690
691 temp = readl(port->addr);
692 temp = xhci_port_state_to_neutral(temp);
693
694 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
695 temp |= PORT_WKCONN_E;
696 else
697 temp &= ~PORT_WKCONN_E;
698
699 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
700 temp |= PORT_WKDISC_E;
701 else
702 temp &= ~PORT_WKDISC_E;
703
704 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
705 temp |= PORT_WKOC_E;
706 else
707 temp &= ~PORT_WKOC_E;
708
709 writel(temp, port->addr);
710}
711
712
713void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
714 u32 port_bit)
715{
716 u32 temp;
717
718 temp = readl(port->addr);
719 if (temp & port_bit) {
720 temp = xhci_port_state_to_neutral(temp);
721 temp |= port_bit;
722 writel(temp, port->addr);
723 }
724}
725
726
727static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
728 u32 *status, u32 status_reg)
729{
730 u32 pls = status_reg & PORT_PLS_MASK;
731
732
733
734
735
736 if (pls == XDEV_RESUME) {
737 *status |= USB_SS_PORT_LS_U3;
738 return;
739 }
740
741
742
743
744 if (status_reg & PORT_CAS) {
745
746
747
748
749
750
751
752 if (pls != USB_SS_PORT_LS_COMP_MOD &&
753 pls != USB_SS_PORT_LS_SS_INACTIVE) {
754 pls = USB_SS_PORT_LS_COMP_MOD;
755 }
756
757
758
759
760 pls |= USB_PORT_STAT_CONNECTION;
761 } else {
762
763
764
765
766
767
768
769
770 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
771 (pls == USB_SS_PORT_LS_COMP_MOD))
772 pls |= USB_PORT_STAT_CONNECTION;
773 }
774
775
776 *status |= pls;
777}
778
779
780
781
782
783
784
785
786static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
787 u16 wIndex)
788{
789 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
790 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
791
792 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
793 return;
794
795 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
796 xhci->port_status_u0 |= 1 << wIndex;
797 if (xhci->port_status_u0 == all_ports_seen_u0) {
798 del_timer_sync(&xhci->comp_mode_recovery_timer);
799 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
800 "All USB3 ports have entered U0 already!");
801 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
802 "Compliance Mode Recovery Timer Deleted.");
803 }
804 }
805}
806
807static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
808 u32 *status, u32 portsc,
809 unsigned long flags)
810{
811 struct xhci_bus_state *bus_state;
812 struct xhci_hcd *xhci;
813 struct usb_hcd *hcd;
814 int slot_id;
815 u32 wIndex;
816
817 hcd = port->rhub->hcd;
818 bus_state = &port->rhub->bus_state;
819 xhci = hcd_to_xhci(hcd);
820 wIndex = port->hcd_portnum;
821
822 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
823 *status = 0xffffffff;
824 return -EINVAL;
825 }
826
827 if (!bus_state->resume_done[wIndex]) {
828
829 if (test_bit(wIndex, &bus_state->resuming_ports)) {
830
831
832
833
834
835
836 } else {
837
838
839
840 unsigned long timeout = jiffies +
841 msecs_to_jiffies(USB_RESUME_TIMEOUT);
842
843 set_bit(wIndex, &bus_state->resuming_ports);
844 bus_state->resume_done[wIndex] = timeout;
845 mod_timer(&hcd->rh_timer, timeout);
846 usb_hcd_start_port_resume(&hcd->self, wIndex);
847 }
848
849 } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
850 int time_left;
851
852 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
853 hcd->self.busnum, wIndex + 1);
854
855 bus_state->resume_done[wIndex] = 0;
856 clear_bit(wIndex, &bus_state->resuming_ports);
857
858 set_bit(wIndex, &bus_state->rexit_ports);
859
860 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
861 xhci_set_link_state(xhci, port, XDEV_U0);
862
863 spin_unlock_irqrestore(&xhci->lock, flags);
864 time_left = wait_for_completion_timeout(
865 &bus_state->rexit_done[wIndex],
866 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
867 spin_lock_irqsave(&xhci->lock, flags);
868
869 if (time_left) {
870 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
871 wIndex + 1);
872 if (!slot_id) {
873 xhci_dbg(xhci, "slot_id is zero\n");
874 *status = 0xffffffff;
875 return -ENODEV;
876 }
877 xhci_ring_device(xhci, slot_id);
878 } else {
879 int port_status = readl(port->addr);
880
881 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
882 hcd->self.busnum, wIndex + 1, port_status);
883 *status |= USB_PORT_STAT_SUSPEND;
884 clear_bit(wIndex, &bus_state->rexit_ports);
885 }
886
887 usb_hcd_end_port_resume(&hcd->self, wIndex);
888 bus_state->port_c_suspend |= 1 << wIndex;
889 bus_state->suspended_ports &= ~(1 << wIndex);
890 } else {
891
892
893
894
895
896
897 *status |= USB_PORT_STAT_SUSPEND;
898 }
899 return 0;
900}
901
902static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
903{
904 u32 ext_stat = 0;
905 int speed_id;
906
907
908 speed_id = DEV_PORT_SPEED(raw_port_status);
909 ext_stat |= speed_id;
910 ext_stat |= speed_id << 4;
911
912 ext_stat |= PORT_RX_LANES(port_li) << 8;
913 ext_stat |= PORT_TX_LANES(port_li) << 12;
914
915 return ext_stat;
916}
917
918static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
919 u32 portsc)
920{
921 struct xhci_bus_state *bus_state;
922 struct xhci_hcd *xhci;
923 u32 link_state;
924 u32 portnum;
925
926 bus_state = &port->rhub->bus_state;
927 xhci = hcd_to_xhci(port->rhub->hcd);
928 link_state = portsc & PORT_PLS_MASK;
929 portnum = port->hcd_portnum;
930
931
932
933
934
935
936
937
938
939
940 if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
941 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
942 if (portsc & PORT_WRC)
943 *status |= USB_PORT_STAT_C_BH_RESET << 16;
944 if (portsc & PORT_CEC)
945 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
946
947
948 if (portsc & PORT_POWER) {
949 *status |= USB_SS_PORT_STAT_POWER;
950
951 if (link_state == XDEV_U0)
952 bus_state->suspended_ports &= ~(1 << portnum);
953 }
954
955 xhci_hub_report_usb3_link_state(xhci, status, portsc);
956 xhci_del_comp_mod_timer(xhci, portsc, portnum);
957}
958
959static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
960 u32 portsc, unsigned long flags)
961{
962 struct xhci_bus_state *bus_state;
963 u32 link_state;
964 u32 portnum;
965 int ret;
966
967 bus_state = &port->rhub->bus_state;
968 link_state = portsc & PORT_PLS_MASK;
969 portnum = port->hcd_portnum;
970
971
972 if (portsc & PORT_POWER) {
973 *status |= USB_PORT_STAT_POWER;
974
975
976 if (link_state == XDEV_U3)
977 *status |= USB_PORT_STAT_SUSPEND;
978 if (link_state == XDEV_U2)
979 *status |= USB_PORT_STAT_L1;
980 if (link_state == XDEV_U0) {
981 bus_state->resume_done[portnum] = 0;
982 clear_bit(portnum, &bus_state->resuming_ports);
983 if (bus_state->suspended_ports & (1 << portnum)) {
984 bus_state->suspended_ports &= ~(1 << portnum);
985 bus_state->port_c_suspend |= 1 << portnum;
986 }
987 }
988 if (link_state == XDEV_RESUME) {
989 ret = xhci_handle_usb2_port_link_resume(port, status,
990 portsc, flags);
991 if (ret)
992 return;
993 }
994 }
995}
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007static u32 xhci_get_port_status(struct usb_hcd *hcd,
1008 struct xhci_bus_state *bus_state,
1009 u16 wIndex, u32 raw_port_status,
1010 unsigned long flags)
1011 __releases(&xhci->lock)
1012 __acquires(&xhci->lock)
1013{
1014 u32 status = 0;
1015 struct xhci_hub *rhub;
1016 struct xhci_port *port;
1017
1018 rhub = xhci_get_rhub(hcd);
1019 port = rhub->ports[wIndex];
1020
1021
1022 if (raw_port_status & PORT_CSC)
1023 status |= USB_PORT_STAT_C_CONNECTION << 16;
1024 if (raw_port_status & PORT_PEC)
1025 status |= USB_PORT_STAT_C_ENABLE << 16;
1026 if ((raw_port_status & PORT_OCC))
1027 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1028 if ((raw_port_status & PORT_RC))
1029 status |= USB_PORT_STAT_C_RESET << 16;
1030
1031
1032 if (raw_port_status & PORT_CONNECT) {
1033 status |= USB_PORT_STAT_CONNECTION;
1034 status |= xhci_port_speed(raw_port_status);
1035 }
1036 if (raw_port_status & PORT_PE)
1037 status |= USB_PORT_STAT_ENABLE;
1038 if (raw_port_status & PORT_OC)
1039 status |= USB_PORT_STAT_OVERCURRENT;
1040 if (raw_port_status & PORT_RESET)
1041 status |= USB_PORT_STAT_RESET;
1042
1043
1044 if (hcd->speed >= HCD_USB3)
1045 xhci_get_usb3_port_status(port, &status, raw_port_status);
1046 else
1047 xhci_get_usb2_port_status(port, &status, raw_port_status,
1048 flags);
1049
1050
1051
1052
1053 if ((bus_state->resume_done[wIndex] ||
1054 test_bit(wIndex, &bus_state->resuming_ports)) &&
1055 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1056 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1057 bus_state->resume_done[wIndex] = 0;
1058 clear_bit(wIndex, &bus_state->resuming_ports);
1059 usb_hcd_end_port_resume(&hcd->self, wIndex);
1060 }
1061
1062 if (bus_state->port_c_suspend & (1 << wIndex))
1063 status |= USB_PORT_STAT_C_SUSPEND << 16;
1064
1065 return status;
1066}
1067
1068int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1069 u16 wIndex, char *buf, u16 wLength)
1070{
1071 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1072 int max_ports;
1073 unsigned long flags;
1074 u32 temp, status;
1075 int retval = 0;
1076 int slot_id;
1077 struct xhci_bus_state *bus_state;
1078 u16 link_state = 0;
1079 u16 wake_mask = 0;
1080 u16 timeout = 0;
1081 u16 test_mode = 0;
1082 struct xhci_hub *rhub;
1083 struct xhci_port **ports;
1084
1085 rhub = xhci_get_rhub(hcd);
1086 ports = rhub->ports;
1087 max_ports = rhub->num_ports;
1088 bus_state = &rhub->bus_state;
1089
1090 spin_lock_irqsave(&xhci->lock, flags);
1091 switch (typeReq) {
1092 case GetHubStatus:
1093
1094 memset(buf, 0, 4);
1095 break;
1096 case GetHubDescriptor:
1097
1098
1099
1100
1101 if (hcd->speed >= HCD_USB3 &&
1102 (wLength < USB_DT_SS_HUB_SIZE ||
1103 wValue != (USB_DT_SS_HUB << 8))) {
1104 xhci_dbg(xhci, "Wrong hub descriptor type for "
1105 "USB 3.0 roothub.\n");
1106 goto error;
1107 }
1108 xhci_hub_descriptor(hcd, xhci,
1109 (struct usb_hub_descriptor *) buf);
1110 break;
1111 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1112 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1113 goto error;
1114
1115 if (hcd->speed < HCD_USB3)
1116 goto error;
1117
1118 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1119 spin_unlock_irqrestore(&xhci->lock, flags);
1120 return retval;
1121 case GetPortStatus:
1122 if (!wIndex || wIndex > max_ports)
1123 goto error;
1124 wIndex--;
1125 temp = readl(ports[wIndex]->addr);
1126 if (temp == ~(u32)0) {
1127 xhci_hc_died(xhci);
1128 retval = -ENODEV;
1129 break;
1130 }
1131 trace_xhci_get_port_status(wIndex, temp);
1132 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1133 flags);
1134 if (status == 0xffffffff)
1135 goto error;
1136
1137 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1138 hcd->self.busnum, wIndex + 1, temp, status);
1139
1140 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1141
1142 if (wValue == 0x02) {
1143 u32 port_li;
1144
1145 if (hcd->speed < HCD_USB31 || wLength != 8) {
1146 xhci_err(xhci, "get ext port status invalid parameter\n");
1147 retval = -EINVAL;
1148 break;
1149 }
1150 port_li = readl(ports[wIndex]->addr + PORTLI);
1151 status = xhci_get_ext_port_status(temp, port_li);
1152 put_unaligned_le32(cpu_to_le32(status), &buf[4]);
1153 }
1154 break;
1155 case SetPortFeature:
1156 if (wValue == USB_PORT_FEAT_LINK_STATE)
1157 link_state = (wIndex & 0xff00) >> 3;
1158 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1159 wake_mask = wIndex & 0xff00;
1160 if (wValue == USB_PORT_FEAT_TEST)
1161 test_mode = (wIndex & 0xff00) >> 8;
1162
1163 timeout = (wIndex & 0xff00) >> 8;
1164 wIndex &= 0xff;
1165 if (!wIndex || wIndex > max_ports)
1166 goto error;
1167 wIndex--;
1168 temp = readl(ports[wIndex]->addr);
1169 if (temp == ~(u32)0) {
1170 xhci_hc_died(xhci);
1171 retval = -ENODEV;
1172 break;
1173 }
1174 temp = xhci_port_state_to_neutral(temp);
1175
1176 switch (wValue) {
1177 case USB_PORT_FEAT_SUSPEND:
1178 temp = readl(ports[wIndex]->addr);
1179 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1180
1181 xhci_set_link_state(xhci, ports[wIndex],
1182 XDEV_U0);
1183 spin_unlock_irqrestore(&xhci->lock, flags);
1184 msleep(10);
1185 spin_lock_irqsave(&xhci->lock, flags);
1186 }
1187
1188
1189
1190
1191 temp = readl(ports[wIndex]->addr);
1192 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1193 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1194 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1195 hcd->self.busnum, wIndex + 1);
1196 goto error;
1197 }
1198
1199 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1200 wIndex + 1);
1201 if (!slot_id) {
1202 xhci_warn(xhci, "slot_id is zero\n");
1203 goto error;
1204 }
1205
1206 spin_unlock_irqrestore(&xhci->lock, flags);
1207 xhci_stop_device(xhci, slot_id, 1);
1208 spin_lock_irqsave(&xhci->lock, flags);
1209
1210 xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1211
1212 spin_unlock_irqrestore(&xhci->lock, flags);
1213 msleep(10);
1214 spin_lock_irqsave(&xhci->lock, flags);
1215
1216 temp = readl(ports[wIndex]->addr);
1217 bus_state->suspended_ports |= 1 << wIndex;
1218 break;
1219 case USB_PORT_FEAT_LINK_STATE:
1220 temp = readl(ports[wIndex]->addr);
1221
1222 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1223 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1224 temp = xhci_port_state_to_neutral(temp);
1225
1226
1227
1228
1229 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1230 PORT_OCC | PORT_RC | PORT_PLC |
1231 PORT_CEC;
1232 writel(temp | PORT_PE, ports[wIndex]->addr);
1233 temp = readl(ports[wIndex]->addr);
1234 break;
1235 }
1236
1237
1238 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1239 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1240 xhci_set_link_state(xhci, ports[wIndex],
1241 link_state);
1242 temp = readl(ports[wIndex]->addr);
1243 break;
1244 }
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260 if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1261 if (!HCC2_CTC(xhci->hcc_params2)) {
1262 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1263 break;
1264 }
1265
1266 if ((temp & PORT_CONNECT)) {
1267 xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1268 goto error;
1269 }
1270
1271 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1272 wIndex);
1273 xhci_set_link_state(xhci, ports[wIndex],
1274 link_state);
1275
1276 temp = readl(ports[wIndex]->addr);
1277 break;
1278 }
1279
1280 if (!(temp & PORT_PE)) {
1281 retval = -ENODEV;
1282 break;
1283 }
1284
1285 if (link_state > USB_SS_PORT_LS_U3) {
1286 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1287 wIndex, link_state);
1288 goto error;
1289 }
1290 if (link_state == USB_SS_PORT_LS_U3) {
1291 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1292 wIndex + 1);
1293 if (slot_id) {
1294
1295
1296 spin_unlock_irqrestore(&xhci->lock,
1297 flags);
1298 xhci_stop_device(xhci, slot_id, 1);
1299 spin_lock_irqsave(&xhci->lock, flags);
1300 }
1301 }
1302
1303 xhci_set_link_state(xhci, ports[wIndex], link_state);
1304
1305 spin_unlock_irqrestore(&xhci->lock, flags);
1306 msleep(20);
1307 spin_lock_irqsave(&xhci->lock, flags);
1308
1309 temp = readl(ports[wIndex]->addr);
1310 if (link_state == USB_SS_PORT_LS_U3)
1311 bus_state->suspended_ports |= 1 << wIndex;
1312 break;
1313 case USB_PORT_FEAT_POWER:
1314
1315
1316
1317
1318
1319
1320 xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1321 break;
1322 case USB_PORT_FEAT_RESET:
1323 temp = (temp | PORT_RESET);
1324 writel(temp, ports[wIndex]->addr);
1325
1326 temp = readl(ports[wIndex]->addr);
1327 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1328 break;
1329 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1330 xhci_set_remote_wake_mask(xhci, ports[wIndex],
1331 wake_mask);
1332 temp = readl(ports[wIndex]->addr);
1333 xhci_dbg(xhci, "set port remote wake mask, "
1334 "actual port %d status = 0x%x\n",
1335 wIndex, temp);
1336 break;
1337 case USB_PORT_FEAT_BH_PORT_RESET:
1338 temp |= PORT_WR;
1339 writel(temp, ports[wIndex]->addr);
1340 temp = readl(ports[wIndex]->addr);
1341 break;
1342 case USB_PORT_FEAT_U1_TIMEOUT:
1343 if (hcd->speed < HCD_USB3)
1344 goto error;
1345 temp = readl(ports[wIndex]->addr + PORTPMSC);
1346 temp &= ~PORT_U1_TIMEOUT_MASK;
1347 temp |= PORT_U1_TIMEOUT(timeout);
1348 writel(temp, ports[wIndex]->addr + PORTPMSC);
1349 break;
1350 case USB_PORT_FEAT_U2_TIMEOUT:
1351 if (hcd->speed < HCD_USB3)
1352 goto error;
1353 temp = readl(ports[wIndex]->addr + PORTPMSC);
1354 temp &= ~PORT_U2_TIMEOUT_MASK;
1355 temp |= PORT_U2_TIMEOUT(timeout);
1356 writel(temp, ports[wIndex]->addr + PORTPMSC);
1357 break;
1358 case USB_PORT_FEAT_TEST:
1359
1360 if (hcd->speed != HCD_USB2)
1361 goto error;
1362 if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1363 goto error;
1364 retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1365 &flags);
1366 break;
1367 default:
1368 goto error;
1369 }
1370
1371 temp = readl(ports[wIndex]->addr);
1372 break;
1373 case ClearPortFeature:
1374 if (!wIndex || wIndex > max_ports)
1375 goto error;
1376 wIndex--;
1377 temp = readl(ports[wIndex]->addr);
1378 if (temp == ~(u32)0) {
1379 xhci_hc_died(xhci);
1380 retval = -ENODEV;
1381 break;
1382 }
1383
1384 temp = xhci_port_state_to_neutral(temp);
1385 switch (wValue) {
1386 case USB_PORT_FEAT_SUSPEND:
1387 temp = readl(ports[wIndex]->addr);
1388 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1389 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1390 if (temp & PORT_RESET)
1391 goto error;
1392 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1393 if ((temp & PORT_PE) == 0)
1394 goto error;
1395
1396 set_bit(wIndex, &bus_state->resuming_ports);
1397 usb_hcd_start_port_resume(&hcd->self, wIndex);
1398 xhci_set_link_state(xhci, ports[wIndex],
1399 XDEV_RESUME);
1400 spin_unlock_irqrestore(&xhci->lock, flags);
1401 msleep(USB_RESUME_TIMEOUT);
1402 spin_lock_irqsave(&xhci->lock, flags);
1403 xhci_set_link_state(xhci, ports[wIndex],
1404 XDEV_U0);
1405 clear_bit(wIndex, &bus_state->resuming_ports);
1406 usb_hcd_end_port_resume(&hcd->self, wIndex);
1407 }
1408 bus_state->port_c_suspend |= 1 << wIndex;
1409
1410 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1411 wIndex + 1);
1412 if (!slot_id) {
1413 xhci_dbg(xhci, "slot_id is zero\n");
1414 goto error;
1415 }
1416 xhci_ring_device(xhci, slot_id);
1417 break;
1418 case USB_PORT_FEAT_C_SUSPEND:
1419 bus_state->port_c_suspend &= ~(1 << wIndex);
1420
1421 case USB_PORT_FEAT_C_RESET:
1422 case USB_PORT_FEAT_C_BH_PORT_RESET:
1423 case USB_PORT_FEAT_C_CONNECTION:
1424 case USB_PORT_FEAT_C_OVER_CURRENT:
1425 case USB_PORT_FEAT_C_ENABLE:
1426 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1427 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1428 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1429 ports[wIndex]->addr, temp);
1430 break;
1431 case USB_PORT_FEAT_ENABLE:
1432 xhci_disable_port(hcd, xhci, wIndex,
1433 ports[wIndex]->addr, temp);
1434 break;
1435 case USB_PORT_FEAT_POWER:
1436 xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1437 break;
1438 case USB_PORT_FEAT_TEST:
1439 retval = xhci_exit_test_mode(xhci);
1440 break;
1441 default:
1442 goto error;
1443 }
1444 break;
1445 default:
1446error:
1447
1448 retval = -EPIPE;
1449 }
1450 spin_unlock_irqrestore(&xhci->lock, flags);
1451 return retval;
1452}
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1463{
1464 unsigned long flags;
1465 u32 temp, status;
1466 u32 mask;
1467 int i, retval;
1468 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1469 int max_ports;
1470 struct xhci_bus_state *bus_state;
1471 bool reset_change = false;
1472 struct xhci_hub *rhub;
1473 struct xhci_port **ports;
1474
1475 rhub = xhci_get_rhub(hcd);
1476 ports = rhub->ports;
1477 max_ports = rhub->num_ports;
1478 bus_state = &rhub->bus_state;
1479
1480
1481 retval = (max_ports + 8) / 8;
1482 memset(buf, 0, retval);
1483
1484
1485
1486
1487
1488 status = bus_state->resuming_ports;
1489
1490 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1491
1492 spin_lock_irqsave(&xhci->lock, flags);
1493
1494 for (i = 0; i < max_ports; i++) {
1495 temp = readl(ports[i]->addr);
1496 if (temp == ~(u32)0) {
1497 xhci_hc_died(xhci);
1498 retval = -ENODEV;
1499 break;
1500 }
1501 trace_xhci_hub_status_data(i, temp);
1502
1503 if ((temp & mask) != 0 ||
1504 (bus_state->port_c_suspend & 1 << i) ||
1505 (bus_state->resume_done[i] && time_after_eq(
1506 jiffies, bus_state->resume_done[i]))) {
1507 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1508 status = 1;
1509 }
1510 if ((temp & PORT_RC))
1511 reset_change = true;
1512 }
1513 if (!status && !reset_change) {
1514 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1515 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1516 }
1517 spin_unlock_irqrestore(&xhci->lock, flags);
1518 return status ? retval : 0;
1519}
1520
1521#ifdef CONFIG_PM
1522
1523int xhci_bus_suspend(struct usb_hcd *hcd)
1524{
1525 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1526 int max_ports, port_index;
1527 struct xhci_bus_state *bus_state;
1528 unsigned long flags;
1529 struct xhci_hub *rhub;
1530 struct xhci_port **ports;
1531 u32 portsc_buf[USB_MAXCHILDREN];
1532 bool wake_enabled;
1533
1534 rhub = xhci_get_rhub(hcd);
1535 ports = rhub->ports;
1536 max_ports = rhub->num_ports;
1537 bus_state = &rhub->bus_state;
1538 wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1539
1540 spin_lock_irqsave(&xhci->lock, flags);
1541
1542 if (wake_enabled) {
1543 if (bus_state->resuming_ports ||
1544 bus_state->port_remote_wakeup) {
1545 spin_unlock_irqrestore(&xhci->lock, flags);
1546 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1547 return -EBUSY;
1548 }
1549 }
1550
1551
1552
1553
1554 bus_state->bus_suspended = 0;
1555 port_index = max_ports;
1556 while (port_index--) {
1557 u32 t1, t2;
1558 int retries = 10;
1559retry:
1560 t1 = readl(ports[port_index]->addr);
1561 t2 = xhci_port_state_to_neutral(t1);
1562 portsc_buf[port_index] = 0;
1563
1564
1565
1566
1567
1568 if ((hcd->speed >= HCD_USB3) && retries-- &&
1569 (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1570 spin_unlock_irqrestore(&xhci->lock, flags);
1571 msleep(XHCI_PORT_POLLING_LFPS_TIME);
1572 spin_lock_irqsave(&xhci->lock, flags);
1573 xhci_dbg(xhci, "port %d polling in bus suspend, waiting\n",
1574 port_index);
1575 goto retry;
1576 }
1577
1578 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1579 if ((t1 & PORT_CSC) && wake_enabled) {
1580 bus_state->bus_suspended = 0;
1581 spin_unlock_irqrestore(&xhci->lock, flags);
1582 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1583 return -EBUSY;
1584 }
1585 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1586 t2 &= ~PORT_PLS_MASK;
1587 t2 |= PORT_LINK_STROBE | XDEV_U3;
1588 set_bit(port_index, &bus_state->bus_suspended);
1589 }
1590
1591
1592
1593
1594 if (wake_enabled) {
1595 if (t1 & PORT_CONNECT) {
1596 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1597 t2 &= ~PORT_WKCONN_E;
1598 } else {
1599 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1600 t2 &= ~PORT_WKDISC_E;
1601 }
1602
1603 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1604 (hcd->speed < HCD_USB3)) {
1605 if (usb_amd_pt_check_port(hcd->self.controller,
1606 port_index))
1607 t2 &= ~PORT_WAKE_BITS;
1608 }
1609 } else
1610 t2 &= ~PORT_WAKE_BITS;
1611
1612 t1 = xhci_port_state_to_neutral(t1);
1613 if (t1 != t2)
1614 portsc_buf[port_index] = t2;
1615 }
1616
1617
1618 port_index = max_ports;
1619 while (port_index--) {
1620 if (!portsc_buf[port_index])
1621 continue;
1622 if (test_bit(port_index, &bus_state->bus_suspended)) {
1623 int slot_id;
1624
1625 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1626 port_index + 1);
1627 if (slot_id) {
1628 spin_unlock_irqrestore(&xhci->lock, flags);
1629 xhci_stop_device(xhci, slot_id, 1);
1630 spin_lock_irqsave(&xhci->lock, flags);
1631 }
1632 }
1633 writel(portsc_buf[port_index], ports[port_index]->addr);
1634 }
1635 hcd->state = HC_STATE_SUSPENDED;
1636 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1637 spin_unlock_irqrestore(&xhci->lock, flags);
1638 return 0;
1639}
1640
1641
1642
1643
1644
1645
1646static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1647{
1648 u32 portsc;
1649
1650 portsc = readl(port->addr);
1651
1652
1653 if (portsc & (PORT_CONNECT | PORT_CAS))
1654 return false;
1655
1656 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1657 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1658 return false;
1659
1660
1661 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1662 portsc |= PORT_WR;
1663 writel(portsc, port->addr);
1664
1665 readl(port->addr);
1666 return true;
1667}
1668
1669int xhci_bus_resume(struct usb_hcd *hcd)
1670{
1671 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1672 struct xhci_bus_state *bus_state;
1673 unsigned long flags;
1674 int max_ports, port_index;
1675 int slot_id;
1676 int sret;
1677 u32 next_state;
1678 u32 temp, portsc;
1679 struct xhci_hub *rhub;
1680 struct xhci_port **ports;
1681
1682 rhub = xhci_get_rhub(hcd);
1683 ports = rhub->ports;
1684 max_ports = rhub->num_ports;
1685 bus_state = &rhub->bus_state;
1686
1687 if (time_before(jiffies, bus_state->next_statechange))
1688 msleep(5);
1689
1690 spin_lock_irqsave(&xhci->lock, flags);
1691 if (!HCD_HW_ACCESSIBLE(hcd)) {
1692 spin_unlock_irqrestore(&xhci->lock, flags);
1693 return -ESHUTDOWN;
1694 }
1695
1696
1697 temp = readl(&xhci->op_regs->command);
1698 temp &= ~CMD_EIE;
1699 writel(temp, &xhci->op_regs->command);
1700
1701
1702 if (hcd->speed >= HCD_USB3)
1703 next_state = XDEV_U0;
1704 else
1705 next_state = XDEV_RESUME;
1706
1707 port_index = max_ports;
1708 while (port_index--) {
1709 portsc = readl(ports[port_index]->addr);
1710
1711
1712 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1713 (hcd->speed >= HCD_USB3) &&
1714 xhci_port_missing_cas_quirk(ports[port_index])) {
1715 xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1716 clear_bit(port_index, &bus_state->bus_suspended);
1717 continue;
1718 }
1719
1720 if (test_bit(port_index, &bus_state->bus_suspended))
1721 switch (portsc & PORT_PLS_MASK) {
1722 case XDEV_U3:
1723 portsc = xhci_port_state_to_neutral(portsc);
1724 portsc &= ~PORT_PLS_MASK;
1725 portsc |= PORT_LINK_STROBE | next_state;
1726 break;
1727 case XDEV_RESUME:
1728
1729 break;
1730 default:
1731
1732 clear_bit(port_index,
1733 &bus_state->bus_suspended);
1734 break;
1735 }
1736
1737 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1738 writel(portsc, ports[port_index]->addr);
1739 }
1740
1741
1742 if (hcd->speed < HCD_USB3) {
1743 if (bus_state->bus_suspended) {
1744 spin_unlock_irqrestore(&xhci->lock, flags);
1745 msleep(USB_RESUME_TIMEOUT);
1746 spin_lock_irqsave(&xhci->lock, flags);
1747 }
1748 for_each_set_bit(port_index, &bus_state->bus_suspended,
1749 BITS_PER_LONG) {
1750
1751 xhci_test_and_clear_bit(xhci, ports[port_index],
1752 PORT_PLC);
1753 xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1754 }
1755 }
1756
1757
1758 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1759 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1760 PORT_PLC, 10 * 1000);
1761 if (sret) {
1762 xhci_warn(xhci, "port %d resume PLC timeout\n",
1763 port_index);
1764 continue;
1765 }
1766 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1767 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1768 if (slot_id)
1769 xhci_ring_device(xhci, slot_id);
1770 }
1771 (void) readl(&xhci->op_regs->command);
1772
1773 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1774
1775 temp = readl(&xhci->op_regs->command);
1776 temp |= CMD_EIE;
1777 writel(temp, &xhci->op_regs->command);
1778 temp = readl(&xhci->op_regs->command);
1779
1780 spin_unlock_irqrestore(&xhci->lock, flags);
1781 return 0;
1782}
1783
1784unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1785{
1786 struct xhci_hub *rhub = xhci_get_rhub(hcd);
1787
1788
1789 return rhub->bus_state.resuming_ports;
1790}
1791
1792#endif
1793