linux/drivers/usb/host/xhci-ring.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * xHCI host controller driver
   4 *
   5 * Copyright (C) 2008 Intel Corp.
   6 *
   7 * Author: Sarah Sharp
   8 * Some code borrowed from the Linux EHCI driver.
   9 */
  10
  11/*
  12 * Ring initialization rules:
  13 * 1. Each segment is initialized to zero, except for link TRBs.
  14 * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  15 *    Consumer Cycle State (CCS), depending on ring function.
  16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  17 *
  18 * Ring behavior rules:
  19 * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  20 *    least one free TRB in the ring.  This is useful if you want to turn that
  21 *    into a link TRB and expand the ring.
  22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  23 *    link TRB, then load the pointer with the address in the link TRB.  If the
  24 *    link TRB had its toggle bit set, you may need to update the ring cycle
  25 *    state (see cycle bit rules).  You may have to do this multiple times
  26 *    until you reach a non-link TRB.
  27 * 3. A ring is full if enqueue++ (for the definition of increment above)
  28 *    equals the dequeue pointer.
  29 *
  30 * Cycle bit rules:
  31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  32 *    in a link TRB, it must toggle the ring cycle state.
  33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  34 *    in a link TRB, it must toggle the ring cycle state.
  35 *
  36 * Producer rules:
  37 * 1. Check if ring is full before you enqueue.
  38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  39 *    Update enqueue pointer between each write (which may update the ring
  40 *    cycle state).
  41 * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  42 *    and endpoint rings.  If HC is the producer for the event ring,
  43 *    and it generates an interrupt according to interrupt modulation rules.
  44 *
  45 * Consumer rules:
  46 * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  47 *    the TRB is owned by the consumer.
  48 * 2. Update dequeue pointer (which may update the ring cycle state) and
  49 *    continue processing TRBs until you reach a TRB which is not owned by you.
  50 * 3. Notify the producer.  SW is the consumer for the event ring, and it
  51 *   updates event ring dequeue pointer.  HC is the consumer for the command and
  52 *   endpoint rings; it generates events on the event ring for these.
  53 */
  54
  55#include <linux/scatterlist.h>
  56#include <linux/slab.h>
  57#include <linux/dma-mapping.h>
  58#include "xhci.h"
  59#include "xhci-trace.h"
  60#include "xhci-mtk.h"
  61
  62/*
  63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  64 * address of the TRB.
  65 */
  66dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  67                union xhci_trb *trb)
  68{
  69        unsigned long segment_offset;
  70
  71        if (!seg || !trb || trb < seg->trbs)
  72                return 0;
  73        /* offset in TRBs */
  74        segment_offset = trb - seg->trbs;
  75        if (segment_offset >= TRBS_PER_SEGMENT)
  76                return 0;
  77        return seg->dma + (segment_offset * sizeof(*trb));
  78}
  79
  80static bool trb_is_noop(union xhci_trb *trb)
  81{
  82        return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
  83}
  84
  85static bool trb_is_link(union xhci_trb *trb)
  86{
  87        return TRB_TYPE_LINK_LE32(trb->link.control);
  88}
  89
  90static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
  91{
  92        return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
  93}
  94
  95static bool last_trb_on_ring(struct xhci_ring *ring,
  96                        struct xhci_segment *seg, union xhci_trb *trb)
  97{
  98        return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
  99}
 100
 101static bool link_trb_toggles_cycle(union xhci_trb *trb)
 102{
 103        return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104}
 105
 106static bool last_td_in_urb(struct xhci_td *td)
 107{
 108        struct urb_priv *urb_priv = td->urb->hcpriv;
 109
 110        return urb_priv->num_tds_done == urb_priv->num_tds;
 111}
 112
 113static void inc_td_cnt(struct urb *urb)
 114{
 115        struct urb_priv *urb_priv = urb->hcpriv;
 116
 117        urb_priv->num_tds_done++;
 118}
 119
 120static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
 121{
 122        if (trb_is_link(trb)) {
 123                /* unchain chained link TRBs */
 124                trb->link.control &= cpu_to_le32(~TRB_CHAIN);
 125        } else {
 126                trb->generic.field[0] = 0;
 127                trb->generic.field[1] = 0;
 128                trb->generic.field[2] = 0;
 129                /* Preserve only the cycle bit of this TRB */
 130                trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 131                trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
 132        }
 133}
 134
 135/* Updates trb to point to the next TRB in the ring, and updates seg if the next
 136 * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 137 * effect the ring dequeue or enqueue pointers.
 138 */
 139static void next_trb(struct xhci_hcd *xhci,
 140                struct xhci_ring *ring,
 141                struct xhci_segment **seg,
 142                union xhci_trb **trb)
 143{
 144        if (trb_is_link(*trb)) {
 145                *seg = (*seg)->next;
 146                *trb = ((*seg)->trbs);
 147        } else {
 148                (*trb)++;
 149        }
 150}
 151
 152/*
 153 * See Cycle bit rules. SW is the consumer for the event ring only.
 154 * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 155 */
 156void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 157{
 158        /* event ring doesn't have link trbs, check for last trb */
 159        if (ring->type == TYPE_EVENT) {
 160                if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
 161                        ring->dequeue++;
 162                        goto out;
 163                }
 164                if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
 165                        ring->cycle_state ^= 1;
 166                ring->deq_seg = ring->deq_seg->next;
 167                ring->dequeue = ring->deq_seg->trbs;
 168                goto out;
 169        }
 170
 171        /* All other rings have link trbs */
 172        if (!trb_is_link(ring->dequeue)) {
 173                ring->dequeue++;
 174                ring->num_trbs_free++;
 175        }
 176        while (trb_is_link(ring->dequeue)) {
 177                ring->deq_seg = ring->deq_seg->next;
 178                ring->dequeue = ring->deq_seg->trbs;
 179        }
 180
 181out:
 182        trace_xhci_inc_deq(ring);
 183
 184        return;
 185}
 186
 187/*
 188 * See Cycle bit rules. SW is the consumer for the event ring only.
 189 * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 190 *
 191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 192 * chain bit is set), then set the chain bit in all the following link TRBs.
 193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 194 * have their chain bit cleared (so that each Link TRB is a separate TD).
 195 *
 196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 197 * set, but other sections talk about dealing with the chain bit set.  This was
 198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 200 *
 201 * @more_trbs_coming:   Will you enqueue more TRBs before calling
 202 *                      prepare_transfer()?
 203 */
 204static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 205                        bool more_trbs_coming)
 206{
 207        u32 chain;
 208        union xhci_trb *next;
 209
 210        chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 211        /* If this is not event ring, there is one less usable TRB */
 212        if (!trb_is_link(ring->enqueue))
 213                ring->num_trbs_free--;
 214        next = ++(ring->enqueue);
 215
 216        /* Update the dequeue pointer further if that was a link TRB */
 217        while (trb_is_link(next)) {
 218
 219                /*
 220                 * If the caller doesn't plan on enqueueing more TDs before
 221                 * ringing the doorbell, then we don't want to give the link TRB
 222                 * to the hardware just yet. We'll give the link TRB back in
 223                 * prepare_ring() just before we enqueue the TD at the top of
 224                 * the ring.
 225                 */
 226                if (!chain && !more_trbs_coming)
 227                        break;
 228
 229                /* If we're not dealing with 0.95 hardware or isoc rings on
 230                 * AMD 0.96 host, carry over the chain bit of the previous TRB
 231                 * (which may mean the chain bit is cleared).
 232                 */
 233                if (!(ring->type == TYPE_ISOC &&
 234                      (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
 235                    !xhci_link_trb_quirk(xhci)) {
 236                        next->link.control &= cpu_to_le32(~TRB_CHAIN);
 237                        next->link.control |= cpu_to_le32(chain);
 238                }
 239                /* Give this link TRB to the hardware */
 240                wmb();
 241                next->link.control ^= cpu_to_le32(TRB_CYCLE);
 242
 243                /* Toggle the cycle bit after the last ring segment. */
 244                if (link_trb_toggles_cycle(next))
 245                        ring->cycle_state ^= 1;
 246
 247                ring->enq_seg = ring->enq_seg->next;
 248                ring->enqueue = ring->enq_seg->trbs;
 249                next = ring->enqueue;
 250        }
 251
 252        trace_xhci_inc_enq(ring);
 253}
 254
 255/*
 256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
 257 * enqueue pointer will not advance into dequeue segment. See rules above.
 258 */
 259static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 260                unsigned int num_trbs)
 261{
 262        int num_trbs_in_deq_seg;
 263
 264        if (ring->num_trbs_free < num_trbs)
 265                return 0;
 266
 267        if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 268                num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 269                if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 270                        return 0;
 271        }
 272
 273        return 1;
 274}
 275
 276/* Ring the host controller doorbell after placing a command on the ring */
 277void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 278{
 279        if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 280                return;
 281
 282        xhci_dbg(xhci, "// Ding dong!\n");
 283        writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 284        /* Flush PCI posted writes */
 285        readl(&xhci->dba->doorbell[0]);
 286}
 287
 288static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
 289{
 290        return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
 291}
 292
 293static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
 294{
 295        return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
 296                                        cmd_list);
 297}
 298
 299/*
 300 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
 301 * If there are other commands waiting then restart the ring and kick the timer.
 302 * This must be called with command ring stopped and xhci->lock held.
 303 */
 304static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
 305                                         struct xhci_command *cur_cmd)
 306{
 307        struct xhci_command *i_cmd;
 308
 309        /* Turn all aborted commands in list to no-ops, then restart */
 310        list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
 311
 312                if (i_cmd->status != COMP_COMMAND_ABORTED)
 313                        continue;
 314
 315                i_cmd->status = COMP_COMMAND_RING_STOPPED;
 316
 317                xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
 318                         i_cmd->command_trb);
 319
 320                trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
 321
 322                /*
 323                 * caller waiting for completion is called when command
 324                 *  completion event is received for these no-op commands
 325                 */
 326        }
 327
 328        xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
 329
 330        /* ring command ring doorbell to restart the command ring */
 331        if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
 332            !(xhci->xhc_state & XHCI_STATE_DYING)) {
 333                xhci->current_cmd = cur_cmd;
 334                xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
 335                xhci_ring_cmd_db(xhci);
 336        }
 337}
 338
 339/* Must be called with xhci->lock held, releases and aquires lock back */
 340static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
 341{
 342        u64 temp_64;
 343        int ret;
 344
 345        xhci_dbg(xhci, "Abort command ring\n");
 346
 347        reinit_completion(&xhci->cmd_ring_stop_completion);
 348
 349        temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 350        xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 351                        &xhci->op_regs->cmd_ring);
 352
 353        /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
 354         * completion of the Command Abort operation. If CRR is not negated in 5
 355         * seconds then driver handles it as if host died (-ENODEV).
 356         * In the future we should distinguish between -ENODEV and -ETIMEDOUT
 357         * and try to recover a -ETIMEDOUT with a host controller reset.
 358         */
 359        ret = xhci_handshake(&xhci->op_regs->cmd_ring,
 360                        CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 361        if (ret < 0) {
 362                xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
 363                xhci_halt(xhci);
 364                xhci_hc_died(xhci);
 365                return ret;
 366        }
 367        /*
 368         * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
 369         * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
 370         * but the completion event in never sent. Wait 2 secs (arbitrary
 371         * number) to handle those cases after negation of CMD_RING_RUNNING.
 372         */
 373        spin_unlock_irqrestore(&xhci->lock, flags);
 374        ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
 375                                          msecs_to_jiffies(2000));
 376        spin_lock_irqsave(&xhci->lock, flags);
 377        if (!ret) {
 378                xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
 379                xhci_cleanup_command_queue(xhci);
 380        } else {
 381                xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
 382        }
 383        return 0;
 384}
 385
 386void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 387                unsigned int slot_id,
 388                unsigned int ep_index,
 389                unsigned int stream_id)
 390{
 391        __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 392        struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 393        unsigned int ep_state = ep->ep_state;
 394
 395        /* Don't ring the doorbell for this endpoint if there are pending
 396         * cancellations because we don't want to interrupt processing.
 397         * We don't want to restart any stream rings if there's a set dequeue
 398         * pointer command pending because the device can choose to start any
 399         * stream once the endpoint is on the HW schedule.
 400         */
 401        if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 402            (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
 403                return;
 404        writel(DB_VALUE(ep_index, stream_id), db_addr);
 405        /* The CPU has better things to do at this point than wait for a
 406         * write-posting flush.  It'll get there soon enough.
 407         */
 408}
 409
 410/* Ring the doorbell for any rings with pending URBs */
 411static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 412                unsigned int slot_id,
 413                unsigned int ep_index)
 414{
 415        unsigned int stream_id;
 416        struct xhci_virt_ep *ep;
 417
 418        ep = &xhci->devs[slot_id]->eps[ep_index];
 419
 420        /* A ring has pending URBs if its TD list is not empty */
 421        if (!(ep->ep_state & EP_HAS_STREAMS)) {
 422                if (ep->ring && !(list_empty(&ep->ring->td_list)))
 423                        xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 424                return;
 425        }
 426
 427        for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 428                        stream_id++) {
 429                struct xhci_stream_info *stream_info = ep->stream_info;
 430                if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 431                        xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 432                                                stream_id);
 433        }
 434}
 435
 436void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 437                unsigned int slot_id,
 438                unsigned int ep_index)
 439{
 440        ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 441}
 442
 443/* Get the right ring for the given slot_id, ep_index and stream_id.
 444 * If the endpoint supports streams, boundary check the URB's stream ID.
 445 * If the endpoint doesn't support streams, return the singular endpoint ring.
 446 */
 447struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 448                unsigned int slot_id, unsigned int ep_index,
 449                unsigned int stream_id)
 450{
 451        struct xhci_virt_ep *ep;
 452
 453        ep = &xhci->devs[slot_id]->eps[ep_index];
 454        /* Common case: no streams */
 455        if (!(ep->ep_state & EP_HAS_STREAMS))
 456                return ep->ring;
 457
 458        if (stream_id == 0) {
 459                xhci_warn(xhci,
 460                                "WARN: Slot ID %u, ep index %u has streams, "
 461                                "but URB has no stream ID.\n",
 462                                slot_id, ep_index);
 463                return NULL;
 464        }
 465
 466        if (stream_id < ep->stream_info->num_streams)
 467                return ep->stream_info->stream_rings[stream_id];
 468
 469        xhci_warn(xhci,
 470                        "WARN: Slot ID %u, ep index %u has "
 471                        "stream IDs 1 to %u allocated, "
 472                        "but stream ID %u is requested.\n",
 473                        slot_id, ep_index,
 474                        ep->stream_info->num_streams - 1,
 475                        stream_id);
 476        return NULL;
 477}
 478
 479
 480/*
 481 * Get the hw dequeue pointer xHC stopped on, either directly from the
 482 * endpoint context, or if streams are in use from the stream context.
 483 * The returned hw_dequeue contains the lowest four bits with cycle state
 484 * and possbile stream context type.
 485 */
 486static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
 487                           unsigned int ep_index, unsigned int stream_id)
 488{
 489        struct xhci_ep_ctx *ep_ctx;
 490        struct xhci_stream_ctx *st_ctx;
 491        struct xhci_virt_ep *ep;
 492
 493        ep = &vdev->eps[ep_index];
 494
 495        if (ep->ep_state & EP_HAS_STREAMS) {
 496                st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
 497                return le64_to_cpu(st_ctx->stream_ring);
 498        }
 499        ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
 500        return le64_to_cpu(ep_ctx->deq);
 501}
 502
 503/*
 504 * Move the xHC's endpoint ring dequeue pointer past cur_td.
 505 * Record the new state of the xHC's endpoint ring dequeue segment,
 506 * dequeue pointer, stream id, and new consumer cycle state in state.
 507 * Update our internal representation of the ring's dequeue pointer.
 508 *
 509 * We do this in three jumps:
 510 *  - First we update our new ring state to be the same as when the xHC stopped.
 511 *  - Then we traverse the ring to find the segment that contains
 512 *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 513 *    any link TRBs with the toggle cycle bit set.
 514 *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 515 *    if we've moved it past a link TRB with the toggle cycle bit set.
 516 *
 517 * Some of the uses of xhci_generic_trb are grotty, but if they're done
 518 * with correct __le32 accesses they should work fine.  Only users of this are
 519 * in here.
 520 */
 521void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 522                unsigned int slot_id, unsigned int ep_index,
 523                unsigned int stream_id, struct xhci_td *cur_td,
 524                struct xhci_dequeue_state *state)
 525{
 526        struct xhci_virt_device *dev = xhci->devs[slot_id];
 527        struct xhci_virt_ep *ep = &dev->eps[ep_index];
 528        struct xhci_ring *ep_ring;
 529        struct xhci_segment *new_seg;
 530        union xhci_trb *new_deq;
 531        dma_addr_t addr;
 532        u64 hw_dequeue;
 533        bool cycle_found = false;
 534        bool td_last_trb_found = false;
 535
 536        ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 537                        ep_index, stream_id);
 538        if (!ep_ring) {
 539                xhci_warn(xhci, "WARN can't find new dequeue state "
 540                                "for invalid stream ID %u.\n",
 541                                stream_id);
 542                return;
 543        }
 544        /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 545        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 546                        "Finding endpoint context");
 547
 548        hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
 549        new_seg = ep_ring->deq_seg;
 550        new_deq = ep_ring->dequeue;
 551        state->new_cycle_state = hw_dequeue & 0x1;
 552        state->stream_id = stream_id;
 553
 554        /*
 555         * We want to find the pointer, segment and cycle state of the new trb
 556         * (the one after current TD's last_trb). We know the cycle state at
 557         * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
 558         * found.
 559         */
 560        do {
 561                if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
 562                    == (dma_addr_t)(hw_dequeue & ~0xf)) {
 563                        cycle_found = true;
 564                        if (td_last_trb_found)
 565                                break;
 566                }
 567                if (new_deq == cur_td->last_trb)
 568                        td_last_trb_found = true;
 569
 570                if (cycle_found && trb_is_link(new_deq) &&
 571                    link_trb_toggles_cycle(new_deq))
 572                        state->new_cycle_state ^= 0x1;
 573
 574                next_trb(xhci, ep_ring, &new_seg, &new_deq);
 575
 576                /* Search wrapped around, bail out */
 577                if (new_deq == ep->ring->dequeue) {
 578                        xhci_err(xhci, "Error: Failed finding new dequeue state\n");
 579                        state->new_deq_seg = NULL;
 580                        state->new_deq_ptr = NULL;
 581                        return;
 582                }
 583
 584        } while (!cycle_found || !td_last_trb_found);
 585
 586        state->new_deq_seg = new_seg;
 587        state->new_deq_ptr = new_deq;
 588
 589        /* Don't update the ring cycle state for the producer (us). */
 590        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 591                        "Cycle state = 0x%x", state->new_cycle_state);
 592
 593        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 594                        "New dequeue segment = %p (virtual)",
 595                        state->new_deq_seg);
 596        addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 597        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 598                        "New dequeue pointer = 0x%llx (DMA)",
 599                        (unsigned long long) addr);
 600}
 601
 602/* flip_cycle means flip the cycle bit of all but the first and last TRB.
 603 * (The last TRB actually points to the ring enqueue pointer, which is not part
 604 * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 605 */
 606static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 607                       struct xhci_td *td, bool flip_cycle)
 608{
 609        struct xhci_segment *seg        = td->start_seg;
 610        union xhci_trb *trb             = td->first_trb;
 611
 612        while (1) {
 613                trb_to_noop(trb, TRB_TR_NOOP);
 614
 615                /* flip cycle if asked to */
 616                if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
 617                        trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
 618
 619                if (trb == td->last_trb)
 620                        break;
 621
 622                next_trb(xhci, ep_ring, &seg, &trb);
 623        }
 624}
 625
 626static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 627                struct xhci_virt_ep *ep)
 628{
 629        ep->ep_state &= ~EP_STOP_CMD_PENDING;
 630        /* Can't del_timer_sync in interrupt */
 631        del_timer(&ep->stop_cmd_timer);
 632}
 633
 634/*
 635 * Must be called with xhci->lock held in interrupt context,
 636 * releases and re-acquires xhci->lock
 637 */
 638static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 639                                     struct xhci_td *cur_td, int status)
 640{
 641        struct urb      *urb            = cur_td->urb;
 642        struct urb_priv *urb_priv       = urb->hcpriv;
 643        struct usb_hcd  *hcd            = bus_to_hcd(urb->dev->bus);
 644
 645        if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 646                xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 647                if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 648                        if (xhci->quirks & XHCI_AMD_PLL_FIX)
 649                                usb_amd_quirk_pll_enable();
 650                }
 651        }
 652        xhci_urb_free_priv(urb_priv);
 653        usb_hcd_unlink_urb_from_ep(hcd, urb);
 654        spin_unlock(&xhci->lock);
 655        trace_xhci_urb_giveback(urb);
 656        usb_hcd_giveback_urb(hcd, urb, status);
 657        spin_lock(&xhci->lock);
 658}
 659
 660static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
 661                struct xhci_ring *ring, struct xhci_td *td)
 662{
 663        struct device *dev = xhci_to_hcd(xhci)->self.controller;
 664        struct xhci_segment *seg = td->bounce_seg;
 665        struct urb *urb = td->urb;
 666        size_t len;
 667
 668        if (!ring || !seg || !urb)
 669                return;
 670
 671        if (usb_urb_dir_out(urb)) {
 672                dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
 673                                 DMA_TO_DEVICE);
 674                return;
 675        }
 676
 677        dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
 678                         DMA_FROM_DEVICE);
 679        /* for in tranfers we need to copy the data from bounce to sg */
 680        len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
 681                             seg->bounce_len, seg->bounce_offs);
 682        if (len != seg->bounce_len)
 683                xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
 684                                len, seg->bounce_len);
 685        seg->bounce_len = 0;
 686        seg->bounce_offs = 0;
 687}
 688
 689/*
 690 * When we get a command completion for a Stop Endpoint Command, we need to
 691 * unlink any cancelled TDs from the ring.  There are two ways to do that:
 692 *
 693 *  1. If the HW was in the middle of processing the TD that needs to be
 694 *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 695 *     in the TD with a Set Dequeue Pointer Command.
 696 *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 697 *     bit cleared) so that the HW will skip over them.
 698 */
 699static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
 700                union xhci_trb *trb, struct xhci_event_cmd *event)
 701{
 702        unsigned int ep_index;
 703        struct xhci_ring *ep_ring;
 704        struct xhci_virt_ep *ep;
 705        struct xhci_td *cur_td = NULL;
 706        struct xhci_td *last_unlinked_td;
 707        struct xhci_ep_ctx *ep_ctx;
 708        struct xhci_virt_device *vdev;
 709        u64 hw_deq;
 710        struct xhci_dequeue_state deq_state;
 711
 712        if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
 713                if (!xhci->devs[slot_id])
 714                        xhci_warn(xhci, "Stop endpoint command "
 715                                "completion for disabled slot %u\n",
 716                                slot_id);
 717                return;
 718        }
 719
 720        memset(&deq_state, 0, sizeof(deq_state));
 721        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 722
 723        vdev = xhci->devs[slot_id];
 724        ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
 725        trace_xhci_handle_cmd_stop_ep(ep_ctx);
 726
 727        ep = &xhci->devs[slot_id]->eps[ep_index];
 728        last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
 729                        struct xhci_td, cancelled_td_list);
 730
 731        if (list_empty(&ep->cancelled_td_list)) {
 732                xhci_stop_watchdog_timer_in_irq(xhci, ep);
 733                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 734                return;
 735        }
 736
 737        /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 738         * We have the xHCI lock, so nothing can modify this list until we drop
 739         * it.  We're also in the event handler, so we can't get re-interrupted
 740         * if another Stop Endpoint command completes
 741         */
 742        list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
 743                xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 744                                "Removing canceled TD starting at 0x%llx (dma).",
 745                                (unsigned long long)xhci_trb_virt_to_dma(
 746                                        cur_td->start_seg, cur_td->first_trb));
 747                ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 748                if (!ep_ring) {
 749                        /* This shouldn't happen unless a driver is mucking
 750                         * with the stream ID after submission.  This will
 751                         * leave the TD on the hardware ring, and the hardware
 752                         * will try to execute it, and may access a buffer
 753                         * that has already been freed.  In the best case, the
 754                         * hardware will execute it, and the event handler will
 755                         * ignore the completion event for that TD, since it was
 756                         * removed from the td_list for that endpoint.  In
 757                         * short, don't muck with the stream ID after
 758                         * submission.
 759                         */
 760                        xhci_warn(xhci, "WARN Cancelled URB %p "
 761                                        "has invalid stream ID %u.\n",
 762                                        cur_td->urb,
 763                                        cur_td->urb->stream_id);
 764                        goto remove_finished_td;
 765                }
 766                /*
 767                 * If we stopped on the TD we need to cancel, then we have to
 768                 * move the xHC endpoint ring dequeue pointer past this TD.
 769                 */
 770                hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
 771                                         cur_td->urb->stream_id);
 772                hw_deq &= ~0xf;
 773
 774                if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
 775                              cur_td->last_trb, hw_deq, false)) {
 776                        xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 777                                                    cur_td->urb->stream_id,
 778                                                    cur_td, &deq_state);
 779                } else {
 780                        td_to_noop(xhci, ep_ring, cur_td, false);
 781                }
 782
 783remove_finished_td:
 784                /*
 785                 * The event handler won't see a completion for this TD anymore,
 786                 * so remove it from the endpoint ring's TD list.  Keep it in
 787                 * the cancelled TD list for URB completion later.
 788                 */
 789                list_del_init(&cur_td->td_list);
 790        }
 791
 792        xhci_stop_watchdog_timer_in_irq(xhci, ep);
 793
 794        /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 795        if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 796                xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
 797                                             &deq_state);
 798                xhci_ring_cmd_db(xhci);
 799        } else {
 800                /* Otherwise ring the doorbell(s) to restart queued transfers */
 801                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 802        }
 803
 804        /*
 805         * Drop the lock and complete the URBs in the cancelled TD list.
 806         * New TDs to be cancelled might be added to the end of the list before
 807         * we can complete all the URBs for the TDs we already unlinked.
 808         * So stop when we've completed the URB for the last TD we unlinked.
 809         */
 810        do {
 811                cur_td = list_first_entry(&ep->cancelled_td_list,
 812                                struct xhci_td, cancelled_td_list);
 813                list_del_init(&cur_td->cancelled_td_list);
 814
 815                /* Clean up the cancelled URB */
 816                /* Doesn't matter what we pass for status, since the core will
 817                 * just overwrite it (because the URB has been unlinked).
 818                 */
 819                ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 820                xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
 821                inc_td_cnt(cur_td->urb);
 822                if (last_td_in_urb(cur_td))
 823                        xhci_giveback_urb_in_irq(xhci, cur_td, 0);
 824
 825                /* Stop processing the cancelled list if the watchdog timer is
 826                 * running.
 827                 */
 828                if (xhci->xhc_state & XHCI_STATE_DYING)
 829                        return;
 830        } while (cur_td != last_unlinked_td);
 831
 832        /* Return to the event handler with xhci->lock re-acquired */
 833}
 834
 835static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
 836{
 837        struct xhci_td *cur_td;
 838        struct xhci_td *tmp;
 839
 840        list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
 841                list_del_init(&cur_td->td_list);
 842
 843                if (!list_empty(&cur_td->cancelled_td_list))
 844                        list_del_init(&cur_td->cancelled_td_list);
 845
 846                xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
 847
 848                inc_td_cnt(cur_td->urb);
 849                if (last_td_in_urb(cur_td))
 850                        xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
 851        }
 852}
 853
 854static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
 855                int slot_id, int ep_index)
 856{
 857        struct xhci_td *cur_td;
 858        struct xhci_td *tmp;
 859        struct xhci_virt_ep *ep;
 860        struct xhci_ring *ring;
 861
 862        ep = &xhci->devs[slot_id]->eps[ep_index];
 863        if ((ep->ep_state & EP_HAS_STREAMS) ||
 864                        (ep->ep_state & EP_GETTING_NO_STREAMS)) {
 865                int stream_id;
 866
 867                for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 868                                stream_id++) {
 869                        ring = ep->stream_info->stream_rings[stream_id];
 870                        if (!ring)
 871                                continue;
 872
 873                        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 874                                        "Killing URBs for slot ID %u, ep index %u, stream %u",
 875                                        slot_id, ep_index, stream_id);
 876                        xhci_kill_ring_urbs(xhci, ring);
 877                }
 878        } else {
 879                ring = ep->ring;
 880                if (!ring)
 881                        return;
 882                xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 883                                "Killing URBs for slot ID %u, ep index %u",
 884                                slot_id, ep_index);
 885                xhci_kill_ring_urbs(xhci, ring);
 886        }
 887
 888        list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
 889                        cancelled_td_list) {
 890                list_del_init(&cur_td->cancelled_td_list);
 891                inc_td_cnt(cur_td->urb);
 892
 893                if (last_td_in_urb(cur_td))
 894                        xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
 895        }
 896}
 897
 898/*
 899 * host controller died, register read returns 0xffffffff
 900 * Complete pending commands, mark them ABORTED.
 901 * URBs need to be given back as usb core might be waiting with device locks
 902 * held for the URBs to finish during device disconnect, blocking host remove.
 903 *
 904 * Call with xhci->lock held.
 905 * lock is relased and re-acquired while giving back urb.
 906 */
 907void xhci_hc_died(struct xhci_hcd *xhci)
 908{
 909        int i, j;
 910
 911        if (xhci->xhc_state & XHCI_STATE_DYING)
 912                return;
 913
 914        xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
 915        xhci->xhc_state |= XHCI_STATE_DYING;
 916
 917        xhci_cleanup_command_queue(xhci);
 918
 919        /* return any pending urbs, remove may be waiting for them */
 920        for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 921                if (!xhci->devs[i])
 922                        continue;
 923                for (j = 0; j < 31; j++)
 924                        xhci_kill_endpoint_urbs(xhci, i, j);
 925        }
 926
 927        /* inform usb core hc died if PCI remove isn't already handling it */
 928        if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
 929                usb_hc_died(xhci_to_hcd(xhci));
 930}
 931
 932/* Watchdog timer function for when a stop endpoint command fails to complete.
 933 * In this case, we assume the host controller is broken or dying or dead.  The
 934 * host may still be completing some other events, so we have to be careful to
 935 * let the event ring handler and the URB dequeueing/enqueueing functions know
 936 * through xhci->state.
 937 *
 938 * The timer may also fire if the host takes a very long time to respond to the
 939 * command, and the stop endpoint command completion handler cannot delete the
 940 * timer before the timer function is called.  Another endpoint cancellation may
 941 * sneak in before the timer function can grab the lock, and that may queue
 942 * another stop endpoint command and add the timer back.  So we cannot use a
 943 * simple flag to say whether there is a pending stop endpoint command for a
 944 * particular endpoint.
 945 *
 946 * Instead we use a combination of that flag and checking if a new timer is
 947 * pending.
 948 */
 949void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
 950{
 951        struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
 952        struct xhci_hcd *xhci = ep->xhci;
 953        unsigned long flags;
 954
 955        spin_lock_irqsave(&xhci->lock, flags);
 956
 957        /* bail out if cmd completed but raced with stop ep watchdog timer.*/
 958        if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
 959            timer_pending(&ep->stop_cmd_timer)) {
 960                spin_unlock_irqrestore(&xhci->lock, flags);
 961                xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
 962                return;
 963        }
 964
 965        xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 966        ep->ep_state &= ~EP_STOP_CMD_PENDING;
 967
 968        xhci_halt(xhci);
 969
 970        /*
 971         * handle a stop endpoint cmd timeout as if host died (-ENODEV).
 972         * In the future we could distinguish between -ENODEV and -ETIMEDOUT
 973         * and try to recover a -ETIMEDOUT with a host controller reset
 974         */
 975        xhci_hc_died(xhci);
 976
 977        spin_unlock_irqrestore(&xhci->lock, flags);
 978        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 979                        "xHCI host controller is dead.");
 980}
 981
 982static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
 983                struct xhci_virt_device *dev,
 984                struct xhci_ring *ep_ring,
 985                unsigned int ep_index)
 986{
 987        union xhci_trb *dequeue_temp;
 988        int num_trbs_free_temp;
 989        bool revert = false;
 990
 991        num_trbs_free_temp = ep_ring->num_trbs_free;
 992        dequeue_temp = ep_ring->dequeue;
 993
 994        /* If we get two back-to-back stalls, and the first stalled transfer
 995         * ends just before a link TRB, the dequeue pointer will be left on
 996         * the link TRB by the code in the while loop.  So we have to update
 997         * the dequeue pointer one segment further, or we'll jump off
 998         * the segment into la-la-land.
 999         */
1000        if (trb_is_link(ep_ring->dequeue)) {
1001                ep_ring->deq_seg = ep_ring->deq_seg->next;
1002                ep_ring->dequeue = ep_ring->deq_seg->trbs;
1003        }
1004
1005        while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1006                /* We have more usable TRBs */
1007                ep_ring->num_trbs_free++;
1008                ep_ring->dequeue++;
1009                if (trb_is_link(ep_ring->dequeue)) {
1010                        if (ep_ring->dequeue ==
1011                                        dev->eps[ep_index].queued_deq_ptr)
1012                                break;
1013                        ep_ring->deq_seg = ep_ring->deq_seg->next;
1014                        ep_ring->dequeue = ep_ring->deq_seg->trbs;
1015                }
1016                if (ep_ring->dequeue == dequeue_temp) {
1017                        revert = true;
1018                        break;
1019                }
1020        }
1021
1022        if (revert) {
1023                xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1024                ep_ring->num_trbs_free = num_trbs_free_temp;
1025        }
1026}
1027
1028/*
1029 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1030 * we need to clear the set deq pending flag in the endpoint ring state, so that
1031 * the TD queueing code can ring the doorbell again.  We also need to ring the
1032 * endpoint doorbell to restart the ring, but only if there aren't more
1033 * cancellations pending.
1034 */
1035static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1036                union xhci_trb *trb, u32 cmd_comp_code)
1037{
1038        unsigned int ep_index;
1039        unsigned int stream_id;
1040        struct xhci_ring *ep_ring;
1041        struct xhci_virt_device *dev;
1042        struct xhci_virt_ep *ep;
1043        struct xhci_ep_ctx *ep_ctx;
1044        struct xhci_slot_ctx *slot_ctx;
1045
1046        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1047        stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1048        dev = xhci->devs[slot_id];
1049        ep = &dev->eps[ep_index];
1050
1051        ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1052        if (!ep_ring) {
1053                xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1054                                stream_id);
1055                /* XXX: Harmless??? */
1056                goto cleanup;
1057        }
1058
1059        ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1060        slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1061        trace_xhci_handle_cmd_set_deq(slot_ctx);
1062        trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1063
1064        if (cmd_comp_code != COMP_SUCCESS) {
1065                unsigned int ep_state;
1066                unsigned int slot_state;
1067
1068                switch (cmd_comp_code) {
1069                case COMP_TRB_ERROR:
1070                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1071                        break;
1072                case COMP_CONTEXT_STATE_ERROR:
1073                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1074                        ep_state = GET_EP_CTX_STATE(ep_ctx);
1075                        slot_state = le32_to_cpu(slot_ctx->dev_state);
1076                        slot_state = GET_SLOT_STATE(slot_state);
1077                        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1078                                        "Slot state = %u, EP state = %u",
1079                                        slot_state, ep_state);
1080                        break;
1081                case COMP_SLOT_NOT_ENABLED_ERROR:
1082                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1083                                        slot_id);
1084                        break;
1085                default:
1086                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1087                                        cmd_comp_code);
1088                        break;
1089                }
1090                /* OK what do we do now?  The endpoint state is hosed, and we
1091                 * should never get to this point if the synchronization between
1092                 * queueing, and endpoint state are correct.  This might happen
1093                 * if the device gets disconnected after we've finished
1094                 * cancelling URBs, which might not be an error...
1095                 */
1096        } else {
1097                u64 deq;
1098                /* 4.6.10 deq ptr is written to the stream ctx for streams */
1099                if (ep->ep_state & EP_HAS_STREAMS) {
1100                        struct xhci_stream_ctx *ctx =
1101                                &ep->stream_info->stream_ctx_array[stream_id];
1102                        deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1103                } else {
1104                        deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1105                }
1106                xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1107                        "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1108                if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1109                                         ep->queued_deq_ptr) == deq) {
1110                        /* Update the ring's dequeue segment and dequeue pointer
1111                         * to reflect the new position.
1112                         */
1113                        update_ring_for_set_deq_completion(xhci, dev,
1114                                ep_ring, ep_index);
1115                } else {
1116                        xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1117                        xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1118                                  ep->queued_deq_seg, ep->queued_deq_ptr);
1119                }
1120        }
1121
1122cleanup:
1123        dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1124        dev->eps[ep_index].queued_deq_seg = NULL;
1125        dev->eps[ep_index].queued_deq_ptr = NULL;
1126        /* Restart any rings with pending URBs */
1127        ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1128}
1129
1130static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1131                union xhci_trb *trb, u32 cmd_comp_code)
1132{
1133        struct xhci_virt_device *vdev;
1134        struct xhci_ep_ctx *ep_ctx;
1135        unsigned int ep_index;
1136
1137        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1138        vdev = xhci->devs[slot_id];
1139        ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1140        trace_xhci_handle_cmd_reset_ep(ep_ctx);
1141
1142        /* This command will only fail if the endpoint wasn't halted,
1143         * but we don't care.
1144         */
1145        xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1146                "Ignoring reset ep completion code of %u", cmd_comp_code);
1147
1148        /* HW with the reset endpoint quirk needs to have a configure endpoint
1149         * command complete before the endpoint can be used.  Queue that here
1150         * because the HW can't handle two commands being queued in a row.
1151         */
1152        if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1153                struct xhci_command *command;
1154
1155                command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1156                if (!command)
1157                        return;
1158
1159                xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1160                                "Queueing configure endpoint command");
1161                xhci_queue_configure_endpoint(xhci, command,
1162                                xhci->devs[slot_id]->in_ctx->dma, slot_id,
1163                                false);
1164                xhci_ring_cmd_db(xhci);
1165        } else {
1166                /* Clear our internal halted state */
1167                xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1168        }
1169
1170        /* if this was a soft reset, then restart */
1171        if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1172                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1173}
1174
1175static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1176                struct xhci_command *command, u32 cmd_comp_code)
1177{
1178        if (cmd_comp_code == COMP_SUCCESS)
1179                command->slot_id = slot_id;
1180        else
1181                command->slot_id = 0;
1182}
1183
1184static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1185{
1186        struct xhci_virt_device *virt_dev;
1187        struct xhci_slot_ctx *slot_ctx;
1188
1189        virt_dev = xhci->devs[slot_id];
1190        if (!virt_dev)
1191                return;
1192
1193        slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1194        trace_xhci_handle_cmd_disable_slot(slot_ctx);
1195
1196        if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1197                /* Delete default control endpoint resources */
1198                xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1199        xhci_free_virt_device(xhci, slot_id);
1200}
1201
1202static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1203                struct xhci_event_cmd *event, u32 cmd_comp_code)
1204{
1205        struct xhci_virt_device *virt_dev;
1206        struct xhci_input_control_ctx *ctrl_ctx;
1207        struct xhci_ep_ctx *ep_ctx;
1208        unsigned int ep_index;
1209        unsigned int ep_state;
1210        u32 add_flags, drop_flags;
1211
1212        /*
1213         * Configure endpoint commands can come from the USB core
1214         * configuration or alt setting changes, or because the HW
1215         * needed an extra configure endpoint command after a reset
1216         * endpoint command or streams were being configured.
1217         * If the command was for a halted endpoint, the xHCI driver
1218         * is not waiting on the configure endpoint command.
1219         */
1220        virt_dev = xhci->devs[slot_id];
1221        ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1222        if (!ctrl_ctx) {
1223                xhci_warn(xhci, "Could not get input context, bad type.\n");
1224                return;
1225        }
1226
1227        add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1228        drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1229        /* Input ctx add_flags are the endpoint index plus one */
1230        ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1231
1232        ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1233        trace_xhci_handle_cmd_config_ep(ep_ctx);
1234
1235        /* A usb_set_interface() call directly after clearing a halted
1236         * condition may race on this quirky hardware.  Not worth
1237         * worrying about, since this is prototype hardware.  Not sure
1238         * if this will work for streams, but streams support was
1239         * untested on this prototype.
1240         */
1241        if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1242                        ep_index != (unsigned int) -1 &&
1243                        add_flags - SLOT_FLAG == drop_flags) {
1244                ep_state = virt_dev->eps[ep_index].ep_state;
1245                if (!(ep_state & EP_HALTED))
1246                        return;
1247                xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1248                                "Completed config ep cmd - "
1249                                "last ep index = %d, state = %d",
1250                                ep_index, ep_state);
1251                /* Clear internal halted state and restart ring(s) */
1252                virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1253                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1254                return;
1255        }
1256        return;
1257}
1258
1259static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1260{
1261        struct xhci_virt_device *vdev;
1262        struct xhci_slot_ctx *slot_ctx;
1263
1264        vdev = xhci->devs[slot_id];
1265        slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1266        trace_xhci_handle_cmd_addr_dev(slot_ctx);
1267}
1268
1269static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1270                struct xhci_event_cmd *event)
1271{
1272        struct xhci_virt_device *vdev;
1273        struct xhci_slot_ctx *slot_ctx;
1274
1275        vdev = xhci->devs[slot_id];
1276        slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1277        trace_xhci_handle_cmd_reset_dev(slot_ctx);
1278
1279        xhci_dbg(xhci, "Completed reset device command.\n");
1280        if (!xhci->devs[slot_id])
1281                xhci_warn(xhci, "Reset device command completion "
1282                                "for disabled slot %u\n", slot_id);
1283}
1284
1285static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1286                struct xhci_event_cmd *event)
1287{
1288        if (!(xhci->quirks & XHCI_NEC_HOST)) {
1289                xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1290                return;
1291        }
1292        xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1293                        "NEC firmware version %2x.%02x",
1294                        NEC_FW_MAJOR(le32_to_cpu(event->status)),
1295                        NEC_FW_MINOR(le32_to_cpu(event->status)));
1296}
1297
1298static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1299{
1300        list_del(&cmd->cmd_list);
1301
1302        if (cmd->completion) {
1303                cmd->status = status;
1304                complete(cmd->completion);
1305        } else {
1306                kfree(cmd);
1307        }
1308}
1309
1310void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1311{
1312        struct xhci_command *cur_cmd, *tmp_cmd;
1313        xhci->current_cmd = NULL;
1314        list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1315                xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1316}
1317
1318void xhci_handle_command_timeout(struct work_struct *work)
1319{
1320        struct xhci_hcd *xhci;
1321        unsigned long flags;
1322        u64 hw_ring_state;
1323
1324        xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1325
1326        spin_lock_irqsave(&xhci->lock, flags);
1327
1328        /*
1329         * If timeout work is pending, or current_cmd is NULL, it means we
1330         * raced with command completion. Command is handled so just return.
1331         */
1332        if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1333                spin_unlock_irqrestore(&xhci->lock, flags);
1334                return;
1335        }
1336        /* mark this command to be cancelled */
1337        xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1338
1339        /* Make sure command ring is running before aborting it */
1340        hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1341        if (hw_ring_state == ~(u64)0) {
1342                xhci_hc_died(xhci);
1343                goto time_out_completed;
1344        }
1345
1346        if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1347            (hw_ring_state & CMD_RING_RUNNING))  {
1348                /* Prevent new doorbell, and start command abort */
1349                xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1350                xhci_dbg(xhci, "Command timeout\n");
1351                xhci_abort_cmd_ring(xhci, flags);
1352                goto time_out_completed;
1353        }
1354
1355        /* host removed. Bail out */
1356        if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1357                xhci_dbg(xhci, "host removed, ring start fail?\n");
1358                xhci_cleanup_command_queue(xhci);
1359
1360                goto time_out_completed;
1361        }
1362
1363        /* command timeout on stopped ring, ring can't be aborted */
1364        xhci_dbg(xhci, "Command timeout on stopped ring\n");
1365        xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1366
1367time_out_completed:
1368        spin_unlock_irqrestore(&xhci->lock, flags);
1369        return;
1370}
1371
1372static void handle_cmd_completion(struct xhci_hcd *xhci,
1373                struct xhci_event_cmd *event)
1374{
1375        int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1376        u64 cmd_dma;
1377        dma_addr_t cmd_dequeue_dma;
1378        u32 cmd_comp_code;
1379        union xhci_trb *cmd_trb;
1380        struct xhci_command *cmd;
1381        u32 cmd_type;
1382
1383        cmd_dma = le64_to_cpu(event->cmd_trb);
1384        cmd_trb = xhci->cmd_ring->dequeue;
1385
1386        trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1387
1388        cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1389                        cmd_trb);
1390        /*
1391         * Check whether the completion event is for our internal kept
1392         * command.
1393         */
1394        if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1395                xhci_warn(xhci,
1396                          "ERROR mismatched command completion event\n");
1397                return;
1398        }
1399
1400        cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1401
1402        cancel_delayed_work(&xhci->cmd_timer);
1403
1404        cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1405
1406        /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1407        if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1408                complete_all(&xhci->cmd_ring_stop_completion);
1409                return;
1410        }
1411
1412        if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1413                xhci_err(xhci,
1414                         "Command completion event does not match command\n");
1415                return;
1416        }
1417
1418        /*
1419         * Host aborted the command ring, check if the current command was
1420         * supposed to be aborted, otherwise continue normally.
1421         * The command ring is stopped now, but the xHC will issue a Command
1422         * Ring Stopped event which will cause us to restart it.
1423         */
1424        if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1425                xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1426                if (cmd->status == COMP_COMMAND_ABORTED) {
1427                        if (xhci->current_cmd == cmd)
1428                                xhci->current_cmd = NULL;
1429                        goto event_handled;
1430                }
1431        }
1432
1433        cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1434        switch (cmd_type) {
1435        case TRB_ENABLE_SLOT:
1436                xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1437                break;
1438        case TRB_DISABLE_SLOT:
1439                xhci_handle_cmd_disable_slot(xhci, slot_id);
1440                break;
1441        case TRB_CONFIG_EP:
1442                if (!cmd->completion)
1443                        xhci_handle_cmd_config_ep(xhci, slot_id, event,
1444                                                  cmd_comp_code);
1445                break;
1446        case TRB_EVAL_CONTEXT:
1447                break;
1448        case TRB_ADDR_DEV:
1449                xhci_handle_cmd_addr_dev(xhci, slot_id);
1450                break;
1451        case TRB_STOP_RING:
1452                WARN_ON(slot_id != TRB_TO_SLOT_ID(
1453                                le32_to_cpu(cmd_trb->generic.field[3])));
1454                if (!cmd->completion)
1455                        xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1456                break;
1457        case TRB_SET_DEQ:
1458                WARN_ON(slot_id != TRB_TO_SLOT_ID(
1459                                le32_to_cpu(cmd_trb->generic.field[3])));
1460                xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1461                break;
1462        case TRB_CMD_NOOP:
1463                /* Is this an aborted command turned to NO-OP? */
1464                if (cmd->status == COMP_COMMAND_RING_STOPPED)
1465                        cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1466                break;
1467        case TRB_RESET_EP:
1468                WARN_ON(slot_id != TRB_TO_SLOT_ID(
1469                                le32_to_cpu(cmd_trb->generic.field[3])));
1470                xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1471                break;
1472        case TRB_RESET_DEV:
1473                /* SLOT_ID field in reset device cmd completion event TRB is 0.
1474                 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1475                 */
1476                slot_id = TRB_TO_SLOT_ID(
1477                                le32_to_cpu(cmd_trb->generic.field[3]));
1478                xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1479                break;
1480        case TRB_NEC_GET_FW:
1481                xhci_handle_cmd_nec_get_fw(xhci, event);
1482                break;
1483        default:
1484                /* Skip over unknown commands on the event ring */
1485                xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1486                break;
1487        }
1488
1489        /* restart timer if this wasn't the last command */
1490        if (!list_is_singular(&xhci->cmd_list)) {
1491                xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1492                                                struct xhci_command, cmd_list);
1493                xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1494        } else if (xhci->current_cmd == cmd) {
1495                xhci->current_cmd = NULL;
1496        }
1497
1498event_handled:
1499        xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1500
1501        inc_deq(xhci, xhci->cmd_ring);
1502}
1503
1504static void handle_vendor_event(struct xhci_hcd *xhci,
1505                union xhci_trb *event)
1506{
1507        u32 trb_type;
1508
1509        trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1510        xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1511        if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1512                handle_cmd_completion(xhci, &event->event_cmd);
1513}
1514
1515static void handle_device_notification(struct xhci_hcd *xhci,
1516                union xhci_trb *event)
1517{
1518        u32 slot_id;
1519        struct usb_device *udev;
1520
1521        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1522        if (!xhci->devs[slot_id]) {
1523                xhci_warn(xhci, "Device Notification event for "
1524                                "unused slot %u\n", slot_id);
1525                return;
1526        }
1527
1528        xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1529                        slot_id);
1530        udev = xhci->devs[slot_id]->udev;
1531        if (udev && udev->parent)
1532                usb_wakeup_notification(udev->parent, udev->portnum);
1533}
1534
1535/*
1536 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1537 * Controller.
1538 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1539 * If a connection to a USB 1 device is followed by another connection
1540 * to a USB 2 device.
1541 *
1542 * Reset the PHY after the USB device is disconnected if device speed
1543 * is less than HCD_USB3.
1544 * Retry the reset sequence max of 4 times checking the PLL lock status.
1545 *
1546 */
1547static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1548{
1549        struct usb_hcd *hcd = xhci_to_hcd(xhci);
1550        u32 pll_lock_check;
1551        u32 retry_count = 4;
1552
1553        do {
1554                /* Assert PHY reset */
1555                writel(0x6F, hcd->regs + 0x1048);
1556                udelay(10);
1557                /* De-assert the PHY reset */
1558                writel(0x7F, hcd->regs + 0x1048);
1559                udelay(200);
1560                pll_lock_check = readl(hcd->regs + 0x1070);
1561        } while (!(pll_lock_check & 0x1) && --retry_count);
1562}
1563
1564static void handle_port_status(struct xhci_hcd *xhci,
1565                union xhci_trb *event)
1566{
1567        struct usb_hcd *hcd;
1568        u32 port_id;
1569        u32 portsc, cmd_reg;
1570        int max_ports;
1571        int slot_id;
1572        unsigned int hcd_portnum;
1573        struct xhci_bus_state *bus_state;
1574        bool bogus_port_status = false;
1575        struct xhci_port *port;
1576
1577        /* Port status change events always have a successful completion code */
1578        if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1579                xhci_warn(xhci,
1580                          "WARN: xHC returned failed port status event\n");
1581
1582        port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1583        max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1584
1585        if ((port_id <= 0) || (port_id > max_ports)) {
1586                xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1587                          port_id);
1588                inc_deq(xhci, xhci->event_ring);
1589                return;
1590        }
1591
1592        port = &xhci->hw_ports[port_id - 1];
1593        if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1594                xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1595                          port_id);
1596                bogus_port_status = true;
1597                goto cleanup;
1598        }
1599
1600        /* We might get interrupts after shared_hcd is removed */
1601        if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1602                xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1603                bogus_port_status = true;
1604                goto cleanup;
1605        }
1606
1607        hcd = port->rhub->hcd;
1608        bus_state = &port->rhub->bus_state;
1609        hcd_portnum = port->hcd_portnum;
1610        portsc = readl(port->addr);
1611
1612        xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1613                 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1614
1615        trace_xhci_handle_port_status(hcd_portnum, portsc);
1616
1617        if (hcd->state == HC_STATE_SUSPENDED) {
1618                xhci_dbg(xhci, "resume root hub\n");
1619                usb_hcd_resume_root_hub(hcd);
1620        }
1621
1622        if (hcd->speed >= HCD_USB3 &&
1623            (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1624                slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1625                if (slot_id && xhci->devs[slot_id])
1626                        xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1627                bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
1628        }
1629
1630        if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1631                xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1632
1633                cmd_reg = readl(&xhci->op_regs->command);
1634                if (!(cmd_reg & CMD_RUN)) {
1635                        xhci_warn(xhci, "xHC is not running.\n");
1636                        goto cleanup;
1637                }
1638
1639                if (DEV_SUPERSPEED_ANY(portsc)) {
1640                        xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1641                        /* Set a flag to say the port signaled remote wakeup,
1642                         * so we can tell the difference between the end of
1643                         * device and host initiated resume.
1644                         */
1645                        bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1646                        xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1647                        xhci_set_link_state(xhci, port, XDEV_U0);
1648                        /* Need to wait until the next link state change
1649                         * indicates the device is actually in U0.
1650                         */
1651                        bogus_port_status = true;
1652                        goto cleanup;
1653                } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1654                        xhci_dbg(xhci, "resume HS port %d\n", port_id);
1655                        bus_state->resume_done[hcd_portnum] = jiffies +
1656                                msecs_to_jiffies(USB_RESUME_TIMEOUT);
1657                        set_bit(hcd_portnum, &bus_state->resuming_ports);
1658                        /* Do the rest in GetPortStatus after resume time delay.
1659                         * Avoid polling roothub status before that so that a
1660                         * usb device auto-resume latency around ~40ms.
1661                         */
1662                        set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1663                        mod_timer(&hcd->rh_timer,
1664                                  bus_state->resume_done[hcd_portnum]);
1665                        usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1666                        bogus_port_status = true;
1667                }
1668        }
1669
1670        if ((portsc & PORT_PLC) &&
1671            DEV_SUPERSPEED_ANY(portsc) &&
1672            ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1673             (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1674             (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1675                xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1676                /* We've just brought the device into U0/1/2 through either the
1677                 * Resume state after a device remote wakeup, or through the
1678                 * U3Exit state after a host-initiated resume.  If it's a device
1679                 * initiated remote wake, don't pass up the link state change,
1680                 * so the roothub behavior is consistent with external
1681                 * USB 3.0 hub behavior.
1682                 */
1683                slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1684                if (slot_id && xhci->devs[slot_id])
1685                        xhci_ring_device(xhci, slot_id);
1686                if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1687                        bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
1688                        xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1689                        usb_wakeup_notification(hcd->self.root_hub,
1690                                        hcd_portnum + 1);
1691                        bogus_port_status = true;
1692                        goto cleanup;
1693                }
1694        }
1695
1696        /*
1697         * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1698         * RExit to a disconnect state).  If so, let the the driver know it's
1699         * out of the RExit state.
1700         */
1701        if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1702                        test_and_clear_bit(hcd_portnum,
1703                                &bus_state->rexit_ports)) {
1704                complete(&bus_state->rexit_done[hcd_portnum]);
1705                bogus_port_status = true;
1706                goto cleanup;
1707        }
1708
1709        if (hcd->speed < HCD_USB3) {
1710                xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1711                if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1712                    (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1713                        xhci_cavium_reset_phy_quirk(xhci);
1714        }
1715
1716cleanup:
1717        /* Update event ring dequeue pointer before dropping the lock */
1718        inc_deq(xhci, xhci->event_ring);
1719
1720        /* Don't make the USB core poll the roothub if we got a bad port status
1721         * change event.  Besides, at that point we can't tell which roothub
1722         * (USB 2.0 or USB 3.0) to kick.
1723         */
1724        if (bogus_port_status)
1725                return;
1726
1727        /*
1728         * xHCI port-status-change events occur when the "or" of all the
1729         * status-change bits in the portsc register changes from 0 to 1.
1730         * New status changes won't cause an event if any other change
1731         * bits are still set.  When an event occurs, switch over to
1732         * polling to avoid losing status changes.
1733         */
1734        xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1735        set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1736        spin_unlock(&xhci->lock);
1737        /* Pass this up to the core */
1738        usb_hcd_poll_rh_status(hcd);
1739        spin_lock(&xhci->lock);
1740}
1741
1742/*
1743 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1744 * at end_trb, which may be in another segment.  If the suspect DMA address is a
1745 * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1746 * returns 0.
1747 */
1748struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1749                struct xhci_segment *start_seg,
1750                union xhci_trb  *start_trb,
1751                union xhci_trb  *end_trb,
1752                dma_addr_t      suspect_dma,
1753                bool            debug)
1754{
1755        dma_addr_t start_dma;
1756        dma_addr_t end_seg_dma;
1757        dma_addr_t end_trb_dma;
1758        struct xhci_segment *cur_seg;
1759
1760        start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1761        cur_seg = start_seg;
1762
1763        do {
1764                if (start_dma == 0)
1765                        return NULL;
1766                /* We may get an event for a Link TRB in the middle of a TD */
1767                end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1768                                &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1769                /* If the end TRB isn't in this segment, this is set to 0 */
1770                end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1771
1772                if (debug)
1773                        xhci_warn(xhci,
1774                                "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1775                                (unsigned long long)suspect_dma,
1776                                (unsigned long long)start_dma,
1777                                (unsigned long long)end_trb_dma,
1778                                (unsigned long long)cur_seg->dma,
1779                                (unsigned long long)end_seg_dma);
1780
1781                if (end_trb_dma > 0) {
1782                        /* The end TRB is in this segment, so suspect should be here */
1783                        if (start_dma <= end_trb_dma) {
1784                                if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1785                                        return cur_seg;
1786                        } else {
1787                                /* Case for one segment with
1788                                 * a TD wrapped around to the top
1789                                 */
1790                                if ((suspect_dma >= start_dma &&
1791                                                        suspect_dma <= end_seg_dma) ||
1792                                                (suspect_dma >= cur_seg->dma &&
1793                                                 suspect_dma <= end_trb_dma))
1794                                        return cur_seg;
1795                        }
1796                        return NULL;
1797                } else {
1798                        /* Might still be somewhere in this segment */
1799                        if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1800                                return cur_seg;
1801                }
1802                cur_seg = cur_seg->next;
1803                start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1804        } while (cur_seg != start_seg);
1805
1806        return NULL;
1807}
1808
1809static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
1810                struct xhci_virt_ep *ep)
1811{
1812        /*
1813         * As part of low/full-speed endpoint-halt processing
1814         * we must clear the TT buffer (USB 2.0 specification 11.17.5).
1815         */
1816        if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
1817            (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
1818            !(ep->ep_state & EP_CLEARING_TT)) {
1819                ep->ep_state |= EP_CLEARING_TT;
1820                td->urb->ep->hcpriv = td->urb->dev;
1821                if (usb_hub_clear_tt_buffer(td->urb))
1822                        ep->ep_state &= ~EP_CLEARING_TT;
1823        }
1824}
1825
1826static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1827                unsigned int slot_id, unsigned int ep_index,
1828                unsigned int stream_id, struct xhci_td *td,
1829                enum xhci_ep_reset_type reset_type)
1830{
1831        struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1832        struct xhci_command *command;
1833
1834        /*
1835         * Avoid resetting endpoint if link is inactive. Can cause host hang.
1836         * Device will be reset soon to recover the link so don't do anything
1837         */
1838        if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR)
1839                return;
1840
1841        command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1842        if (!command)
1843                return;
1844
1845        ep->ep_state |= EP_HALTED;
1846
1847        xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1848
1849        if (reset_type == EP_HARD_RESET) {
1850                ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1851                xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1852                xhci_clear_hub_tt_buffer(xhci, td, ep);
1853        }
1854        xhci_ring_cmd_db(xhci);
1855}
1856
1857/* Check if an error has halted the endpoint ring.  The class driver will
1858 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1859 * However, a babble and other errors also halt the endpoint ring, and the class
1860 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1861 * Ring Dequeue Pointer command manually.
1862 */
1863static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1864                struct xhci_ep_ctx *ep_ctx,
1865                unsigned int trb_comp_code)
1866{
1867        /* TRB completion codes that may require a manual halt cleanup */
1868        if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1869                        trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1870                        trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1871                /* The 0.95 spec says a babbling control endpoint
1872                 * is not halted. The 0.96 spec says it is.  Some HW
1873                 * claims to be 0.95 compliant, but it halts the control
1874                 * endpoint anyway.  Check if a babble halted the
1875                 * endpoint.
1876                 */
1877                if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1878                        return 1;
1879
1880        return 0;
1881}
1882
1883int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1884{
1885        if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1886                /* Vendor defined "informational" completion code,
1887                 * treat as not-an-error.
1888                 */
1889                xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1890                                trb_comp_code);
1891                xhci_dbg(xhci, "Treating code as success.\n");
1892                return 1;
1893        }
1894        return 0;
1895}
1896
1897static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1898                struct xhci_ring *ep_ring, int *status)
1899{
1900        struct urb *urb = NULL;
1901
1902        /* Clean up the endpoint's TD list */
1903        urb = td->urb;
1904
1905        /* if a bounce buffer was used to align this td then unmap it */
1906        xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1907
1908        /* Do one last check of the actual transfer length.
1909         * If the host controller said we transferred more data than the buffer
1910         * length, urb->actual_length will be a very big number (since it's
1911         * unsigned).  Play it safe and say we didn't transfer anything.
1912         */
1913        if (urb->actual_length > urb->transfer_buffer_length) {
1914                xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1915                          urb->transfer_buffer_length, urb->actual_length);
1916                urb->actual_length = 0;
1917                *status = 0;
1918        }
1919        list_del_init(&td->td_list);
1920        /* Was this TD slated to be cancelled but completed anyway? */
1921        if (!list_empty(&td->cancelled_td_list))
1922                list_del_init(&td->cancelled_td_list);
1923
1924        inc_td_cnt(urb);
1925        /* Giveback the urb when all the tds are completed */
1926        if (last_td_in_urb(td)) {
1927                if ((urb->actual_length != urb->transfer_buffer_length &&
1928                     (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1929                    (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1930                        xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1931                                 urb, urb->actual_length,
1932                                 urb->transfer_buffer_length, *status);
1933
1934                /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
1935                if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1936                        *status = 0;
1937                xhci_giveback_urb_in_irq(xhci, td, *status);
1938        }
1939
1940        return 0;
1941}
1942
1943static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1944        struct xhci_transfer_event *event,
1945        struct xhci_virt_ep *ep, int *status)
1946{
1947        struct xhci_virt_device *xdev;
1948        struct xhci_ep_ctx *ep_ctx;
1949        struct xhci_ring *ep_ring;
1950        unsigned int slot_id;
1951        u32 trb_comp_code;
1952        int ep_index;
1953
1954        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1955        xdev = xhci->devs[slot_id];
1956        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1957        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1958        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1959        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1960
1961        if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1962                        trb_comp_code == COMP_STOPPED ||
1963                        trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1964                /* The Endpoint Stop Command completion will take care of any
1965                 * stopped TDs.  A stopped TD may be restarted, so don't update
1966                 * the ring dequeue pointer or take this TD off any lists yet.
1967                 */
1968                return 0;
1969        }
1970        if (trb_comp_code == COMP_STALL_ERROR ||
1971                xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1972                                                trb_comp_code)) {
1973                /* Issue a reset endpoint command to clear the host side
1974                 * halt, followed by a set dequeue command to move the
1975                 * dequeue pointer past the TD.
1976                 * The class driver clears the device side halt later.
1977                 */
1978                xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1979                                        ep_ring->stream_id, td, EP_HARD_RESET);
1980        } else {
1981                /* Update ring dequeue pointer */
1982                while (ep_ring->dequeue != td->last_trb)
1983                        inc_deq(xhci, ep_ring);
1984                inc_deq(xhci, ep_ring);
1985        }
1986
1987        return xhci_td_cleanup(xhci, td, ep_ring, status);
1988}
1989
1990/* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
1991static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
1992                           union xhci_trb *stop_trb)
1993{
1994        u32 sum;
1995        union xhci_trb *trb = ring->dequeue;
1996        struct xhci_segment *seg = ring->deq_seg;
1997
1998        for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
1999                if (!trb_is_noop(trb) && !trb_is_link(trb))
2000                        sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2001        }
2002        return sum;
2003}
2004
2005/*
2006 * Process control tds, update urb status and actual_length.
2007 */
2008static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2009        union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2010        struct xhci_virt_ep *ep, int *status)
2011{
2012        struct xhci_virt_device *xdev;
2013        unsigned int slot_id;
2014        int ep_index;
2015        struct xhci_ep_ctx *ep_ctx;
2016        u32 trb_comp_code;
2017        u32 remaining, requested;
2018        u32 trb_type;
2019
2020        trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2021        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2022        xdev = xhci->devs[slot_id];
2023        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2024        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2025        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2026        requested = td->urb->transfer_buffer_length;
2027        remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2028
2029        switch (trb_comp_code) {
2030        case COMP_SUCCESS:
2031                if (trb_type != TRB_STATUS) {
2032                        xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2033                                  (trb_type == TRB_DATA) ? "data" : "setup");
2034                        *status = -ESHUTDOWN;
2035                        break;
2036                }
2037                *status = 0;
2038                break;
2039        case COMP_SHORT_PACKET:
2040                *status = 0;
2041                break;
2042        case COMP_STOPPED_SHORT_PACKET:
2043                if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2044                        td->urb->actual_length = remaining;
2045                else
2046                        xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2047                goto finish_td;
2048        case COMP_STOPPED:
2049                switch (trb_type) {
2050                case TRB_SETUP:
2051                        td->urb->actual_length = 0;
2052                        goto finish_td;
2053                case TRB_DATA:
2054                case TRB_NORMAL:
2055                        td->urb->actual_length = requested - remaining;
2056                        goto finish_td;
2057                case TRB_STATUS:
2058                        td->urb->actual_length = requested;
2059                        goto finish_td;
2060                default:
2061                        xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2062                                  trb_type);
2063                        goto finish_td;
2064                }
2065        case COMP_STOPPED_LENGTH_INVALID:
2066                goto finish_td;
2067        default:
2068                if (!xhci_requires_manual_halt_cleanup(xhci,
2069                                                       ep_ctx, trb_comp_code))
2070                        break;
2071                xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2072                         trb_comp_code, ep_index);
2073                /* else fall through */
2074        case COMP_STALL_ERROR:
2075                /* Did we transfer part of the data (middle) phase? */
2076                if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2077                        td->urb->actual_length = requested - remaining;
2078                else if (!td->urb_length_set)
2079                        td->urb->actual_length = 0;
2080                goto finish_td;
2081        }
2082
2083        /* stopped at setup stage, no data transferred */
2084        if (trb_type == TRB_SETUP)
2085                goto finish_td;
2086
2087        /*
2088         * if on data stage then update the actual_length of the URB and flag it
2089         * as set, so it won't be overwritten in the event for the last TRB.
2090         */
2091        if (trb_type == TRB_DATA ||
2092                trb_type == TRB_NORMAL) {
2093                td->urb_length_set = true;
2094                td->urb->actual_length = requested - remaining;
2095                xhci_dbg(xhci, "Waiting for status stage event\n");
2096                return 0;
2097        }
2098
2099        /* at status stage */
2100        if (!td->urb_length_set)
2101                td->urb->actual_length = requested;
2102
2103finish_td:
2104        return finish_td(xhci, td, event, ep, status);
2105}
2106
2107/*
2108 * Process isochronous tds, update urb packet status and actual_length.
2109 */
2110static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2111        union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2112        struct xhci_virt_ep *ep, int *status)
2113{
2114        struct xhci_ring *ep_ring;
2115        struct urb_priv *urb_priv;
2116        int idx;
2117        struct usb_iso_packet_descriptor *frame;
2118        u32 trb_comp_code;
2119        bool sum_trbs_for_length = false;
2120        u32 remaining, requested, ep_trb_len;
2121        int short_framestatus;
2122
2123        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2124        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2125        urb_priv = td->urb->hcpriv;
2126        idx = urb_priv->num_tds_done;
2127        frame = &td->urb->iso_frame_desc[idx];
2128        requested = frame->length;
2129        remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2130        ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2131        short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2132                -EREMOTEIO : 0;
2133
2134        /* handle completion code */
2135        switch (trb_comp_code) {
2136        case COMP_SUCCESS:
2137                if (remaining) {
2138                        frame->status = short_framestatus;
2139                        if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2140                                sum_trbs_for_length = true;
2141                        break;
2142                }
2143                frame->status = 0;
2144                break;
2145        case COMP_SHORT_PACKET:
2146                frame->status = short_framestatus;
2147                sum_trbs_for_length = true;
2148                break;
2149        case COMP_BANDWIDTH_OVERRUN_ERROR:
2150                frame->status = -ECOMM;
2151                break;
2152        case COMP_ISOCH_BUFFER_OVERRUN:
2153        case COMP_BABBLE_DETECTED_ERROR:
2154                frame->status = -EOVERFLOW;
2155                break;
2156        case COMP_INCOMPATIBLE_DEVICE_ERROR:
2157        case COMP_STALL_ERROR:
2158                frame->status = -EPROTO;
2159                break;
2160        case COMP_USB_TRANSACTION_ERROR:
2161                frame->status = -EPROTO;
2162                if (ep_trb != td->last_trb)
2163                        return 0;
2164                break;
2165        case COMP_STOPPED:
2166                sum_trbs_for_length = true;
2167                break;
2168        case COMP_STOPPED_SHORT_PACKET:
2169                /* field normally containing residue now contains tranferred */
2170                frame->status = short_framestatus;
2171                requested = remaining;
2172                break;
2173        case COMP_STOPPED_LENGTH_INVALID:
2174                requested = 0;
2175                remaining = 0;
2176                break;
2177        default:
2178                sum_trbs_for_length = true;
2179                frame->status = -1;
2180                break;
2181        }
2182
2183        if (sum_trbs_for_length)
2184                frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2185                        ep_trb_len - remaining;
2186        else
2187                frame->actual_length = requested;
2188
2189        td->urb->actual_length += frame->actual_length;
2190
2191        return finish_td(xhci, td, event, ep, status);
2192}
2193
2194static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2195                        struct xhci_transfer_event *event,
2196                        struct xhci_virt_ep *ep, int *status)
2197{
2198        struct xhci_ring *ep_ring;
2199        struct urb_priv *urb_priv;
2200        struct usb_iso_packet_descriptor *frame;
2201        int idx;
2202
2203        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2204        urb_priv = td->urb->hcpriv;
2205        idx = urb_priv->num_tds_done;
2206        frame = &td->urb->iso_frame_desc[idx];
2207
2208        /* The transfer is partly done. */
2209        frame->status = -EXDEV;
2210
2211        /* calc actual length */
2212        frame->actual_length = 0;
2213
2214        /* Update ring dequeue pointer */
2215        while (ep_ring->dequeue != td->last_trb)
2216                inc_deq(xhci, ep_ring);
2217        inc_deq(xhci, ep_ring);
2218
2219        return xhci_td_cleanup(xhci, td, ep_ring, status);
2220}
2221
2222/*
2223 * Process bulk and interrupt tds, update urb status and actual_length.
2224 */
2225static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2226        union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2227        struct xhci_virt_ep *ep, int *status)
2228{
2229        struct xhci_slot_ctx *slot_ctx;
2230        struct xhci_ring *ep_ring;
2231        u32 trb_comp_code;
2232        u32 remaining, requested, ep_trb_len;
2233        unsigned int slot_id;
2234        int ep_index;
2235
2236        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2237        slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[slot_id]->out_ctx);
2238        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2239        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2240        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2241        remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2242        ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2243        requested = td->urb->transfer_buffer_length;
2244
2245        switch (trb_comp_code) {
2246        case COMP_SUCCESS:
2247                ep_ring->err_count = 0;
2248                /* handle success with untransferred data as short packet */
2249                if (ep_trb != td->last_trb || remaining) {
2250                        xhci_warn(xhci, "WARN Successful completion on short TX\n");
2251                        xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2252                                 td->urb->ep->desc.bEndpointAddress,
2253                                 requested, remaining);
2254                }
2255                *status = 0;
2256                break;
2257        case COMP_SHORT_PACKET:
2258                xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2259                         td->urb->ep->desc.bEndpointAddress,
2260                         requested, remaining);
2261                *status = 0;
2262                break;
2263        case COMP_STOPPED_SHORT_PACKET:
2264                td->urb->actual_length = remaining;
2265                goto finish_td;
2266        case COMP_STOPPED_LENGTH_INVALID:
2267                /* stopped on ep trb with invalid length, exclude it */
2268                ep_trb_len      = 0;
2269                remaining       = 0;
2270                break;
2271        case COMP_USB_TRANSACTION_ERROR:
2272                if ((ep_ring->err_count++ > MAX_SOFT_RETRY) ||
2273                    le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2274                        break;
2275                *status = 0;
2276                xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2277                                        ep_ring->stream_id, td, EP_SOFT_RESET);
2278                return 0;
2279        default:
2280                /* do nothing */
2281                break;
2282        }
2283
2284        if (ep_trb == td->last_trb)
2285                td->urb->actual_length = requested - remaining;
2286        else
2287                td->urb->actual_length =
2288                        sum_trb_lengths(xhci, ep_ring, ep_trb) +
2289                        ep_trb_len - remaining;
2290finish_td:
2291        if (remaining > requested) {
2292                xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2293                          remaining);
2294                td->urb->actual_length = 0;
2295        }
2296        return finish_td(xhci, td, event, ep, status);
2297}
2298
2299/*
2300 * If this function returns an error condition, it means it got a Transfer
2301 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2302 * At this point, the host controller is probably hosed and should be reset.
2303 */
2304static int handle_tx_event(struct xhci_hcd *xhci,
2305                struct xhci_transfer_event *event)
2306{
2307        struct xhci_virt_device *xdev;
2308        struct xhci_virt_ep *ep;
2309        struct xhci_ring *ep_ring;
2310        unsigned int slot_id;
2311        int ep_index;
2312        struct xhci_td *td = NULL;
2313        dma_addr_t ep_trb_dma;
2314        struct xhci_segment *ep_seg;
2315        union xhci_trb *ep_trb;
2316        int status = -EINPROGRESS;
2317        struct xhci_ep_ctx *ep_ctx;
2318        struct list_head *tmp;
2319        u32 trb_comp_code;
2320        int td_num = 0;
2321        bool handling_skipped_tds = false;
2322
2323        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2324        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2325        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2326        ep_trb_dma = le64_to_cpu(event->buffer);
2327
2328        xdev = xhci->devs[slot_id];
2329        if (!xdev) {
2330                xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n",
2331                         slot_id);
2332                goto err_out;
2333        }
2334
2335        ep = &xdev->eps[ep_index];
2336        ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2337        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2338
2339        if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2340                xhci_err(xhci,
2341                         "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2342                          slot_id, ep_index);
2343                goto err_out;
2344        }
2345
2346        /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2347        if (!ep_ring) {
2348                switch (trb_comp_code) {
2349                case COMP_STALL_ERROR:
2350                case COMP_USB_TRANSACTION_ERROR:
2351                case COMP_INVALID_STREAM_TYPE_ERROR:
2352                case COMP_INVALID_STREAM_ID_ERROR:
2353                        xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2354                                                     NULL, EP_SOFT_RESET);
2355                        goto cleanup;
2356                case COMP_RING_UNDERRUN:
2357                case COMP_RING_OVERRUN:
2358                case COMP_STOPPED_LENGTH_INVALID:
2359                        goto cleanup;
2360                default:
2361                        xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2362                                 slot_id, ep_index);
2363                        goto err_out;
2364                }
2365        }
2366
2367        /* Count current td numbers if ep->skip is set */
2368        if (ep->skip) {
2369                list_for_each(tmp, &ep_ring->td_list)
2370                        td_num++;
2371        }
2372
2373        /* Look for common error cases */
2374        switch (trb_comp_code) {
2375        /* Skip codes that require special handling depending on
2376         * transfer type
2377         */
2378        case COMP_SUCCESS:
2379                if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2380                        break;
2381                if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2382                        trb_comp_code = COMP_SHORT_PACKET;
2383                else
2384                        xhci_warn_ratelimited(xhci,
2385                                              "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2386                                              slot_id, ep_index);
2387        case COMP_SHORT_PACKET:
2388                break;
2389        /* Completion codes for endpoint stopped state */
2390        case COMP_STOPPED:
2391                xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2392                         slot_id, ep_index);
2393                break;
2394        case COMP_STOPPED_LENGTH_INVALID:
2395                xhci_dbg(xhci,
2396                         "Stopped on No-op or Link TRB for slot %u ep %u\n",
2397                         slot_id, ep_index);
2398                break;
2399        case COMP_STOPPED_SHORT_PACKET:
2400                xhci_dbg(xhci,
2401                         "Stopped with short packet transfer detected for slot %u ep %u\n",
2402                         slot_id, ep_index);
2403                break;
2404        /* Completion codes for endpoint halted state */
2405        case COMP_STALL_ERROR:
2406                xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2407                         ep_index);
2408                ep->ep_state |= EP_HALTED;
2409                status = -EPIPE;
2410                break;
2411        case COMP_SPLIT_TRANSACTION_ERROR:
2412        case COMP_USB_TRANSACTION_ERROR:
2413                xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2414                         slot_id, ep_index);
2415                status = -EPROTO;
2416                break;
2417        case COMP_BABBLE_DETECTED_ERROR:
2418                xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2419                         slot_id, ep_index);
2420                status = -EOVERFLOW;
2421                break;
2422        /* Completion codes for endpoint error state */
2423        case COMP_TRB_ERROR:
2424                xhci_warn(xhci,
2425                          "WARN: TRB error for slot %u ep %u on endpoint\n",
2426                          slot_id, ep_index);
2427                status = -EILSEQ;
2428                break;
2429        /* completion codes not indicating endpoint state change */
2430        case COMP_DATA_BUFFER_ERROR:
2431                xhci_warn(xhci,
2432                          "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2433                          slot_id, ep_index);
2434                status = -ENOSR;
2435                break;
2436        case COMP_BANDWIDTH_OVERRUN_ERROR:
2437                xhci_warn(xhci,
2438                          "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2439                          slot_id, ep_index);
2440                break;
2441        case COMP_ISOCH_BUFFER_OVERRUN:
2442                xhci_warn(xhci,
2443                          "WARN: buffer overrun event for slot %u ep %u on endpoint",
2444                          slot_id, ep_index);
2445                break;
2446        case COMP_RING_UNDERRUN:
2447                /*
2448                 * When the Isoch ring is empty, the xHC will generate
2449                 * a Ring Overrun Event for IN Isoch endpoint or Ring
2450                 * Underrun Event for OUT Isoch endpoint.
2451                 */
2452                xhci_dbg(xhci, "underrun event on endpoint\n");
2453                if (!list_empty(&ep_ring->td_list))
2454                        xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2455                                        "still with TDs queued?\n",
2456                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2457                                 ep_index);
2458                goto cleanup;
2459        case COMP_RING_OVERRUN:
2460                xhci_dbg(xhci, "overrun event on endpoint\n");
2461                if (!list_empty(&ep_ring->td_list))
2462                        xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2463                                        "still with TDs queued?\n",
2464                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2465                                 ep_index);
2466                goto cleanup;
2467        case COMP_MISSED_SERVICE_ERROR:
2468                /*
2469                 * When encounter missed service error, one or more isoc tds
2470                 * may be missed by xHC.
2471                 * Set skip flag of the ep_ring; Complete the missed tds as
2472                 * short transfer when process the ep_ring next time.
2473                 */
2474                ep->skip = true;
2475                xhci_dbg(xhci,
2476                         "Miss service interval error for slot %u ep %u, set skip flag\n",
2477                         slot_id, ep_index);
2478                goto cleanup;
2479        case COMP_NO_PING_RESPONSE_ERROR:
2480                ep->skip = true;
2481                xhci_dbg(xhci,
2482                         "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2483                         slot_id, ep_index);
2484                goto cleanup;
2485
2486        case COMP_INCOMPATIBLE_DEVICE_ERROR:
2487                /* needs disable slot command to recover */
2488                xhci_warn(xhci,
2489                          "WARN: detect an incompatible device for slot %u ep %u",
2490                          slot_id, ep_index);
2491                status = -EPROTO;
2492                break;
2493        default:
2494                if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2495                        status = 0;
2496                        break;
2497                }
2498                xhci_warn(xhci,
2499                          "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2500                          trb_comp_code, slot_id, ep_index);
2501                goto cleanup;
2502        }
2503
2504        do {
2505                /* This TRB should be in the TD at the head of this ring's
2506                 * TD list.
2507                 */
2508                if (list_empty(&ep_ring->td_list)) {
2509                        /*
2510                         * Don't print wanings if it's due to a stopped endpoint
2511                         * generating an extra completion event if the device
2512                         * was suspended. Or, a event for the last TRB of a
2513                         * short TD we already got a short event for.
2514                         * The short TD is already removed from the TD list.
2515                         */
2516
2517                        if (!(trb_comp_code == COMP_STOPPED ||
2518                              trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2519                              ep_ring->last_td_was_short)) {
2520                                xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2521                                                TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2522                                                ep_index);
2523                        }
2524                        if (ep->skip) {
2525                                ep->skip = false;
2526                                xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2527                                         slot_id, ep_index);
2528                        }
2529                        goto cleanup;
2530                }
2531
2532                /* We've skipped all the TDs on the ep ring when ep->skip set */
2533                if (ep->skip && td_num == 0) {
2534                        ep->skip = false;
2535                        xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2536                                 slot_id, ep_index);
2537                        goto cleanup;
2538                }
2539
2540                td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2541                                      td_list);
2542                if (ep->skip)
2543                        td_num--;
2544
2545                /* Is this a TRB in the currently executing TD? */
2546                ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2547                                td->last_trb, ep_trb_dma, false);
2548
2549                /*
2550                 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2551                 * is not in the current TD pointed by ep_ring->dequeue because
2552                 * that the hardware dequeue pointer still at the previous TRB
2553                 * of the current TD. The previous TRB maybe a Link TD or the
2554                 * last TRB of the previous TD. The command completion handle
2555                 * will take care the rest.
2556                 */
2557                if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2558                           trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2559                        goto cleanup;
2560                }
2561
2562                if (!ep_seg) {
2563                        if (!ep->skip ||
2564                            !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2565                                /* Some host controllers give a spurious
2566                                 * successful event after a short transfer.
2567                                 * Ignore it.
2568                                 */
2569                                if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2570                                                ep_ring->last_td_was_short) {
2571                                        ep_ring->last_td_was_short = false;
2572                                        goto cleanup;
2573                                }
2574                                /* HC is busted, give up! */
2575                                xhci_err(xhci,
2576                                        "ERROR Transfer event TRB DMA ptr not "
2577                                        "part of current TD ep_index %d "
2578                                        "comp_code %u\n", ep_index,
2579                                        trb_comp_code);
2580                                trb_in_td(xhci, ep_ring->deq_seg,
2581                                          ep_ring->dequeue, td->last_trb,
2582                                          ep_trb_dma, true);
2583                                return -ESHUTDOWN;
2584                        }
2585
2586                        skip_isoc_td(xhci, td, event, ep, &status);
2587                        goto cleanup;
2588                }
2589                if (trb_comp_code == COMP_SHORT_PACKET)
2590                        ep_ring->last_td_was_short = true;
2591                else
2592                        ep_ring->last_td_was_short = false;
2593
2594                if (ep->skip) {
2595                        xhci_dbg(xhci,
2596                                 "Found td. Clear skip flag for slot %u ep %u.\n",
2597                                 slot_id, ep_index);
2598                        ep->skip = false;
2599                }
2600
2601                ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2602                                                sizeof(*ep_trb)];
2603
2604                trace_xhci_handle_transfer(ep_ring,
2605                                (struct xhci_generic_trb *) ep_trb);
2606
2607                /*
2608                 * No-op TRB could trigger interrupts in a case where
2609                 * a URB was killed and a STALL_ERROR happens right
2610                 * after the endpoint ring stopped. Reset the halted
2611                 * endpoint. Otherwise, the endpoint remains stalled
2612                 * indefinitely.
2613                 */
2614                if (trb_is_noop(ep_trb)) {
2615                        if (trb_comp_code == COMP_STALL_ERROR ||
2616                            xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2617                                                              trb_comp_code))
2618                                xhci_cleanup_halted_endpoint(xhci, slot_id,
2619                                                             ep_index,
2620                                                             ep_ring->stream_id,
2621                                                             td, EP_HARD_RESET);
2622                        goto cleanup;
2623                }
2624
2625                /* update the urb's actual_length and give back to the core */
2626                if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2627                        process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2628                else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2629                        process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2630                else
2631                        process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2632                                             &status);
2633cleanup:
2634                handling_skipped_tds = ep->skip &&
2635                        trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2636                        trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2637
2638                /*
2639                 * Do not update event ring dequeue pointer if we're in a loop
2640                 * processing missed tds.
2641                 */
2642                if (!handling_skipped_tds)
2643                        inc_deq(xhci, xhci->event_ring);
2644
2645        /*
2646         * If ep->skip is set, it means there are missed tds on the
2647         * endpoint ring need to take care of.
2648         * Process them as short transfer until reach the td pointed by
2649         * the event.
2650         */
2651        } while (handling_skipped_tds);
2652
2653        return 0;
2654
2655err_out:
2656        xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2657                 (unsigned long long) xhci_trb_virt_to_dma(
2658                         xhci->event_ring->deq_seg,
2659                         xhci->event_ring->dequeue),
2660                 lower_32_bits(le64_to_cpu(event->buffer)),
2661                 upper_32_bits(le64_to_cpu(event->buffer)),
2662                 le32_to_cpu(event->transfer_len),
2663                 le32_to_cpu(event->flags));
2664        return -ENODEV;
2665}
2666
2667/*
2668 * This function handles all OS-owned events on the event ring.  It may drop
2669 * xhci->lock between event processing (e.g. to pass up port status changes).
2670 * Returns >0 for "possibly more events to process" (caller should call again),
2671 * otherwise 0 if done.  In future, <0 returns should indicate error code.
2672 */
2673static int xhci_handle_event(struct xhci_hcd *xhci)
2674{
2675        union xhci_trb *event;
2676        int update_ptrs = 1;
2677        int ret;
2678
2679        /* Event ring hasn't been allocated yet. */
2680        if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2681                xhci_err(xhci, "ERROR event ring not ready\n");
2682                return -ENOMEM;
2683        }
2684
2685        event = xhci->event_ring->dequeue;
2686        /* Does the HC or OS own the TRB? */
2687        if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2688            xhci->event_ring->cycle_state)
2689                return 0;
2690
2691        trace_xhci_handle_event(xhci->event_ring, &event->generic);
2692
2693        /*
2694         * Barrier between reading the TRB_CYCLE (valid) flag above and any
2695         * speculative reads of the event's flags/data below.
2696         */
2697        rmb();
2698        /* FIXME: Handle more event types. */
2699        switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2700        case TRB_TYPE(TRB_COMPLETION):
2701                handle_cmd_completion(xhci, &event->event_cmd);
2702                break;
2703        case TRB_TYPE(TRB_PORT_STATUS):
2704                handle_port_status(xhci, event);
2705                update_ptrs = 0;
2706                break;
2707        case TRB_TYPE(TRB_TRANSFER):
2708                ret = handle_tx_event(xhci, &event->trans_event);
2709                if (ret >= 0)
2710                        update_ptrs = 0;
2711                break;
2712        case TRB_TYPE(TRB_DEV_NOTE):
2713                handle_device_notification(xhci, event);
2714                break;
2715        default:
2716                if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2717                    TRB_TYPE(48))
2718                        handle_vendor_event(xhci, event);
2719                else
2720                        xhci_warn(xhci, "ERROR unknown event type %d\n",
2721                                  TRB_FIELD_TO_TYPE(
2722                                  le32_to_cpu(event->event_cmd.flags)));
2723        }
2724        /* Any of the above functions may drop and re-acquire the lock, so check
2725         * to make sure a watchdog timer didn't mark the host as non-responsive.
2726         */
2727        if (xhci->xhc_state & XHCI_STATE_DYING) {
2728                xhci_dbg(xhci, "xHCI host dying, returning from "
2729                                "event handler.\n");
2730                return 0;
2731        }
2732
2733        if (update_ptrs)
2734                /* Update SW event ring dequeue pointer */
2735                inc_deq(xhci, xhci->event_ring);
2736
2737        /* Are there more items on the event ring?  Caller will call us again to
2738         * check.
2739         */
2740        return 1;
2741}
2742
2743/*
2744 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2745 * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2746 * indicators of an event TRB error, but we check the status *first* to be safe.
2747 */
2748irqreturn_t xhci_irq(struct usb_hcd *hcd)
2749{
2750        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2751        union xhci_trb *event_ring_deq;
2752        irqreturn_t ret = IRQ_NONE;
2753        unsigned long flags;
2754        dma_addr_t deq;
2755        u64 temp_64;
2756        u32 status;
2757
2758        spin_lock_irqsave(&xhci->lock, flags);
2759        /* Check if the xHC generated the interrupt, or the irq is shared */
2760        status = readl(&xhci->op_regs->status);
2761        if (status == ~(u32)0) {
2762                xhci_hc_died(xhci);
2763                ret = IRQ_HANDLED;
2764                goto out;
2765        }
2766
2767        if (!(status & STS_EINT))
2768                goto out;
2769
2770        if (status & STS_FATAL) {
2771                xhci_warn(xhci, "WARNING: Host System Error\n");
2772                xhci_halt(xhci);
2773                ret = IRQ_HANDLED;
2774                goto out;
2775        }
2776
2777        /*
2778         * Clear the op reg interrupt status first,
2779         * so we can receive interrupts from other MSI-X interrupters.
2780         * Write 1 to clear the interrupt status.
2781         */
2782        status |= STS_EINT;
2783        writel(status, &xhci->op_regs->status);
2784
2785        if (!hcd->msi_enabled) {
2786                u32 irq_pending;
2787                irq_pending = readl(&xhci->ir_set->irq_pending);
2788                irq_pending |= IMAN_IP;
2789                writel(irq_pending, &xhci->ir_set->irq_pending);
2790        }
2791
2792        if (xhci->xhc_state & XHCI_STATE_DYING ||
2793            xhci->xhc_state & XHCI_STATE_HALTED) {
2794                xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2795                                "Shouldn't IRQs be disabled?\n");
2796                /* Clear the event handler busy flag (RW1C);
2797                 * the event ring should be empty.
2798                 */
2799                temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2800                xhci_write_64(xhci, temp_64 | ERST_EHB,
2801                                &xhci->ir_set->erst_dequeue);
2802                ret = IRQ_HANDLED;
2803                goto out;
2804        }
2805
2806        event_ring_deq = xhci->event_ring->dequeue;
2807        /* FIXME this should be a delayed service routine
2808         * that clears the EHB.
2809         */
2810        while (xhci_handle_event(xhci) > 0) {}
2811
2812        temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2813        /* If necessary, update the HW's version of the event ring deq ptr. */
2814        if (event_ring_deq != xhci->event_ring->dequeue) {
2815                deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2816                                xhci->event_ring->dequeue);
2817                if (deq == 0)
2818                        xhci_warn(xhci, "WARN something wrong with SW event "
2819                                        "ring dequeue ptr.\n");
2820                /* Update HC event ring dequeue pointer */
2821                temp_64 &= ERST_PTR_MASK;
2822                temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2823        }
2824
2825        /* Clear the event handler busy flag (RW1C); event ring is empty. */
2826        temp_64 |= ERST_EHB;
2827        xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2828        ret = IRQ_HANDLED;
2829
2830out:
2831        spin_unlock_irqrestore(&xhci->lock, flags);
2832
2833        return ret;
2834}
2835
2836irqreturn_t xhci_msi_irq(int irq, void *hcd)
2837{
2838        return xhci_irq(hcd);
2839}
2840
2841/****           Endpoint Ring Operations        ****/
2842
2843/*
2844 * Generic function for queueing a TRB on a ring.
2845 * The caller must have checked to make sure there's room on the ring.
2846 *
2847 * @more_trbs_coming:   Will you enqueue more TRBs before calling
2848 *                      prepare_transfer()?
2849 */
2850static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2851                bool more_trbs_coming,
2852                u32 field1, u32 field2, u32 field3, u32 field4)
2853{
2854        struct xhci_generic_trb *trb;
2855
2856        trb = &ring->enqueue->generic;
2857        trb->field[0] = cpu_to_le32(field1);
2858        trb->field[1] = cpu_to_le32(field2);
2859        trb->field[2] = cpu_to_le32(field3);
2860        trb->field[3] = cpu_to_le32(field4);
2861
2862        trace_xhci_queue_trb(ring, trb);
2863
2864        inc_enq(xhci, ring, more_trbs_coming);
2865}
2866
2867/*
2868 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2869 * FIXME allocate segments if the ring is full.
2870 */
2871static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2872                u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2873{
2874        unsigned int num_trbs_needed;
2875
2876        /* Make sure the endpoint has been added to xHC schedule */
2877        switch (ep_state) {
2878        case EP_STATE_DISABLED:
2879                /*
2880                 * USB core changed config/interfaces without notifying us,
2881                 * or hardware is reporting the wrong state.
2882                 */
2883                xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2884                return -ENOENT;
2885        case EP_STATE_ERROR:
2886                xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2887                /* FIXME event handling code for error needs to clear it */
2888                /* XXX not sure if this should be -ENOENT or not */
2889                return -EINVAL;
2890        case EP_STATE_HALTED:
2891                xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2892        case EP_STATE_STOPPED:
2893        case EP_STATE_RUNNING:
2894                break;
2895        default:
2896                xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2897                /*
2898                 * FIXME issue Configure Endpoint command to try to get the HC
2899                 * back into a known state.
2900                 */
2901                return -EINVAL;
2902        }
2903
2904        while (1) {
2905                if (room_on_ring(xhci, ep_ring, num_trbs))
2906                        break;
2907
2908                if (ep_ring == xhci->cmd_ring) {
2909                        xhci_err(xhci, "Do not support expand command ring\n");
2910                        return -ENOMEM;
2911                }
2912
2913                xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2914                                "ERROR no room on ep ring, try ring expansion");
2915                num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2916                if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2917                                        mem_flags)) {
2918                        xhci_err(xhci, "Ring expansion failed\n");
2919                        return -ENOMEM;
2920                }
2921        }
2922
2923        while (trb_is_link(ep_ring->enqueue)) {
2924                /* If we're not dealing with 0.95 hardware or isoc rings
2925                 * on AMD 0.96 host, clear the chain bit.
2926                 */
2927                if (!xhci_link_trb_quirk(xhci) &&
2928                    !(ep_ring->type == TYPE_ISOC &&
2929                      (xhci->quirks & XHCI_AMD_0x96_HOST)))
2930                        ep_ring->enqueue->link.control &=
2931                                cpu_to_le32(~TRB_CHAIN);
2932                else
2933                        ep_ring->enqueue->link.control |=
2934                                cpu_to_le32(TRB_CHAIN);
2935
2936                wmb();
2937                ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2938
2939                /* Toggle the cycle bit after the last ring segment. */
2940                if (link_trb_toggles_cycle(ep_ring->enqueue))
2941                        ep_ring->cycle_state ^= 1;
2942
2943                ep_ring->enq_seg = ep_ring->enq_seg->next;
2944                ep_ring->enqueue = ep_ring->enq_seg->trbs;
2945        }
2946        return 0;
2947}
2948
2949static int prepare_transfer(struct xhci_hcd *xhci,
2950                struct xhci_virt_device *xdev,
2951                unsigned int ep_index,
2952                unsigned int stream_id,
2953                unsigned int num_trbs,
2954                struct urb *urb,
2955                unsigned int td_index,
2956                gfp_t mem_flags)
2957{
2958        int ret;
2959        struct urb_priv *urb_priv;
2960        struct xhci_td  *td;
2961        struct xhci_ring *ep_ring;
2962        struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2963
2964        ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2965        if (!ep_ring) {
2966                xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2967                                stream_id);
2968                return -EINVAL;
2969        }
2970
2971        ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
2972                           num_trbs, mem_flags);
2973        if (ret)
2974                return ret;
2975
2976        urb_priv = urb->hcpriv;
2977        td = &urb_priv->td[td_index];
2978
2979        INIT_LIST_HEAD(&td->td_list);
2980        INIT_LIST_HEAD(&td->cancelled_td_list);
2981
2982        if (td_index == 0) {
2983                ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2984                if (unlikely(ret))
2985                        return ret;
2986        }
2987
2988        td->urb = urb;
2989        /* Add this TD to the tail of the endpoint ring's TD list */
2990        list_add_tail(&td->td_list, &ep_ring->td_list);
2991        td->start_seg = ep_ring->enq_seg;
2992        td->first_trb = ep_ring->enqueue;
2993
2994        return 0;
2995}
2996
2997unsigned int count_trbs(u64 addr, u64 len)
2998{
2999        unsigned int num_trbs;
3000
3001        num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3002                        TRB_MAX_BUFF_SIZE);
3003        if (num_trbs == 0)
3004                num_trbs++;
3005
3006        return num_trbs;
3007}
3008
3009static inline unsigned int count_trbs_needed(struct urb *urb)
3010{
3011        return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3012}
3013
3014static unsigned int count_sg_trbs_needed(struct urb *urb)
3015{
3016        struct scatterlist *sg;
3017        unsigned int i, len, full_len, num_trbs = 0;
3018
3019        full_len = urb->transfer_buffer_length;
3020
3021        for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3022                len = sg_dma_len(sg);
3023                num_trbs += count_trbs(sg_dma_address(sg), len);
3024                len = min_t(unsigned int, len, full_len);
3025                full_len -= len;
3026                if (full_len == 0)
3027                        break;
3028        }
3029
3030        return num_trbs;
3031}
3032
3033static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3034{
3035        u64 addr, len;
3036
3037        addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3038        len = urb->iso_frame_desc[i].length;
3039
3040        return count_trbs(addr, len);
3041}
3042
3043static void check_trb_math(struct urb *urb, int running_total)
3044{
3045        if (unlikely(running_total != urb->transfer_buffer_length))
3046                dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3047                                "queued %#x (%d), asked for %#x (%d)\n",
3048                                __func__,
3049                                urb->ep->desc.bEndpointAddress,
3050                                running_total, running_total,
3051                                urb->transfer_buffer_length,
3052                                urb->transfer_buffer_length);
3053}
3054
3055static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3056                unsigned int ep_index, unsigned int stream_id, int start_cycle,
3057                struct xhci_generic_trb *start_trb)
3058{
3059        /*
3060         * Pass all the TRBs to the hardware at once and make sure this write
3061         * isn't reordered.
3062         */
3063        wmb();
3064        if (start_cycle)
3065                start_trb->field[3] |= cpu_to_le32(start_cycle);
3066        else
3067                start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3068        xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3069}
3070
3071static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3072                                                struct xhci_ep_ctx *ep_ctx)
3073{
3074        int xhci_interval;
3075        int ep_interval;
3076
3077        xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3078        ep_interval = urb->interval;
3079
3080        /* Convert to microframes */
3081        if (urb->dev->speed == USB_SPEED_LOW ||
3082                        urb->dev->speed == USB_SPEED_FULL)
3083                ep_interval *= 8;
3084
3085        /* FIXME change this to a warning and a suggestion to use the new API
3086         * to set the polling interval (once the API is added).
3087         */
3088        if (xhci_interval != ep_interval) {
3089                dev_dbg_ratelimited(&urb->dev->dev,
3090                                "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3091                                ep_interval, ep_interval == 1 ? "" : "s",
3092                                xhci_interval, xhci_interval == 1 ? "" : "s");
3093                urb->interval = xhci_interval;
3094                /* Convert back to frames for LS/FS devices */
3095                if (urb->dev->speed == USB_SPEED_LOW ||
3096                                urb->dev->speed == USB_SPEED_FULL)
3097                        urb->interval /= 8;
3098        }
3099}
3100
3101/*
3102 * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3103 * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3104 * (comprised of sg list entries) can take several service intervals to
3105 * transmit.
3106 */
3107int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3108                struct urb *urb, int slot_id, unsigned int ep_index)
3109{
3110        struct xhci_ep_ctx *ep_ctx;
3111
3112        ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3113        check_interval(xhci, urb, ep_ctx);
3114
3115        return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3116}
3117
3118/*
3119 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3120 * packets remaining in the TD (*not* including this TRB).
3121 *
3122 * Total TD packet count = total_packet_count =
3123 *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3124 *
3125 * Packets transferred up to and including this TRB = packets_transferred =
3126 *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3127 *
3128 * TD size = total_packet_count - packets_transferred
3129 *
3130 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3131 * including this TRB, right shifted by 10
3132 *
3133 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3134 * This is taken care of in the TRB_TD_SIZE() macro
3135 *
3136 * The last TRB in a TD must have the TD size set to zero.
3137 */
3138static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3139                              int trb_buff_len, unsigned int td_total_len,
3140                              struct urb *urb, bool more_trbs_coming)
3141{
3142        u32 maxp, total_packet_count;
3143
3144        /* MTK xHCI 0.96 contains some features from 1.0 */
3145        if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3146                return ((td_total_len - transferred) >> 10);
3147
3148        /* One TRB with a zero-length data packet. */
3149        if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3150            trb_buff_len == td_total_len)
3151                return 0;
3152
3153        /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3154        if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3155                trb_buff_len = 0;
3156
3157        maxp = usb_endpoint_maxp(&urb->ep->desc);
3158        total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3159
3160        /* Queueing functions don't count the current TRB into transferred */
3161        return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3162}
3163
3164
3165static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3166                         u32 *trb_buff_len, struct xhci_segment *seg)
3167{
3168        struct device *dev = xhci_to_hcd(xhci)->self.controller;
3169        unsigned int unalign;
3170        unsigned int max_pkt;
3171        u32 new_buff_len;
3172        size_t len;
3173
3174        max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3175        unalign = (enqd_len + *trb_buff_len) % max_pkt;
3176
3177        /* we got lucky, last normal TRB data on segment is packet aligned */
3178        if (unalign == 0)
3179                return 0;
3180
3181        xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3182                 unalign, *trb_buff_len);
3183
3184        /* is the last nornal TRB alignable by splitting it */
3185        if (*trb_buff_len > unalign) {
3186                *trb_buff_len -= unalign;
3187                xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3188                return 0;
3189        }
3190
3191        /*
3192         * We want enqd_len + trb_buff_len to sum up to a number aligned to
3193         * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3194         * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3195         */
3196        new_buff_len = max_pkt - (enqd_len % max_pkt);
3197
3198        if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3199                new_buff_len = (urb->transfer_buffer_length - enqd_len);
3200
3201        /* create a max max_pkt sized bounce buffer pointed to by last trb */
3202        if (usb_urb_dir_out(urb)) {
3203                len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3204                                   seg->bounce_buf, new_buff_len, enqd_len);
3205                if (len != seg->bounce_len)
3206                        xhci_warn(xhci,
3207                                "WARN Wrong bounce buffer write length: %zu != %d\n",
3208                                len, seg->bounce_len);
3209                seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3210                                                 max_pkt, DMA_TO_DEVICE);
3211        } else {
3212                seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3213                                                 max_pkt, DMA_FROM_DEVICE);
3214        }
3215
3216        if (dma_mapping_error(dev, seg->bounce_dma)) {
3217                /* try without aligning. Some host controllers survive */
3218                xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3219                return 0;
3220        }
3221        *trb_buff_len = new_buff_len;
3222        seg->bounce_len = new_buff_len;
3223        seg->bounce_offs = enqd_len;
3224
3225        xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3226
3227        return 1;
3228}
3229
3230/* This is very similar to what ehci-q.c qtd_fill() does */
3231int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3232                struct urb *urb, int slot_id, unsigned int ep_index)
3233{
3234        struct xhci_ring *ring;
3235        struct urb_priv *urb_priv;
3236        struct xhci_td *td;
3237        struct xhci_generic_trb *start_trb;
3238        struct scatterlist *sg = NULL;
3239        bool more_trbs_coming = true;
3240        bool need_zero_pkt = false;
3241        bool first_trb = true;
3242        unsigned int num_trbs;
3243        unsigned int start_cycle, num_sgs = 0;
3244        unsigned int enqd_len, block_len, trb_buff_len, full_len;
3245        int sent_len, ret;
3246        u32 field, length_field, remainder;
3247        u64 addr, send_addr;
3248
3249        ring = xhci_urb_to_transfer_ring(xhci, urb);
3250        if (!ring)
3251                return -EINVAL;
3252
3253        full_len = urb->transfer_buffer_length;
3254        /* If we have scatter/gather list, we use it. */
3255        if (urb->num_sgs) {
3256                num_sgs = urb->num_mapped_sgs;
3257                sg = urb->sg;
3258                addr = (u64) sg_dma_address(sg);
3259                block_len = sg_dma_len(sg);
3260                num_trbs = count_sg_trbs_needed(urb);
3261        } else {
3262                num_trbs = count_trbs_needed(urb);
3263                addr = (u64) urb->transfer_dma;
3264                block_len = full_len;
3265        }
3266        ret = prepare_transfer(xhci, xhci->devs[slot_id],
3267                        ep_index, urb->stream_id,
3268                        num_trbs, urb, 0, mem_flags);
3269        if (unlikely(ret < 0))
3270                return ret;
3271
3272        urb_priv = urb->hcpriv;
3273
3274        /* Deal with URB_ZERO_PACKET - need one more td/trb */
3275        if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3276                need_zero_pkt = true;
3277
3278        td = &urb_priv->td[0];
3279
3280        /*
3281         * Don't give the first TRB to the hardware (by toggling the cycle bit)
3282         * until we've finished creating all the other TRBs.  The ring's cycle
3283         * state may change as we enqueue the other TRBs, so save it too.
3284         */
3285        start_trb = &ring->enqueue->generic;
3286        start_cycle = ring->cycle_state;
3287        send_addr = addr;
3288
3289        /* Queue the TRBs, even if they are zero-length */
3290        for (enqd_len = 0; first_trb || enqd_len < full_len;
3291                        enqd_len += trb_buff_len) {
3292                field = TRB_TYPE(TRB_NORMAL);
3293
3294                /* TRB buffer should not cross 64KB boundaries */
3295                trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3296                trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3297
3298                if (enqd_len + trb_buff_len > full_len)
3299                        trb_buff_len = full_len - enqd_len;
3300
3301                /* Don't change the cycle bit of the first TRB until later */
3302                if (first_trb) {
3303                        first_trb = false;
3304                        if (start_cycle == 0)
3305                                field |= TRB_CYCLE;
3306                } else
3307                        field |= ring->cycle_state;
3308
3309                /* Chain all the TRBs together; clear the chain bit in the last
3310                 * TRB to indicate it's the last TRB in the chain.
3311                 */
3312                if (enqd_len + trb_buff_len < full_len) {
3313                        field |= TRB_CHAIN;
3314                        if (trb_is_link(ring->enqueue + 1)) {
3315                                if (xhci_align_td(xhci, urb, enqd_len,
3316                                                  &trb_buff_len,
3317                                                  ring->enq_seg)) {
3318                                        send_addr = ring->enq_seg->bounce_dma;
3319                                        /* assuming TD won't span 2 segs */
3320                                        td->bounce_seg = ring->enq_seg;
3321                                }
3322                        }
3323                }
3324                if (enqd_len + trb_buff_len >= full_len) {
3325                        field &= ~TRB_CHAIN;
3326                        field |= TRB_IOC;
3327                        more_trbs_coming = false;
3328                        td->last_trb = ring->enqueue;
3329
3330                        if (xhci_urb_suitable_for_idt(urb)) {
3331                                memcpy(&send_addr, urb->transfer_buffer,
3332                                       trb_buff_len);
3333                                field |= TRB_IDT;
3334                        }
3335                }
3336
3337                /* Only set interrupt on short packet for IN endpoints */
3338                if (usb_urb_dir_in(urb))
3339                        field |= TRB_ISP;
3340
3341                /* Set the TRB length, TD size, and interrupter fields. */
3342                remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3343                                              full_len, urb, more_trbs_coming);
3344
3345                length_field = TRB_LEN(trb_buff_len) |
3346                        TRB_TD_SIZE(remainder) |
3347                        TRB_INTR_TARGET(0);
3348
3349                queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3350                                lower_32_bits(send_addr),
3351                                upper_32_bits(send_addr),
3352                                length_field,
3353                                field);
3354
3355                addr += trb_buff_len;
3356                sent_len = trb_buff_len;
3357
3358                while (sg && sent_len >= block_len) {
3359                        /* New sg entry */
3360                        --num_sgs;
3361                        sent_len -= block_len;
3362                        if (num_sgs != 0) {
3363                                sg = sg_next(sg);
3364                                block_len = sg_dma_len(sg);
3365                                addr = (u64) sg_dma_address(sg);
3366                                addr += sent_len;
3367                        }
3368                }
3369                block_len -= sent_len;
3370                send_addr = addr;
3371        }
3372
3373        if (need_zero_pkt) {
3374                ret = prepare_transfer(xhci, xhci->devs[slot_id],
3375                                       ep_index, urb->stream_id,
3376                                       1, urb, 1, mem_flags);
3377                urb_priv->td[1].last_trb = ring->enqueue;
3378                field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3379                queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3380        }
3381
3382        check_trb_math(urb, enqd_len);
3383        giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3384                        start_cycle, start_trb);
3385        return 0;
3386}
3387
3388/* Caller must have locked xhci->lock */
3389int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3390                struct urb *urb, int slot_id, unsigned int ep_index)
3391{
3392        struct xhci_ring *ep_ring;
3393        int num_trbs;
3394        int ret;
3395        struct usb_ctrlrequest *setup;
3396        struct xhci_generic_trb *start_trb;
3397        int start_cycle;
3398        u32 field;
3399        struct urb_priv *urb_priv;
3400        struct xhci_td *td;
3401
3402        ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3403        if (!ep_ring)
3404                return -EINVAL;
3405
3406        /*
3407         * Need to copy setup packet into setup TRB, so we can't use the setup
3408         * DMA address.
3409         */
3410        if (!urb->setup_packet)
3411                return -EINVAL;
3412
3413        /* 1 TRB for setup, 1 for status */
3414        num_trbs = 2;
3415        /*
3416         * Don't need to check if we need additional event data and normal TRBs,
3417         * since data in control transfers will never get bigger than 16MB
3418         * XXX: can we get a buffer that crosses 64KB boundaries?
3419         */
3420        if (urb->transfer_buffer_length > 0)
3421                num_trbs++;
3422        ret = prepare_transfer(xhci, xhci->devs[slot_id],
3423                        ep_index, urb->stream_id,
3424                        num_trbs, urb, 0, mem_flags);
3425        if (ret < 0)
3426                return ret;
3427
3428        urb_priv = urb->hcpriv;
3429        td = &urb_priv->td[0];
3430
3431        /*
3432         * Don't give the first TRB to the hardware (by toggling the cycle bit)
3433         * until we've finished creating all the other TRBs.  The ring's cycle
3434         * state may change as we enqueue the other TRBs, so save it too.
3435         */
3436        start_trb = &ep_ring->enqueue->generic;
3437        start_cycle = ep_ring->cycle_state;
3438
3439        /* Queue setup TRB - see section 6.4.1.2.1 */
3440        /* FIXME better way to translate setup_packet into two u32 fields? */
3441        setup = (struct usb_ctrlrequest *) urb->setup_packet;
3442        field = 0;
3443        field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3444        if (start_cycle == 0)
3445                field |= 0x1;
3446
3447        /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3448        if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3449                if (urb->transfer_buffer_length > 0) {
3450                        if (setup->bRequestType & USB_DIR_IN)
3451                                field |= TRB_TX_TYPE(TRB_DATA_IN);
3452                        else
3453                                field |= TRB_TX_TYPE(TRB_DATA_OUT);
3454                }
3455        }
3456
3457        queue_trb(xhci, ep_ring, true,
3458                  setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3459                  le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3460                  TRB_LEN(8) | TRB_INTR_TARGET(0),
3461                  /* Immediate data in pointer */
3462                  field);
3463
3464        /* If there's data, queue data TRBs */
3465        /* Only set interrupt on short packet for IN endpoints */
3466        if (usb_urb_dir_in(urb))
3467                field = TRB_ISP | TRB_TYPE(TRB_DATA);
3468        else
3469                field = TRB_TYPE(TRB_DATA);
3470
3471        if (urb->transfer_buffer_length > 0) {
3472                u32 length_field, remainder;
3473                u64 addr;
3474
3475                if (xhci_urb_suitable_for_idt(urb)) {
3476                        memcpy(&addr, urb->transfer_buffer,
3477                               urb->transfer_buffer_length);
3478                        field |= TRB_IDT;
3479                } else {
3480                        addr = (u64) urb->transfer_dma;
3481                }
3482
3483                remainder = xhci_td_remainder(xhci, 0,
3484                                urb->transfer_buffer_length,
3485                                urb->transfer_buffer_length,
3486                                urb, 1);
3487                length_field = TRB_LEN(urb->transfer_buffer_length) |
3488                                TRB_TD_SIZE(remainder) |
3489                                TRB_INTR_TARGET(0);
3490                if (setup->bRequestType & USB_DIR_IN)
3491                        field |= TRB_DIR_IN;
3492                queue_trb(xhci, ep_ring, true,
3493                                lower_32_bits(addr),
3494                                upper_32_bits(addr),
3495                                length_field,
3496                                field | ep_ring->cycle_state);
3497        }
3498
3499        /* Save the DMA address of the last TRB in the TD */
3500        td->last_trb = ep_ring->enqueue;
3501
3502        /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3503        /* If the device sent data, the status stage is an OUT transfer */
3504        if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3505                field = 0;
3506        else
3507                field = TRB_DIR_IN;
3508        queue_trb(xhci, ep_ring, false,
3509                        0,
3510                        0,
3511                        TRB_INTR_TARGET(0),
3512                        /* Event on completion */
3513                        field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3514
3515        giveback_first_trb(xhci, slot_id, ep_index, 0,
3516                        start_cycle, start_trb);
3517        return 0;
3518}
3519
3520/*
3521 * The transfer burst count field of the isochronous TRB defines the number of
3522 * bursts that are required to move all packets in this TD.  Only SuperSpeed
3523 * devices can burst up to bMaxBurst number of packets per service interval.
3524 * This field is zero based, meaning a value of zero in the field means one
3525 * burst.  Basically, for everything but SuperSpeed devices, this field will be
3526 * zero.  Only xHCI 1.0 host controllers support this field.
3527 */
3528static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3529                struct urb *urb, unsigned int total_packet_count)
3530{
3531        unsigned int max_burst;
3532
3533        if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3534                return 0;
3535
3536        max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3537        return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3538}
3539
3540/*
3541 * Returns the number of packets in the last "burst" of packets.  This field is
3542 * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3543 * the last burst packet count is equal to the total number of packets in the
3544 * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3545 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3546 * contain 1 to (bMaxBurst + 1) packets.
3547 */
3548static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3549                struct urb *urb, unsigned int total_packet_count)
3550{
3551        unsigned int max_burst;
3552        unsigned int residue;
3553
3554        if (xhci->hci_version < 0x100)
3555                return 0;
3556
3557        if (urb->dev->speed >= USB_SPEED_SUPER) {
3558                /* bMaxBurst is zero based: 0 means 1 packet per burst */
3559                max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3560                residue = total_packet_count % (max_burst + 1);
3561                /* If residue is zero, the last burst contains (max_burst + 1)
3562                 * number of packets, but the TLBPC field is zero-based.
3563                 */
3564                if (residue == 0)
3565                        return max_burst;
3566                return residue - 1;
3567        }
3568        if (total_packet_count == 0)
3569                return 0;
3570        return total_packet_count - 1;
3571}
3572
3573/*
3574 * Calculates Frame ID field of the isochronous TRB identifies the
3575 * target frame that the Interval associated with this Isochronous
3576 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3577 *
3578 * Returns actual frame id on success, negative value on error.
3579 */
3580static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3581                struct urb *urb, int index)
3582{
3583        int start_frame, ist, ret = 0;
3584        int start_frame_id, end_frame_id, current_frame_id;
3585
3586        if (urb->dev->speed == USB_SPEED_LOW ||
3587                        urb->dev->speed == USB_SPEED_FULL)
3588                start_frame = urb->start_frame + index * urb->interval;
3589        else
3590                start_frame = (urb->start_frame + index * urb->interval) >> 3;
3591
3592        /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3593         *
3594         * If bit [3] of IST is cleared to '0', software can add a TRB no
3595         * later than IST[2:0] Microframes before that TRB is scheduled to
3596         * be executed.
3597         * If bit [3] of IST is set to '1', software can add a TRB no later
3598         * than IST[2:0] Frames before that TRB is scheduled to be executed.
3599         */
3600        ist = HCS_IST(xhci->hcs_params2) & 0x7;
3601        if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3602                ist <<= 3;
3603
3604        /* Software shall not schedule an Isoch TD with a Frame ID value that
3605         * is less than the Start Frame ID or greater than the End Frame ID,
3606         * where:
3607         *
3608         * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3609         * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3610         *
3611         * Both the End Frame ID and Start Frame ID values are calculated
3612         * in microframes. When software determines the valid Frame ID value;
3613         * The End Frame ID value should be rounded down to the nearest Frame
3614         * boundary, and the Start Frame ID value should be rounded up to the
3615         * nearest Frame boundary.
3616         */
3617        current_frame_id = readl(&xhci->run_regs->microframe_index);
3618        start_frame_id = roundup(current_frame_id + ist + 1, 8);
3619        end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3620
3621        start_frame &= 0x7ff;
3622        start_frame_id = (start_frame_id >> 3) & 0x7ff;
3623        end_frame_id = (end_frame_id >> 3) & 0x7ff;
3624
3625        xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3626                 __func__, index, readl(&xhci->run_regs->microframe_index),
3627                 start_frame_id, end_frame_id, start_frame);
3628
3629        if (start_frame_id < end_frame_id) {
3630                if (start_frame > end_frame_id ||
3631                                start_frame < start_frame_id)
3632                        ret = -EINVAL;
3633        } else if (start_frame_id > end_frame_id) {
3634                if ((start_frame > end_frame_id &&
3635                                start_frame < start_frame_id))
3636                        ret = -EINVAL;
3637        } else {
3638                        ret = -EINVAL;
3639        }
3640
3641        if (index == 0) {
3642                if (ret == -EINVAL || start_frame == start_frame_id) {
3643                        start_frame = start_frame_id + 1;
3644                        if (urb->dev->speed == USB_SPEED_LOW ||
3645                                        urb->dev->speed == USB_SPEED_FULL)
3646                                urb->start_frame = start_frame;
3647                        else
3648                                urb->start_frame = start_frame << 3;
3649                        ret = 0;
3650                }
3651        }
3652
3653        if (ret) {
3654                xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3655                                start_frame, current_frame_id, index,
3656                                start_frame_id, end_frame_id);
3657                xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3658                return ret;
3659        }
3660
3661        return start_frame;
3662}
3663
3664/* This is for isoc transfer */
3665static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3666                struct urb *urb, int slot_id, unsigned int ep_index)
3667{
3668        struct xhci_ring *ep_ring;
3669        struct urb_priv *urb_priv;
3670        struct xhci_td *td;
3671        int num_tds, trbs_per_td;
3672        struct xhci_generic_trb *start_trb;
3673        bool first_trb;
3674        int start_cycle;
3675        u32 field, length_field;
3676        int running_total, trb_buff_len, td_len, td_remain_len, ret;
3677        u64 start_addr, addr;
3678        int i, j;
3679        bool more_trbs_coming;
3680        struct xhci_virt_ep *xep;
3681        int frame_id;
3682
3683        xep = &xhci->devs[slot_id]->eps[ep_index];
3684        ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3685
3686        num_tds = urb->number_of_packets;
3687        if (num_tds < 1) {
3688                xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3689                return -EINVAL;
3690        }
3691        start_addr = (u64) urb->transfer_dma;
3692        start_trb = &ep_ring->enqueue->generic;
3693        start_cycle = ep_ring->cycle_state;
3694
3695        urb_priv = urb->hcpriv;
3696        /* Queue the TRBs for each TD, even if they are zero-length */
3697        for (i = 0; i < num_tds; i++) {
3698                unsigned int total_pkt_count, max_pkt;
3699                unsigned int burst_count, last_burst_pkt_count;
3700                u32 sia_frame_id;
3701
3702                first_trb = true;
3703                running_total = 0;
3704                addr = start_addr + urb->iso_frame_desc[i].offset;
3705                td_len = urb->iso_frame_desc[i].length;
3706                td_remain_len = td_len;
3707                max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3708                total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3709
3710                /* A zero-length transfer still involves at least one packet. */
3711                if (total_pkt_count == 0)
3712                        total_pkt_count++;
3713                burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3714                last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3715                                                        urb, total_pkt_count);
3716
3717                trbs_per_td = count_isoc_trbs_needed(urb, i);
3718
3719                ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3720                                urb->stream_id, trbs_per_td, urb, i, mem_flags);
3721                if (ret < 0) {
3722                        if (i == 0)
3723                                return ret;
3724                        goto cleanup;
3725                }
3726                td = &urb_priv->td[i];
3727
3728                /* use SIA as default, if frame id is used overwrite it */
3729                sia_frame_id = TRB_SIA;
3730                if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3731                    HCC_CFC(xhci->hcc_params)) {
3732                        frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3733                        if (frame_id >= 0)
3734                                sia_frame_id = TRB_FRAME_ID(frame_id);
3735                }
3736                /*
3737                 * Set isoc specific data for the first TRB in a TD.
3738                 * Prevent HW from getting the TRBs by keeping the cycle state
3739                 * inverted in the first TDs isoc TRB.
3740                 */
3741                field = TRB_TYPE(TRB_ISOC) |
3742                        TRB_TLBPC(last_burst_pkt_count) |
3743                        sia_frame_id |
3744                        (i ? ep_ring->cycle_state : !start_cycle);
3745
3746                /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3747                if (!xep->use_extended_tbc)
3748                        field |= TRB_TBC(burst_count);
3749
3750                /* fill the rest of the TRB fields, and remaining normal TRBs */
3751                for (j = 0; j < trbs_per_td; j++) {
3752                        u32 remainder = 0;
3753
3754                        /* only first TRB is isoc, overwrite otherwise */
3755                        if (!first_trb)
3756                                field = TRB_TYPE(TRB_NORMAL) |
3757                                        ep_ring->cycle_state;
3758
3759                        /* Only set interrupt on short packet for IN EPs */
3760                        if (usb_urb_dir_in(urb))
3761                                field |= TRB_ISP;
3762
3763                        /* Set the chain bit for all except the last TRB  */
3764                        if (j < trbs_per_td - 1) {
3765                                more_trbs_coming = true;
3766                                field |= TRB_CHAIN;
3767                        } else {
3768                                more_trbs_coming = false;
3769                                td->last_trb = ep_ring->enqueue;
3770                                field |= TRB_IOC;
3771                                /* set BEI, except for the last TD */
3772                                if (xhci->hci_version >= 0x100 &&
3773                                    !(xhci->quirks & XHCI_AVOID_BEI) &&
3774                                    i < num_tds - 1)
3775                                        field |= TRB_BEI;
3776                        }
3777                        /* Calculate TRB length */
3778                        trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3779                        if (trb_buff_len > td_remain_len)
3780                                trb_buff_len = td_remain_len;
3781
3782                        /* Set the TRB length, TD size, & interrupter fields. */
3783                        remainder = xhci_td_remainder(xhci, running_total,
3784                                                   trb_buff_len, td_len,
3785                                                   urb, more_trbs_coming);
3786
3787                        length_field = TRB_LEN(trb_buff_len) |
3788                                TRB_INTR_TARGET(0);
3789
3790                        /* xhci 1.1 with ETE uses TD Size field for TBC */
3791                        if (first_trb && xep->use_extended_tbc)
3792                                length_field |= TRB_TD_SIZE_TBC(burst_count);
3793                        else
3794                                length_field |= TRB_TD_SIZE(remainder);
3795                        first_trb = false;
3796
3797                        queue_trb(xhci, ep_ring, more_trbs_coming,
3798                                lower_32_bits(addr),
3799                                upper_32_bits(addr),
3800                                length_field,
3801                                field);
3802                        running_total += trb_buff_len;
3803
3804                        addr += trb_buff_len;
3805                        td_remain_len -= trb_buff_len;
3806                }
3807
3808                /* Check TD length */
3809                if (running_total != td_len) {
3810                        xhci_err(xhci, "ISOC TD length unmatch\n");
3811                        ret = -EINVAL;
3812                        goto cleanup;
3813                }
3814        }
3815
3816        /* store the next frame id */
3817        if (HCC_CFC(xhci->hcc_params))
3818                xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3819
3820        if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3821                if (xhci->quirks & XHCI_AMD_PLL_FIX)
3822                        usb_amd_quirk_pll_disable();
3823        }
3824        xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3825
3826        giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3827                        start_cycle, start_trb);
3828        return 0;
3829cleanup:
3830        /* Clean up a partially enqueued isoc transfer. */
3831
3832        for (i--; i >= 0; i--)
3833                list_del_init(&urb_priv->td[i].td_list);
3834
3835        /* Use the first TD as a temporary variable to turn the TDs we've queued
3836         * into No-ops with a software-owned cycle bit. That way the hardware
3837         * won't accidentally start executing bogus TDs when we partially
3838         * overwrite them.  td->first_trb and td->start_seg are already set.
3839         */
3840        urb_priv->td[0].last_trb = ep_ring->enqueue;
3841        /* Every TRB except the first & last will have its cycle bit flipped. */
3842        td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3843
3844        /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3845        ep_ring->enqueue = urb_priv->td[0].first_trb;
3846        ep_ring->enq_seg = urb_priv->td[0].start_seg;
3847        ep_ring->cycle_state = start_cycle;
3848        ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3849        usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3850        return ret;
3851}
3852
3853/*
3854 * Check transfer ring to guarantee there is enough room for the urb.
3855 * Update ISO URB start_frame and interval.
3856 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3857 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3858 * Contiguous Frame ID is not supported by HC.
3859 */
3860int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3861                struct urb *urb, int slot_id, unsigned int ep_index)
3862{
3863        struct xhci_virt_device *xdev;
3864        struct xhci_ring *ep_ring;
3865        struct xhci_ep_ctx *ep_ctx;
3866        int start_frame;
3867        int num_tds, num_trbs, i;
3868        int ret;
3869        struct xhci_virt_ep *xep;
3870        int ist;
3871
3872        xdev = xhci->devs[slot_id];
3873        xep = &xhci->devs[slot_id]->eps[ep_index];
3874        ep_ring = xdev->eps[ep_index].ring;
3875        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3876
3877        num_trbs = 0;
3878        num_tds = urb->number_of_packets;
3879        for (i = 0; i < num_tds; i++)
3880                num_trbs += count_isoc_trbs_needed(urb, i);
3881
3882        /* Check the ring to guarantee there is enough room for the whole urb.
3883         * Do not insert any td of the urb to the ring if the check failed.
3884         */
3885        ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3886                           num_trbs, mem_flags);
3887        if (ret)
3888                return ret;
3889
3890        /*
3891         * Check interval value. This should be done before we start to
3892         * calculate the start frame value.
3893         */
3894        check_interval(xhci, urb, ep_ctx);
3895
3896        /* Calculate the start frame and put it in urb->start_frame. */
3897        if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3898                if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3899                        urb->start_frame = xep->next_frame_id;
3900                        goto skip_start_over;
3901                }
3902        }
3903
3904        start_frame = readl(&xhci->run_regs->microframe_index);
3905        start_frame &= 0x3fff;
3906        /*
3907         * Round up to the next frame and consider the time before trb really
3908         * gets scheduled by hardare.
3909         */
3910        ist = HCS_IST(xhci->hcs_params2) & 0x7;
3911        if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3912                ist <<= 3;
3913        start_frame += ist + XHCI_CFC_DELAY;
3914        start_frame = roundup(start_frame, 8);
3915
3916        /*
3917         * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3918         * is greate than 8 microframes.
3919         */
3920        if (urb->dev->speed == USB_SPEED_LOW ||
3921                        urb->dev->speed == USB_SPEED_FULL) {
3922                start_frame = roundup(start_frame, urb->interval << 3);
3923                urb->start_frame = start_frame >> 3;
3924        } else {
3925                start_frame = roundup(start_frame, urb->interval);
3926                urb->start_frame = start_frame;
3927        }
3928
3929skip_start_over:
3930        ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3931
3932        return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3933}
3934
3935/****           Command Ring Operations         ****/
3936
3937/* Generic function for queueing a command TRB on the command ring.
3938 * Check to make sure there's room on the command ring for one command TRB.
3939 * Also check that there's room reserved for commands that must not fail.
3940 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3941 * then only check for the number of reserved spots.
3942 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3943 * because the command event handler may want to resubmit a failed command.
3944 */
3945static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3946                         u32 field1, u32 field2,
3947                         u32 field3, u32 field4, bool command_must_succeed)
3948{
3949        int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3950        int ret;
3951
3952        if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3953                (xhci->xhc_state & XHCI_STATE_HALTED)) {
3954                xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3955                return -ESHUTDOWN;
3956        }
3957
3958        if (!command_must_succeed)
3959                reserved_trbs++;
3960
3961        ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3962                        reserved_trbs, GFP_ATOMIC);
3963        if (ret < 0) {
3964                xhci_err(xhci, "ERR: No room for command on command ring\n");
3965                if (command_must_succeed)
3966                        xhci_err(xhci, "ERR: Reserved TRB counting for "
3967                                        "unfailable commands failed.\n");
3968                return ret;
3969        }
3970
3971        cmd->command_trb = xhci->cmd_ring->enqueue;
3972
3973        /* if there are no other commands queued we start the timeout timer */
3974        if (list_empty(&xhci->cmd_list)) {
3975                xhci->current_cmd = cmd;
3976                xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3977        }
3978
3979        list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3980
3981        queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3982                        field4 | xhci->cmd_ring->cycle_state);
3983        return 0;
3984}
3985
3986/* Queue a slot enable or disable request on the command ring */
3987int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3988                u32 trb_type, u32 slot_id)
3989{
3990        return queue_command(xhci, cmd, 0, 0, 0,
3991                        TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3992}
3993
3994/* Queue an address device command TRB */
3995int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3996                dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3997{
3998        return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3999                        upper_32_bits(in_ctx_ptr), 0,
4000                        TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4001                        | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4002}
4003
4004int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4005                u32 field1, u32 field2, u32 field3, u32 field4)
4006{
4007        return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4008}
4009
4010/* Queue a reset device command TRB */
4011int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4012                u32 slot_id)
4013{
4014        return queue_command(xhci, cmd, 0, 0, 0,
4015                        TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4016                        false);
4017}
4018
4019/* Queue a configure endpoint command TRB */
4020int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4021                struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4022                u32 slot_id, bool command_must_succeed)
4023{
4024        return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4025                        upper_32_bits(in_ctx_ptr), 0,
4026                        TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4027                        command_must_succeed);
4028}
4029
4030/* Queue an evaluate context command TRB */
4031int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4032                dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4033{
4034        return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4035                        upper_32_bits(in_ctx_ptr), 0,
4036                        TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4037                        command_must_succeed);
4038}
4039
4040/*
4041 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4042 * activity on an endpoint that is about to be suspended.
4043 */
4044int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4045                             int slot_id, unsigned int ep_index, int suspend)
4046{
4047        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4048        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4049        u32 type = TRB_TYPE(TRB_STOP_RING);
4050        u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4051
4052        return queue_command(xhci, cmd, 0, 0, 0,
4053                        trb_slot_id | trb_ep_index | type | trb_suspend, false);
4054}
4055
4056/* Set Transfer Ring Dequeue Pointer command */
4057void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4058                unsigned int slot_id, unsigned int ep_index,
4059                struct xhci_dequeue_state *deq_state)
4060{
4061        dma_addr_t addr;
4062        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4063        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4064        u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4065        u32 trb_sct = 0;
4066        u32 type = TRB_TYPE(TRB_SET_DEQ);
4067        struct xhci_virt_ep *ep;
4068        struct xhci_command *cmd;
4069        int ret;
4070
4071        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4072                "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4073                deq_state->new_deq_seg,
4074                (unsigned long long)deq_state->new_deq_seg->dma,
4075                deq_state->new_deq_ptr,
4076                (unsigned long long)xhci_trb_virt_to_dma(
4077                        deq_state->new_deq_seg, deq_state->new_deq_ptr),
4078                deq_state->new_cycle_state);
4079
4080        addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4081                                    deq_state->new_deq_ptr);
4082        if (addr == 0) {
4083                xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4084                xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4085                          deq_state->new_deq_seg, deq_state->new_deq_ptr);
4086                return;
4087        }
4088        ep = &xhci->devs[slot_id]->eps[ep_index];
4089        if ((ep->ep_state & SET_DEQ_PENDING)) {
4090                xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4091                xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4092                return;
4093        }
4094
4095        /* This function gets called from contexts where it cannot sleep */
4096        cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4097        if (!cmd)
4098                return;
4099
4100        ep->queued_deq_seg = deq_state->new_deq_seg;
4101        ep->queued_deq_ptr = deq_state->new_deq_ptr;
4102        if (deq_state->stream_id)
4103                trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4104        ret = queue_command(xhci, cmd,
4105                lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4106                upper_32_bits(addr), trb_stream_id,
4107                trb_slot_id | trb_ep_index | type, false);
4108        if (ret < 0) {
4109                xhci_free_command(xhci, cmd);
4110                return;
4111        }
4112
4113        /* Stop the TD queueing code from ringing the doorbell until
4114         * this command completes.  The HC won't set the dequeue pointer
4115         * if the ring is running, and ringing the doorbell starts the
4116         * ring running.
4117         */
4118        ep->ep_state |= SET_DEQ_PENDING;
4119}
4120
4121int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4122                        int slot_id, unsigned int ep_index,
4123                        enum xhci_ep_reset_type reset_type)
4124{
4125        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4126        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4127        u32 type = TRB_TYPE(TRB_RESET_EP);
4128
4129        if (reset_type == EP_SOFT_RESET)
4130                type |= TRB_TSP;
4131
4132        return queue_command(xhci, cmd, 0, 0, 0,
4133                        trb_slot_id | trb_ep_index | type, false);
4134}
4135