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11#include <linux/dma-mapping.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/platform_device.h>
17
18#include "mtu3.h"
19#include "mtu3_debug.h"
20#include "mtu3_trace.h"
21
22static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
23{
24 struct mtu3_fifo_info *fifo = mep->fifo;
25 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
26 u32 start_bit;
27
28
29 num_bits = roundup_pow_of_two(num_bits);
30 if (num_bits > fifo->limit)
31 return -EINVAL;
32
33 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
34 num_bits = num_bits * (mep->slot + 1);
35 start_bit = bitmap_find_next_zero_area(fifo->bitmap,
36 fifo->limit, 0, num_bits, 0);
37 if (start_bit >= fifo->limit)
38 return -EOVERFLOW;
39
40 bitmap_set(fifo->bitmap, start_bit, num_bits);
41 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
42 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
43
44 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
45 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
46
47 return mep->fifo_addr;
48}
49
50static void ep_fifo_free(struct mtu3_ep *mep)
51{
52 struct mtu3_fifo_info *fifo = mep->fifo;
53 u32 addr = mep->fifo_addr;
54 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
55 u32 start_bit;
56
57 if (unlikely(addr < fifo->base || bits > fifo->limit))
58 return;
59
60 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
61 bitmap_clear(fifo->bitmap, start_bit, bits);
62 mep->fifo_size = 0;
63 mep->fifo_seg_size = 0;
64
65 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
66 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
67}
68
69
70static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
71{
72
73 if (enable)
74 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
75 else
76 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
77
78 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
79}
80
81
82static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
83{
84 if (enable) {
85 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
86 SOFT_CONN | SUSPENDM_ENABLE);
87 } else {
88 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
89 SOFT_CONN | SUSPENDM_ENABLE);
90 }
91 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
92}
93
94
95static int mtu3_device_enable(struct mtu3 *mtu)
96{
97 void __iomem *ibase = mtu->ippc_base;
98 u32 check_clk = 0;
99
100 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
101
102 if (mtu->is_u3_ip) {
103 check_clk = SSUSB_U3_MAC_RST_B_STS;
104 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
105 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
106 SSUSB_U3_PORT_HOST_SEL));
107 }
108 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
109 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
110 SSUSB_U2_PORT_HOST_SEL));
111
112 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
113 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
114 if (mtu->is_u3_ip)
115 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
116 SSUSB_U3_PORT_DUAL_MODE);
117 }
118
119 return ssusb_check_clocks(mtu->ssusb, check_clk);
120}
121
122static void mtu3_device_disable(struct mtu3 *mtu)
123{
124 void __iomem *ibase = mtu->ippc_base;
125
126 if (mtu->is_u3_ip)
127 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
128 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
129
130 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
131 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
132
133 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
134 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
135
136 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
137}
138
139
140static void mtu3_device_reset(struct mtu3 *mtu)
141{
142 void __iomem *ibase = mtu->ippc_base;
143
144 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
145 udelay(1);
146 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
147}
148
149
150static void mtu3_intr_disable(struct mtu3 *mtu)
151{
152 void __iomem *mbase = mtu->mac_base;
153
154
155 mtu3_writel(mbase, U3D_LV1IECR, ~0x0);
156
157 mtu3_writel(mbase, U3D_EPIECR, ~0x0);
158}
159
160static void mtu3_intr_status_clear(struct mtu3 *mtu)
161{
162 void __iomem *mbase = mtu->mac_base;
163
164
165 mtu3_writel(mbase, U3D_EPISR, ~0x0);
166
167 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
168
169 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
170
171 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
172}
173
174
175static void mtu3_intr_enable(struct mtu3 *mtu)
176{
177 void __iomem *mbase = mtu->mac_base;
178 u32 value;
179
180
181 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
182 mtu3_writel(mbase, U3D_LV1IESR, value);
183
184
185 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
186 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
187
188 if (mtu->is_u3_ip) {
189
190 value = HOT_RST_INTR | WARM_RST_INTR |
191 ENTER_U3_INTR | EXIT_U3_INTR;
192 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
193 }
194
195
196 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
197 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
198 mtu3_writel(mbase, U3D_QIESR1, value);
199
200
201 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
202}
203
204
205static void mtu3_ep_reset(struct mtu3_ep *mep)
206{
207 struct mtu3 *mtu = mep->mtu;
208 u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
209
210 mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
211 mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
212}
213
214
215void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
216{
217 struct mtu3 *mtu = mep->mtu;
218 void __iomem *mbase = mtu->mac_base;
219 u8 epnum = mep->epnum;
220 u32 csr;
221
222 if (mep->is_in) {
223 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
224 if (set)
225 csr |= TX_SENDSTALL;
226 else
227 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
228 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
229 } else {
230 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
231 if (set)
232 csr |= RX_SENDSTALL;
233 else
234 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
235 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
236 }
237
238 if (!set) {
239 mtu3_ep_reset(mep);
240 mep->flags &= ~MTU3_EP_STALL;
241 } else {
242 mep->flags |= MTU3_EP_STALL;
243 }
244
245 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
246 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
247}
248
249void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
250{
251 if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER)
252 mtu3_ss_func_set(mtu, is_on);
253 else
254 mtu3_hs_softconn_set(mtu, is_on);
255
256 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
257 usb_speed_string(mtu->max_speed), is_on ? "+" : "-");
258}
259
260void mtu3_start(struct mtu3 *mtu)
261{
262 void __iomem *mbase = mtu->mac_base;
263
264 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
265 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
266
267 mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
268
269
270
271
272
273
274 if (mtu->max_speed == USB_SPEED_FULL)
275 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
276
277
278 mtu3_intr_enable(mtu);
279 mtu->is_active = 1;
280
281 if (mtu->softconnect)
282 mtu3_dev_on_off(mtu, 1);
283}
284
285void mtu3_stop(struct mtu3 *mtu)
286{
287 dev_dbg(mtu->dev, "%s\n", __func__);
288
289 mtu3_intr_disable(mtu);
290 mtu3_intr_status_clear(mtu);
291
292 if (mtu->softconnect)
293 mtu3_dev_on_off(mtu, 0);
294
295 mtu->is_active = 0;
296 mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
297}
298
299
300int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
301 int interval, int burst, int mult)
302{
303 void __iomem *mbase = mtu->mac_base;
304 bool gen2cp = mtu->gen2cp;
305 int epnum = mep->epnum;
306 u32 csr0, csr1, csr2;
307 int fifo_sgsz, fifo_addr;
308 int num_pkts;
309
310 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
311 if (fifo_addr < 0) {
312 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
313 return -ENOMEM;
314 }
315 fifo_sgsz = ilog2(mep->fifo_seg_size);
316 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
317 mep->fifo_seg_size, mep->fifo_size);
318
319 if (mep->is_in) {
320 csr0 = TX_TXMAXPKTSZ(mep->maxp);
321 csr0 |= TX_DMAREQEN;
322
323 num_pkts = (burst + 1) * (mult + 1) - 1;
324 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
325 csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
326
327 csr2 = TX_FIFOADDR(fifo_addr >> 4);
328 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
329
330 switch (mep->type) {
331 case USB_ENDPOINT_XFER_BULK:
332 csr1 |= TX_TYPE(TYPE_BULK);
333 break;
334 case USB_ENDPOINT_XFER_ISOC:
335 csr1 |= TX_TYPE(TYPE_ISO);
336 csr2 |= TX_BINTERVAL(interval);
337 break;
338 case USB_ENDPOINT_XFER_INT:
339 csr1 |= TX_TYPE(TYPE_INT);
340 csr2 |= TX_BINTERVAL(interval);
341 break;
342 }
343
344
345 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
346
347 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
348 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
349 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
350
351 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
352 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
353 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
354 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
355 } else {
356 csr0 = RX_RXMAXPKTSZ(mep->maxp);
357 csr0 |= RX_DMAREQEN;
358
359 num_pkts = (burst + 1) * (mult + 1) - 1;
360 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
361 csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
362
363 csr2 = RX_FIFOADDR(fifo_addr >> 4);
364 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
365
366 switch (mep->type) {
367 case USB_ENDPOINT_XFER_BULK:
368 csr1 |= RX_TYPE(TYPE_BULK);
369 break;
370 case USB_ENDPOINT_XFER_ISOC:
371 csr1 |= RX_TYPE(TYPE_ISO);
372 csr2 |= RX_BINTERVAL(interval);
373 break;
374 case USB_ENDPOINT_XFER_INT:
375 csr1 |= RX_TYPE(TYPE_INT);
376 csr2 |= RX_BINTERVAL(interval);
377 break;
378 }
379
380
381 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
382
383 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
384 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
385 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
386
387 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
388 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
389 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
390 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
391 }
392
393 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
394 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
395 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
396 fifo_sgsz, mep->fifo_seg_size);
397
398 return 0;
399}
400
401
402void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
403{
404 void __iomem *mbase = mtu->mac_base;
405 int epnum = mep->epnum;
406
407 if (mep->is_in) {
408 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
409 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
410 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
411 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
412 } else {
413 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
414 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
415 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
416 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
417 }
418
419 mtu3_ep_reset(mep);
420 ep_fifo_free(mep);
421
422 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
423}
424
425
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431
432
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434
435
436
437static void get_ep_fifo_config(struct mtu3 *mtu)
438{
439 struct mtu3_fifo_info *tx_fifo;
440 struct mtu3_fifo_info *rx_fifo;
441 u32 fifosize;
442
443 if (mtu->is_u3_ip) {
444 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
445 tx_fifo = &mtu->tx_fifo;
446 tx_fifo->base = 0;
447 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
448 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
449
450 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
451 rx_fifo = &mtu->rx_fifo;
452 rx_fifo->base = 0;
453 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
454 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
455 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
456 } else {
457 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
458 tx_fifo = &mtu->tx_fifo;
459 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
460 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
461 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
462
463 rx_fifo = &mtu->rx_fifo;
464 rx_fifo->base =
465 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
466 rx_fifo->limit = tx_fifo->limit;
467 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
468 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
469 }
470
471 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
472 __func__, tx_fifo->base, tx_fifo->limit,
473 rx_fifo->base, rx_fifo->limit);
474}
475
476void mtu3_ep0_setup(struct mtu3 *mtu)
477{
478 u32 maxpacket = mtu->g.ep0->maxpacket;
479 u32 csr;
480
481 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
482
483 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
484 csr &= ~EP0_MAXPKTSZ_MSK;
485 csr |= EP0_MAXPKTSZ(maxpacket);
486 csr &= EP0_W1C_BITS;
487 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
488
489
490 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
491}
492
493static int mtu3_mem_alloc(struct mtu3 *mtu)
494{
495 void __iomem *mbase = mtu->mac_base;
496 struct mtu3_ep *ep_array;
497 int in_ep_num, out_ep_num;
498 u32 cap_epinfo;
499 int ret;
500 int i;
501
502 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
503 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
504 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
505
506 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
507 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
508 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
509
510
511 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
512 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
513 if (ep_array == NULL)
514 return -ENOMEM;
515
516 mtu->ep_array = ep_array;
517 mtu->in_eps = ep_array;
518 mtu->out_eps = &ep_array[mtu->num_eps];
519
520 mtu->ep0 = mtu->in_eps;
521 mtu->ep0->mtu = mtu;
522 mtu->ep0->epnum = 0;
523
524 for (i = 1; i < mtu->num_eps; i++) {
525 struct mtu3_ep *mep = mtu->in_eps + i;
526
527 mep->fifo = &mtu->tx_fifo;
528 mep = mtu->out_eps + i;
529 mep->fifo = &mtu->rx_fifo;
530 }
531
532 get_ep_fifo_config(mtu);
533
534 ret = mtu3_qmu_init(mtu);
535 if (ret)
536 kfree(mtu->ep_array);
537
538 return ret;
539}
540
541static void mtu3_mem_free(struct mtu3 *mtu)
542{
543 mtu3_qmu_exit(mtu);
544 kfree(mtu->ep_array);
545}
546
547static void mtu3_set_speed(struct mtu3 *mtu)
548{
549 void __iomem *mbase = mtu->mac_base;
550
551 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
552 mtu->max_speed = USB_SPEED_HIGH;
553
554 if (mtu->max_speed == USB_SPEED_FULL) {
555
556 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
557
558 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
559 } else if (mtu->max_speed == USB_SPEED_HIGH) {
560 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
561
562 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
563 } else if (mtu->max_speed == USB_SPEED_SUPER) {
564 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
565 SSUSB_U3_PORT_SSP_SPEED);
566 }
567
568 dev_info(mtu->dev, "max_speed: %s\n",
569 usb_speed_string(mtu->max_speed));
570}
571
572static void mtu3_regs_init(struct mtu3 *mtu)
573{
574
575 void __iomem *mbase = mtu->mac_base;
576
577
578 mtu3_intr_disable(mtu);
579 mtu3_intr_status_clear(mtu);
580
581 if (mtu->is_u3_ip) {
582
583 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
584 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
585
586 mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
587 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
588
589 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
590
591 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
592
593 mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
594 }
595
596 mtu3_set_speed(mtu);
597
598
599 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
600
601 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
602
603 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
604
605 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
606
607
608 if (mtu->gen2cp)
609 mtu3_writel(mbase, U3D_QFCR, ~0x0);
610}
611
612static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
613{
614 void __iomem *mbase = mtu->mac_base;
615 enum usb_device_speed udev_speed;
616 u32 maxpkt = 64;
617 u32 link;
618 u32 speed;
619
620 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
621 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
622 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link);
623 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
624
625 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
626 return IRQ_NONE;
627
628 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
629
630 switch (speed) {
631 case MTU3_SPEED_FULL:
632 udev_speed = USB_SPEED_FULL;
633
634 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
635 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
636 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
637 LPM_BESL_STALL | LPM_BESLD_STALL);
638 break;
639 case MTU3_SPEED_HIGH:
640 udev_speed = USB_SPEED_HIGH;
641
642 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
643 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
644 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
645 LPM_BESL_STALL | LPM_BESLD_STALL);
646 break;
647 case MTU3_SPEED_SUPER:
648 udev_speed = USB_SPEED_SUPER;
649 maxpkt = 512;
650 break;
651 case MTU3_SPEED_SUPER_PLUS:
652 udev_speed = USB_SPEED_SUPER_PLUS;
653 maxpkt = 512;
654 break;
655 default:
656 udev_speed = USB_SPEED_UNKNOWN;
657 break;
658 }
659 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
660 mtu3_dbg_trace(mtu->dev, "link speed %s",
661 usb_speed_string(udev_speed));
662
663 mtu->g.speed = udev_speed;
664 mtu->g.ep0->maxpacket = maxpkt;
665 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
666
667 if (udev_speed == USB_SPEED_UNKNOWN)
668 mtu3_gadget_disconnect(mtu);
669 else
670 mtu3_ep0_setup(mtu);
671
672 return IRQ_HANDLED;
673}
674
675static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
676{
677 void __iomem *mbase = mtu->mac_base;
678 u32 ltssm;
679
680 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
681 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
682 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm);
683 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
684 trace_mtu3_u3_ltssm_isr(ltssm);
685
686 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
687 mtu3_gadget_reset(mtu);
688
689 if (ltssm & VBUS_FALL_INTR) {
690 mtu3_ss_func_set(mtu, false);
691 mtu3_gadget_reset(mtu);
692 }
693
694 if (ltssm & VBUS_RISE_INTR)
695 mtu3_ss_func_set(mtu, true);
696
697 if (ltssm & EXIT_U3_INTR)
698 mtu3_gadget_resume(mtu);
699
700 if (ltssm & ENTER_U3_INTR)
701 mtu3_gadget_suspend(mtu);
702
703 return IRQ_HANDLED;
704}
705
706static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
707{
708 void __iomem *mbase = mtu->mac_base;
709 u32 u2comm;
710
711 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
712 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
713 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm);
714 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
715 trace_mtu3_u2_common_isr(u2comm);
716
717 if (u2comm & SUSPEND_INTR)
718 mtu3_gadget_suspend(mtu);
719
720 if (u2comm & RESUME_INTR)
721 mtu3_gadget_resume(mtu);
722
723 if (u2comm & RESET_INTR)
724 mtu3_gadget_reset(mtu);
725
726 return IRQ_HANDLED;
727}
728
729static irqreturn_t mtu3_irq(int irq, void *data)
730{
731 struct mtu3 *mtu = (struct mtu3 *)data;
732 unsigned long flags;
733 u32 level1;
734
735 spin_lock_irqsave(&mtu->lock, flags);
736
737
738 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
739 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
740
741 if (level1 & EP_CTRL_INTR)
742 mtu3_link_isr(mtu);
743
744 if (level1 & MAC2_INTR)
745 mtu3_u2_common_isr(mtu);
746
747 if (level1 & MAC3_INTR)
748 mtu3_u3_ltssm_isr(mtu);
749
750 if (level1 & BMU_INTR)
751 mtu3_ep0_isr(mtu);
752
753 if (level1 & QMU_INTR)
754 mtu3_qmu_isr(mtu);
755
756 spin_unlock_irqrestore(&mtu->lock, flags);
757
758 return IRQ_HANDLED;
759}
760
761static int mtu3_hw_init(struct mtu3 *mtu)
762{
763 u32 value;
764 int ret;
765
766 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
767 mtu->hw_version = IP_TRUNK_VERS(value);
768 mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
769
770 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
771 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
772
773 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
774 mtu->is_u3_ip ? "U3" : "U2");
775
776 mtu3_device_reset(mtu);
777
778 ret = mtu3_device_enable(mtu);
779 if (ret) {
780 dev_err(mtu->dev, "device enable failed %d\n", ret);
781 return ret;
782 }
783
784 ret = mtu3_mem_alloc(mtu);
785 if (ret)
786 return -ENOMEM;
787
788 mtu3_regs_init(mtu);
789
790 return 0;
791}
792
793static void mtu3_hw_exit(struct mtu3 *mtu)
794{
795 mtu3_device_disable(mtu);
796 mtu3_mem_free(mtu);
797}
798
799
800
801
802
803static int mtu3_set_dma_mask(struct mtu3 *mtu)
804{
805 struct device *dev = mtu->dev;
806 bool is_36bit = false;
807 int ret = 0;
808 u32 value;
809
810 value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
811 if (value & DMA_ADDR_36BIT) {
812 is_36bit = true;
813 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
814
815 if (ret) {
816 is_36bit = false;
817 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
818 }
819 }
820 dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
821
822 return ret;
823}
824
825int ssusb_gadget_init(struct ssusb_mtk *ssusb)
826{
827 struct device *dev = ssusb->dev;
828 struct platform_device *pdev = to_platform_device(dev);
829 struct mtu3 *mtu = NULL;
830 struct resource *res;
831 int ret = -ENOMEM;
832
833 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
834 if (mtu == NULL)
835 return -ENOMEM;
836
837 mtu->irq = platform_get_irq(pdev, 0);
838 if (mtu->irq < 0) {
839 dev_err(dev, "fail to get irq number\n");
840 return mtu->irq;
841 }
842 dev_info(dev, "irq %d\n", mtu->irq);
843
844 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
845 mtu->mac_base = devm_ioremap_resource(dev, res);
846 if (IS_ERR(mtu->mac_base)) {
847 dev_err(dev, "error mapping memory for dev mac\n");
848 return PTR_ERR(mtu->mac_base);
849 }
850
851 spin_lock_init(&mtu->lock);
852 mtu->dev = dev;
853 mtu->ippc_base = ssusb->ippc_base;
854 ssusb->mac_base = mtu->mac_base;
855 ssusb->u3d = mtu;
856 mtu->ssusb = ssusb;
857 mtu->max_speed = usb_get_maximum_speed(dev);
858
859
860 switch (mtu->max_speed) {
861 case USB_SPEED_FULL:
862 case USB_SPEED_HIGH:
863 case USB_SPEED_SUPER:
864 case USB_SPEED_SUPER_PLUS:
865 break;
866 default:
867 dev_err(dev, "invalid max_speed: %s\n",
868 usb_speed_string(mtu->max_speed));
869
870 case USB_SPEED_UNKNOWN:
871
872 mtu->max_speed = USB_SPEED_SUPER_PLUS;
873 break;
874 }
875
876 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
877 mtu->mac_base, mtu->ippc_base);
878
879 ret = mtu3_hw_init(mtu);
880 if (ret) {
881 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
882 return ret;
883 }
884
885 ret = mtu3_set_dma_mask(mtu);
886 if (ret) {
887 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
888 goto dma_mask_err;
889 }
890
891 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
892 if (ret) {
893 dev_err(dev, "request irq %d failed!\n", mtu->irq);
894 goto irq_err;
895 }
896
897 device_init_wakeup(dev, true);
898
899 ret = mtu3_gadget_setup(mtu);
900 if (ret) {
901 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
902 goto gadget_err;
903 }
904
905
906 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
907 mtu3_stop(mtu);
908
909 ssusb_dev_debugfs_init(ssusb);
910
911 dev_dbg(dev, " %s() done...\n", __func__);
912
913 return 0;
914
915gadget_err:
916 device_init_wakeup(dev, false);
917
918dma_mask_err:
919irq_err:
920 mtu3_hw_exit(mtu);
921 ssusb->u3d = NULL;
922 dev_err(dev, " %s() fail...\n", __func__);
923
924 return ret;
925}
926
927void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
928{
929 struct mtu3 *mtu = ssusb->u3d;
930
931 mtu3_gadget_cleanup(mtu);
932 device_init_wakeup(ssusb->dev, false);
933 mtu3_hw_exit(mtu);
934}
935
