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11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/sched.h>
15#include <linux/slab.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/dma-mapping.h>
19
20#include "musb_core.h"
21#include "musb_host.h"
22#include "musb_trace.h"
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72
73struct musb *hcd_to_musb(struct usb_hcd *hcd)
74{
75 return *(struct musb **) hcd->hcd_priv;
76}
77
78
79static void musb_ep_program(struct musb *musb, u8 epnum,
80 struct urb *urb, int is_out,
81 u8 *buf, u32 offset, u32 len);
82
83
84
85
86static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
87{
88 struct musb *musb = ep->musb;
89 void __iomem *epio = ep->regs;
90 u16 csr;
91 int retries = 1000;
92
93 csr = musb_readw(epio, MUSB_TXCSR);
94 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
95 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY;
96 musb_writew(epio, MUSB_TXCSR, csr);
97 csr = musb_readw(epio, MUSB_TXCSR);
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113 if (dev_WARN_ONCE(musb->controller, retries-- < 1,
114 "Could not flush host TX%d fifo: csr: %04x\n",
115 ep->epnum, csr))
116 return;
117 mdelay(1);
118 }
119}
120
121static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
122{
123 void __iomem *epio = ep->regs;
124 u16 csr;
125 int retries = 5;
126
127
128 do {
129 csr = musb_readw(epio, MUSB_TXCSR);
130 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
131 break;
132 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
133 csr = musb_readw(epio, MUSB_TXCSR);
134 udelay(10);
135 } while (--retries);
136
137 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
138 ep->epnum, csr);
139
140
141 musb_writew(epio, MUSB_TXCSR, 0);
142}
143
144
145
146
147
148static inline void musb_h_tx_start(struct musb_hw_ep *ep)
149{
150 u16 txcsr;
151
152
153 if (ep->epnum) {
154 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
155 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
156 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
157 } else {
158 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
159 musb_writew(ep->regs, MUSB_CSR0, txcsr);
160 }
161
162}
163
164static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
165{
166 u16 txcsr;
167
168
169 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
170 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
171 if (is_cppi_enabled(ep->musb))
172 txcsr |= MUSB_TXCSR_DMAMODE;
173 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
174}
175
176static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
177{
178 if (is_in != 0 || ep->is_shared_fifo)
179 ep->in_qh = qh;
180 if (is_in == 0 || ep->is_shared_fifo)
181 ep->out_qh = qh;
182}
183
184static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
185{
186 return is_in ? ep->in_qh : ep->out_qh;
187}
188
189
190
191
192
193
194
195static void
196musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
197{
198 u32 len;
199 void __iomem *mbase = musb->mregs;
200 struct urb *urb = next_urb(qh);
201 void *buf = urb->transfer_buffer;
202 u32 offset = 0;
203 struct musb_hw_ep *hw_ep = qh->hw_ep;
204 int epnum = hw_ep->epnum;
205
206
207 qh->offset = 0;
208 qh->segsize = 0;
209
210
211 switch (qh->type) {
212 case USB_ENDPOINT_XFER_CONTROL:
213
214 is_in = 0;
215 musb->ep0_stage = MUSB_EP0_START;
216 buf = urb->setup_packet;
217 len = 8;
218 break;
219 case USB_ENDPOINT_XFER_ISOC:
220 qh->iso_idx = 0;
221 qh->frame = 0;
222 offset = urb->iso_frame_desc[0].offset;
223 len = urb->iso_frame_desc[0].length;
224 break;
225 default:
226
227 buf = urb->transfer_buffer + urb->actual_length;
228 len = urb->transfer_buffer_length - urb->actual_length;
229 }
230
231 trace_musb_urb_start(musb, urb);
232
233
234 musb_ep_set_qh(hw_ep, is_in, qh);
235 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
236
237
238 if (is_in)
239 return;
240
241
242 switch (qh->type) {
243 case USB_ENDPOINT_XFER_ISOC:
244 case USB_ENDPOINT_XFER_INT:
245 musb_dbg(musb, "check whether there's still time for periodic Tx");
246
247
248
249 if (1) {
250
251
252
253 qh->frame = 0;
254 goto start;
255 } else {
256 qh->frame = urb->start_frame;
257
258 musb_dbg(musb, "SOF for %d", epnum);
259#if 1
260 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
261#endif
262 }
263 break;
264 default:
265start:
266 musb_dbg(musb, "Start TX%d %s", epnum,
267 hw_ep->tx_channel ? "dma" : "pio");
268
269 if (!hw_ep->tx_channel)
270 musb_h_tx_start(hw_ep);
271 else if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
272 musb_h_tx_dma_start(hw_ep);
273 }
274}
275
276
277static void musb_giveback(struct musb *musb, struct urb *urb, int status)
278__releases(musb->lock)
279__acquires(musb->lock)
280{
281 trace_musb_urb_gb(musb, urb);
282
283 usb_hcd_unlink_urb_from_ep(musb->hcd, urb);
284 spin_unlock(&musb->lock);
285 usb_hcd_giveback_urb(musb->hcd, urb, status);
286 spin_lock(&musb->lock);
287}
288
289
290static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
291 struct urb *urb)
292{
293 void __iomem *epio = qh->hw_ep->regs;
294 u16 csr;
295
296
297
298
299
300
301 if (is_in)
302 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
303 else
304 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
305
306 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
307}
308
309
310
311
312
313
314
315
316static void musb_advance_schedule(struct musb *musb, struct urb *urb,
317 struct musb_hw_ep *hw_ep, int is_in)
318{
319 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
320 struct musb_hw_ep *ep = qh->hw_ep;
321 int ready = qh->is_ready;
322 int status;
323
324 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
325
326
327 switch (qh->type) {
328 case USB_ENDPOINT_XFER_BULK:
329 case USB_ENDPOINT_XFER_INT:
330 musb_save_toggle(qh, is_in, urb);
331 break;
332 case USB_ENDPOINT_XFER_ISOC:
333 if (status == 0 && urb->error_count)
334 status = -EXDEV;
335 break;
336 }
337
338 qh->is_ready = 0;
339 musb_giveback(musb, urb, status);
340 qh->is_ready = ready;
341
342
343
344
345 if (list_empty(&qh->hep->urb_list)) {
346 struct list_head *head;
347 struct dma_controller *dma = musb->dma_controller;
348
349 if (is_in) {
350 ep->rx_reinit = 1;
351 if (ep->rx_channel) {
352 dma->channel_release(ep->rx_channel);
353 ep->rx_channel = NULL;
354 }
355 } else {
356 ep->tx_reinit = 1;
357 if (ep->tx_channel) {
358 dma->channel_release(ep->tx_channel);
359 ep->tx_channel = NULL;
360 }
361 }
362
363
364 musb_ep_set_qh(ep, is_in, NULL);
365 qh->hep->hcpriv = NULL;
366
367 switch (qh->type) {
368
369 case USB_ENDPOINT_XFER_CONTROL:
370 case USB_ENDPOINT_XFER_BULK:
371
372
373
374 if (qh->mux == 1) {
375 head = qh->ring.prev;
376 list_del(&qh->ring);
377 kfree(qh);
378 qh = first_qh(head);
379 break;
380 }
381
382
383 case USB_ENDPOINT_XFER_ISOC:
384 case USB_ENDPOINT_XFER_INT:
385
386
387
388
389 kfree(qh);
390 qh = NULL;
391 break;
392 }
393 }
394
395 if (qh != NULL && qh->is_ready) {
396 musb_dbg(musb, "... next ep%d %cX urb %p",
397 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
398 musb_start_urb(musb, is_in, qh);
399 }
400}
401
402static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
403{
404
405
406
407
408 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
409 csr &= ~(MUSB_RXCSR_H_REQPKT
410 | MUSB_RXCSR_H_AUTOREQ
411 | MUSB_RXCSR_AUTOCLEAR);
412
413
414 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
415 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
416
417
418 return musb_readw(hw_ep->regs, MUSB_RXCSR);
419}
420
421
422
423
424static bool
425musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
426{
427 u16 rx_count;
428 u8 *buf;
429 u16 csr;
430 bool done = false;
431 u32 length;
432 int do_flush = 0;
433 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
434 void __iomem *epio = hw_ep->regs;
435 struct musb_qh *qh = hw_ep->in_qh;
436 int pipe = urb->pipe;
437 void *buffer = urb->transfer_buffer;
438
439
440 rx_count = musb_readw(epio, MUSB_RXCOUNT);
441 musb_dbg(musb, "RX%d count %d, buffer %p len %d/%d", epnum, rx_count,
442 urb->transfer_buffer, qh->offset,
443 urb->transfer_buffer_length);
444
445
446 if (usb_pipeisoc(pipe)) {
447 int status = 0;
448 struct usb_iso_packet_descriptor *d;
449
450 if (iso_err) {
451 status = -EILSEQ;
452 urb->error_count++;
453 }
454
455 d = urb->iso_frame_desc + qh->iso_idx;
456 buf = buffer + d->offset;
457 length = d->length;
458 if (rx_count > length) {
459 if (status == 0) {
460 status = -EOVERFLOW;
461 urb->error_count++;
462 }
463 musb_dbg(musb, "OVERFLOW %d into %d", rx_count, length);
464 do_flush = 1;
465 } else
466 length = rx_count;
467 urb->actual_length += length;
468 d->actual_length = length;
469
470 d->status = status;
471
472
473 done = (++qh->iso_idx >= urb->number_of_packets);
474 } else {
475
476 buf = buffer + qh->offset;
477 length = urb->transfer_buffer_length - qh->offset;
478 if (rx_count > length) {
479 if (urb->status == -EINPROGRESS)
480 urb->status = -EOVERFLOW;
481 musb_dbg(musb, "OVERFLOW %d into %d", rx_count, length);
482 do_flush = 1;
483 } else
484 length = rx_count;
485 urb->actual_length += length;
486 qh->offset += length;
487
488
489 done = (urb->actual_length == urb->transfer_buffer_length)
490 || (rx_count < qh->maxpacket)
491 || (urb->status != -EINPROGRESS);
492 if (done
493 && (urb->status == -EINPROGRESS)
494 && (urb->transfer_flags & URB_SHORT_NOT_OK)
495 && (urb->actual_length
496 < urb->transfer_buffer_length))
497 urb->status = -EREMOTEIO;
498 }
499
500 musb_read_fifo(hw_ep, length, buf);
501
502 csr = musb_readw(epio, MUSB_RXCSR);
503 csr |= MUSB_RXCSR_H_WZC_BITS;
504 if (unlikely(do_flush))
505 musb_h_flush_rxfifo(hw_ep, csr);
506 else {
507
508 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
509 if (!done)
510 csr |= MUSB_RXCSR_H_REQPKT;
511 musb_writew(epio, MUSB_RXCSR, csr);
512 }
513
514 return done;
515}
516
517
518
519
520
521
522
523
524
525static void
526musb_rx_reinit(struct musb *musb, struct musb_qh *qh, u8 epnum)
527{
528 struct musb_hw_ep *ep = musb->endpoints + epnum;
529 u16 csr;
530
531
532
533
534
535
536
537 if (ep->is_shared_fifo) {
538 csr = musb_readw(ep->regs, MUSB_TXCSR);
539 if (csr & MUSB_TXCSR_MODE) {
540 musb_h_tx_flush_fifo(ep);
541 csr = musb_readw(ep->regs, MUSB_TXCSR);
542 musb_writew(ep->regs, MUSB_TXCSR,
543 csr | MUSB_TXCSR_FRCDATATOG);
544 }
545
546
547
548
549
550 if (csr & MUSB_TXCSR_DMAMODE)
551 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
552 musb_writew(ep->regs, MUSB_TXCSR, 0);
553
554
555 }
556 csr = musb_readw(ep->regs, MUSB_RXCSR);
557 if (csr & MUSB_RXCSR_RXPKTRDY)
558 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
559 musb_readw(ep->regs, MUSB_RXCOUNT));
560
561 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
562
563
564 if (musb->is_multipoint) {
565 musb_write_rxfunaddr(musb, epnum, qh->addr_reg);
566 musb_write_rxhubaddr(musb, epnum, qh->h_addr_reg);
567 musb_write_rxhubport(musb, epnum, qh->h_port_reg);
568 } else
569 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
570
571
572 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
573 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
574
575
576
577
578 musb_writew(ep->regs, MUSB_RXMAXP,
579 qh->maxpacket | ((qh->hb_mult - 1) << 11));
580
581 ep->rx_reinit = 0;
582}
583
584static void musb_tx_dma_set_mode_mentor(struct dma_controller *dma,
585 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
586 struct urb *urb, u32 offset,
587 u32 *length, u8 *mode)
588{
589 struct dma_channel *channel = hw_ep->tx_channel;
590 void __iomem *epio = hw_ep->regs;
591 u16 pkt_size = qh->maxpacket;
592 u16 csr;
593
594 if (*length > channel->max_len)
595 *length = channel->max_len;
596
597 csr = musb_readw(epio, MUSB_TXCSR);
598 if (*length > pkt_size) {
599 *mode = 1;
600 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
601
602
603
604
605
606
607
608
609
610
611 if (qh->hb_mult == 1 || (qh->hb_mult > 1 &&
612 can_bulk_split(hw_ep->musb, qh->type)))
613 csr |= MUSB_TXCSR_AUTOSET;
614 } else {
615 *mode = 0;
616 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
617 csr |= MUSB_TXCSR_DMAENAB;
618 }
619 channel->desired_mode = *mode;
620 musb_writew(epio, MUSB_TXCSR, csr);
621}
622
623static void musb_tx_dma_set_mode_cppi_tusb(struct dma_controller *dma,
624 struct musb_hw_ep *hw_ep,
625 struct musb_qh *qh,
626 struct urb *urb,
627 u32 offset,
628 u32 *length,
629 u8 *mode)
630{
631 struct dma_channel *channel = hw_ep->tx_channel;
632
633 channel->actual_len = 0;
634
635
636
637
638
639 *mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
640}
641
642static bool musb_tx_dma_program(struct dma_controller *dma,
643 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
644 struct urb *urb, u32 offset, u32 length)
645{
646 struct dma_channel *channel = hw_ep->tx_channel;
647 u16 pkt_size = qh->maxpacket;
648 u8 mode;
649
650 if (musb_dma_inventra(hw_ep->musb) || musb_dma_ux500(hw_ep->musb))
651 musb_tx_dma_set_mode_mentor(dma, hw_ep, qh, urb, offset,
652 &length, &mode);
653 else if (is_cppi_enabled(hw_ep->musb) || tusb_dma_omap(hw_ep->musb))
654 musb_tx_dma_set_mode_cppi_tusb(dma, hw_ep, qh, urb, offset,
655 &length, &mode);
656 else
657 return false;
658
659 qh->segsize = length;
660
661
662
663
664
665 wmb();
666
667 if (!dma->channel_program(channel, pkt_size, mode,
668 urb->transfer_dma + offset, length)) {
669 void __iomem *epio = hw_ep->regs;
670 u16 csr;
671
672 dma->channel_release(channel);
673 hw_ep->tx_channel = NULL;
674
675 csr = musb_readw(epio, MUSB_TXCSR);
676 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
677 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
678 return false;
679 }
680 return true;
681}
682
683
684
685
686
687static void musb_ep_program(struct musb *musb, u8 epnum,
688 struct urb *urb, int is_out,
689 u8 *buf, u32 offset, u32 len)
690{
691 struct dma_controller *dma_controller;
692 struct dma_channel *dma_channel;
693 u8 dma_ok;
694 void __iomem *mbase = musb->mregs;
695 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
696 void __iomem *epio = hw_ep->regs;
697 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
698 u16 packet_sz = qh->maxpacket;
699 u8 use_dma = 1;
700 u16 csr;
701
702 musb_dbg(musb, "%s hw%d urb %p spd%d dev%d ep%d%s "
703 "h_addr%02x h_port%02x bytes %d",
704 is_out ? "-->" : "<--",
705 epnum, urb, urb->dev->speed,
706 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
707 qh->h_addr_reg, qh->h_port_reg,
708 len);
709
710 musb_ep_select(mbase, epnum);
711
712 if (is_out && !len) {
713 use_dma = 0;
714 csr = musb_readw(epio, MUSB_TXCSR);
715 csr &= ~MUSB_TXCSR_DMAENAB;
716 musb_writew(epio, MUSB_TXCSR, csr);
717 hw_ep->tx_channel = NULL;
718 }
719
720
721 dma_controller = musb->dma_controller;
722 if (use_dma && is_dma_capable() && epnum && dma_controller) {
723 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
724 if (!dma_channel) {
725 dma_channel = dma_controller->channel_alloc(
726 dma_controller, hw_ep, is_out);
727 if (is_out)
728 hw_ep->tx_channel = dma_channel;
729 else
730 hw_ep->rx_channel = dma_channel;
731 }
732 } else
733 dma_channel = NULL;
734
735
736
737
738 if (is_out) {
739 u16 csr;
740 u16 int_txe;
741 u16 load_count;
742
743 csr = musb_readw(epio, MUSB_TXCSR);
744
745
746 int_txe = musb->intrtxe;
747 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
748
749
750 if (epnum) {
751
752
753
754
755
756
757 if (!hw_ep->tx_double_buffered)
758 musb_h_tx_flush_fifo(hw_ep);
759
760
761
762
763
764
765 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
766 | MUSB_TXCSR_AUTOSET
767 | MUSB_TXCSR_DMAENAB
768 | MUSB_TXCSR_FRCDATATOG
769 | MUSB_TXCSR_H_RXSTALL
770 | MUSB_TXCSR_H_ERROR
771 | MUSB_TXCSR_TXPKTRDY
772 );
773 csr |= MUSB_TXCSR_MODE;
774
775 if (!hw_ep->tx_double_buffered) {
776 if (usb_gettoggle(urb->dev, qh->epnum, 1))
777 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
778 | MUSB_TXCSR_H_DATATOGGLE;
779 else
780 csr |= MUSB_TXCSR_CLRDATATOG;
781 }
782
783 musb_writew(epio, MUSB_TXCSR, csr);
784
785 csr &= ~MUSB_TXCSR_DMAMODE;
786 musb_writew(epio, MUSB_TXCSR, csr);
787 csr = musb_readw(epio, MUSB_TXCSR);
788 } else {
789
790 musb_h_ep0_flush_fifo(hw_ep);
791 }
792
793
794 if (musb->is_multipoint) {
795 musb_write_txfunaddr(musb, epnum, qh->addr_reg);
796 musb_write_txhubaddr(musb, epnum, qh->h_addr_reg);
797 musb_write_txhubport(musb, epnum, qh->h_port_reg);
798
799 } else
800 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
801
802
803 if (epnum) {
804 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
805 if (can_bulk_split(musb, qh->type)) {
806 qh->hb_mult = hw_ep->max_packet_sz_tx
807 / packet_sz;
808 musb_writew(epio, MUSB_TXMAXP, packet_sz
809 | ((qh->hb_mult) - 1) << 11);
810 } else {
811 musb_writew(epio, MUSB_TXMAXP,
812 qh->maxpacket |
813 ((qh->hb_mult - 1) << 11));
814 }
815 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
816 } else {
817 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
818 if (musb->is_multipoint)
819 musb_writeb(epio, MUSB_TYPE0,
820 qh->type_reg);
821 }
822
823 if (can_bulk_split(musb, qh->type))
824 load_count = min((u32) hw_ep->max_packet_sz_tx,
825 len);
826 else
827 load_count = min((u32) packet_sz, len);
828
829 if (dma_channel && musb_tx_dma_program(dma_controller,
830 hw_ep, qh, urb, offset, len))
831 load_count = 0;
832
833 if (load_count) {
834
835 qh->segsize = load_count;
836 if (!buf) {
837 sg_miter_start(&qh->sg_miter, urb->sg, 1,
838 SG_MITER_ATOMIC
839 | SG_MITER_FROM_SG);
840 if (!sg_miter_next(&qh->sg_miter)) {
841 dev_err(musb->controller,
842 "error: sg"
843 "list empty\n");
844 sg_miter_stop(&qh->sg_miter);
845 goto finish;
846 }
847 buf = qh->sg_miter.addr + urb->sg->offset +
848 urb->actual_length;
849 load_count = min_t(u32, load_count,
850 qh->sg_miter.length);
851 musb_write_fifo(hw_ep, load_count, buf);
852 qh->sg_miter.consumed = load_count;
853 sg_miter_stop(&qh->sg_miter);
854 } else
855 musb_write_fifo(hw_ep, load_count, buf);
856 }
857finish:
858
859 musb_writew(mbase, MUSB_INTRTXE, int_txe);
860
861
862 } else {
863 u16 csr;
864
865 if (hw_ep->rx_reinit) {
866 musb_rx_reinit(musb, qh, epnum);
867
868
869 if (usb_gettoggle(urb->dev, qh->epnum, 0))
870 csr = MUSB_RXCSR_H_WR_DATATOGGLE
871 | MUSB_RXCSR_H_DATATOGGLE;
872 else
873 csr = 0;
874 if (qh->type == USB_ENDPOINT_XFER_INT)
875 csr |= MUSB_RXCSR_DISNYET;
876
877 } else {
878 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
879
880 if (csr & (MUSB_RXCSR_RXPKTRDY
881 | MUSB_RXCSR_DMAENAB
882 | MUSB_RXCSR_H_REQPKT))
883 ERR("broken !rx_reinit, ep%d csr %04x\n",
884 hw_ep->epnum, csr);
885
886
887 csr &= MUSB_RXCSR_DISNYET;
888 }
889
890
891
892 if ((is_cppi_enabled(musb) || tusb_dma_omap(musb)) && dma_channel) {
893
894 dma_channel->actual_len = 0L;
895 qh->segsize = len;
896
897
898 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
899 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
900
901
902
903
904
905 dma_ok = dma_controller->channel_program(dma_channel,
906 packet_sz, !(urb->transfer_flags &
907 URB_SHORT_NOT_OK),
908 urb->transfer_dma + offset,
909 qh->segsize);
910 if (!dma_ok) {
911 dma_controller->channel_release(dma_channel);
912 hw_ep->rx_channel = dma_channel = NULL;
913 } else
914 csr |= MUSB_RXCSR_DMAENAB;
915 }
916
917 csr |= MUSB_RXCSR_H_REQPKT;
918 musb_dbg(musb, "RXCSR%d := %04x", epnum, csr);
919 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
920 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
921 }
922}
923
924
925
926
927static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
928 int is_in)
929{
930 struct dma_channel *dma;
931 struct urb *urb;
932 void __iomem *mbase = musb->mregs;
933 void __iomem *epio = ep->regs;
934 struct musb_qh *cur_qh, *next_qh;
935 u16 rx_csr, tx_csr;
936
937 musb_ep_select(mbase, ep->epnum);
938 if (is_in) {
939 dma = is_dma_capable() ? ep->rx_channel : NULL;
940
941
942
943
944
945
946 rx_csr = musb_readw(epio, MUSB_RXCSR);
947 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
948 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
949 musb_writew(epio, MUSB_RXCSR, rx_csr);
950 rx_csr &= ~MUSB_RXCSR_DATAERROR;
951 musb_writew(epio, MUSB_RXCSR, rx_csr);
952
953 cur_qh = first_qh(&musb->in_bulk);
954 } else {
955 dma = is_dma_capable() ? ep->tx_channel : NULL;
956
957
958 tx_csr = musb_readw(epio, MUSB_TXCSR);
959 tx_csr |= MUSB_TXCSR_H_WZC_BITS;
960 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
961 musb_writew(epio, MUSB_TXCSR, tx_csr);
962
963 cur_qh = first_qh(&musb->out_bulk);
964 }
965 if (cur_qh) {
966 urb = next_urb(cur_qh);
967 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
968 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
969 musb->dma_controller->channel_abort(dma);
970 urb->actual_length += dma->actual_len;
971 dma->actual_len = 0L;
972 }
973 musb_save_toggle(cur_qh, is_in, urb);
974
975 if (is_in) {
976
977 list_move_tail(&cur_qh->ring, &musb->in_bulk);
978
979
980 next_qh = first_qh(&musb->in_bulk);
981
982
983 ep->rx_reinit = 1;
984 } else {
985
986 list_move_tail(&cur_qh->ring, &musb->out_bulk);
987
988
989 next_qh = first_qh(&musb->out_bulk);
990
991
992 ep->tx_reinit = 1;
993 }
994
995 if (next_qh)
996 musb_start_urb(musb, is_in, next_qh);
997 }
998}
999
1000
1001
1002
1003
1004static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
1005{
1006 bool more = false;
1007 u8 *fifo_dest = NULL;
1008 u16 fifo_count = 0;
1009 struct musb_hw_ep *hw_ep = musb->control_ep;
1010 struct musb_qh *qh = hw_ep->in_qh;
1011 struct usb_ctrlrequest *request;
1012
1013 switch (musb->ep0_stage) {
1014 case MUSB_EP0_IN:
1015 fifo_dest = urb->transfer_buffer + urb->actual_length;
1016 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
1017 urb->actual_length);
1018 if (fifo_count < len)
1019 urb->status = -EOVERFLOW;
1020
1021 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
1022
1023 urb->actual_length += fifo_count;
1024 if (len < qh->maxpacket) {
1025
1026
1027
1028 } else if (urb->actual_length <
1029 urb->transfer_buffer_length)
1030 more = true;
1031 break;
1032 case MUSB_EP0_START:
1033 request = (struct usb_ctrlrequest *) urb->setup_packet;
1034
1035 if (!request->wLength) {
1036 musb_dbg(musb, "start no-DATA");
1037 break;
1038 } else if (request->bRequestType & USB_DIR_IN) {
1039 musb_dbg(musb, "start IN-DATA");
1040 musb->ep0_stage = MUSB_EP0_IN;
1041 more = true;
1042 break;
1043 } else {
1044 musb_dbg(musb, "start OUT-DATA");
1045 musb->ep0_stage = MUSB_EP0_OUT;
1046 more = true;
1047 }
1048
1049 case MUSB_EP0_OUT:
1050 fifo_count = min_t(size_t, qh->maxpacket,
1051 urb->transfer_buffer_length -
1052 urb->actual_length);
1053 if (fifo_count) {
1054 fifo_dest = (u8 *) (urb->transfer_buffer
1055 + urb->actual_length);
1056 musb_dbg(musb, "Sending %d byte%s to ep0 fifo %p",
1057 fifo_count,
1058 (fifo_count == 1) ? "" : "s",
1059 fifo_dest);
1060 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
1061
1062 urb->actual_length += fifo_count;
1063 more = true;
1064 }
1065 break;
1066 default:
1067 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
1068 break;
1069 }
1070
1071 return more;
1072}
1073
1074
1075
1076
1077
1078
1079
1080irqreturn_t musb_h_ep0_irq(struct musb *musb)
1081{
1082 struct urb *urb;
1083 u16 csr, len;
1084 int status = 0;
1085 void __iomem *mbase = musb->mregs;
1086 struct musb_hw_ep *hw_ep = musb->control_ep;
1087 void __iomem *epio = hw_ep->regs;
1088 struct musb_qh *qh = hw_ep->in_qh;
1089 bool complete = false;
1090 irqreturn_t retval = IRQ_NONE;
1091
1092
1093 urb = next_urb(qh);
1094
1095 musb_ep_select(mbase, 0);
1096 csr = musb_readw(epio, MUSB_CSR0);
1097 len = (csr & MUSB_CSR0_RXPKTRDY)
1098 ? musb_readb(epio, MUSB_COUNT0)
1099 : 0;
1100
1101 musb_dbg(musb, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d",
1102 csr, qh, len, urb, musb->ep0_stage);
1103
1104
1105 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1106 retval = IRQ_HANDLED;
1107 complete = true;
1108 }
1109
1110
1111 if (csr & MUSB_CSR0_H_RXSTALL) {
1112 musb_dbg(musb, "STALLING ENDPOINT");
1113 status = -EPIPE;
1114
1115 } else if (csr & MUSB_CSR0_H_ERROR) {
1116 musb_dbg(musb, "no response, csr0 %04x", csr);
1117 status = -EPROTO;
1118
1119 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1120 musb_dbg(musb, "control NAK timeout");
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130 musb_writew(epio, MUSB_CSR0, 0);
1131 retval = IRQ_HANDLED;
1132 }
1133
1134 if (status) {
1135 musb_dbg(musb, "aborting");
1136 retval = IRQ_HANDLED;
1137 if (urb)
1138 urb->status = status;
1139 complete = true;
1140
1141
1142 if (csr & MUSB_CSR0_H_REQPKT) {
1143 csr &= ~MUSB_CSR0_H_REQPKT;
1144 musb_writew(epio, MUSB_CSR0, csr);
1145 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1146 musb_writew(epio, MUSB_CSR0, csr);
1147 } else {
1148 musb_h_ep0_flush_fifo(hw_ep);
1149 }
1150
1151 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1152
1153
1154 musb_writew(epio, MUSB_CSR0, 0);
1155 }
1156
1157 if (unlikely(!urb)) {
1158
1159
1160 ERR("no URB for end 0\n");
1161
1162 musb_h_ep0_flush_fifo(hw_ep);
1163 goto done;
1164 }
1165
1166 if (!complete) {
1167
1168 if (musb_h_ep0_continue(musb, len, urb)) {
1169
1170 csr = (MUSB_EP0_IN == musb->ep0_stage)
1171 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1172 } else {
1173
1174 if (usb_pipeout(urb->pipe)
1175 || !urb->transfer_buffer_length)
1176 csr = MUSB_CSR0_H_STATUSPKT
1177 | MUSB_CSR0_H_REQPKT;
1178 else
1179 csr = MUSB_CSR0_H_STATUSPKT
1180 | MUSB_CSR0_TXPKTRDY;
1181
1182
1183 csr |= MUSB_CSR0_H_DIS_PING;
1184
1185
1186 musb->ep0_stage = MUSB_EP0_STATUS;
1187
1188 musb_dbg(musb, "ep0 STATUS, csr %04x", csr);
1189
1190 }
1191 musb_writew(epio, MUSB_CSR0, csr);
1192 retval = IRQ_HANDLED;
1193 } else
1194 musb->ep0_stage = MUSB_EP0_IDLE;
1195
1196
1197 if (complete)
1198 musb_advance_schedule(musb, urb, hw_ep, 1);
1199done:
1200 return retval;
1201}
1202
1203
1204#ifdef CONFIG_USB_INVENTRA_DMA
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218#endif
1219
1220
1221void musb_host_tx(struct musb *musb, u8 epnum)
1222{
1223 int pipe;
1224 bool done = false;
1225 u16 tx_csr;
1226 size_t length = 0;
1227 size_t offset = 0;
1228 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1229 void __iomem *epio = hw_ep->regs;
1230 struct musb_qh *qh = hw_ep->out_qh;
1231 struct urb *urb = next_urb(qh);
1232 u32 status = 0;
1233 void __iomem *mbase = musb->mregs;
1234 struct dma_channel *dma;
1235 bool transfer_pending = false;
1236
1237 musb_ep_select(mbase, epnum);
1238 tx_csr = musb_readw(epio, MUSB_TXCSR);
1239
1240
1241 if (!urb) {
1242 musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr);
1243 return;
1244 }
1245
1246 pipe = urb->pipe;
1247 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1248 trace_musb_urb_tx(musb, urb);
1249 musb_dbg(musb, "OUT/TX%d end, csr %04x%s", epnum, tx_csr,
1250 dma ? ", dma" : "");
1251
1252
1253 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1254
1255 musb_dbg(musb, "TX end %d stall", epnum);
1256
1257
1258 status = -EPIPE;
1259
1260 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1261
1262 musb_dbg(musb, "TX 3strikes on ep=%d", epnum);
1263
1264 status = -ETIMEDOUT;
1265
1266 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1267 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
1268 && !list_is_singular(&musb->out_bulk)) {
1269 musb_dbg(musb, "NAK timeout on TX%d ep", epnum);
1270 musb_bulk_nak_timeout(musb, hw_ep, 0);
1271 } else {
1272 musb_dbg(musb, "TX ep%d device not responding", epnum);
1273
1274
1275
1276
1277
1278
1279
1280
1281 musb_ep_select(mbase, epnum);
1282 musb_writew(epio, MUSB_TXCSR,
1283 MUSB_TXCSR_H_WZC_BITS
1284 | MUSB_TXCSR_TXPKTRDY);
1285 }
1286 return;
1287 }
1288
1289done:
1290 if (status) {
1291 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1292 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1293 musb->dma_controller->channel_abort(dma);
1294 }
1295
1296
1297
1298
1299 musb_h_tx_flush_fifo(hw_ep);
1300 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1301 | MUSB_TXCSR_DMAENAB
1302 | MUSB_TXCSR_H_ERROR
1303 | MUSB_TXCSR_H_RXSTALL
1304 | MUSB_TXCSR_H_NAKTIMEOUT
1305 );
1306
1307 musb_ep_select(mbase, epnum);
1308 musb_writew(epio, MUSB_TXCSR, tx_csr);
1309
1310 musb_writew(epio, MUSB_TXCSR, tx_csr);
1311 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1312
1313 done = true;
1314 }
1315
1316
1317 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1318 musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr);
1319 return;
1320 }
1321
1322 if (is_dma_capable() && dma && !status) {
1323
1324
1325
1326
1327
1328
1329
1330
1331 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1349 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1350 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1351 MUSB_TXCSR_TXPKTRDY);
1352 musb_writew(epio, MUSB_TXCSR,
1353 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1354 }
1355 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1356 MUSB_TXCSR_TXPKTRDY);
1357 musb_writew(epio, MUSB_TXCSR,
1358 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1359
1360
1361
1362
1363
1364
1365
1366 tx_csr = musb_readw(epio, MUSB_TXCSR);
1367 }
1368
1369
1370
1371
1372
1373
1374
1375
1376 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1377 musb_dbg(musb,
1378 "DMA complete but FIFO not empty, CSR %04x",
1379 tx_csr);
1380 return;
1381 }
1382 }
1383
1384 if (!status || dma || usb_pipeisoc(pipe)) {
1385 if (dma)
1386 length = dma->actual_len;
1387 else
1388 length = qh->segsize;
1389 qh->offset += length;
1390
1391 if (usb_pipeisoc(pipe)) {
1392 struct usb_iso_packet_descriptor *d;
1393
1394 d = urb->iso_frame_desc + qh->iso_idx;
1395 d->actual_length = length;
1396 d->status = status;
1397 if (++qh->iso_idx >= urb->number_of_packets) {
1398 done = true;
1399 } else {
1400 d++;
1401 offset = d->offset;
1402 length = d->length;
1403 }
1404 } else if (dma && urb->transfer_buffer_length == qh->offset) {
1405 done = true;
1406 } else {
1407
1408 if (qh->segsize < qh->maxpacket)
1409 done = true;
1410 else if (qh->offset == urb->transfer_buffer_length
1411 && !(urb->transfer_flags
1412 & URB_ZERO_PACKET))
1413 done = true;
1414 if (!done) {
1415 offset = qh->offset;
1416 length = urb->transfer_buffer_length - offset;
1417 transfer_pending = true;
1418 }
1419 }
1420 }
1421
1422
1423
1424
1425 if (urb->status != -EINPROGRESS) {
1426 done = true;
1427 if (status == 0)
1428 status = urb->status;
1429 }
1430
1431 if (done) {
1432
1433 urb->status = status;
1434 urb->actual_length = qh->offset;
1435 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1436 return;
1437 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1438 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1439 offset, length)) {
1440 if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
1441 musb_h_tx_dma_start(hw_ep);
1442 return;
1443 }
1444 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1445 musb_dbg(musb, "not complete, but DMA enabled?");
1446 return;
1447 }
1448
1449
1450
1451
1452
1453
1454
1455
1456 if (length > qh->maxpacket)
1457 length = qh->maxpacket;
1458
1459 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1460
1461
1462
1463
1464
1465 if (!urb->transfer_buffer)
1466 qh->use_sg = true;
1467
1468 if (qh->use_sg) {
1469
1470 if (!sg_miter_next(&qh->sg_miter)) {
1471 dev_err(musb->controller, "error: sg list empty\n");
1472 sg_miter_stop(&qh->sg_miter);
1473 status = -EINVAL;
1474 goto done;
1475 }
1476 urb->transfer_buffer = qh->sg_miter.addr;
1477 length = min_t(u32, length, qh->sg_miter.length);
1478 musb_write_fifo(hw_ep, length, urb->transfer_buffer);
1479 qh->sg_miter.consumed = length;
1480 sg_miter_stop(&qh->sg_miter);
1481 } else {
1482 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1483 }
1484
1485 qh->segsize = length;
1486
1487 if (qh->use_sg) {
1488 if (offset + length >= urb->transfer_buffer_length)
1489 qh->use_sg = false;
1490 }
1491
1492 musb_ep_select(mbase, epnum);
1493 musb_writew(epio, MUSB_TXCSR,
1494 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1495}
1496
1497#ifdef CONFIG_USB_TI_CPPI41_DMA
1498
1499static int musb_rx_dma_iso_cppi41(struct dma_controller *dma,
1500 struct musb_hw_ep *hw_ep,
1501 struct musb_qh *qh,
1502 struct urb *urb,
1503 size_t len)
1504{
1505 struct dma_channel *channel = hw_ep->rx_channel;
1506 void __iomem *epio = hw_ep->regs;
1507 dma_addr_t *buf;
1508 u32 length;
1509 u16 val;
1510
1511 buf = (void *)urb->iso_frame_desc[qh->iso_idx].offset +
1512 (u32)urb->transfer_dma;
1513
1514 length = urb->iso_frame_desc[qh->iso_idx].length;
1515
1516 val = musb_readw(epio, MUSB_RXCSR);
1517 val |= MUSB_RXCSR_DMAENAB;
1518 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1519
1520 return dma->channel_program(channel, qh->maxpacket, 0,
1521 (u32)buf, length);
1522}
1523#else
1524static inline int musb_rx_dma_iso_cppi41(struct dma_controller *dma,
1525 struct musb_hw_ep *hw_ep,
1526 struct musb_qh *qh,
1527 struct urb *urb,
1528 size_t len)
1529{
1530 return false;
1531}
1532#endif
1533
1534#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \
1535 defined(CONFIG_USB_TI_CPPI41_DMA)
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570static int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
1571 struct musb_hw_ep *hw_ep,
1572 struct musb_qh *qh,
1573 struct urb *urb,
1574 size_t len)
1575{
1576 struct dma_channel *channel = hw_ep->rx_channel;
1577 void __iomem *epio = hw_ep->regs;
1578 u16 val;
1579 int pipe;
1580 bool done;
1581
1582 pipe = urb->pipe;
1583
1584 if (usb_pipeisoc(pipe)) {
1585 struct usb_iso_packet_descriptor *d;
1586
1587 d = urb->iso_frame_desc + qh->iso_idx;
1588 d->actual_length = len;
1589
1590
1591
1592
1593 if (d->status != -EILSEQ && d->status != -EOVERFLOW)
1594 d->status = 0;
1595
1596 if (++qh->iso_idx >= urb->number_of_packets) {
1597 done = true;
1598 } else {
1599
1600 if (musb_dma_cppi41(hw_ep->musb))
1601 done = musb_rx_dma_iso_cppi41(dma, hw_ep, qh,
1602 urb, len);
1603 done = false;
1604 }
1605
1606 } else {
1607
1608 done = (urb->actual_length + len >=
1609 urb->transfer_buffer_length
1610 || channel->actual_len < qh->maxpacket
1611 || channel->rx_packet_done);
1612 }
1613
1614
1615 if (!done) {
1616 val = musb_readw(epio, MUSB_RXCSR);
1617 val |= MUSB_RXCSR_H_REQPKT;
1618 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
1619 }
1620
1621 return done;
1622}
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640static int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
1641 struct musb_hw_ep *hw_ep,
1642 struct musb_qh *qh,
1643 struct urb *urb,
1644 size_t len,
1645 u8 iso_err)
1646{
1647 struct musb *musb = hw_ep->musb;
1648 void __iomem *epio = hw_ep->regs;
1649 struct dma_channel *channel = hw_ep->rx_channel;
1650 u16 rx_count, val;
1651 int length, pipe, done;
1652 dma_addr_t buf;
1653
1654 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1655 pipe = urb->pipe;
1656
1657 if (usb_pipeisoc(pipe)) {
1658 int d_status = 0;
1659 struct usb_iso_packet_descriptor *d;
1660
1661 d = urb->iso_frame_desc + qh->iso_idx;
1662
1663 if (iso_err) {
1664 d_status = -EILSEQ;
1665 urb->error_count++;
1666 }
1667 if (rx_count > d->length) {
1668 if (d_status == 0) {
1669 d_status = -EOVERFLOW;
1670 urb->error_count++;
1671 }
1672 musb_dbg(musb, "** OVERFLOW %d into %d",
1673 rx_count, d->length);
1674
1675 length = d->length;
1676 } else
1677 length = rx_count;
1678 d->status = d_status;
1679 buf = urb->transfer_dma + d->offset;
1680 } else {
1681 length = rx_count;
1682 buf = urb->transfer_dma + urb->actual_length;
1683 }
1684
1685 channel->desired_mode = 0;
1686#ifdef USE_MODE1
1687
1688
1689
1690 if ((urb->transfer_flags & URB_SHORT_NOT_OK)
1691 && (urb->transfer_buffer_length - urb->actual_length)
1692 > qh->maxpacket)
1693 channel->desired_mode = 1;
1694 if (rx_count < hw_ep->max_packet_sz_rx) {
1695 length = rx_count;
1696 channel->desired_mode = 0;
1697 } else {
1698 length = urb->transfer_buffer_length;
1699 }
1700#endif
1701
1702
1703 val = musb_readw(epio, MUSB_RXCSR);
1704 val &= ~MUSB_RXCSR_H_REQPKT;
1705
1706 if (channel->desired_mode == 0)
1707 val &= ~MUSB_RXCSR_H_AUTOREQ;
1708 else
1709 val |= MUSB_RXCSR_H_AUTOREQ;
1710 val |= MUSB_RXCSR_DMAENAB;
1711
1712
1713 if (qh->hb_mult == 1)
1714 val |= MUSB_RXCSR_AUTOCLEAR;
1715
1716 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
1717
1718
1719
1720
1721
1722 done = dma->channel_program(channel, qh->maxpacket,
1723 channel->desired_mode,
1724 buf, length);
1725
1726 if (!done) {
1727 dma->channel_release(channel);
1728 hw_ep->rx_channel = NULL;
1729 channel = NULL;
1730 val = musb_readw(epio, MUSB_RXCSR);
1731 val &= ~(MUSB_RXCSR_DMAENAB
1732 | MUSB_RXCSR_H_AUTOREQ
1733 | MUSB_RXCSR_AUTOCLEAR);
1734 musb_writew(epio, MUSB_RXCSR, val);
1735 }
1736
1737 return done;
1738}
1739#else
1740static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
1741 struct musb_hw_ep *hw_ep,
1742 struct musb_qh *qh,
1743 struct urb *urb,
1744 size_t len)
1745{
1746 return false;
1747}
1748
1749static inline int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
1750 struct musb_hw_ep *hw_ep,
1751 struct musb_qh *qh,
1752 struct urb *urb,
1753 size_t len,
1754 u8 iso_err)
1755{
1756 return false;
1757}
1758#endif
1759
1760
1761
1762
1763
1764void musb_host_rx(struct musb *musb, u8 epnum)
1765{
1766 struct urb *urb;
1767 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1768 struct dma_controller *c = musb->dma_controller;
1769 void __iomem *epio = hw_ep->regs;
1770 struct musb_qh *qh = hw_ep->in_qh;
1771 size_t xfer_len;
1772 void __iomem *mbase = musb->mregs;
1773 u16 rx_csr, val;
1774 bool iso_err = false;
1775 bool done = false;
1776 u32 status;
1777 struct dma_channel *dma;
1778 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
1779
1780 musb_ep_select(mbase, epnum);
1781
1782 urb = next_urb(qh);
1783 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1784 status = 0;
1785 xfer_len = 0;
1786
1787 rx_csr = musb_readw(epio, MUSB_RXCSR);
1788 val = rx_csr;
1789
1790 if (unlikely(!urb)) {
1791
1792
1793
1794
1795 musb_dbg(musb, "BOGUS RX%d ready, csr %04x, count %d",
1796 epnum, val, musb_readw(epio, MUSB_RXCOUNT));
1797 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1798 return;
1799 }
1800
1801 trace_musb_urb_rx(musb, urb);
1802
1803
1804
1805 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1806 musb_dbg(musb, "RX end %d STALL", epnum);
1807
1808
1809 status = -EPIPE;
1810
1811 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1812 musb_dbg(musb, "end %d RX proto error", epnum);
1813
1814 status = -EPROTO;
1815 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1816
1817 rx_csr &= ~MUSB_RXCSR_H_ERROR;
1818 musb_writew(epio, MUSB_RXCSR, rx_csr);
1819
1820 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1821
1822 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1823 musb_dbg(musb, "RX end %d NAK timeout", epnum);
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833 if (usb_pipebulk(urb->pipe)
1834 && qh->mux == 1
1835 && !list_is_singular(&musb->in_bulk)) {
1836 musb_bulk_nak_timeout(musb, hw_ep, 1);
1837 return;
1838 }
1839 musb_ep_select(mbase, epnum);
1840 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1841 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1842 musb_writew(epio, MUSB_RXCSR, rx_csr);
1843
1844 goto finish;
1845 } else {
1846 musb_dbg(musb, "RX end %d ISO data error", epnum);
1847
1848 iso_err = true;
1849 }
1850 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1851 musb_dbg(musb, "end %d high bandwidth incomplete ISO packet RX",
1852 epnum);
1853 status = -EPROTO;
1854 }
1855
1856
1857 if (status) {
1858
1859 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1860 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1861 musb->dma_controller->channel_abort(dma);
1862 xfer_len = dma->actual_len;
1863 }
1864 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1865 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1866 done = true;
1867 goto finish;
1868 }
1869
1870 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1871
1872 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1873 goto finish;
1874 }
1875
1876
1877
1878
1879
1880
1881
1882 if (!musb_dma_inventra(musb) && !musb_dma_ux500(musb) &&
1883 (rx_csr & MUSB_RXCSR_H_REQPKT)) {
1884
1885
1886
1887
1888
1889 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1890 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1891 musb->dma_controller->channel_abort(dma);
1892 xfer_len = dma->actual_len;
1893 done = true;
1894 }
1895
1896 musb_dbg(musb, "RXCSR%d %04x, reqpkt, len %zu%s", epnum, rx_csr,
1897 xfer_len, dma ? ", dma" : "");
1898 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1899
1900 musb_ep_select(mbase, epnum);
1901 musb_writew(epio, MUSB_RXCSR,
1902 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1903 }
1904
1905 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1906 xfer_len = dma->actual_len;
1907
1908 val &= ~(MUSB_RXCSR_DMAENAB
1909 | MUSB_RXCSR_H_AUTOREQ
1910 | MUSB_RXCSR_AUTOCLEAR
1911 | MUSB_RXCSR_RXPKTRDY);
1912 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1913
1914 if (musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
1915 musb_dma_cppi41(musb)) {
1916 done = musb_rx_dma_inventra_cppi41(c, hw_ep, qh, urb, xfer_len);
1917 musb_dbg(hw_ep->musb,
1918 "ep %d dma %s, rxcsr %04x, rxcount %d",
1919 epnum, done ? "off" : "reset",
1920 musb_readw(epio, MUSB_RXCSR),
1921 musb_readw(epio, MUSB_RXCOUNT));
1922 } else {
1923 done = true;
1924 }
1925
1926 } else if (urb->status == -EINPROGRESS) {
1927
1928 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1929 status = -EPROTO;
1930 ERR("Rx interrupt with no errors or packet!\n");
1931
1932
1933
1934
1935
1936 musb_ep_select(mbase, epnum);
1937 val &= ~MUSB_RXCSR_H_REQPKT;
1938 musb_writew(epio, MUSB_RXCSR, val);
1939 goto finish;
1940 }
1941
1942
1943 if ((musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
1944 musb_dma_cppi41(musb)) && dma) {
1945 musb_dbg(hw_ep->musb,
1946 "RX%d count %d, buffer 0x%llx len %d/%d",
1947 epnum, musb_readw(epio, MUSB_RXCOUNT),
1948 (unsigned long long) urb->transfer_dma
1949 + urb->actual_length,
1950 qh->offset,
1951 urb->transfer_buffer_length);
1952
1953 if (musb_rx_dma_in_inventra_cppi41(c, hw_ep, qh, urb,
1954 xfer_len, iso_err))
1955 goto finish;
1956 else
1957 dev_err(musb->controller, "error: rx_dma failed\n");
1958 }
1959
1960 if (!dma) {
1961 unsigned int received_len;
1962
1963
1964 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1965
1966
1967
1968
1969
1970 if (!urb->transfer_buffer) {
1971 qh->use_sg = true;
1972 sg_miter_start(&qh->sg_miter, urb->sg, 1,
1973 sg_flags);
1974 }
1975
1976 if (qh->use_sg) {
1977 if (!sg_miter_next(&qh->sg_miter)) {
1978 dev_err(musb->controller, "error: sg list empty\n");
1979 sg_miter_stop(&qh->sg_miter);
1980 status = -EINVAL;
1981 done = true;
1982 goto finish;
1983 }
1984 urb->transfer_buffer = qh->sg_miter.addr;
1985 received_len = urb->actual_length;
1986 qh->offset = 0x0;
1987 done = musb_host_packet_rx(musb, urb, epnum,
1988 iso_err);
1989
1990 received_len = urb->actual_length -
1991 received_len;
1992 qh->sg_miter.consumed = received_len;
1993 sg_miter_stop(&qh->sg_miter);
1994 } else {
1995 done = musb_host_packet_rx(musb, urb,
1996 epnum, iso_err);
1997 }
1998 musb_dbg(musb, "read %spacket", done ? "last " : "");
1999 }
2000 }
2001
2002finish:
2003 urb->actual_length += xfer_len;
2004 qh->offset += xfer_len;
2005 if (done) {
2006 if (qh->use_sg)
2007 qh->use_sg = false;
2008
2009 if (urb->status == -EINPROGRESS)
2010 urb->status = status;
2011 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
2012 }
2013}
2014
2015
2016
2017
2018
2019
2020static int musb_schedule(
2021 struct musb *musb,
2022 struct musb_qh *qh,
2023 int is_in)
2024{
2025 int idle = 0;
2026 int best_diff;
2027 int best_end, epnum;
2028 struct musb_hw_ep *hw_ep = NULL;
2029 struct list_head *head = NULL;
2030 u8 toggle;
2031 u8 txtype;
2032 struct urb *urb = next_urb(qh);
2033
2034
2035 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
2036 head = &musb->control;
2037 hw_ep = musb->control_ep;
2038 goto success;
2039 }
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050 best_diff = 4096;
2051 best_end = -1;
2052
2053 for (epnum = 1, hw_ep = musb->endpoints + 1;
2054 epnum < musb->nr_endpoints;
2055 epnum++, hw_ep++) {
2056 int diff;
2057
2058 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
2059 continue;
2060
2061 if (hw_ep == musb->bulk_ep)
2062 continue;
2063
2064 if (is_in)
2065 diff = hw_ep->max_packet_sz_rx;
2066 else
2067 diff = hw_ep->max_packet_sz_tx;
2068 diff -= (qh->maxpacket * qh->hb_mult);
2069
2070 if (diff >= 0 && best_diff > diff) {
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084 hw_ep = musb->endpoints + epnum;
2085 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
2086 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
2087 >> 4) & 0x3;
2088 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
2089 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
2090 continue;
2091
2092 best_diff = diff;
2093 best_end = epnum;
2094 }
2095 }
2096
2097 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
2098 hw_ep = musb->bulk_ep;
2099 if (is_in)
2100 head = &musb->in_bulk;
2101 else
2102 head = &musb->out_bulk;
2103
2104
2105
2106
2107
2108
2109
2110
2111 if (qh->dev)
2112 qh->intv_reg =
2113 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
2114 goto success;
2115 } else if (best_end < 0) {
2116 dev_err(musb->controller,
2117 "%s hwep alloc failed for %dx%d\n",
2118 musb_ep_xfertype_string(qh->type),
2119 qh->hb_mult, qh->maxpacket);
2120 return -ENOSPC;
2121 }
2122
2123 idle = 1;
2124 qh->mux = 0;
2125 hw_ep = musb->endpoints + best_end;
2126 musb_dbg(musb, "qh %p periodic slot %d", qh, best_end);
2127success:
2128 if (head) {
2129 idle = list_empty(head);
2130 list_add_tail(&qh->ring, head);
2131 qh->mux = 1;
2132 }
2133 qh->hw_ep = hw_ep;
2134 qh->hep->hcpriv = qh;
2135 if (idle)
2136 musb_start_urb(musb, is_in, qh);
2137 return 0;
2138}
2139
2140static int musb_urb_enqueue(
2141 struct usb_hcd *hcd,
2142 struct urb *urb,
2143 gfp_t mem_flags)
2144{
2145 unsigned long flags;
2146 struct musb *musb = hcd_to_musb(hcd);
2147 struct usb_host_endpoint *hep = urb->ep;
2148 struct musb_qh *qh;
2149 struct usb_endpoint_descriptor *epd = &hep->desc;
2150 int ret;
2151 unsigned type_reg;
2152 unsigned interval;
2153
2154
2155 if (!is_host_active(musb) || !musb->is_active)
2156 return -ENODEV;
2157
2158 trace_musb_urb_enq(musb, urb);
2159
2160 spin_lock_irqsave(&musb->lock, flags);
2161 ret = usb_hcd_link_urb_to_ep(hcd, urb);
2162 qh = ret ? NULL : hep->hcpriv;
2163 if (qh)
2164 urb->hcpriv = qh;
2165 spin_unlock_irqrestore(&musb->lock, flags);
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175 if (qh || ret)
2176 return ret;
2177
2178
2179
2180
2181
2182
2183
2184 qh = kzalloc(sizeof *qh, mem_flags);
2185 if (!qh) {
2186 spin_lock_irqsave(&musb->lock, flags);
2187 usb_hcd_unlink_urb_from_ep(hcd, urb);
2188 spin_unlock_irqrestore(&musb->lock, flags);
2189 return -ENOMEM;
2190 }
2191
2192 qh->hep = hep;
2193 qh->dev = urb->dev;
2194 INIT_LIST_HEAD(&qh->ring);
2195 qh->is_ready = 1;
2196
2197 qh->maxpacket = usb_endpoint_maxp(epd);
2198 qh->type = usb_endpoint_type(epd);
2199
2200
2201
2202
2203
2204 qh->hb_mult = usb_endpoint_maxp_mult(epd);
2205 if (qh->hb_mult > 1) {
2206 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
2207
2208 if (ok)
2209 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
2210 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
2211 if (!ok) {
2212 dev_err(musb->controller,
2213 "high bandwidth %s (%dx%d) not supported\n",
2214 musb_ep_xfertype_string(qh->type),
2215 qh->hb_mult, qh->maxpacket & 0x7ff);
2216 ret = -EMSGSIZE;
2217 goto done;
2218 }
2219 qh->maxpacket &= 0x7ff;
2220 }
2221
2222 qh->epnum = usb_endpoint_num(epd);
2223
2224
2225 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
2226
2227
2228 type_reg = (qh->type << 4) | qh->epnum;
2229 switch (urb->dev->speed) {
2230 case USB_SPEED_LOW:
2231 type_reg |= 0xc0;
2232 break;
2233 case USB_SPEED_FULL:
2234 type_reg |= 0x80;
2235 break;
2236 default:
2237 type_reg |= 0x40;
2238 }
2239 qh->type_reg = type_reg;
2240
2241
2242 switch (qh->type) {
2243 case USB_ENDPOINT_XFER_INT:
2244
2245
2246
2247
2248 if (urb->dev->speed <= USB_SPEED_FULL) {
2249 interval = max_t(u8, epd->bInterval, 1);
2250 break;
2251 }
2252
2253 case USB_ENDPOINT_XFER_ISOC:
2254
2255 interval = min_t(u8, epd->bInterval, 16);
2256 break;
2257 default:
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272 interval = 0;
2273 }
2274 qh->intv_reg = interval;
2275
2276
2277 if (musb->is_multipoint) {
2278 struct usb_device *parent = urb->dev->parent;
2279
2280 if (parent != hcd->self.root_hub) {
2281 qh->h_addr_reg = (u8) parent->devnum;
2282
2283
2284 if (urb->dev->tt) {
2285 qh->h_port_reg = (u8) urb->dev->ttport;
2286 if (urb->dev->tt->hub)
2287 qh->h_addr_reg =
2288 (u8) urb->dev->tt->hub->devnum;
2289 if (urb->dev->tt->multi)
2290 qh->h_addr_reg |= 0x80;
2291 }
2292 }
2293 }
2294
2295
2296
2297
2298
2299 spin_lock_irqsave(&musb->lock, flags);
2300 if (hep->hcpriv || !next_urb(qh)) {
2301
2302
2303
2304 kfree(qh);
2305 qh = NULL;
2306 ret = 0;
2307 } else
2308 ret = musb_schedule(musb, qh,
2309 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2310
2311 if (ret == 0) {
2312 urb->hcpriv = qh;
2313
2314
2315
2316 }
2317 spin_unlock_irqrestore(&musb->lock, flags);
2318
2319done:
2320 if (ret != 0) {
2321 spin_lock_irqsave(&musb->lock, flags);
2322 usb_hcd_unlink_urb_from_ep(hcd, urb);
2323 spin_unlock_irqrestore(&musb->lock, flags);
2324 kfree(qh);
2325 }
2326 return ret;
2327}
2328
2329
2330
2331
2332
2333
2334
2335static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2336{
2337 struct musb_hw_ep *ep = qh->hw_ep;
2338 struct musb *musb = ep->musb;
2339 void __iomem *epio = ep->regs;
2340 unsigned hw_end = ep->epnum;
2341 void __iomem *regs = ep->musb->mregs;
2342 int is_in = usb_pipein(urb->pipe);
2343 int status = 0;
2344 u16 csr;
2345 struct dma_channel *dma = NULL;
2346
2347 musb_ep_select(regs, hw_end);
2348
2349 if (is_dma_capable()) {
2350 dma = is_in ? ep->rx_channel : ep->tx_channel;
2351 if (dma) {
2352 status = ep->musb->dma_controller->channel_abort(dma);
2353 musb_dbg(musb, "abort %cX%d DMA for urb %p --> %d",
2354 is_in ? 'R' : 'T', ep->epnum,
2355 urb, status);
2356 urb->actual_length += dma->actual_len;
2357 }
2358 }
2359
2360
2361 if (ep->epnum && is_in) {
2362
2363 csr = musb_h_flush_rxfifo(ep, 0);
2364
2365
2366 if (is_dma_capable() && dma)
2367 musb_platform_clear_ep_rxintr(musb, ep->epnum);
2368 } else if (ep->epnum) {
2369 musb_h_tx_flush_fifo(ep);
2370 csr = musb_readw(epio, MUSB_TXCSR);
2371 csr &= ~(MUSB_TXCSR_AUTOSET
2372 | MUSB_TXCSR_DMAENAB
2373 | MUSB_TXCSR_H_RXSTALL
2374 | MUSB_TXCSR_H_NAKTIMEOUT
2375 | MUSB_TXCSR_H_ERROR
2376 | MUSB_TXCSR_TXPKTRDY);
2377 musb_writew(epio, MUSB_TXCSR, csr);
2378
2379 musb_writew(epio, MUSB_TXCSR, csr);
2380
2381 csr = musb_readw(epio, MUSB_TXCSR);
2382 } else {
2383 musb_h_ep0_flush_fifo(ep);
2384 }
2385 if (status == 0)
2386 musb_advance_schedule(ep->musb, urb, ep, is_in);
2387 return status;
2388}
2389
2390static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2391{
2392 struct musb *musb = hcd_to_musb(hcd);
2393 struct musb_qh *qh;
2394 unsigned long flags;
2395 int is_in = usb_pipein(urb->pipe);
2396 int ret;
2397
2398 trace_musb_urb_deq(musb, urb);
2399
2400 spin_lock_irqsave(&musb->lock, flags);
2401 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2402 if (ret)
2403 goto done;
2404
2405 qh = urb->hcpriv;
2406 if (!qh)
2407 goto done;
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421 if (!qh->is_ready
2422 || urb->urb_list.prev != &qh->hep->urb_list
2423 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2424 int ready = qh->is_ready;
2425
2426 qh->is_ready = 0;
2427 musb_giveback(musb, urb, 0);
2428 qh->is_ready = ready;
2429
2430
2431
2432
2433 if (ready && list_empty(&qh->hep->urb_list)) {
2434 qh->hep->hcpriv = NULL;
2435 list_del(&qh->ring);
2436 kfree(qh);
2437 }
2438 } else
2439 ret = musb_cleanup_urb(urb, qh);
2440done:
2441 spin_unlock_irqrestore(&musb->lock, flags);
2442 return ret;
2443}
2444
2445
2446static void
2447musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2448{
2449 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2450 unsigned long flags;
2451 struct musb *musb = hcd_to_musb(hcd);
2452 struct musb_qh *qh;
2453 struct urb *urb;
2454
2455 spin_lock_irqsave(&musb->lock, flags);
2456
2457 qh = hep->hcpriv;
2458 if (qh == NULL)
2459 goto exit;
2460
2461
2462
2463
2464 qh->is_ready = 0;
2465 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2466 urb = next_urb(qh);
2467
2468
2469 if (!urb->unlinked)
2470 urb->status = -ESHUTDOWN;
2471
2472
2473 musb_cleanup_urb(urb, qh);
2474
2475
2476
2477
2478 while (!list_empty(&hep->urb_list)) {
2479 urb = next_urb(qh);
2480 urb->status = -ESHUTDOWN;
2481 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2482 }
2483 } else {
2484
2485
2486
2487
2488 while (!list_empty(&hep->urb_list))
2489 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2490
2491 hep->hcpriv = NULL;
2492 list_del(&qh->ring);
2493 kfree(qh);
2494 }
2495exit:
2496 spin_unlock_irqrestore(&musb->lock, flags);
2497}
2498
2499static int musb_h_get_frame_number(struct usb_hcd *hcd)
2500{
2501 struct musb *musb = hcd_to_musb(hcd);
2502
2503 return musb_readw(musb->mregs, MUSB_FRAME);
2504}
2505
2506static int musb_h_start(struct usb_hcd *hcd)
2507{
2508 struct musb *musb = hcd_to_musb(hcd);
2509
2510
2511
2512
2513 hcd->state = HC_STATE_RUNNING;
2514 musb->port1_status = 0;
2515 return 0;
2516}
2517
2518static void musb_h_stop(struct usb_hcd *hcd)
2519{
2520 musb_stop(hcd_to_musb(hcd));
2521 hcd->state = HC_STATE_HALT;
2522}
2523
2524static int musb_bus_suspend(struct usb_hcd *hcd)
2525{
2526 struct musb *musb = hcd_to_musb(hcd);
2527 u8 devctl;
2528 int ret;
2529
2530 ret = musb_port_suspend(musb, true);
2531 if (ret)
2532 return ret;
2533
2534 if (!is_host_active(musb))
2535 return 0;
2536
2537 switch (musb->xceiv->otg->state) {
2538 case OTG_STATE_A_SUSPEND:
2539 return 0;
2540 case OTG_STATE_A_WAIT_VRISE:
2541
2542
2543
2544
2545 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2546 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2547 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
2548 break;
2549 default:
2550 break;
2551 }
2552
2553 if (musb->is_active) {
2554 WARNING("trying to suspend as %s while active\n",
2555 usb_otg_state_string(musb->xceiv->otg->state));
2556 return -EBUSY;
2557 } else
2558 return 0;
2559}
2560
2561static int musb_bus_resume(struct usb_hcd *hcd)
2562{
2563 struct musb *musb = hcd_to_musb(hcd);
2564
2565 if (musb->config &&
2566 musb->config->host_port_deassert_reset_at_resume)
2567 musb_port_reset(musb, false);
2568
2569 return 0;
2570}
2571
2572#ifndef CONFIG_MUSB_PIO_ONLY
2573
2574#define MUSB_USB_DMA_ALIGN 4
2575
2576struct musb_temp_buffer {
2577 void *kmalloc_ptr;
2578 void *old_xfer_buffer;
2579 u8 data[0];
2580};
2581
2582static void musb_free_temp_buffer(struct urb *urb)
2583{
2584 enum dma_data_direction dir;
2585 struct musb_temp_buffer *temp;
2586 size_t length;
2587
2588 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2589 return;
2590
2591 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2592
2593 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer,
2594 data);
2595
2596 if (dir == DMA_FROM_DEVICE) {
2597 if (usb_pipeisoc(urb->pipe))
2598 length = urb->transfer_buffer_length;
2599 else
2600 length = urb->actual_length;
2601
2602 memcpy(temp->old_xfer_buffer, temp->data, length);
2603 }
2604 urb->transfer_buffer = temp->old_xfer_buffer;
2605 kfree(temp->kmalloc_ptr);
2606
2607 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2608}
2609
2610static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
2611{
2612 enum dma_data_direction dir;
2613 struct musb_temp_buffer *temp;
2614 void *kmalloc_ptr;
2615 size_t kmalloc_size;
2616
2617 if (urb->num_sgs || urb->sg ||
2618 urb->transfer_buffer_length == 0 ||
2619 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1)))
2620 return 0;
2621
2622 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2623
2624
2625 kmalloc_size = urb->transfer_buffer_length +
2626 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1;
2627
2628 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2629 if (!kmalloc_ptr)
2630 return -ENOMEM;
2631
2632
2633 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN);
2634
2635
2636 temp->kmalloc_ptr = kmalloc_ptr;
2637 temp->old_xfer_buffer = urb->transfer_buffer;
2638 if (dir == DMA_TO_DEVICE)
2639 memcpy(temp->data, urb->transfer_buffer,
2640 urb->transfer_buffer_length);
2641 urb->transfer_buffer = temp->data;
2642
2643 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2644
2645 return 0;
2646}
2647
2648static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2649 gfp_t mem_flags)
2650{
2651 struct musb *musb = hcd_to_musb(hcd);
2652 int ret;
2653
2654
2655
2656
2657
2658
2659
2660 if (musb->hwvers < MUSB_HWVERS_1800)
2661 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2662
2663 ret = musb_alloc_temp_buffer(urb, mem_flags);
2664 if (ret)
2665 return ret;
2666
2667 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2668 if (ret)
2669 musb_free_temp_buffer(urb);
2670
2671 return ret;
2672}
2673
2674static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2675{
2676 struct musb *musb = hcd_to_musb(hcd);
2677
2678 usb_hcd_unmap_urb_for_dma(hcd, urb);
2679
2680
2681 if (musb->hwvers < MUSB_HWVERS_1800)
2682 return;
2683
2684 musb_free_temp_buffer(urb);
2685}
2686#endif
2687
2688static const struct hc_driver musb_hc_driver = {
2689 .description = "musb-hcd",
2690 .product_desc = "MUSB HDRC host driver",
2691 .hcd_priv_size = sizeof(struct musb *),
2692 .flags = HCD_USB2 | HCD_MEMORY,
2693
2694
2695
2696
2697
2698 .start = musb_h_start,
2699 .stop = musb_h_stop,
2700
2701 .get_frame_number = musb_h_get_frame_number,
2702
2703 .urb_enqueue = musb_urb_enqueue,
2704 .urb_dequeue = musb_urb_dequeue,
2705 .endpoint_disable = musb_h_disable,
2706
2707#ifndef CONFIG_MUSB_PIO_ONLY
2708 .map_urb_for_dma = musb_map_urb_for_dma,
2709 .unmap_urb_for_dma = musb_unmap_urb_for_dma,
2710#endif
2711
2712 .hub_status_data = musb_hub_status_data,
2713 .hub_control = musb_hub_control,
2714 .bus_suspend = musb_bus_suspend,
2715 .bus_resume = musb_bus_resume,
2716
2717
2718};
2719
2720int musb_host_alloc(struct musb *musb)
2721{
2722 struct device *dev = musb->controller;
2723
2724
2725 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2726 if (!musb->hcd)
2727 return -EINVAL;
2728
2729 *musb->hcd->hcd_priv = (unsigned long) musb;
2730 musb->hcd->self.uses_pio_for_control = 1;
2731 musb->hcd->uses_new_polling = 1;
2732 musb->hcd->has_tt = 1;
2733
2734 return 0;
2735}
2736
2737void musb_host_cleanup(struct musb *musb)
2738{
2739 if (musb->port_mode == MUSB_PERIPHERAL)
2740 return;
2741 usb_remove_hcd(musb->hcd);
2742}
2743
2744void musb_host_free(struct musb *musb)
2745{
2746 usb_put_hcd(musb->hcd);
2747}
2748
2749int musb_host_setup(struct musb *musb, int power_budget)
2750{
2751 int ret;
2752 struct usb_hcd *hcd = musb->hcd;
2753
2754 if (musb->port_mode == MUSB_HOST) {
2755 MUSB_HST_MODE(musb);
2756 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2757 }
2758 otg_set_host(musb->xceiv->otg, &hcd->self);
2759
2760 hcd->self.otg_port = 0;
2761 musb->xceiv->otg->host = &hcd->self;
2762 hcd->power_budget = 2 * (power_budget ? : 250);
2763 hcd->skip_phy_initialization = 1;
2764
2765 ret = usb_add_hcd(hcd, 0, 0);
2766 if (ret < 0)
2767 return ret;
2768
2769 device_wakeup_enable(hcd->self.controller);
2770 return 0;
2771}
2772
2773void musb_host_resume_root_hub(struct musb *musb)
2774{
2775 usb_hcd_resume_root_hub(musb->hcd);
2776}
2777
2778void musb_host_poke_root_hub(struct musb *musb)
2779{
2780 MUSB_HST_MODE(musb);
2781 if (musb->hcd->status_urb)
2782 usb_hcd_poll_rh_status(musb->hcd);
2783 else
2784 usb_hcd_resume_root_hub(musb->hcd);
2785}
2786