1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 */ 6 7#ifndef _DT_BINDINGS_CLK_MT8183_H 8#define _DT_BINDINGS_CLK_MT8183_H 9 10/* APMIXED */ 11#define CLK_APMIXED_ARMPLL_LL 0 12#define CLK_APMIXED_ARMPLL_L 1 13#define CLK_APMIXED_CCIPLL 2 14#define CLK_APMIXED_MAINPLL 3 15#define CLK_APMIXED_UNIV2PLL 4 16#define CLK_APMIXED_MSDCPLL 5 17#define CLK_APMIXED_MMPLL 6 18#define CLK_APMIXED_MFGPLL 7 19#define CLK_APMIXED_TVDPLL 8 20#define CLK_APMIXED_APLL1 9 21#define CLK_APMIXED_APLL2 10 22#define CLK_APMIXED_SSUSB_26M 11 23#define CLK_APMIXED_APPLL_26M 12 24#define CLK_APMIXED_MIPIC0_26M 13 25#define CLK_APMIXED_MDPLLGP_26M 14 26#define CLK_APMIXED_MMSYS_26M 15 27#define CLK_APMIXED_UFS_26M 16 28#define CLK_APMIXED_MIPIC1_26M 17 29#define CLK_APMIXED_MEMPLL_26M 18 30#define CLK_APMIXED_CLKSQ_LVPLL_26M 19 31#define CLK_APMIXED_MIPID0_26M 20 32#define CLK_APMIXED_MIPID1_26M 21 33#define CLK_APMIXED_NR_CLK 22 34 35/* TOPCKGEN */ 36#define CLK_TOP_MUX_AXI 0 37#define CLK_TOP_MUX_MM 1 38#define CLK_TOP_MUX_CAM 2 39#define CLK_TOP_MUX_MFG 3 40#define CLK_TOP_MUX_CAMTG 4 41#define CLK_TOP_MUX_UART 5 42#define CLK_TOP_MUX_SPI 6 43#define CLK_TOP_MUX_MSDC50_0_HCLK 7 44#define CLK_TOP_MUX_MSDC50_0 8 45#define CLK_TOP_MUX_MSDC30_1 9 46#define CLK_TOP_MUX_MSDC30_2 10 47#define CLK_TOP_MUX_AUDIO 11 48#define CLK_TOP_MUX_AUD_INTBUS 12 49#define CLK_TOP_MUX_FPWRAP_ULPOSC 13 50#define CLK_TOP_MUX_SCP 14 51#define CLK_TOP_MUX_ATB 15 52#define CLK_TOP_MUX_SSPM 16 53#define CLK_TOP_MUX_DPI0 17 54#define CLK_TOP_MUX_SCAM 18 55#define CLK_TOP_MUX_AUD_1 19 56#define CLK_TOP_MUX_AUD_2 20 57#define CLK_TOP_MUX_DISP_PWM 21 58#define CLK_TOP_MUX_SSUSB_TOP_XHCI 22 59#define CLK_TOP_MUX_USB_TOP 23 60#define CLK_TOP_MUX_SPM 24 61#define CLK_TOP_MUX_I2C 25 62#define CLK_TOP_MUX_F52M_MFG 26 63#define CLK_TOP_MUX_SENINF 27 64#define CLK_TOP_MUX_DXCC 28 65#define CLK_TOP_MUX_CAMTG2 29 66#define CLK_TOP_MUX_AUD_ENG1 30 67#define CLK_TOP_MUX_AUD_ENG2 31 68#define CLK_TOP_MUX_FAES_UFSFDE 32 69#define CLK_TOP_MUX_FUFS 33 70#define CLK_TOP_MUX_IMG 34 71#define CLK_TOP_MUX_DSP 35 72#define CLK_TOP_MUX_DSP1 36 73#define CLK_TOP_MUX_DSP2 37 74#define CLK_TOP_MUX_IPU_IF 38 75#define CLK_TOP_MUX_CAMTG3 39 76#define CLK_TOP_MUX_CAMTG4 40 77#define CLK_TOP_MUX_PMICSPI 41 78#define CLK_TOP_SYSPLL_CK 42 79#define CLK_TOP_SYSPLL_D2 43 80#define CLK_TOP_SYSPLL_D3 44 81#define CLK_TOP_SYSPLL_D5 45 82#define CLK_TOP_SYSPLL_D7 46 83#define CLK_TOP_SYSPLL_D2_D2 47 84#define CLK_TOP_SYSPLL_D2_D4 48 85#define CLK_TOP_SYSPLL_D2_D8 49 86#define CLK_TOP_SYSPLL_D2_D16 50 87#define CLK_TOP_SYSPLL_D3_D2 51 88#define CLK_TOP_SYSPLL_D3_D4 52 89#define CLK_TOP_SYSPLL_D3_D8 53 90#define CLK_TOP_SYSPLL_D5_D2 54 91#define CLK_TOP_SYSPLL_D5_D4 55 92#define CLK_TOP_SYSPLL_D7_D2 56 93#define CLK_TOP_SYSPLL_D7_D4 57 94#define CLK_TOP_UNIVPLL_CK 58 95#define CLK_TOP_UNIVPLL_D2 59 96#define CLK_TOP_UNIVPLL_D3 60 97#define CLK_TOP_UNIVPLL_D5 61 98#define CLK_TOP_UNIVPLL_D7 62 99#define CLK_TOP_UNIVPLL_D2_D2 63 100#define CLK_TOP_UNIVPLL_D2_D4 64 101#define CLK_TOP_UNIVPLL_D2_D8 65 102#define CLK_TOP_UNIVPLL_D3_D2 66 103#define CLK_TOP_UNIVPLL_D3_D4 67 104#define CLK_TOP_UNIVPLL_D3_D8 68 105#define CLK_TOP_UNIVPLL_D5_D2 69 106#define CLK_TOP_UNIVPLL_D5_D4 70 107#define CLK_TOP_UNIVPLL_D5_D8 71 108#define CLK_TOP_APLL1_CK 72 109#define CLK_TOP_APLL1_D2 73 110#define CLK_TOP_APLL1_D4 74 111#define CLK_TOP_APLL1_D8 75 112#define CLK_TOP_APLL2_CK 76 113#define CLK_TOP_APLL2_D2 77 114#define CLK_TOP_APLL2_D4 78 115#define CLK_TOP_APLL2_D8 79 116#define CLK_TOP_TVDPLL_CK 80 117#define CLK_TOP_TVDPLL_D2 81 118#define CLK_TOP_TVDPLL_D4 82 119#define CLK_TOP_TVDPLL_D8 83 120#define CLK_TOP_TVDPLL_D16 84 121#define CLK_TOP_MSDCPLL_CK 85 122#define CLK_TOP_MSDCPLL_D2 86 123#define CLK_TOP_MSDCPLL_D4 87 124#define CLK_TOP_MSDCPLL_D8 88 125#define CLK_TOP_MSDCPLL_D16 89 126#define CLK_TOP_AD_OSC_CK 90 127#define CLK_TOP_OSC_D2 91 128#define CLK_TOP_OSC_D4 92 129#define CLK_TOP_OSC_D8 93 130#define CLK_TOP_OSC_D16 94 131#define CLK_TOP_F26M_CK_D2 95 132#define CLK_TOP_MFGPLL_CK 96 133#define CLK_TOP_UNIVP_192M_CK 97 134#define CLK_TOP_UNIVP_192M_D2 98 135#define CLK_TOP_UNIVP_192M_D4 99 136#define CLK_TOP_UNIVP_192M_D8 100 137#define CLK_TOP_UNIVP_192M_D16 101 138#define CLK_TOP_UNIVP_192M_D32 102 139#define CLK_TOP_MMPLL_CK 103 140#define CLK_TOP_MMPLL_D4 104 141#define CLK_TOP_MMPLL_D4_D2 105 142#define CLK_TOP_MMPLL_D4_D4 106 143#define CLK_TOP_MMPLL_D5 107 144#define CLK_TOP_MMPLL_D5_D2 108 145#define CLK_TOP_MMPLL_D5_D4 109 146#define CLK_TOP_MMPLL_D6 110 147#define CLK_TOP_MMPLL_D7 111 148#define CLK_TOP_CLK26M 112 149#define CLK_TOP_CLK13M 113 150#define CLK_TOP_ULPOSC 114 151#define CLK_TOP_UNIVP_192M 115 152#define CLK_TOP_MUX_APLL_I2S0 116 153#define CLK_TOP_MUX_APLL_I2S1 117 154#define CLK_TOP_MUX_APLL_I2S2 118 155#define CLK_TOP_MUX_APLL_I2S3 119 156#define CLK_TOP_MUX_APLL_I2S4 120 157#define CLK_TOP_MUX_APLL_I2S5 121 158#define CLK_TOP_APLL12_DIV0 122 159#define CLK_TOP_APLL12_DIV1 123 160#define CLK_TOP_APLL12_DIV2 124 161#define CLK_TOP_APLL12_DIV3 125 162#define CLK_TOP_APLL12_DIV4 126 163#define CLK_TOP_APLL12_DIVB 127 164#define CLK_TOP_UNIVPLL 128 165#define CLK_TOP_ARMPLL_DIV_PLL1 129 166#define CLK_TOP_ARMPLL_DIV_PLL2 130 167#define CLK_TOP_UNIVPLL_D3_D16 131 168#define CLK_TOP_NR_CLK 132 169 170/* CAMSYS */ 171#define CLK_CAM_LARB6 0 172#define CLK_CAM_DFP_VAD 1 173#define CLK_CAM_CAM 2 174#define CLK_CAM_CAMTG 3 175#define CLK_CAM_SENINF 4 176#define CLK_CAM_CAMSV0 5 177#define CLK_CAM_CAMSV1 6 178#define CLK_CAM_CAMSV2 7 179#define CLK_CAM_CCU 8 180#define CLK_CAM_LARB3 9 181#define CLK_CAM_NR_CLK 10 182 183/* INFRACFG_AO */ 184#define CLK_INFRA_PMIC_TMR 0 185#define CLK_INFRA_PMIC_AP 1 186#define CLK_INFRA_PMIC_MD 2 187#define CLK_INFRA_PMIC_CONN 3 188#define CLK_INFRA_SCPSYS 4 189#define CLK_INFRA_SEJ 5 190#define CLK_INFRA_APXGPT 6 191#define CLK_INFRA_ICUSB 7 192#define CLK_INFRA_GCE 8 193#define CLK_INFRA_THERM 9 194#define CLK_INFRA_I2C0 10 195#define CLK_INFRA_I2C1 11 196#define CLK_INFRA_I2C2 12 197#define CLK_INFRA_I2C3 13 198#define CLK_INFRA_PWM_HCLK 14 199#define CLK_INFRA_PWM1 15 200#define CLK_INFRA_PWM2 16 201#define CLK_INFRA_PWM3 17 202#define CLK_INFRA_PWM4 18 203#define CLK_INFRA_PWM 19 204#define CLK_INFRA_UART0 20 205#define CLK_INFRA_UART1 21 206#define CLK_INFRA_UART2 22 207#define CLK_INFRA_UART3 23 208#define CLK_INFRA_GCE_26M 24 209#define CLK_INFRA_CQ_DMA_FPC 25 210#define CLK_INFRA_BTIF 26 211#define CLK_INFRA_SPI0 27 212#define CLK_INFRA_MSDC0 28 213#define CLK_INFRA_MSDC1 29 214#define CLK_INFRA_MSDC2 30 215#define CLK_INFRA_MSDC0_SCK 31 216#define CLK_INFRA_DVFSRC 32 217#define CLK_INFRA_GCPU 33 218#define CLK_INFRA_TRNG 34 219#define CLK_INFRA_AUXADC 35 220#define CLK_INFRA_CPUM 36 221#define CLK_INFRA_CCIF1_AP 37 222#define CLK_INFRA_CCIF1_MD 38 223#define CLK_INFRA_AUXADC_MD 39 224#define CLK_INFRA_MSDC1_SCK 40 225#define CLK_INFRA_MSDC2_SCK 41 226#define CLK_INFRA_AP_DMA 42 227#define CLK_INFRA_XIU 43 228#define CLK_INFRA_DEVICE_APC 44 229#define CLK_INFRA_CCIF_AP 45 230#define CLK_INFRA_DEBUGSYS 46 231#define CLK_INFRA_AUDIO 47 232#define CLK_INFRA_CCIF_MD 48 233#define CLK_INFRA_DXCC_SEC_CORE 49 234#define CLK_INFRA_DXCC_AO 50 235#define CLK_INFRA_DRAMC_F26M 51 236#define CLK_INFRA_IRTX 52 237#define CLK_INFRA_DISP_PWM 53 238#define CLK_INFRA_CLDMA_BCLK 54 239#define CLK_INFRA_AUDIO_26M_BCLK 55 240#define CLK_INFRA_SPI1 56 241#define CLK_INFRA_I2C4 57 242#define CLK_INFRA_MODEM_TEMP_SHARE 58 243#define CLK_INFRA_SPI2 59 244#define CLK_INFRA_SPI3 60 245#define CLK_INFRA_UNIPRO_SCK 61 246#define CLK_INFRA_UNIPRO_TICK 62 247#define CLK_INFRA_UFS_MP_SAP_BCLK 63 248#define CLK_INFRA_MD32_BCLK 64 249#define CLK_INFRA_SSPM 65 250#define CLK_INFRA_UNIPRO_MBIST 66 251#define CLK_INFRA_SSPM_BUS_HCLK 67 252#define CLK_INFRA_I2C5 68 253#define CLK_INFRA_I2C5_ARBITER 69 254#define CLK_INFRA_I2C5_IMM 70 255#define CLK_INFRA_I2C1_ARBITER 71 256#define CLK_INFRA_I2C1_IMM 72 257#define CLK_INFRA_I2C2_ARBITER 73 258#define CLK_INFRA_I2C2_IMM 74 259#define CLK_INFRA_SPI4 75 260#define CLK_INFRA_SPI5 76 261#define CLK_INFRA_CQ_DMA 77 262#define CLK_INFRA_UFS 78 263#define CLK_INFRA_AES_UFSFDE 79 264#define CLK_INFRA_UFS_TICK 80 265#define CLK_INFRA_MSDC0_SELF 81 266#define CLK_INFRA_MSDC1_SELF 82 267#define CLK_INFRA_MSDC2_SELF 83 268#define CLK_INFRA_SSPM_26M_SELF 84 269#define CLK_INFRA_SSPM_32K_SELF 85 270#define CLK_INFRA_UFS_AXI 86 271#define CLK_INFRA_I2C6 87 272#define CLK_INFRA_AP_MSDC0 88 273#define CLK_INFRA_MD_MSDC0 89 274#define CLK_INFRA_USB 90 275#define CLK_INFRA_DEVMPU_BCLK 91 276#define CLK_INFRA_CCIF2_AP 92 277#define CLK_INFRA_CCIF2_MD 93 278#define CLK_INFRA_CCIF3_AP 94 279#define CLK_INFRA_CCIF3_MD 95 280#define CLK_INFRA_SEJ_F13M 96 281#define CLK_INFRA_AES_BCLK 97 282#define CLK_INFRA_I2C7 98 283#define CLK_INFRA_I2C8 99 284#define CLK_INFRA_FBIST2FPC 100 285#define CLK_INFRA_NR_CLK 101 286 287/* MFGCFG */ 288#define CLK_MFG_BG3D 0 289#define CLK_MFG_NR_CLK 1 290 291/* IMG */ 292#define CLK_IMG_OWE 0 293#define CLK_IMG_WPE_B 1 294#define CLK_IMG_WPE_A 2 295#define CLK_IMG_MFB 3 296#define CLK_IMG_RSC 4 297#define CLK_IMG_DPE 5 298#define CLK_IMG_FDVT 6 299#define CLK_IMG_DIP 7 300#define CLK_IMG_LARB2 8 301#define CLK_IMG_LARB5 9 302#define CLK_IMG_NR_CLK 10 303 304/* MMSYS_CONFIG */ 305#define CLK_MM_SMI_COMMON 0 306#define CLK_MM_SMI_LARB0 1 307#define CLK_MM_SMI_LARB1 2 308#define CLK_MM_GALS_COMM0 3 309#define CLK_MM_GALS_COMM1 4 310#define CLK_MM_GALS_CCU2MM 5 311#define CLK_MM_GALS_IPU12MM 6 312#define CLK_MM_GALS_IMG2MM 7 313#define CLK_MM_GALS_CAM2MM 8 314#define CLK_MM_GALS_IPU2MM 9 315#define CLK_MM_MDP_DL_TXCK 10 316#define CLK_MM_IPU_DL_TXCK 11 317#define CLK_MM_MDP_RDMA0 12 318#define CLK_MM_MDP_RDMA1 13 319#define CLK_MM_MDP_RSZ0 14 320#define CLK_MM_MDP_RSZ1 15 321#define CLK_MM_MDP_TDSHP 16 322#define CLK_MM_MDP_WROT0 17 323#define CLK_MM_FAKE_ENG 18 324#define CLK_MM_DISP_OVL0 19 325#define CLK_MM_DISP_OVL0_2L 20 326#define CLK_MM_DISP_OVL1_2L 21 327#define CLK_MM_DISP_RDMA0 22 328#define CLK_MM_DISP_RDMA1 23 329#define CLK_MM_DISP_WDMA0 24 330#define CLK_MM_DISP_COLOR0 25 331#define CLK_MM_DISP_CCORR0 26 332#define CLK_MM_DISP_AAL0 27 333#define CLK_MM_DISP_GAMMA0 28 334#define CLK_MM_DISP_DITHER0 29 335#define CLK_MM_DISP_SPLIT 30 336#define CLK_MM_DSI0_MM 31 337#define CLK_MM_DSI0_IF 32 338#define CLK_MM_DPI_MM 33 339#define CLK_MM_DPI_IF 34 340#define CLK_MM_FAKE_ENG2 35 341#define CLK_MM_MDP_DL_RX 36 342#define CLK_MM_IPU_DL_RX 37 343#define CLK_MM_26M 38 344#define CLK_MM_MMSYS_R2Y 39 345#define CLK_MM_DISP_RSZ 40 346#define CLK_MM_MDP_WDMA0 41 347#define CLK_MM_MDP_AAL 42 348#define CLK_MM_MDP_CCORR 43 349#define CLK_MM_DBI_MM 44 350#define CLK_MM_DBI_IF 45 351#define CLK_MM_NR_CLK 46 352 353/* VDEC_GCON */ 354#define CLK_VDEC_VDEC 0 355#define CLK_VDEC_LARB1 1 356#define CLK_VDEC_NR_CLK 2 357 358/* VENC_GCON */ 359#define CLK_VENC_LARB 0 360#define CLK_VENC_VENC 1 361#define CLK_VENC_JPGENC 2 362#define CLK_VENC_NR_CLK 3 363 364/* AUDIO */ 365#define CLK_AUDIO_TML 0 366#define CLK_AUDIO_DAC_PREDIS 1 367#define CLK_AUDIO_DAC 2 368#define CLK_AUDIO_ADC 3 369#define CLK_AUDIO_APLL_TUNER 4 370#define CLK_AUDIO_APLL2_TUNER 5 371#define CLK_AUDIO_24M 6 372#define CLK_AUDIO_22M 7 373#define CLK_AUDIO_AFE 8 374#define CLK_AUDIO_I2S4 9 375#define CLK_AUDIO_I2S3 10 376#define CLK_AUDIO_I2S2 11 377#define CLK_AUDIO_I2S1 12 378#define CLK_AUDIO_PDN_ADDA6_ADC 13 379#define CLK_AUDIO_TDM 14 380#define CLK_AUDIO_NR_CLK 15 381 382/* IPU_CONN */ 383#define CLK_IPU_CONN_IPU 0 384#define CLK_IPU_CONN_AHB 1 385#define CLK_IPU_CONN_AXI 2 386#define CLK_IPU_CONN_ISP 3 387#define CLK_IPU_CONN_CAM_ADL 4 388#define CLK_IPU_CONN_IMG_ADL 5 389#define CLK_IPU_CONN_DAP_RX 6 390#define CLK_IPU_CONN_APB2AXI 7 391#define CLK_IPU_CONN_APB2AHB 8 392#define CLK_IPU_CONN_IPU_CAB1TO2 9 393#define CLK_IPU_CONN_IPU1_CAB1TO2 10 394#define CLK_IPU_CONN_IPU2_CAB1TO2 11 395#define CLK_IPU_CONN_CAB3TO3 12 396#define CLK_IPU_CONN_CAB2TO1 13 397#define CLK_IPU_CONN_CAB3TO1_SLICE 14 398#define CLK_IPU_CONN_NR_CLK 15 399 400/* IPU_ADL */ 401#define CLK_IPU_ADL_CABGEN 0 402#define CLK_IPU_ADL_NR_CLK 1 403 404/* IPU_CORE0 */ 405#define CLK_IPU_CORE0_JTAG 0 406#define CLK_IPU_CORE0_AXI 1 407#define CLK_IPU_CORE0_IPU 2 408#define CLK_IPU_CORE0_NR_CLK 3 409 410/* IPU_CORE1 */ 411#define CLK_IPU_CORE1_JTAG 0 412#define CLK_IPU_CORE1_AXI 1 413#define CLK_IPU_CORE1_IPU 2 414#define CLK_IPU_CORE1_NR_CLK 3 415 416/* MCUCFG */ 417#define CLK_MCU_MP0_SEL 0 418#define CLK_MCU_MP2_SEL 1 419#define CLK_MCU_BUS_SEL 2 420#define CLK_MCU_NR_CLK 3 421 422#endif /* _DT_BINDINGS_CLK_MT8183_H */ 423