1/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2/* 3 * Copyright (c) 2016 BayLibre, SAS. 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * 6 * Copyright (c) 2017 Amlogic, inc. 7 * Author: Yixun Lan <yixun.lan@amlogic.com> 8 * 9 */ 10 11#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H 12#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H 13 14/* RESET0 */ 15#define RESET_HIU 0 16#define RESET_PCIE_A 1 17#define RESET_PCIE_B 2 18#define RESET_DDR_TOP 3 19/* 4 */ 20#define RESET_VIU 5 21#define RESET_PCIE_PHY 6 22#define RESET_PCIE_APB 7 23/* 8 */ 24/* 9 */ 25#define RESET_VENC 10 26#define RESET_ASSIST 11 27/* 12 */ 28#define RESET_VCBUS 13 29/* 14 */ 30/* 15 */ 31#define RESET_GIC 16 32#define RESET_CAPB3_DECODE 17 33/* 18-21 */ 34#define RESET_SYS_CPU_CAPB3 22 35#define RESET_CBUS_CAPB3 23 36#define RESET_AHB_CNTL 24 37#define RESET_AHB_DATA 25 38#define RESET_VCBUS_CLK81 26 39#define RESET_MMC 27 40/* 28-31 */ 41/* RESET1 */ 42/* 32 */ 43/* 33 */ 44#define RESET_USB_OTG 34 45#define RESET_DDR 35 46#define RESET_AO_RESET 36 47/* 37 */ 48#define RESET_AHB_SRAM 38 49/* 39 */ 50/* 40 */ 51#define RESET_DMA 41 52#define RESET_ISA 42 53#define RESET_ETHERNET 43 54/* 44 */ 55#define RESET_SD_EMMC_B 45 56#define RESET_SD_EMMC_C 46 57#define RESET_ROM_BOOT 47 58#define RESET_SYS_CPU_0 48 59#define RESET_SYS_CPU_1 49 60#define RESET_SYS_CPU_2 50 61#define RESET_SYS_CPU_3 51 62#define RESET_SYS_CPU_CORE_0 52 63#define RESET_SYS_CPU_CORE_1 53 64#define RESET_SYS_CPU_CORE_2 54 65#define RESET_SYS_CPU_CORE_3 55 66#define RESET_SYS_PLL_DIV 56 67#define RESET_SYS_CPU_AXI 57 68#define RESET_SYS_CPU_L2 58 69#define RESET_SYS_CPU_P 59 70#define RESET_SYS_CPU_MBIST 60 71/* 61-63 */ 72/* RESET2 */ 73/* 64 */ 74/* 65 */ 75#define RESET_AUDIO 66 76/* 67 */ 77#define RESET_MIPI_HOST 68 78#define RESET_AUDIO_LOCKER 69 79#define RESET_GE2D 70 80/* 71-76 */ 81#define RESET_AO_CPU_RESET 77 82/* 78-95 */ 83/* RESET3 */ 84#define RESET_RING_OSCILLATOR 96 85/* 97-127 */ 86/* RESET4 */ 87/* 128 */ 88/* 129 */ 89#define RESET_MIPI_PHY 130 90/* 131-140 */ 91#define RESET_VENCL 141 92#define RESET_I2C_MASTER_2 142 93#define RESET_I2C_MASTER_1 143 94/* 144-159 */ 95/* RESET5 */ 96/* 160-191 */ 97/* RESET6 */ 98#define RESET_PERIPHS_GENERAL 192 99#define RESET_PERIPHS_SPICC 193 100/* 194 */ 101/* 195 */ 102#define RESET_PERIPHS_I2C_MASTER_0 196 103/* 197-200 */ 104#define RESET_PERIPHS_UART_0 201 105#define RESET_PERIPHS_UART_1 202 106/* 203-204 */ 107#define RESET_PERIPHS_SPI_0 205 108#define RESET_PERIPHS_I2C_MASTER_3 206 109/* 207-223 */ 110/* RESET7 */ 111#define RESET_USB_DDR_0 224 112#define RESET_USB_DDR_1 225 113#define RESET_USB_DDR_2 226 114#define RESET_USB_DDR_3 227 115/* 228 */ 116#define RESET_DEVICE_MMC_ARB 229 117/* 230 */ 118#define RESET_VID_LOCK 231 119#define RESET_A9_DMC_PIPEL 232 120#define RESET_DMC_VPU_PIPEL 233 121/* 234-255 */ 122 123#endif 124