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6#ifndef __LINUX_CLK_PROVIDER_H
7#define __LINUX_CLK_PROVIDER_H
8
9#include <linux/of.h>
10#include <linux/of_clk.h>
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19#define CLK_SET_RATE_GATE BIT(0)
20#define CLK_SET_PARENT_GATE BIT(1)
21#define CLK_SET_RATE_PARENT BIT(2)
22#define CLK_IGNORE_UNUSED BIT(3)
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24
25#define CLK_GET_RATE_NOCACHE BIT(6)
26#define CLK_SET_RATE_NO_REPARENT BIT(7)
27#define CLK_GET_ACCURACY_NOCACHE BIT(8)
28#define CLK_RECALC_NEW_RATES BIT(9)
29#define CLK_SET_RATE_UNGATE BIT(10)
30#define CLK_IS_CRITICAL BIT(11)
31
32#define CLK_OPS_PARENT_ENABLE BIT(12)
33
34#define CLK_DUTY_CYCLE_PARENT BIT(13)
35
36struct clk;
37struct clk_hw;
38struct clk_core;
39struct dentry;
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55struct clk_rate_request {
56 unsigned long rate;
57 unsigned long min_rate;
58 unsigned long max_rate;
59 unsigned long best_parent_rate;
60 struct clk_hw *best_parent_hw;
61};
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69struct clk_duty {
70 unsigned int num;
71 unsigned int den;
72};
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214struct clk_ops {
215 int (*prepare)(struct clk_hw *hw);
216 void (*unprepare)(struct clk_hw *hw);
217 int (*is_prepared)(struct clk_hw *hw);
218 void (*unprepare_unused)(struct clk_hw *hw);
219 int (*enable)(struct clk_hw *hw);
220 void (*disable)(struct clk_hw *hw);
221 int (*is_enabled)(struct clk_hw *hw);
222 void (*disable_unused)(struct clk_hw *hw);
223 int (*save_context)(struct clk_hw *hw);
224 void (*restore_context)(struct clk_hw *hw);
225 unsigned long (*recalc_rate)(struct clk_hw *hw,
226 unsigned long parent_rate);
227 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
228 unsigned long *parent_rate);
229 int (*determine_rate)(struct clk_hw *hw,
230 struct clk_rate_request *req);
231 int (*set_parent)(struct clk_hw *hw, u8 index);
232 u8 (*get_parent)(struct clk_hw *hw);
233 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
234 unsigned long parent_rate);
235 int (*set_rate_and_parent)(struct clk_hw *hw,
236 unsigned long rate,
237 unsigned long parent_rate, u8 index);
238 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
239 unsigned long parent_accuracy);
240 int (*get_phase)(struct clk_hw *hw);
241 int (*set_phase)(struct clk_hw *hw, int degrees);
242 int (*get_duty_cycle)(struct clk_hw *hw,
243 struct clk_duty *duty);
244 int (*set_duty_cycle)(struct clk_hw *hw,
245 struct clk_duty *duty);
246 void (*init)(struct clk_hw *hw);
247 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
248};
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257struct clk_parent_data {
258 const struct clk_hw *hw;
259 const char *fw_name;
260 const char *name;
261 int index;
262};
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278struct clk_init_data {
279 const char *name;
280 const struct clk_ops *ops;
281
282 const char * const *parent_names;
283 const struct clk_parent_data *parent_data;
284 const struct clk_hw **parent_hws;
285 u8 num_parents;
286 unsigned long flags;
287};
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304struct clk_hw {
305 struct clk_core *core;
306 struct clk *clk;
307 const struct clk_init_data *init;
308};
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324struct clk_fixed_rate {
325 struct clk_hw hw;
326 unsigned long fixed_rate;
327 unsigned long fixed_accuracy;
328};
329
330#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
331
332extern const struct clk_ops clk_fixed_rate_ops;
333struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
334 const char *parent_name, unsigned long flags,
335 unsigned long fixed_rate);
336struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
337 const char *parent_name, unsigned long flags,
338 unsigned long fixed_rate);
339struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
340 const char *name, const char *parent_name, unsigned long flags,
341 unsigned long fixed_rate, unsigned long fixed_accuracy);
342void clk_unregister_fixed_rate(struct clk *clk);
343struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
344 const char *name, const char *parent_name, unsigned long flags,
345 unsigned long fixed_rate, unsigned long fixed_accuracy);
346void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
347
348void of_fixed_clk_setup(struct device_node *np);
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373struct clk_gate {
374 struct clk_hw hw;
375 void __iomem *reg;
376 u8 bit_idx;
377 u8 flags;
378 spinlock_t *lock;
379};
380
381#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
382
383#define CLK_GATE_SET_TO_DISABLE BIT(0)
384#define CLK_GATE_HIWORD_MASK BIT(1)
385#define CLK_GATE_BIG_ENDIAN BIT(2)
386
387extern const struct clk_ops clk_gate_ops;
388struct clk *clk_register_gate(struct device *dev, const char *name,
389 const char *parent_name, unsigned long flags,
390 void __iomem *reg, u8 bit_idx,
391 u8 clk_gate_flags, spinlock_t *lock);
392struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
393 const char *parent_name, unsigned long flags,
394 void __iomem *reg, u8 bit_idx,
395 u8 clk_gate_flags, spinlock_t *lock);
396void clk_unregister_gate(struct clk *clk);
397void clk_hw_unregister_gate(struct clk_hw *hw);
398int clk_gate_is_enabled(struct clk_hw *hw);
399
400struct clk_div_table {
401 unsigned int val;
402 unsigned int div;
403};
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445struct clk_divider {
446 struct clk_hw hw;
447 void __iomem *reg;
448 u8 shift;
449 u8 width;
450 u8 flags;
451 const struct clk_div_table *table;
452 spinlock_t *lock;
453};
454
455#define clk_div_mask(width) ((1 << (width)) - 1)
456#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
457
458#define CLK_DIVIDER_ONE_BASED BIT(0)
459#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
460#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
461#define CLK_DIVIDER_HIWORD_MASK BIT(3)
462#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
463#define CLK_DIVIDER_READ_ONLY BIT(5)
464#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
465#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
466
467extern const struct clk_ops clk_divider_ops;
468extern const struct clk_ops clk_divider_ro_ops;
469
470unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
471 unsigned int val, const struct clk_div_table *table,
472 unsigned long flags, unsigned long width);
473long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
474 unsigned long rate, unsigned long *prate,
475 const struct clk_div_table *table,
476 u8 width, unsigned long flags);
477long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
478 unsigned long rate, unsigned long *prate,
479 const struct clk_div_table *table, u8 width,
480 unsigned long flags, unsigned int val);
481int divider_get_val(unsigned long rate, unsigned long parent_rate,
482 const struct clk_div_table *table, u8 width,
483 unsigned long flags);
484
485struct clk *clk_register_divider(struct device *dev, const char *name,
486 const char *parent_name, unsigned long flags,
487 void __iomem *reg, u8 shift, u8 width,
488 u8 clk_divider_flags, spinlock_t *lock);
489struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
490 const char *parent_name, unsigned long flags,
491 void __iomem *reg, u8 shift, u8 width,
492 u8 clk_divider_flags, spinlock_t *lock);
493struct clk *clk_register_divider_table(struct device *dev, const char *name,
494 const char *parent_name, unsigned long flags,
495 void __iomem *reg, u8 shift, u8 width,
496 u8 clk_divider_flags, const struct clk_div_table *table,
497 spinlock_t *lock);
498struct clk_hw *clk_hw_register_divider_table(struct device *dev,
499 const char *name, const char *parent_name, unsigned long flags,
500 void __iomem *reg, u8 shift, u8 width,
501 u8 clk_divider_flags, const struct clk_div_table *table,
502 spinlock_t *lock);
503void clk_unregister_divider(struct clk *clk);
504void clk_hw_unregister_divider(struct clk_hw *hw);
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535struct clk_mux {
536 struct clk_hw hw;
537 void __iomem *reg;
538 u32 *table;
539 u32 mask;
540 u8 shift;
541 u8 flags;
542 spinlock_t *lock;
543};
544
545#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
546
547#define CLK_MUX_INDEX_ONE BIT(0)
548#define CLK_MUX_INDEX_BIT BIT(1)
549#define CLK_MUX_HIWORD_MASK BIT(2)
550#define CLK_MUX_READ_ONLY BIT(3)
551#define CLK_MUX_ROUND_CLOSEST BIT(4)
552#define CLK_MUX_BIG_ENDIAN BIT(5)
553
554extern const struct clk_ops clk_mux_ops;
555extern const struct clk_ops clk_mux_ro_ops;
556
557struct clk *clk_register_mux(struct device *dev, const char *name,
558 const char * const *parent_names, u8 num_parents,
559 unsigned long flags,
560 void __iomem *reg, u8 shift, u8 width,
561 u8 clk_mux_flags, spinlock_t *lock);
562struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
563 const char * const *parent_names, u8 num_parents,
564 unsigned long flags,
565 void __iomem *reg, u8 shift, u8 width,
566 u8 clk_mux_flags, spinlock_t *lock);
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568struct clk *clk_register_mux_table(struct device *dev, const char *name,
569 const char * const *parent_names, u8 num_parents,
570 unsigned long flags,
571 void __iomem *reg, u8 shift, u32 mask,
572 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
573struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
574 const char * const *parent_names, u8 num_parents,
575 unsigned long flags,
576 void __iomem *reg, u8 shift, u32 mask,
577 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
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579int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
580 unsigned int val);
581unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
582
583void clk_unregister_mux(struct clk *clk);
584void clk_hw_unregister_mux(struct clk_hw *hw);
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586void of_fixed_factor_clk_setup(struct device_node *node);
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600struct clk_fixed_factor {
601 struct clk_hw hw;
602 unsigned int mult;
603 unsigned int div;
604};
605
606#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
607
608extern const struct clk_ops clk_fixed_factor_ops;
609struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
610 const char *parent_name, unsigned long flags,
611 unsigned int mult, unsigned int div);
612void clk_unregister_fixed_factor(struct clk *clk);
613struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
614 const char *name, const char *parent_name, unsigned long flags,
615 unsigned int mult, unsigned int div);
616void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
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640struct clk_fractional_divider {
641 struct clk_hw hw;
642 void __iomem *reg;
643 u8 mshift;
644 u8 mwidth;
645 u32 mmask;
646 u8 nshift;
647 u8 nwidth;
648 u32 nmask;
649 u8 flags;
650 void (*approximation)(struct clk_hw *hw,
651 unsigned long rate, unsigned long *parent_rate,
652 unsigned long *m, unsigned long *n);
653 spinlock_t *lock;
654};
655
656#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
657
658#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
659#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
660
661extern const struct clk_ops clk_fractional_divider_ops;
662struct clk *clk_register_fractional_divider(struct device *dev,
663 const char *name, const char *parent_name, unsigned long flags,
664 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
665 u8 clk_divider_flags, spinlock_t *lock);
666struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
667 const char *name, const char *parent_name, unsigned long flags,
668 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
669 u8 clk_divider_flags, spinlock_t *lock);
670void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
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696struct clk_multiplier {
697 struct clk_hw hw;
698 void __iomem *reg;
699 u8 shift;
700 u8 width;
701 u8 flags;
702 spinlock_t *lock;
703};
704
705#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
706
707#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
708#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
709#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
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711extern const struct clk_ops clk_multiplier_ops;
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724struct clk_composite {
725 struct clk_hw hw;
726 struct clk_ops ops;
727
728 struct clk_hw *mux_hw;
729 struct clk_hw *rate_hw;
730 struct clk_hw *gate_hw;
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732 const struct clk_ops *mux_ops;
733 const struct clk_ops *rate_ops;
734 const struct clk_ops *gate_ops;
735};
736
737#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
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739struct clk *clk_register_composite(struct device *dev, const char *name,
740 const char * const *parent_names, int num_parents,
741 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
742 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
743 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
744 unsigned long flags);
745void clk_unregister_composite(struct clk *clk);
746struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
747 const char * const *parent_names, int num_parents,
748 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
749 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
750 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
751 unsigned long flags);
752void clk_hw_unregister_composite(struct clk_hw *hw);
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767struct clk_gpio {
768 struct clk_hw hw;
769 struct gpio_desc *gpiod;
770};
771
772#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
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774extern const struct clk_ops clk_gpio_gate_ops;
775struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
776 const char *parent_name, struct gpio_desc *gpiod,
777 unsigned long flags);
778struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
779 const char *parent_name, struct gpio_desc *gpiod,
780 unsigned long flags);
781void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
782
783extern const struct clk_ops clk_gpio_mux_ops;
784struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
785 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
786 unsigned long flags);
787struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
788 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
789 unsigned long flags);
790void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
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792struct clk *clk_register(struct device *dev, struct clk_hw *hw);
793struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
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795int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
796int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
797int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
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799void clk_unregister(struct clk *clk);
800void devm_clk_unregister(struct device *dev, struct clk *clk);
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802void clk_hw_unregister(struct clk_hw *hw);
803void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
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806const char *__clk_get_name(const struct clk *clk);
807const char *clk_hw_get_name(const struct clk_hw *hw);
808#ifdef CONFIG_COMMON_CLK
809struct clk_hw *__clk_get_hw(struct clk *clk);
810#else
811static inline struct clk_hw *__clk_get_hw(struct clk *clk)
812{
813 return (struct clk_hw *)clk;
814}
815#endif
816unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
817struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
818struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
819 unsigned int index);
820unsigned int __clk_get_enable_count(struct clk *clk);
821unsigned long clk_hw_get_rate(const struct clk_hw *hw);
822unsigned long __clk_get_flags(struct clk *clk);
823unsigned long clk_hw_get_flags(const struct clk_hw *hw);
824#define clk_hw_can_set_rate_parent(hw) \
825 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
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827bool clk_hw_is_prepared(const struct clk_hw *hw);
828bool clk_hw_rate_is_protected(const struct clk_hw *hw);
829bool clk_hw_is_enabled(const struct clk_hw *hw);
830bool __clk_is_enabled(struct clk *clk);
831struct clk *__clk_lookup(const char *name);
832int __clk_mux_determine_rate(struct clk_hw *hw,
833 struct clk_rate_request *req);
834int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
835int __clk_mux_determine_rate_closest(struct clk_hw *hw,
836 struct clk_rate_request *req);
837int clk_mux_determine_rate_flags(struct clk_hw *hw,
838 struct clk_rate_request *req,
839 unsigned long flags);
840void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
841void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
842 unsigned long max_rate);
843
844static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
845{
846 dst->clk = src->clk;
847 dst->core = src->core;
848}
849
850static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
851 unsigned long *prate,
852 const struct clk_div_table *table,
853 u8 width, unsigned long flags)
854{
855 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
856 rate, prate, table, width, flags);
857}
858
859static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
860 unsigned long *prate,
861 const struct clk_div_table *table,
862 u8 width, unsigned long flags,
863 unsigned int val)
864{
865 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
866 rate, prate, table, width, flags,
867 val);
868}
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873unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
874
875struct clk_onecell_data {
876 struct clk **clks;
877 unsigned int clk_num;
878};
879
880struct clk_hw_onecell_data {
881 unsigned int num;
882 struct clk_hw *hws[];
883};
884
885#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
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891#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
892 static void __init name##_of_clk_init_driver(struct device_node *np) \
893 { \
894 of_node_clear_flag(np, OF_POPULATED); \
895 fn(np); \
896 } \
897 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
898
899#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
900 (&(struct clk_init_data) { \
901 .flags = _flags, \
902 .name = _name, \
903 .parent_names = (const char *[]) { _parent }, \
904 .num_parents = 1, \
905 .ops = _ops, \
906 })
907
908#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
909 (&(struct clk_init_data) { \
910 .flags = _flags, \
911 .name = _name, \
912 .parent_hws = (const struct clk_hw*[]) { _parent }, \
913 .num_parents = 1, \
914 .ops = _ops, \
915 })
916
917
918
919
920
921
922#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
923 (&(struct clk_init_data) { \
924 .flags = _flags, \
925 .name = _name, \
926 .parent_hws = _parent, \
927 .num_parents = 1, \
928 .ops = _ops, \
929 })
930
931#define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
932 (&(struct clk_init_data) { \
933 .flags = _flags, \
934 .name = _name, \
935 .parent_data = (const struct clk_parent_data[]) { \
936 { .fw_name = _parent }, \
937 }, \
938 .num_parents = 1, \
939 .ops = _ops, \
940 })
941
942#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
943 (&(struct clk_init_data) { \
944 .flags = _flags, \
945 .name = _name, \
946 .parent_names = _parents, \
947 .num_parents = ARRAY_SIZE(_parents), \
948 .ops = _ops, \
949 })
950
951#define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
952 (&(struct clk_init_data) { \
953 .flags = _flags, \
954 .name = _name, \
955 .parent_hws = _parents, \
956 .num_parents = ARRAY_SIZE(_parents), \
957 .ops = _ops, \
958 })
959
960#define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
961 (&(struct clk_init_data) { \
962 .flags = _flags, \
963 .name = _name, \
964 .parent_data = _parents, \
965 .num_parents = ARRAY_SIZE(_parents), \
966 .ops = _ops, \
967 })
968
969#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
970 (&(struct clk_init_data) { \
971 .flags = _flags, \
972 .name = _name, \
973 .parent_names = NULL, \
974 .num_parents = 0, \
975 .ops = _ops, \
976 })
977
978#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
979 _div, _mult, _flags) \
980 struct clk_fixed_factor _struct = { \
981 .div = _div, \
982 .mult = _mult, \
983 .hw.init = CLK_HW_INIT(_name, \
984 _parent, \
985 &clk_fixed_factor_ops, \
986 _flags), \
987 }
988
989#define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
990 _div, _mult, _flags) \
991 struct clk_fixed_factor _struct = { \
992 .div = _div, \
993 .mult = _mult, \
994 .hw.init = CLK_HW_INIT_HW(_name, \
995 _parent, \
996 &clk_fixed_factor_ops, \
997 _flags), \
998 }
999
1000
1001
1002
1003
1004#define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1005 _div, _mult, _flags) \
1006 struct clk_fixed_factor _struct = { \
1007 .div = _div, \
1008 .mult = _mult, \
1009 .hw.init = CLK_HW_INIT_HWS(_name, \
1010 _parent, \
1011 &clk_fixed_factor_ops, \
1012 _flags), \
1013 }
1014
1015#define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1016 _div, _mult, _flags) \
1017 struct clk_fixed_factor _struct = { \
1018 .div = _div, \
1019 .mult = _mult, \
1020 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1021 _parent, \
1022 &clk_fixed_factor_ops, \
1023 _flags), \
1024 }
1025
1026#ifdef CONFIG_OF
1027int of_clk_add_provider(struct device_node *np,
1028 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1029 void *data),
1030 void *data);
1031int of_clk_add_hw_provider(struct device_node *np,
1032 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1033 void *data),
1034 void *data);
1035int devm_of_clk_add_hw_provider(struct device *dev,
1036 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1037 void *data),
1038 void *data);
1039void of_clk_del_provider(struct device_node *np);
1040void devm_of_clk_del_provider(struct device *dev);
1041struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1042 void *data);
1043struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1044 void *data);
1045struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1046struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1047 void *data);
1048int of_clk_parent_fill(struct device_node *np, const char **parents,
1049 unsigned int size);
1050int of_clk_detect_critical(struct device_node *np, int index,
1051 unsigned long *flags);
1052
1053#else
1054
1055static inline int of_clk_add_provider(struct device_node *np,
1056 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1057 void *data),
1058 void *data)
1059{
1060 return 0;
1061}
1062static inline int of_clk_add_hw_provider(struct device_node *np,
1063 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1064 void *data),
1065 void *data)
1066{
1067 return 0;
1068}
1069static inline int devm_of_clk_add_hw_provider(struct device *dev,
1070 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1071 void *data),
1072 void *data)
1073{
1074 return 0;
1075}
1076static inline void of_clk_del_provider(struct device_node *np) {}
1077static inline void devm_of_clk_del_provider(struct device *dev) {}
1078static inline struct clk *of_clk_src_simple_get(
1079 struct of_phandle_args *clkspec, void *data)
1080{
1081 return ERR_PTR(-ENOENT);
1082}
1083static inline struct clk_hw *
1084of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1085{
1086 return ERR_PTR(-ENOENT);
1087}
1088static inline struct clk *of_clk_src_onecell_get(
1089 struct of_phandle_args *clkspec, void *data)
1090{
1091 return ERR_PTR(-ENOENT);
1092}
1093static inline struct clk_hw *
1094of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1095{
1096 return ERR_PTR(-ENOENT);
1097}
1098static inline int of_clk_parent_fill(struct device_node *np,
1099 const char **parents, unsigned int size)
1100{
1101 return 0;
1102}
1103static inline int of_clk_detect_critical(struct device_node *np, int index,
1104 unsigned long *flags)
1105{
1106 return 0;
1107}
1108#endif
1109
1110void clk_gate_restore_context(struct clk_hw *hw);
1111
1112#endif
1113