linux/include/linux/dmar.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2006, Intel Corporation.
   4 *
   5 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
   6 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
   7 */
   8
   9#ifndef __DMAR_H__
  10#define __DMAR_H__
  11
  12#include <linux/acpi.h>
  13#include <linux/types.h>
  14#include <linux/msi.h>
  15#include <linux/irqreturn.h>
  16#include <linux/rwsem.h>
  17#include <linux/rculist.h>
  18
  19struct acpi_dmar_header;
  20
  21#ifdef  CONFIG_X86
  22# define        DMAR_UNITS_SUPPORTED    MAX_IO_APICS
  23#else
  24# define        DMAR_UNITS_SUPPORTED    64
  25#endif
  26
  27/* DMAR Flags */
  28#define DMAR_INTR_REMAP         0x1
  29#define DMAR_X2APIC_OPT_OUT     0x2
  30#define DMAR_PLATFORM_OPT_IN    0x4
  31
  32struct intel_iommu;
  33
  34struct dmar_dev_scope {
  35        struct device __rcu *dev;
  36        u8 bus;
  37        u8 devfn;
  38};
  39
  40#ifdef CONFIG_DMAR_TABLE
  41extern struct acpi_table_header *dmar_tbl;
  42struct dmar_drhd_unit {
  43        struct list_head list;          /* list of drhd units   */
  44        struct  acpi_dmar_header *hdr;  /* ACPI header          */
  45        u64     reg_base_addr;          /* register base address*/
  46        struct  dmar_dev_scope *devices;/* target device array  */
  47        int     devices_cnt;            /* target device count  */
  48        u16     segment;                /* PCI domain           */
  49        u8      ignored:1;              /* ignore drhd          */
  50        u8      include_all:1;
  51        struct intel_iommu *iommu;
  52};
  53
  54struct dmar_pci_path {
  55        u8 bus;
  56        u8 device;
  57        u8 function;
  58};
  59
  60struct dmar_pci_notify_info {
  61        struct pci_dev                  *dev;
  62        unsigned long                   event;
  63        int                             bus;
  64        u16                             seg;
  65        u16                             level;
  66        struct dmar_pci_path            path[];
  67}  __attribute__((packed));
  68
  69extern struct rw_semaphore dmar_global_lock;
  70extern struct list_head dmar_drhd_units;
  71
  72#define for_each_drhd_unit(drhd) \
  73        list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)
  74
  75#define for_each_active_drhd_unit(drhd)                                 \
  76        list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)           \
  77                if (drhd->ignored) {} else
  78
  79#define for_each_active_iommu(i, drhd)                                  \
  80        list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)           \
  81                if (i=drhd->iommu, drhd->ignored) {} else
  82
  83#define for_each_iommu(i, drhd)                                         \
  84        list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)           \
  85                if (i=drhd->iommu, 0) {} else 
  86
  87static inline bool dmar_rcu_check(void)
  88{
  89        return rwsem_is_locked(&dmar_global_lock) ||
  90               system_state == SYSTEM_BOOTING;
  91}
  92
  93#define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check())
  94
  95#define for_each_dev_scope(devs, cnt, i, tmp)                           \
  96        for ((i) = 0; ((tmp) = (i) < (cnt) ?                            \
  97            dmar_rcu_dereference((devs)[(i)].dev) : NULL, (i) < (cnt)); \
  98            (i)++)
  99
 100#define for_each_active_dev_scope(devs, cnt, i, tmp)                    \
 101        for_each_dev_scope((devs), (cnt), (i), (tmp))                   \
 102                if (!(tmp)) { continue; } else
 103
 104extern int dmar_table_init(void);
 105extern int dmar_dev_scope_init(void);
 106extern void dmar_register_bus_notifier(void);
 107extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
 108                                struct dmar_dev_scope **devices, u16 segment);
 109extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt);
 110extern void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt);
 111extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
 112                                 void *start, void*end, u16 segment,
 113                                 struct dmar_dev_scope *devices,
 114                                 int devices_cnt);
 115extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info,
 116                                 u16 segment, struct dmar_dev_scope *devices,
 117                                 int count);
 118/* Intel IOMMU detection */
 119extern int detect_intel_iommu(void);
 120extern int enable_drhd_fault_handling(void);
 121extern int dmar_device_add(acpi_handle handle);
 122extern int dmar_device_remove(acpi_handle handle);
 123
 124static inline int dmar_res_noop(struct acpi_dmar_header *hdr, void *arg)
 125{
 126        return 0;
 127}
 128
 129#ifdef CONFIG_INTEL_IOMMU
 130extern int iommu_detected, no_iommu;
 131extern int intel_iommu_init(void);
 132extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg);
 133extern int dmar_parse_one_atsr(struct acpi_dmar_header *header, void *arg);
 134extern int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg);
 135extern int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg);
 136extern int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
 137extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info);
 138#else /* !CONFIG_INTEL_IOMMU: */
 139static inline int intel_iommu_init(void) { return -ENODEV; }
 140
 141#define dmar_parse_one_rmrr             dmar_res_noop
 142#define dmar_parse_one_atsr             dmar_res_noop
 143#define dmar_check_one_atsr             dmar_res_noop
 144#define dmar_release_one_atsr           dmar_res_noop
 145
 146static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
 147{
 148        return 0;
 149}
 150
 151static inline int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
 152{
 153        return 0;
 154}
 155#endif /* CONFIG_INTEL_IOMMU */
 156
 157#ifdef CONFIG_IRQ_REMAP
 158extern int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
 159#else  /* CONFIG_IRQ_REMAP */
 160static inline int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
 161{ return 0; }
 162#endif /* CONFIG_IRQ_REMAP */
 163
 164extern bool dmar_platform_optin(void);
 165
 166#else /* CONFIG_DMAR_TABLE */
 167
 168static inline int dmar_device_add(void *handle)
 169{
 170        return 0;
 171}
 172
 173static inline int dmar_device_remove(void *handle)
 174{
 175        return 0;
 176}
 177
 178static inline bool dmar_platform_optin(void)
 179{
 180        return false;
 181}
 182
 183#endif /* CONFIG_DMAR_TABLE */
 184
 185struct irte {
 186        union {
 187                /* Shared between remapped and posted mode*/
 188                struct {
 189                        __u64   present         : 1,  /*  0      */
 190                                fpd             : 1,  /*  1      */
 191                                __res0          : 6,  /*  2 -  6 */
 192                                avail           : 4,  /*  8 - 11 */
 193                                __res1          : 3,  /* 12 - 14 */
 194                                pst             : 1,  /* 15      */
 195                                vector          : 8,  /* 16 - 23 */
 196                                __res2          : 40; /* 24 - 63 */
 197                };
 198
 199                /* Remapped mode */
 200                struct {
 201                        __u64   r_present       : 1,  /*  0      */
 202                                r_fpd           : 1,  /*  1      */
 203                                dst_mode        : 1,  /*  2      */
 204                                redir_hint      : 1,  /*  3      */
 205                                trigger_mode    : 1,  /*  4      */
 206                                dlvry_mode      : 3,  /*  5 -  7 */
 207                                r_avail         : 4,  /*  8 - 11 */
 208                                r_res0          : 4,  /* 12 - 15 */
 209                                r_vector        : 8,  /* 16 - 23 */
 210                                r_res1          : 8,  /* 24 - 31 */
 211                                dest_id         : 32; /* 32 - 63 */
 212                };
 213
 214                /* Posted mode */
 215                struct {
 216                        __u64   p_present       : 1,  /*  0      */
 217                                p_fpd           : 1,  /*  1      */
 218                                p_res0          : 6,  /*  2 -  7 */
 219                                p_avail         : 4,  /*  8 - 11 */
 220                                p_res1          : 2,  /* 12 - 13 */
 221                                p_urgent        : 1,  /* 14      */
 222                                p_pst           : 1,  /* 15      */
 223                                p_vector        : 8,  /* 16 - 23 */
 224                                p_res2          : 14, /* 24 - 37 */
 225                                pda_l           : 26; /* 38 - 63 */
 226                };
 227                __u64 low;
 228        };
 229
 230        union {
 231                /* Shared between remapped and posted mode*/
 232                struct {
 233                        __u64   sid             : 16,  /* 64 - 79  */
 234                                sq              : 2,   /* 80 - 81  */
 235                                svt             : 2,   /* 82 - 83  */
 236                                __res3          : 44;  /* 84 - 127 */
 237                };
 238
 239                /* Posted mode*/
 240                struct {
 241                        __u64   p_sid           : 16,  /* 64 - 79  */
 242                                p_sq            : 2,   /* 80 - 81  */
 243                                p_svt           : 2,   /* 82 - 83  */
 244                                p_res3          : 12,  /* 84 - 95  */
 245                                pda_h           : 32;  /* 96 - 127 */
 246                };
 247                __u64 high;
 248        };
 249};
 250
 251static inline void dmar_copy_shared_irte(struct irte *dst, struct irte *src)
 252{
 253        dst->present    = src->present;
 254        dst->fpd        = src->fpd;
 255        dst->avail      = src->avail;
 256        dst->pst        = src->pst;
 257        dst->vector     = src->vector;
 258        dst->sid        = src->sid;
 259        dst->sq         = src->sq;
 260        dst->svt        = src->svt;
 261}
 262
 263#define PDA_LOW_BIT    26
 264#define PDA_HIGH_BIT   32
 265
 266/* Can't use the common MSI interrupt functions
 267 * since DMAR is not a pci device
 268 */
 269struct irq_data;
 270extern void dmar_msi_unmask(struct irq_data *data);
 271extern void dmar_msi_mask(struct irq_data *data);
 272extern void dmar_msi_read(int irq, struct msi_msg *msg);
 273extern void dmar_msi_write(int irq, struct msi_msg *msg);
 274extern int dmar_set_interrupt(struct intel_iommu *iommu);
 275extern irqreturn_t dmar_fault(int irq, void *dev_id);
 276extern int dmar_alloc_hwirq(int id, int node, void *arg);
 277extern void dmar_free_hwirq(int irq);
 278
 279#endif /* __DMAR_H__ */
 280