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10#ifndef _INTEL_IOMMU_H_
11#define _INTEL_IOMMU_H_
12
13#include <linux/types.h>
14#include <linux/iova.h>
15#include <linux/io.h>
16#include <linux/idr.h>
17#include <linux/mmu_notifier.h>
18#include <linux/list.h>
19#include <linux/iommu.h>
20#include <linux/io-64-nonatomic-lo-hi.h>
21#include <linux/dmar.h>
22
23#include <asm/cacheflush.h>
24#include <asm/iommu.h>
25
26
27
28
29#define VTD_PAGE_SHIFT (12)
30#define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
31#define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
32#define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
33
34#define VTD_STRIDE_SHIFT (9)
35#define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
36
37#define DMA_PTE_READ (1)
38#define DMA_PTE_WRITE (2)
39#define DMA_PTE_LARGE_PAGE (1 << 7)
40#define DMA_PTE_SNP (1 << 11)
41
42#define CONTEXT_TT_MULTI_LEVEL 0
43#define CONTEXT_TT_DEV_IOTLB 1
44#define CONTEXT_TT_PASS_THROUGH 2
45#define CONTEXT_PASIDE BIT_ULL(3)
46
47
48
49
50#define DMAR_VER_REG 0x0
51#define DMAR_CAP_REG 0x8
52#define DMAR_ECAP_REG 0x10
53#define DMAR_GCMD_REG 0x18
54#define DMAR_GSTS_REG 0x1c
55#define DMAR_RTADDR_REG 0x20
56#define DMAR_CCMD_REG 0x28
57#define DMAR_FSTS_REG 0x34
58#define DMAR_FECTL_REG 0x38
59#define DMAR_FEDATA_REG 0x3c
60#define DMAR_FEADDR_REG 0x40
61#define DMAR_FEUADDR_REG 0x44
62#define DMAR_AFLOG_REG 0x58
63#define DMAR_PMEN_REG 0x64
64#define DMAR_PLMBASE_REG 0x68
65#define DMAR_PLMLIMIT_REG 0x6c
66#define DMAR_PHMBASE_REG 0x70
67#define DMAR_PHMLIMIT_REG 0x78
68#define DMAR_IQH_REG 0x80
69#define DMAR_IQT_REG 0x88
70#define DMAR_IQ_SHIFT 4
71#define DMAR_IQA_REG 0x90
72#define DMAR_ICS_REG 0x9c
73#define DMAR_IRTA_REG 0xb8
74#define DMAR_PQH_REG 0xc0
75#define DMAR_PQT_REG 0xc8
76#define DMAR_PQA_REG 0xd0
77#define DMAR_PRS_REG 0xdc
78#define DMAR_PECTL_REG 0xe0
79#define DMAR_PEDATA_REG 0xe4
80#define DMAR_PEADDR_REG 0xe8
81#define DMAR_PEUADDR_REG 0xec
82#define DMAR_MTRRCAP_REG 0x100
83#define DMAR_MTRRDEF_REG 0x108
84#define DMAR_MTRR_FIX64K_00000_REG 0x120
85#define DMAR_MTRR_FIX16K_80000_REG 0x128
86#define DMAR_MTRR_FIX16K_A0000_REG 0x130
87#define DMAR_MTRR_FIX4K_C0000_REG 0x138
88#define DMAR_MTRR_FIX4K_C8000_REG 0x140
89#define DMAR_MTRR_FIX4K_D0000_REG 0x148
90#define DMAR_MTRR_FIX4K_D8000_REG 0x150
91#define DMAR_MTRR_FIX4K_E0000_REG 0x158
92#define DMAR_MTRR_FIX4K_E8000_REG 0x160
93#define DMAR_MTRR_FIX4K_F0000_REG 0x168
94#define DMAR_MTRR_FIX4K_F8000_REG 0x170
95#define DMAR_MTRR_PHYSBASE0_REG 0x180
96#define DMAR_MTRR_PHYSMASK0_REG 0x188
97#define DMAR_MTRR_PHYSBASE1_REG 0x190
98#define DMAR_MTRR_PHYSMASK1_REG 0x198
99#define DMAR_MTRR_PHYSBASE2_REG 0x1a0
100#define DMAR_MTRR_PHYSMASK2_REG 0x1a8
101#define DMAR_MTRR_PHYSBASE3_REG 0x1b0
102#define DMAR_MTRR_PHYSMASK3_REG 0x1b8
103#define DMAR_MTRR_PHYSBASE4_REG 0x1c0
104#define DMAR_MTRR_PHYSMASK4_REG 0x1c8
105#define DMAR_MTRR_PHYSBASE5_REG 0x1d0
106#define DMAR_MTRR_PHYSMASK5_REG 0x1d8
107#define DMAR_MTRR_PHYSBASE6_REG 0x1e0
108#define DMAR_MTRR_PHYSMASK6_REG 0x1e8
109#define DMAR_MTRR_PHYSBASE7_REG 0x1f0
110#define DMAR_MTRR_PHYSMASK7_REG 0x1f8
111#define DMAR_MTRR_PHYSBASE8_REG 0x200
112#define DMAR_MTRR_PHYSMASK8_REG 0x208
113#define DMAR_MTRR_PHYSBASE9_REG 0x210
114#define DMAR_MTRR_PHYSMASK9_REG 0x218
115#define DMAR_VCCAP_REG 0xe00
116#define DMAR_VCMD_REG 0xe10
117#define DMAR_VCRSP_REG 0xe20
118
119#define OFFSET_STRIDE (9)
120
121#define dmar_readq(a) readq(a)
122#define dmar_writeq(a,v) writeq(v,a)
123
124#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
125#define DMAR_VER_MINOR(v) ((v) & 0x0f)
126
127
128
129
130#define cap_5lp_support(c) (((c) >> 60) & 1)
131#define cap_pi_support(c) (((c) >> 59) & 1)
132#define cap_fl1gp_support(c) (((c) >> 56) & 1)
133#define cap_read_drain(c) (((c) >> 55) & 1)
134#define cap_write_drain(c) (((c) >> 54) & 1)
135#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
136#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
137#define cap_pgsel_inv(c) (((c) >> 39) & 1)
138
139#define cap_super_page_val(c) (((c) >> 34) & 0xf)
140#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
141 * OFFSET_STRIDE) + 21)
142
143#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
144#define cap_max_fault_reg_offset(c) \
145 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
146
147#define cap_zlr(c) (((c) >> 22) & 1)
148#define cap_isoch(c) (((c) >> 23) & 1)
149#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
150#define cap_sagaw(c) (((c) >> 8) & 0x1f)
151#define cap_caching_mode(c) (((c) >> 7) & 1)
152#define cap_phmr(c) (((c) >> 6) & 1)
153#define cap_plmr(c) (((c) >> 5) & 1)
154#define cap_rwbf(c) (((c) >> 4) & 1)
155#define cap_afl(c) (((c) >> 3) & 1)
156#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
157
158
159
160
161#define ecap_smpwc(e) (((e) >> 48) & 0x1)
162#define ecap_flts(e) (((e) >> 47) & 0x1)
163#define ecap_slts(e) (((e) >> 46) & 0x1)
164#define ecap_smts(e) (((e) >> 43) & 0x1)
165#define ecap_dit(e) ((e >> 41) & 0x1)
166#define ecap_pasid(e) ((e >> 40) & 0x1)
167#define ecap_pss(e) ((e >> 35) & 0x1f)
168#define ecap_eafs(e) ((e >> 34) & 0x1)
169#define ecap_nwfs(e) ((e >> 33) & 0x1)
170#define ecap_srs(e) ((e >> 31) & 0x1)
171#define ecap_ers(e) ((e >> 30) & 0x1)
172#define ecap_prs(e) ((e >> 29) & 0x1)
173#define ecap_broken_pasid(e) ((e >> 28) & 0x1)
174#define ecap_dis(e) ((e >> 27) & 0x1)
175#define ecap_nest(e) ((e >> 26) & 0x1)
176#define ecap_mts(e) ((e >> 25) & 0x1)
177#define ecap_ecs(e) ((e >> 24) & 0x1)
178#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
179#define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
180#define ecap_coherent(e) ((e) & 0x1)
181#define ecap_qis(e) ((e) & 0x2)
182#define ecap_pass_through(e) ((e >> 6) & 0x1)
183#define ecap_eim_support(e) ((e >> 4) & 0x1)
184#define ecap_ir_support(e) ((e >> 3) & 0x1)
185#define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
186#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
187#define ecap_sc_support(e) ((e >> 7) & 0x1)
188
189
190#define DMA_TLB_FLUSH_GRANU_OFFSET 60
191#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
192#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
193#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
194#define DMA_TLB_IIRG(type) ((type >> 60) & 3)
195#define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
196#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
197#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
198#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
199#define DMA_TLB_IVT (((u64)1) << 63)
200#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
201#define DMA_TLB_MAX_SIZE (0x3f)
202
203
204#define DMA_CCMD_INVL_GRANU_OFFSET 61
205#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
206#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
207#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
208#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
209#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
210#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
211#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
212#define DMA_ID_TLB_ADDR(addr) (addr)
213#define DMA_ID_TLB_ADDR_MASK(mask) (mask)
214
215
216#define DMA_PMEN_EPM (((u32)1)<<31)
217#define DMA_PMEN_PRS (((u32)1)<<0)
218
219
220#define DMA_GCMD_TE (((u32)1) << 31)
221#define DMA_GCMD_SRTP (((u32)1) << 30)
222#define DMA_GCMD_SFL (((u32)1) << 29)
223#define DMA_GCMD_EAFL (((u32)1) << 28)
224#define DMA_GCMD_WBF (((u32)1) << 27)
225#define DMA_GCMD_QIE (((u32)1) << 26)
226#define DMA_GCMD_SIRTP (((u32)1) << 24)
227#define DMA_GCMD_IRE (((u32) 1) << 25)
228#define DMA_GCMD_CFI (((u32) 1) << 23)
229
230
231#define DMA_GSTS_TES (((u32)1) << 31)
232#define DMA_GSTS_RTPS (((u32)1) << 30)
233#define DMA_GSTS_FLS (((u32)1) << 29)
234#define DMA_GSTS_AFLS (((u32)1) << 28)
235#define DMA_GSTS_WBFS (((u32)1) << 27)
236#define DMA_GSTS_QIES (((u32)1) << 26)
237#define DMA_GSTS_IRTPS (((u32)1) << 24)
238#define DMA_GSTS_IRES (((u32)1) << 25)
239#define DMA_GSTS_CFIS (((u32)1) << 23)
240
241
242#define DMA_RTADDR_RTT (((u64)1) << 11)
243#define DMA_RTADDR_SMT (((u64)1) << 10)
244
245
246#define DMA_CCMD_ICC (((u64)1) << 63)
247#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
248#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
249#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
250#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
251#define DMA_CCMD_MASK_NOBIT 0
252#define DMA_CCMD_MASK_1BIT 1
253#define DMA_CCMD_MASK_2BIT 2
254#define DMA_CCMD_MASK_3BIT 3
255#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
256#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
257
258
259#define DMA_FECTL_IM (((u32)1) << 31)
260
261
262#define DMA_FSTS_PFO (1 << 0)
263#define DMA_FSTS_PPF (1 << 1)
264#define DMA_FSTS_IQE (1 << 4)
265#define DMA_FSTS_ICE (1 << 5)
266#define DMA_FSTS_ITE (1 << 6)
267#define DMA_FSTS_PRO (1 << 7)
268#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
269
270
271#define DMA_FRCD_F (((u32)1) << 31)
272#define dma_frcd_type(d) ((d >> 30) & 1)
273#define dma_frcd_fault_reason(c) (c & 0xff)
274#define dma_frcd_source_id(c) (c & 0xffff)
275
276#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
277
278
279#define DMA_PRS_PPR ((u32)1)
280
281#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
282do { \
283 cycles_t start_time = get_cycles(); \
284 while (1) { \
285 sts = op(iommu->reg + offset); \
286 if (cond) \
287 break; \
288 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
289 panic("DMAR hardware is malfunctioning\n"); \
290 cpu_relax(); \
291 } \
292} while (0)
293
294#define QI_LENGTH 256
295
296enum {
297 QI_FREE,
298 QI_IN_USE,
299 QI_DONE,
300 QI_ABORT
301};
302
303#define QI_CC_TYPE 0x1
304#define QI_IOTLB_TYPE 0x2
305#define QI_DIOTLB_TYPE 0x3
306#define QI_IEC_TYPE 0x4
307#define QI_IWD_TYPE 0x5
308#define QI_EIOTLB_TYPE 0x6
309#define QI_PC_TYPE 0x7
310#define QI_DEIOTLB_TYPE 0x8
311#define QI_PGRP_RESP_TYPE 0x9
312#define QI_PSTRM_RESP_TYPE 0xa
313
314#define QI_IEC_SELECTIVE (((u64)1) << 4)
315#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
316#define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
317
318#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
319#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
320
321#define QI_IOTLB_DID(did) (((u64)did) << 16)
322#define QI_IOTLB_DR(dr) (((u64)dr) << 7)
323#define QI_IOTLB_DW(dw) (((u64)dw) << 6)
324#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
325#define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
326#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
327#define QI_IOTLB_AM(am) (((u8)am))
328
329#define QI_CC_FM(fm) (((u64)fm) << 48)
330#define QI_CC_SID(sid) (((u64)sid) << 32)
331#define QI_CC_DID(did) (((u64)did) << 16)
332#define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
333
334#define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
335#define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
336#define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
337#define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
338#define QI_DEV_IOTLB_SIZE 1
339#define QI_DEV_IOTLB_MAX_INVS 32
340
341#define QI_PC_PASID(pasid) (((u64)pasid) << 32)
342#define QI_PC_DID(did) (((u64)did) << 16)
343#define QI_PC_GRAN(gran) (((u64)gran) << 4)
344
345#define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
346#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
347
348#define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
349#define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
350#define QI_EIOTLB_AM(am) (((u64)am))
351#define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
352#define QI_EIOTLB_DID(did) (((u64)did) << 16)
353#define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
354
355#define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
356#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
357#define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
358#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
359#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
360#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
361#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
362#define QI_DEV_EIOTLB_MAX_INVS 32
363
364
365#define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
366#define QI_PGRP_PDP(p) (((u64)(p)) << 5)
367#define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12)
368#define QI_PGRP_DID(rid) (((u64)(rid)) << 16)
369#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
370
371
372#define QI_PGRP_LPIG(x) (((u64)(x)) << 2)
373#define QI_PGRP_IDX(idx) (((u64)(idx)) << 3)
374
375
376#define QI_RESP_SUCCESS 0x0
377#define QI_RESP_INVALID 0x1
378#define QI_RESP_FAILURE 0xf
379
380#define QI_GRAN_NONG_PASID 2
381#define QI_GRAN_PSI_PASID 3
382
383#define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap))
384
385struct qi_desc {
386 u64 qw0;
387 u64 qw1;
388 u64 qw2;
389 u64 qw3;
390};
391
392struct q_inval {
393 raw_spinlock_t q_lock;
394 void *desc;
395 int *desc_status;
396 int free_head;
397 int free_tail;
398 int free_cnt;
399};
400
401#ifdef CONFIG_IRQ_REMAP
402
403#define INTR_REMAP_PAGE_ORDER 8
404#define INTR_REMAP_TABLE_REG_SIZE 0xf
405#define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
406
407#define INTR_REMAP_TABLE_ENTRIES 65536
408
409struct irq_domain;
410
411struct ir_table {
412 struct irte *base;
413 unsigned long *bitmap;
414};
415#endif
416
417struct iommu_flush {
418 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
419 u8 fm, u64 type);
420 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
421 unsigned int size_order, u64 type);
422};
423
424enum {
425 SR_DMAR_FECTL_REG,
426 SR_DMAR_FEDATA_REG,
427 SR_DMAR_FEADDR_REG,
428 SR_DMAR_FEUADDR_REG,
429 MAX_SR_DMAR_REGS
430};
431
432#define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
433#define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
434
435extern int intel_iommu_sm;
436
437#define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap))
438#define pasid_supported(iommu) (sm_supported(iommu) && \
439 ecap_pasid((iommu)->ecap))
440
441struct pasid_entry;
442struct pasid_state_entry;
443struct page_req_dsc;
444
445
446
447
448
449
450
451struct root_entry {
452 u64 lo;
453 u64 hi;
454};
455
456
457
458
459
460
461
462
463
464
465
466
467struct context_entry {
468 u64 lo;
469 u64 hi;
470};
471
472struct dmar_domain {
473 int nid;
474
475 unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED];
476
477
478
479 u16 iommu_did[DMAR_UNITS_SUPPORTED];
480
481
482
483 unsigned int auxd_refcnt;
484
485 bool has_iotlb_device;
486 struct list_head devices;
487 struct list_head auxd;
488 struct iova_domain iovad;
489
490 struct dma_pte *pgd;
491 int gaw;
492
493
494 int agaw;
495
496 int flags;
497
498 int iommu_coherency;
499 int iommu_snooping;
500 int iommu_count;
501 int iommu_superpage;
502
503
504 u64 max_addr;
505
506 int default_pasid;
507
508
509
510
511 struct iommu_domain domain;
512
513};
514
515struct intel_iommu {
516 void __iomem *reg;
517 u64 reg_phys;
518 u64 reg_size;
519 u64 cap;
520 u64 ecap;
521 u32 gcmd;
522 raw_spinlock_t register_lock;
523 int seq_id;
524 int agaw;
525 int msagaw;
526 unsigned int irq, pr_irq;
527 u16 segment;
528 unsigned char name[13];
529
530#ifdef CONFIG_INTEL_IOMMU
531 unsigned long *domain_ids;
532 struct dmar_domain ***domains;
533 spinlock_t lock;
534 struct root_entry *root_entry;
535
536 struct iommu_flush flush;
537#endif
538#ifdef CONFIG_INTEL_IOMMU_SVM
539 struct page_req_dsc *prq;
540 unsigned char prq_name[16];
541#endif
542 struct q_inval *qi;
543 u32 *iommu_state;
544
545#ifdef CONFIG_IRQ_REMAP
546 struct ir_table *ir_table;
547 struct irq_domain *ir_domain;
548 struct irq_domain *ir_msi_domain;
549#endif
550 struct iommu_device iommu;
551 int node;
552 u32 flags;
553};
554
555
556struct device_domain_info {
557 struct list_head link;
558 struct list_head global;
559 struct list_head table;
560 struct list_head auxiliary_domains;
561
562
563 u8 bus;
564 u8 devfn;
565 u16 pfsid;
566 u8 pasid_supported:3;
567 u8 pasid_enabled:1;
568 u8 pri_supported:1;
569 u8 pri_enabled:1;
570 u8 ats_supported:1;
571 u8 ats_enabled:1;
572 u8 auxd_enabled:1;
573 u8 ats_qdep;
574 struct device *dev;
575 struct intel_iommu *iommu;
576 struct dmar_domain *domain;
577 struct pasid_table *pasid_table;
578};
579
580static inline void __iommu_flush_cache(
581 struct intel_iommu *iommu, void *addr, int size)
582{
583 if (!ecap_coherent(iommu->ecap))
584 clflush_cache_range(addr, size);
585}
586
587
588
589
590
591
592
593
594
595
596struct dma_pte {
597 u64 val;
598};
599
600static inline void dma_clear_pte(struct dma_pte *pte)
601{
602 pte->val = 0;
603}
604
605static inline u64 dma_pte_addr(struct dma_pte *pte)
606{
607#ifdef CONFIG_64BIT
608 return pte->val & VTD_PAGE_MASK;
609#else
610
611 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
612#endif
613}
614
615static inline bool dma_pte_present(struct dma_pte *pte)
616{
617 return (pte->val & 3) != 0;
618}
619
620static inline bool dma_pte_superpage(struct dma_pte *pte)
621{
622 return (pte->val & DMA_PTE_LARGE_PAGE);
623}
624
625static inline int first_pte_in_page(struct dma_pte *pte)
626{
627 return !((unsigned long)pte & ~VTD_PAGE_MASK);
628}
629
630extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
631extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
632
633extern int dmar_enable_qi(struct intel_iommu *iommu);
634extern void dmar_disable_qi(struct intel_iommu *iommu);
635extern int dmar_reenable_qi(struct intel_iommu *iommu);
636extern void qi_global_iec(struct intel_iommu *iommu);
637
638extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
639 u8 fm, u64 type);
640extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
641 unsigned int size_order, u64 type);
642extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
643 u16 qdep, u64 addr, unsigned mask);
644extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
645
646extern int dmar_ir_support(void);
647
648void *alloc_pgtable_page(int node);
649void free_pgtable_page(void *vaddr);
650struct intel_iommu *domain_get_iommu(struct dmar_domain *domain);
651int for_each_device_domain(int (*fn)(struct device_domain_info *info,
652 void *data), void *data);
653void iommu_flush_write_buffer(struct intel_iommu *iommu);
654int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev);
655
656#ifdef CONFIG_INTEL_IOMMU_SVM
657int intel_svm_init(struct intel_iommu *iommu);
658extern int intel_svm_enable_prq(struct intel_iommu *iommu);
659extern int intel_svm_finish_prq(struct intel_iommu *iommu);
660
661struct svm_dev_ops;
662
663struct intel_svm_dev {
664 struct list_head list;
665 struct rcu_head rcu;
666 struct device *dev;
667 struct svm_dev_ops *ops;
668 int users;
669 u16 did;
670 u16 dev_iotlb:1;
671 u16 sid, qdep;
672};
673
674struct intel_svm {
675 struct mmu_notifier notifier;
676 struct mm_struct *mm;
677 struct intel_iommu *iommu;
678 int flags;
679 int pasid;
680 struct list_head devs;
681 struct list_head list;
682};
683
684extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
685#endif
686
687#ifdef CONFIG_INTEL_IOMMU_DEBUGFS
688void intel_iommu_debugfs_init(void);
689#else
690static inline void intel_iommu_debugfs_init(void) {}
691#endif
692
693extern const struct attribute_group *intel_iommu_groups[];
694bool context_present(struct context_entry *context);
695struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
696 u8 devfn, int alloc);
697
698#ifdef CONFIG_INTEL_IOMMU
699extern int iommu_calculate_agaw(struct intel_iommu *iommu);
700extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
701extern int dmar_disabled;
702extern int intel_iommu_enabled;
703extern int intel_iommu_tboot_noforce;
704#else
705static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
706{
707 return 0;
708}
709static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
710{
711 return 0;
712}
713#define dmar_disabled (1)
714#define intel_iommu_enabled (0)
715#endif
716
717#endif
718