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33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70#define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld)))
71
72
73#define MLX5_SET(typ, p, fld, v) do { \
74 u32 _v = v; \
75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
82#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
84 MLX5_SET(typ, p, fld[idx], v); \
85} while (0)
86
87#define MLX5_SET_TO_ONES(typ, p, fld) do { \
88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
92 << __mlx5_dw_bit_off(typ, fld))); \
93} while (0)
94
95#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
96__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
97__mlx5_mask(typ, fld))
98
99#define MLX5_GET_PR(typ, p, fld) ({ \
100 u32 ___t = MLX5_GET(typ, p, fld); \
101 pr_debug(#fld " = 0x%x\n", ___t); \
102 ___t; \
103})
104
105#define __MLX5_SET64(typ, p, fld, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
108} while (0)
109
110#define MLX5_SET64(typ, p, fld, v) do { \
111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 __MLX5_SET64(typ, p, fld, v); \
113} while (0)
114
115#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
117 __MLX5_SET64(typ, p, fld[idx], v); \
118} while (0)
119
120#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
121
122#define MLX5_GET64_PR(typ, p, fld) ({ \
123 u64 ___t = MLX5_GET64(typ, p, fld); \
124 pr_debug(#fld " = 0x%llx\n", ___t); \
125 ___t; \
126})
127
128#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
129__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
130__mlx5_mask16(typ, fld))
131
132#define MLX5_SET16(typ, p, fld, v) do { \
133 u16 _v = v; \
134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
138 << __mlx5_16_bit_off(typ, fld))); \
139} while (0)
140
141
142#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
143 __mlx5_64_off(typ, fld)))
144
145#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
146 type_t tmp; \
147 switch (sizeof(tmp)) { \
148 case sizeof(u8): \
149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
150 break; \
151 case sizeof(u16): \
152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
153 break; \
154 case sizeof(u32): \
155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
156 break; \
157 case sizeof(u64): \
158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
159 break; \
160 } \
161 tmp; \
162 })
163
164enum mlx5_inline_modes {
165 MLX5_INLINE_MODE_NONE,
166 MLX5_INLINE_MODE_L2,
167 MLX5_INLINE_MODE_IP,
168 MLX5_INLINE_MODE_TCP_UDP,
169};
170
171enum {
172 MLX5_MAX_COMMANDS = 32,
173 MLX5_CMD_DATA_BLOCK_SIZE = 512,
174 MLX5_PCI_CMD_XPORT = 7,
175 MLX5_MKEY_BSF_OCTO_SIZE = 4,
176 MLX5_MAX_PSVS = 4,
177};
178
179enum {
180 MLX5_EXTENDED_UD_AV = 0x80000000,
181};
182
183enum {
184 MLX5_CQ_STATE_ARMED = 9,
185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
186 MLX5_CQ_STATE_FIRED = 0xa,
187};
188
189enum {
190 MLX5_STAT_RATE_OFFSET = 5,
191};
192
193enum {
194 MLX5_INLINE_SEG = 0x80000000,
195};
196
197enum {
198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
199};
200
201enum {
202 MLX5_MIN_PKEY_TABLE_SIZE = 128,
203 MLX5_MAX_LOG_PKEY_TABLE = 5,
204};
205
206enum {
207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
208};
209
210enum {
211 MLX5_PFAULT_SUBTYPE_WQE = 0,
212 MLX5_PFAULT_SUBTYPE_RDMA = 1,
213};
214
215enum wqe_page_fault_type {
216 MLX5_WQE_PF_TYPE_RMP = 0,
217 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
218 MLX5_WQE_PF_TYPE_RESP = 2,
219 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
220};
221
222enum {
223 MLX5_PERM_LOCAL_READ = 1 << 2,
224 MLX5_PERM_LOCAL_WRITE = 1 << 3,
225 MLX5_PERM_REMOTE_READ = 1 << 4,
226 MLX5_PERM_REMOTE_WRITE = 1 << 5,
227 MLX5_PERM_ATOMIC = 1 << 6,
228 MLX5_PERM_UMR_EN = 1 << 7,
229};
230
231enum {
232 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
233 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
234 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
235 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
236 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
237};
238
239enum {
240 MLX5_EN_RD = (u64)1,
241 MLX5_EN_WR = (u64)2
242};
243
244enum {
245 MLX5_ADAPTER_PAGE_SHIFT = 12,
246 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
247};
248
249enum {
250 MLX5_BFREGS_PER_UAR = 4,
251 MLX5_MAX_UARS = 1 << 8,
252 MLX5_NON_FP_BFREGS_PER_UAR = 2,
253 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
254 MLX5_NON_FP_BFREGS_PER_UAR,
255 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
256 MLX5_NON_FP_BFREGS_PER_UAR,
257 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
258 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
259 MLX5_MIN_DYN_BFREGS = 512,
260 MLX5_MAX_DYN_BFREGS = 1024,
261};
262
263enum {
264 MLX5_MKEY_MASK_LEN = 1ull << 0,
265 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
266 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
267 MLX5_MKEY_MASK_PD = 1ull << 7,
268 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
269 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
270 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
271 MLX5_MKEY_MASK_KEY = 1ull << 13,
272 MLX5_MKEY_MASK_QPN = 1ull << 14,
273 MLX5_MKEY_MASK_LR = 1ull << 17,
274 MLX5_MKEY_MASK_LW = 1ull << 18,
275 MLX5_MKEY_MASK_RR = 1ull << 19,
276 MLX5_MKEY_MASK_RW = 1ull << 20,
277 MLX5_MKEY_MASK_A = 1ull << 21,
278 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
279 MLX5_MKEY_MASK_FREE = 1ull << 29,
280};
281
282enum {
283 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
284
285 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
286 MLX5_UMR_CHECK_FREE = (2 << 5),
287
288 MLX5_UMR_INLINE = (1 << 7),
289};
290
291#define MLX5_UMR_MTT_ALIGNMENT 0x40
292#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
293#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
294
295#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
296
297enum {
298 MLX5_EVENT_QUEUE_TYPE_QP = 0,
299 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
300 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
301 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
302};
303
304
305
306
307enum mlx5_event {
308
309 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
310
311 MLX5_EVENT_TYPE_COMP = 0x0,
312
313 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
314 MLX5_EVENT_TYPE_COMM_EST = 0x02,
315 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
316 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
317 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
318
319 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
320 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
321 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
322 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
323 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
324 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
325
326 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
327 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
328 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
329 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
330 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
331 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
332 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
333 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24,
334 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
335
336 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
337 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
338
339 MLX5_EVENT_TYPE_CMD = 0x0a,
340 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
341
342 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
343 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
344
345 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
346
347 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
348
349 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
350 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
351
352 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
353
354 MLX5_EVENT_TYPE_MAX = 0x100,
355};
356
357enum {
358 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
359 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
360};
361
362enum {
363 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
364 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
365};
366
367enum {
368 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
369 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
370 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
371 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
372 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
373 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
374 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
375};
376
377enum {
378 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
379 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
380 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
381 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
382 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
383 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
384 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
385 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
386 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
387 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
388 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
389 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
390};
391
392enum {
393 MLX5_ROCE_VERSION_1 = 0,
394 MLX5_ROCE_VERSION_2 = 2,
395};
396
397enum {
398 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
399 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
400};
401
402enum {
403 MLX5_ROCE_L3_TYPE_IPV4 = 0,
404 MLX5_ROCE_L3_TYPE_IPV6 = 1,
405};
406
407enum {
408 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
409 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
410};
411
412enum {
413 MLX5_OPCODE_NOP = 0x00,
414 MLX5_OPCODE_SEND_INVAL = 0x01,
415 MLX5_OPCODE_RDMA_WRITE = 0x08,
416 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
417 MLX5_OPCODE_SEND = 0x0a,
418 MLX5_OPCODE_SEND_IMM = 0x0b,
419 MLX5_OPCODE_LSO = 0x0e,
420 MLX5_OPCODE_RDMA_READ = 0x10,
421 MLX5_OPCODE_ATOMIC_CS = 0x11,
422 MLX5_OPCODE_ATOMIC_FA = 0x12,
423 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
424 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
425 MLX5_OPCODE_BIND_MW = 0x18,
426 MLX5_OPCODE_CONFIG_CMD = 0x1f,
427 MLX5_OPCODE_ENHANCED_MPSW = 0x29,
428
429 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
430 MLX5_RECV_OPCODE_SEND = 0x01,
431 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
432 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
433
434 MLX5_CQE_OPCODE_ERROR = 0x1e,
435 MLX5_CQE_OPCODE_RESIZE = 0x16,
436
437 MLX5_OPCODE_SET_PSV = 0x20,
438 MLX5_OPCODE_GET_PSV = 0x21,
439 MLX5_OPCODE_CHECK_PSV = 0x22,
440 MLX5_OPCODE_DUMP = 0x23,
441 MLX5_OPCODE_RGET_PSV = 0x26,
442 MLX5_OPCODE_RCHECK_PSV = 0x27,
443
444 MLX5_OPCODE_UMR = 0x25,
445
446};
447
448enum {
449 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
450};
451
452enum {
453 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
454};
455
456enum {
457 MLX5_SET_PORT_RESET_QKEY = 0,
458 MLX5_SET_PORT_GUID0 = 16,
459 MLX5_SET_PORT_NODE_GUID = 17,
460 MLX5_SET_PORT_SYS_GUID = 18,
461 MLX5_SET_PORT_GID_TABLE = 19,
462 MLX5_SET_PORT_PKEY_TABLE = 20,
463};
464
465enum {
466 MLX5_BW_NO_LIMIT = 0,
467 MLX5_100_MBPS_UNIT = 3,
468 MLX5_GBPS_UNIT = 4,
469};
470
471enum {
472 MLX5_MAX_PAGE_SHIFT = 31
473};
474
475enum {
476 MLX5_CAP_OFF_CMDIF_CSUM = 46,
477};
478
479enum {
480
481
482
483
484
485
486
487 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
488};
489
490enum mlx5_odp_transport_cap_bits {
491 MLX5_ODP_SUPPORT_SEND = 1 << 31,
492 MLX5_ODP_SUPPORT_RECV = 1 << 30,
493 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
494 MLX5_ODP_SUPPORT_READ = 1 << 28,
495};
496
497struct mlx5_odp_caps {
498 char reserved[0x10];
499 struct {
500 __be32 rc_odp_caps;
501 __be32 uc_odp_caps;
502 __be32 ud_odp_caps;
503 } per_transport_caps;
504 char reserved2[0xe4];
505};
506
507struct mlx5_cmd_layout {
508 u8 type;
509 u8 rsvd0[3];
510 __be32 inlen;
511 __be64 in_ptr;
512 __be32 in[4];
513 __be32 out[4];
514 __be64 out_ptr;
515 __be32 outlen;
516 u8 token;
517 u8 sig;
518 u8 rsvd1;
519 u8 status_own;
520};
521
522enum mlx5_fatal_assert_bit_offsets {
523 MLX5_RFR_OFFSET = 31,
524};
525
526struct health_buffer {
527 __be32 assert_var[5];
528 __be32 rsvd0[3];
529 __be32 assert_exit_ptr;
530 __be32 assert_callra;
531 __be32 rsvd1[2];
532 __be32 fw_ver;
533 __be32 hw_id;
534 __be32 rfr;
535 u8 irisc_index;
536 u8 synd;
537 __be16 ext_synd;
538};
539
540enum mlx5_initializing_bit_offsets {
541 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
542};
543
544enum mlx5_cmd_addr_l_sz_offset {
545 MLX5_NIC_IFC_OFFSET = 8,
546};
547
548struct mlx5_init_seg {
549 __be32 fw_rev;
550 __be32 cmdif_rev_fw_sub;
551 __be32 rsvd0[2];
552 __be32 cmdq_addr_h;
553 __be32 cmdq_addr_l_sz;
554 __be32 cmd_dbell;
555 __be32 rsvd1[120];
556 __be32 initializing;
557 struct health_buffer health;
558 __be32 rsvd2[880];
559 __be32 internal_timer_h;
560 __be32 internal_timer_l;
561 __be32 rsvd3[2];
562 __be32 health_counter;
563 __be32 rsvd4[1019];
564 __be64 ieee1588_clk;
565 __be32 ieee1588_clk_type;
566 __be32 clr_intx;
567};
568
569struct mlx5_eqe_comp {
570 __be32 reserved[6];
571 __be32 cqn;
572};
573
574struct mlx5_eqe_qp_srq {
575 __be32 reserved1[5];
576 u8 type;
577 u8 reserved2[3];
578 __be32 qp_srq_n;
579};
580
581struct mlx5_eqe_cq_err {
582 __be32 cqn;
583 u8 reserved1[7];
584 u8 syndrome;
585};
586
587struct mlx5_eqe_port_state {
588 u8 reserved0[8];
589 u8 port;
590};
591
592struct mlx5_eqe_gpio {
593 __be32 reserved0[2];
594 __be64 gpio_event;
595};
596
597struct mlx5_eqe_congestion {
598 u8 type;
599 u8 rsvd0;
600 u8 congestion_level;
601};
602
603struct mlx5_eqe_stall_vl {
604 u8 rsvd0[3];
605 u8 port_vl;
606};
607
608struct mlx5_eqe_cmd {
609 __be32 vector;
610 __be32 rsvd[6];
611};
612
613struct mlx5_eqe_page_req {
614 __be16 ec_function;
615 __be16 func_id;
616 __be32 num_pages;
617 __be32 rsvd1[5];
618};
619
620struct mlx5_eqe_page_fault {
621 __be32 bytes_committed;
622 union {
623 struct {
624 u16 reserved1;
625 __be16 wqe_index;
626 u16 reserved2;
627 __be16 packet_length;
628 __be32 token;
629 u8 reserved4[8];
630 __be32 pftype_wq;
631 } __packed wqe;
632 struct {
633 __be32 r_key;
634 u16 reserved1;
635 __be16 packet_length;
636 __be32 rdma_op_len;
637 __be64 rdma_va;
638 __be32 pftype_token;
639 } __packed rdma;
640 } __packed;
641} __packed;
642
643struct mlx5_eqe_vport_change {
644 u8 rsvd0[2];
645 __be16 vport_num;
646 __be32 rsvd1[6];
647} __packed;
648
649struct mlx5_eqe_port_module {
650 u8 reserved_at_0[1];
651 u8 module;
652 u8 reserved_at_2[1];
653 u8 module_status;
654 u8 reserved_at_4[2];
655 u8 error_type;
656} __packed;
657
658struct mlx5_eqe_pps {
659 u8 rsvd0[3];
660 u8 pin;
661 u8 rsvd1[4];
662 union {
663 struct {
664 __be32 time_sec;
665 __be32 time_nsec;
666 };
667 struct {
668 __be64 time_stamp;
669 };
670 };
671 u8 rsvd2[12];
672} __packed;
673
674struct mlx5_eqe_dct {
675 __be32 reserved[6];
676 __be32 dctn;
677};
678
679struct mlx5_eqe_temp_warning {
680 __be64 sensor_warning_msb;
681 __be64 sensor_warning_lsb;
682} __packed;
683
684union ev_data {
685 __be32 raw[7];
686 struct mlx5_eqe_cmd cmd;
687 struct mlx5_eqe_comp comp;
688 struct mlx5_eqe_qp_srq qp_srq;
689 struct mlx5_eqe_cq_err cq_err;
690 struct mlx5_eqe_port_state port;
691 struct mlx5_eqe_gpio gpio;
692 struct mlx5_eqe_congestion cong;
693 struct mlx5_eqe_stall_vl stall_vl;
694 struct mlx5_eqe_page_req req_pages;
695 struct mlx5_eqe_page_fault page_fault;
696 struct mlx5_eqe_vport_change vport_change;
697 struct mlx5_eqe_port_module port_module;
698 struct mlx5_eqe_pps pps;
699 struct mlx5_eqe_dct dct;
700 struct mlx5_eqe_temp_warning temp_warning;
701} __packed;
702
703struct mlx5_eqe {
704 u8 rsvd0;
705 u8 type;
706 u8 rsvd1;
707 u8 sub_type;
708 __be32 rsvd2[7];
709 union ev_data data;
710 __be16 rsvd3;
711 u8 signature;
712 u8 owner;
713} __packed;
714
715struct mlx5_cmd_prot_block {
716 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
717 u8 rsvd0[48];
718 __be64 next;
719 __be32 block_num;
720 u8 rsvd1;
721 u8 token;
722 u8 ctrl_sig;
723 u8 sig;
724};
725
726enum {
727 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
728};
729
730struct mlx5_err_cqe {
731 u8 rsvd0[32];
732 __be32 srqn;
733 u8 rsvd1[18];
734 u8 vendor_err_synd;
735 u8 syndrome;
736 __be32 s_wqe_opcode_qpn;
737 __be16 wqe_counter;
738 u8 signature;
739 u8 op_own;
740};
741
742struct mlx5_cqe64 {
743 u8 outer_l3_tunneled;
744 u8 rsvd0;
745 __be16 wqe_id;
746 u8 lro_tcppsh_abort_dupack;
747 u8 lro_min_ttl;
748 __be16 lro_tcp_win;
749 __be32 lro_ack_seq_num;
750 __be32 rss_hash_result;
751 u8 rss_hash_type;
752 u8 ml_path;
753 u8 rsvd20[2];
754 __be16 check_sum;
755 __be16 slid;
756 __be32 flags_rqpn;
757 u8 hds_ip_ext;
758 u8 l4_l3_hdr_type;
759 __be16 vlan_info;
760 __be32 srqn;
761 __be32 imm_inval_pkey;
762 u8 rsvd40[4];
763 __be32 byte_cnt;
764 __be32 timestamp_h;
765 __be32 timestamp_l;
766 __be32 sop_drop_qpn;
767 __be16 wqe_counter;
768 u8 signature;
769 u8 op_own;
770};
771
772struct mlx5_mini_cqe8 {
773 union {
774 __be32 rx_hash_result;
775 struct {
776 __be16 checksum;
777 __be16 rsvd;
778 };
779 struct {
780 __be16 wqe_counter;
781 u8 s_wqe_opcode;
782 u8 reserved;
783 } s_wqe_info;
784 };
785 __be32 byte_cnt;
786};
787
788enum {
789 MLX5_NO_INLINE_DATA,
790 MLX5_INLINE_DATA32_SEG,
791 MLX5_INLINE_DATA64_SEG,
792 MLX5_COMPRESSED,
793};
794
795enum {
796 MLX5_CQE_FORMAT_CSUM = 0x1,
797};
798
799#define MLX5_MINI_CQE_ARRAY_SIZE 8
800
801static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
802{
803 return (cqe->op_own >> 2) & 0x3;
804}
805
806static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
807{
808 return cqe->op_own >> 4;
809}
810
811static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
812{
813 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
814}
815
816static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
817{
818 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
819}
820
821static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
822{
823 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
824}
825
826static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
827{
828 return cqe->outer_l3_tunneled & 0x1;
829}
830
831static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
832{
833 return cqe->l4_l3_hdr_type & 0x1;
834}
835
836static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
837{
838 u32 hi, lo;
839
840 hi = be32_to_cpu(cqe->timestamp_h);
841 lo = be32_to_cpu(cqe->timestamp_l);
842
843 return (u64)lo | ((u64)hi << 32);
844}
845
846#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9)
847#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6)
848
849struct mpwrq_cqe_bc {
850 __be16 filler_consumed_strides;
851 __be16 byte_cnt;
852};
853
854static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
855{
856 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
857
858 return be16_to_cpu(bc->byte_cnt);
859}
860
861static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
862{
863 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
864}
865
866static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
867{
868 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
869
870 return mpwrq_get_cqe_bc_consumed_strides(bc);
871}
872
873static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
874{
875 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
876
877 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
878}
879
880static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
881{
882 return be16_to_cpu(cqe->wqe_counter);
883}
884
885enum {
886 CQE_L4_HDR_TYPE_NONE = 0x0,
887 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
888 CQE_L4_HDR_TYPE_UDP = 0x2,
889 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
890 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
891};
892
893enum {
894 CQE_RSS_HTYPE_IP = 0x3 << 2,
895
896
897
898 CQE_RSS_HTYPE_L4 = 0x3 << 6,
899
900
901
902};
903
904enum {
905 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
906 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
907 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
908};
909
910enum {
911 CQE_L2_OK = 1 << 0,
912 CQE_L3_OK = 1 << 1,
913 CQE_L4_OK = 1 << 2,
914};
915
916struct mlx5_sig_err_cqe {
917 u8 rsvd0[16];
918 __be32 expected_trans_sig;
919 __be32 actual_trans_sig;
920 __be32 expected_reftag;
921 __be32 actual_reftag;
922 __be16 syndrome;
923 u8 rsvd22[2];
924 __be32 mkey;
925 __be64 err_offset;
926 u8 rsvd30[8];
927 __be32 qpn;
928 u8 rsvd38[2];
929 u8 signature;
930 u8 op_own;
931};
932
933struct mlx5_wqe_srq_next_seg {
934 u8 rsvd0[2];
935 __be16 next_wqe_index;
936 u8 signature;
937 u8 rsvd1[11];
938};
939
940union mlx5_ext_cqe {
941 struct ib_grh grh;
942 u8 inl[64];
943};
944
945struct mlx5_cqe128 {
946 union mlx5_ext_cqe inl_grh;
947 struct mlx5_cqe64 cqe64;
948};
949
950enum {
951 MLX5_MKEY_STATUS_FREE = 1 << 6,
952};
953
954enum {
955 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
956 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
957 MLX5_MKEY_BSF_EN = 1 << 30,
958 MLX5_MKEY_LEN64 = 1 << 31,
959};
960
961struct mlx5_mkey_seg {
962
963
964
965
966 u8 status;
967 u8 pcie_control;
968 u8 flags;
969 u8 version;
970 __be32 qpn_mkey7_0;
971 u8 rsvd1[4];
972 __be32 flags_pd;
973 __be64 start_addr;
974 __be64 len;
975 __be32 bsfs_octo_size;
976 u8 rsvd2[16];
977 __be32 xlt_oct_size;
978 u8 rsvd3[3];
979 u8 log2_page_size;
980 u8 rsvd4[4];
981};
982
983#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
984
985enum {
986 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
987};
988
989enum {
990 VPORT_STATE_DOWN = 0x0,
991 VPORT_STATE_UP = 0x1,
992};
993
994enum {
995 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
996 MLX5_VPORT_ADMIN_STATE_UP = 0x1,
997 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
998};
999
1000enum {
1001 MLX5_L3_PROT_TYPE_IPV4 = 0,
1002 MLX5_L3_PROT_TYPE_IPV6 = 1,
1003};
1004
1005enum {
1006 MLX5_L4_PROT_TYPE_TCP = 0,
1007 MLX5_L4_PROT_TYPE_UDP = 1,
1008};
1009
1010enum {
1011 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1012 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1013 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1014 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1015 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1016};
1017
1018enum {
1019 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1020 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1021 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1022 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,
1023 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,
1024};
1025
1026enum {
1027 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1028 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1029};
1030
1031enum {
1032 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1033 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1034 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1035};
1036
1037enum mlx5_list_type {
1038 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1039 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1040 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1041};
1042
1043enum {
1044 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1045 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1046};
1047
1048enum mlx5_wol_mode {
1049 MLX5_WOL_DISABLE = 0,
1050 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1051 MLX5_WOL_MAGIC = 1 << 2,
1052 MLX5_WOL_ARP = 1 << 3,
1053 MLX5_WOL_BROADCAST = 1 << 4,
1054 MLX5_WOL_MULTICAST = 1 << 5,
1055 MLX5_WOL_UNICAST = 1 << 6,
1056 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1057};
1058
1059enum mlx5_mpls_supported_fields {
1060 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1061 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1062 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1063 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1064};
1065
1066enum mlx5_flex_parser_protos {
1067 MLX5_FLEX_PROTO_GENEVE = 1 << 3,
1068 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1069 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1070};
1071
1072
1073
1074
1075enum mlx5_cap_mode {
1076 HCA_CAP_OPMOD_GET_MAX = 0,
1077 HCA_CAP_OPMOD_GET_CUR = 1,
1078};
1079
1080enum mlx5_cap_type {
1081 MLX5_CAP_GENERAL = 0,
1082 MLX5_CAP_ETHERNET_OFFLOADS,
1083 MLX5_CAP_ODP,
1084 MLX5_CAP_ATOMIC,
1085 MLX5_CAP_ROCE,
1086 MLX5_CAP_IPOIB_OFFLOADS,
1087 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1088 MLX5_CAP_FLOW_TABLE,
1089 MLX5_CAP_ESWITCH_FLOW_TABLE,
1090 MLX5_CAP_ESWITCH,
1091 MLX5_CAP_RESERVED,
1092 MLX5_CAP_VECTOR_CALC,
1093 MLX5_CAP_QOS,
1094 MLX5_CAP_DEBUG,
1095 MLX5_CAP_RESERVED_14,
1096 MLX5_CAP_DEV_MEM,
1097 MLX5_CAP_RESERVED_16,
1098 MLX5_CAP_TLS,
1099 MLX5_CAP_DEV_EVENT = 0x14,
1100
1101 MLX5_CAP_NUM
1102};
1103
1104enum mlx5_pcam_reg_groups {
1105 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1106};
1107
1108enum mlx5_pcam_feature_groups {
1109 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1110};
1111
1112enum mlx5_mcam_reg_groups {
1113 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1114};
1115
1116enum mlx5_mcam_feature_groups {
1117 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1118};
1119
1120enum mlx5_qcam_reg_groups {
1121 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1122};
1123
1124enum mlx5_qcam_feature_groups {
1125 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1126};
1127
1128
1129#define MLX5_CAP_GEN(mdev, cap) \
1130 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1131
1132#define MLX5_CAP_GEN_64(mdev, cap) \
1133 MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1134
1135#define MLX5_CAP_GEN_MAX(mdev, cap) \
1136 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1137
1138#define MLX5_CAP_ETH(mdev, cap) \
1139 MLX5_GET(per_protocol_networking_offload_caps,\
1140 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1141
1142#define MLX5_CAP_ETH_MAX(mdev, cap) \
1143 MLX5_GET(per_protocol_networking_offload_caps,\
1144 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1145
1146#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1147 MLX5_GET(per_protocol_networking_offload_caps,\
1148 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1149
1150#define MLX5_CAP_ROCE(mdev, cap) \
1151 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1152
1153#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1154 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1155
1156#define MLX5_CAP_ATOMIC(mdev, cap) \
1157 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1158
1159#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1160 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1161
1162#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1163 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1164
1165#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1166 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1167
1168#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1169 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1170
1171#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1172 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1173
1174#define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1175 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1176
1177#define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \
1178 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1179
1180#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1181 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1182
1183#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1184 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1185
1186#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1187 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1188
1189#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1190 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1191
1192#define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \
1193 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1194
1195#define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \
1196 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1197
1198#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1199 MLX5_GET(flow_table_eswitch_cap, \
1200 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1201
1202#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1203 MLX5_GET(flow_table_eswitch_cap, \
1204 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1205
1206#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1207 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1208
1209#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1210 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1211
1212#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1213 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1214
1215#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1216 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1217
1218#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1219 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1220
1221#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1222 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1223
1224#define MLX5_CAP_ESW(mdev, cap) \
1225 MLX5_GET(e_switch_cap, \
1226 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1227
1228#define MLX5_CAP_ESW_MAX(mdev, cap) \
1229 MLX5_GET(e_switch_cap, \
1230 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1231
1232#define MLX5_CAP_ODP(mdev, cap)\
1233 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1234
1235#define MLX5_CAP_ODP_MAX(mdev, cap)\
1236 MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap)
1237
1238#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1239 MLX5_GET(vector_calc_cap, \
1240 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1241
1242#define MLX5_CAP_QOS(mdev, cap)\
1243 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1244
1245#define MLX5_CAP_DEBUG(mdev, cap)\
1246 MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1247
1248#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1249 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1250
1251#define MLX5_CAP_PCAM_REG(mdev, reg) \
1252 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1253
1254#define MLX5_CAP_MCAM_REG(mdev, reg) \
1255 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1256
1257#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1258 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1259
1260#define MLX5_CAP_QCAM_REG(mdev, fld) \
1261 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1262
1263#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1264 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1265
1266#define MLX5_CAP_FPGA(mdev, cap) \
1267 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1268
1269#define MLX5_CAP64_FPGA(mdev, cap) \
1270 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1271
1272#define MLX5_CAP_DEV_MEM(mdev, cap)\
1273 MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1274
1275#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1276 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1277
1278#define MLX5_CAP_TLS(mdev, cap) \
1279 MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
1280
1281#define MLX5_CAP_DEV_EVENT(mdev, cap)\
1282 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
1283
1284enum {
1285 MLX5_CMD_STAT_OK = 0x0,
1286 MLX5_CMD_STAT_INT_ERR = 0x1,
1287 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1288 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1289 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1290 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1291 MLX5_CMD_STAT_RES_BUSY = 0x6,
1292 MLX5_CMD_STAT_LIM_ERR = 0x8,
1293 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1294 MLX5_CMD_STAT_IX_ERR = 0xa,
1295 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1296 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1297 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1298 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1299 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1300 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1301};
1302
1303enum {
1304 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1305 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1306 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1307 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1308 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1309 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1310 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1311 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1312 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1313 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1314};
1315
1316enum {
1317 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1318};
1319
1320static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1321{
1322 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1323 return 0;
1324 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1325}
1326
1327#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1328#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1329#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1330#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1331 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1332 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1333
1334#endif
1335
