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6#ifndef __LINUX_MTD_SPI_NOR_H
7#define __LINUX_MTD_SPI_NOR_H
8
9#include <linux/bitops.h>
10#include <linux/mtd/cfi.h>
11#include <linux/mtd/mtd.h>
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18
19#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
20#define SNOR_MFR_GIGADEVICE 0xc8
21#define SNOR_MFR_INTEL CFI_MFR_INTEL
22#define SNOR_MFR_ST CFI_MFR_ST
23#define SNOR_MFR_MICRON CFI_MFR_MICRON
24#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
25#define SNOR_MFR_SPANSION CFI_MFR_AMD
26#define SNOR_MFR_SST CFI_MFR_SST
27#define SNOR_MFR_WINBOND 0xef
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37
38#define SPINOR_OP_WREN 0x06
39#define SPINOR_OP_RDSR 0x05
40#define SPINOR_OP_WRSR 0x01
41#define SPINOR_OP_RDSR2 0x3f
42#define SPINOR_OP_WRSR2 0x3e
43#define SPINOR_OP_READ 0x03
44#define SPINOR_OP_READ_FAST 0x0b
45#define SPINOR_OP_READ_1_1_2 0x3b
46#define SPINOR_OP_READ_1_2_2 0xbb
47#define SPINOR_OP_READ_1_1_4 0x6b
48#define SPINOR_OP_READ_1_4_4 0xeb
49#define SPINOR_OP_READ_1_1_8 0x8b
50#define SPINOR_OP_READ_1_8_8 0xcb
51#define SPINOR_OP_PP 0x02
52#define SPINOR_OP_PP_1_1_4 0x32
53#define SPINOR_OP_PP_1_4_4 0x38
54#define SPINOR_OP_PP_1_1_8 0x82
55#define SPINOR_OP_PP_1_8_8 0xc2
56#define SPINOR_OP_BE_4K 0x20
57#define SPINOR_OP_BE_4K_PMC 0xd7
58#define SPINOR_OP_BE_32K 0x52
59#define SPINOR_OP_CHIP_ERASE 0xc7
60#define SPINOR_OP_SE 0xd8
61#define SPINOR_OP_RDID 0x9f
62#define SPINOR_OP_RDSFDP 0x5a
63#define SPINOR_OP_RDCR 0x35
64#define SPINOR_OP_RDFSR 0x70
65#define SPINOR_OP_CLFSR 0x50
66#define SPINOR_OP_RDEAR 0xc8
67#define SPINOR_OP_WREAR 0xc5
68
69
70#define SPINOR_OP_READ_4B 0x13
71#define SPINOR_OP_READ_FAST_4B 0x0c
72#define SPINOR_OP_READ_1_1_2_4B 0x3c
73#define SPINOR_OP_READ_1_2_2_4B 0xbc
74#define SPINOR_OP_READ_1_1_4_4B 0x6c
75#define SPINOR_OP_READ_1_4_4_4B 0xec
76#define SPINOR_OP_READ_1_1_8_4B 0x7c
77#define SPINOR_OP_READ_1_8_8_4B 0xcc
78#define SPINOR_OP_PP_4B 0x12
79#define SPINOR_OP_PP_1_1_4_4B 0x34
80#define SPINOR_OP_PP_1_4_4_4B 0x3e
81#define SPINOR_OP_PP_1_1_8_4B 0x84
82#define SPINOR_OP_PP_1_8_8_4B 0x8e
83#define SPINOR_OP_BE_4K_4B 0x21
84#define SPINOR_OP_BE_32K_4B 0x5c
85#define SPINOR_OP_SE_4B 0xdc
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87
88#define SPINOR_OP_READ_1_1_1_DTR 0x0d
89#define SPINOR_OP_READ_1_2_2_DTR 0xbd
90#define SPINOR_OP_READ_1_4_4_DTR 0xed
91
92#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
93#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
94#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
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96
97#define SPINOR_OP_BP 0x02
98#define SPINOR_OP_WRDI 0x04
99#define SPINOR_OP_AAI_WP 0xad
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101
102#define SPINOR_OP_XSE 0x50
103#define SPINOR_OP_XPP 0x82
104#define SPINOR_OP_XRDSR 0xd7
105
106#define XSR_PAGESIZE BIT(0)
107#define XSR_RDY BIT(7)
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111#define SPINOR_OP_EN4B 0xb7
112#define SPINOR_OP_EX4B 0xe9
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115#define SPINOR_OP_BRWR 0x17
116#define SPINOR_OP_CLSR 0x30
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119#define SPINOR_OP_RD_EVCR 0x65
120#define SPINOR_OP_WD_EVCR 0x61
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122
123#define SR_WIP BIT(0)
124#define SR_WEL BIT(1)
125
126#define SR_BP0 BIT(2)
127#define SR_BP1 BIT(3)
128#define SR_BP2 BIT(4)
129#define SR_TB BIT(5)
130#define SR_SRWD BIT(7)
131
132#define SR_E_ERR BIT(5)
133#define SR_P_ERR BIT(6)
134
135#define SR_QUAD_EN_MX BIT(6)
136
137
138#define EVCR_QUAD_EN_MICRON BIT(7)
139
140
141#define FSR_READY BIT(7)
142#define FSR_E_ERR BIT(5)
143#define FSR_P_ERR BIT(4)
144#define FSR_PT_ERR BIT(1)
145
146
147#define CR_QUAD_EN_SPAN BIT(1)
148
149
150#define SR2_QUAD_EN_BIT7 BIT(7)
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152
153#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
154#define SNOR_PROTO_INST_SHIFT 16
155#define SNOR_PROTO_INST(_nbits) \
156 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
157 SNOR_PROTO_INST_MASK)
158
159#define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
160#define SNOR_PROTO_ADDR_SHIFT 8
161#define SNOR_PROTO_ADDR(_nbits) \
162 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
163 SNOR_PROTO_ADDR_MASK)
164
165#define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
166#define SNOR_PROTO_DATA_SHIFT 0
167#define SNOR_PROTO_DATA(_nbits) \
168 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
169 SNOR_PROTO_DATA_MASK)
170
171#define SNOR_PROTO_IS_DTR BIT(24)
172
173#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
174 (SNOR_PROTO_INST(_inst_nbits) | \
175 SNOR_PROTO_ADDR(_addr_nbits) | \
176 SNOR_PROTO_DATA(_data_nbits))
177#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
178 (SNOR_PROTO_IS_DTR | \
179 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
180
181enum spi_nor_protocol {
182 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
183 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
184 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
185 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
186 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
187 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
188 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
189 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
190 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
191 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
192
193 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
194 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
195 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
196 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
197};
198
199static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
200{
201 return !!(proto & SNOR_PROTO_IS_DTR);
202}
203
204static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
205{
206 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
207 SNOR_PROTO_INST_SHIFT;
208}
209
210static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
211{
212 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
213 SNOR_PROTO_ADDR_SHIFT;
214}
215
216static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
217{
218 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
219 SNOR_PROTO_DATA_SHIFT;
220}
221
222static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
223{
224 return spi_nor_get_protocol_data_nbits(proto);
225}
226
227#define SPI_NOR_MAX_CMD_SIZE 8
228enum spi_nor_ops {
229 SPI_NOR_OPS_READ = 0,
230 SPI_NOR_OPS_WRITE,
231 SPI_NOR_OPS_ERASE,
232 SPI_NOR_OPS_LOCK,
233 SPI_NOR_OPS_UNLOCK,
234};
235
236enum spi_nor_option_flags {
237 SNOR_F_USE_FSR = BIT(0),
238 SNOR_F_HAS_SR_TB = BIT(1),
239 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
240 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
241 SNOR_F_READY_XSR_RDY = BIT(4),
242 SNOR_F_USE_CLSR = BIT(5),
243 SNOR_F_BROKEN_RESET = BIT(6),
244 SNOR_F_4B_OPCODES = BIT(7),
245 SNOR_F_HAS_4BAIT = BIT(8),
246};
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261struct spi_nor_erase_type {
262 u32 size;
263 u32 size_shift;
264 u32 size_mask;
265 u8 opcode;
266 u8 idx;
267};
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280struct spi_nor_erase_command {
281 struct list_head list;
282 u32 count;
283 u32 size;
284 u8 opcode;
285};
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298struct spi_nor_erase_region {
299 u64 offset;
300 u64 size;
301};
302
303#define SNOR_ERASE_TYPE_MAX 4
304#define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
305
306#define SNOR_LAST_REGION BIT(4)
307#define SNOR_OVERLAID_REGION BIT(5)
308
309#define SNOR_ERASE_FLAGS_MAX 6
310#define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
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329struct spi_nor_erase_map {
330 struct spi_nor_erase_region *regions;
331 struct spi_nor_erase_region uniform_region;
332 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
333 u8 uniform_erase_type;
334};
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340struct flash_info;
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381struct spi_nor {
382 struct mtd_info mtd;
383 struct mutex lock;
384 struct device *dev;
385 const struct flash_info *info;
386 u32 page_size;
387 u8 addr_width;
388 u8 erase_opcode;
389 u8 read_opcode;
390 u8 read_dummy;
391 u8 program_opcode;
392 enum spi_nor_protocol read_proto;
393 enum spi_nor_protocol write_proto;
394 enum spi_nor_protocol reg_proto;
395 bool sst_write_second;
396 u32 flags;
397 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
398 struct spi_nor_erase_map erase_map;
399
400 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
401 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
402 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
403 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
404
405 ssize_t (*read)(struct spi_nor *nor, loff_t from,
406 size_t len, u_char *read_buf);
407 ssize_t (*write)(struct spi_nor *nor, loff_t to,
408 size_t len, const u_char *write_buf);
409 int (*erase)(struct spi_nor *nor, loff_t offs);
410
411 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
412 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
413 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
414 int (*quad_enable)(struct spi_nor *nor);
415 int (*clear_sr_bp)(struct spi_nor *nor);
416
417 void *priv;
418};
419
420static u64 __maybe_unused
421spi_nor_region_is_last(const struct spi_nor_erase_region *region)
422{
423 return region->offset & SNOR_LAST_REGION;
424}
425
426static u64 __maybe_unused
427spi_nor_region_end(const struct spi_nor_erase_region *region)
428{
429 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
430}
431
432static void __maybe_unused
433spi_nor_region_mark_end(struct spi_nor_erase_region *region)
434{
435 region->offset |= SNOR_LAST_REGION;
436}
437
438static void __maybe_unused
439spi_nor_region_mark_overlay(struct spi_nor_erase_region *region)
440{
441 region->offset |= SNOR_OVERLAID_REGION;
442}
443
444static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor)
445{
446 return !!nor->erase_map.uniform_erase_type;
447}
448
449static inline void spi_nor_set_flash_node(struct spi_nor *nor,
450 struct device_node *np)
451{
452 mtd_set_of_node(&nor->mtd, np);
453}
454
455static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
456{
457 return mtd_get_of_node(&nor->mtd);
458}
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465struct spi_nor_hwcaps {
466 u32 mask;
467};
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476#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
477#define SNOR_HWCAPS_READ BIT(0)
478#define SNOR_HWCAPS_READ_FAST BIT(1)
479#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
480
481#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
482#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
483#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
484#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
485#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
486
487#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
488#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
489#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
490#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
491#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
492
493#define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11)
494#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
495#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
496#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
497#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
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508#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
509#define SNOR_HWCAPS_PP BIT(16)
510
511#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
512#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
513#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
514#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
515
516#define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20)
517#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
518#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
519#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
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535int spi_nor_scan(struct spi_nor *nor, const char *name,
536 const struct spi_nor_hwcaps *hwcaps);
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542void spi_nor_restore(struct spi_nor *nor);
543
544#endif
545