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17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20
21#include <linux/mod_devicetable.h>
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/list.h>
27#include <linux/compiler.h>
28#include <linux/errno.h>
29#include <linux/kobject.h>
30#include <linux/atomic.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/io.h>
34#include <linux/resource_ext.h>
35#include <uapi/linux/pci.h>
36
37#include <linux/pci_ids.h>
38
39
40
41
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43
44
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46
47
48
49
50
51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
55
56struct pci_slot {
57 struct pci_bus *bus;
58 struct list_head list;
59 struct hotplug_slot *hotplug;
60 unsigned char number;
61 struct kobject kobj;
62};
63
64static inline const char *pci_slot_name(const struct pci_slot *slot)
65{
66 return kobject_name(&slot->kobj);
67}
68
69
70enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73};
74
75
76enum {
77
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81
82 PCI_ROM_RESOURCE,
83
84
85#ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88#endif
89
90
91#define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
97
98 PCI_NUM_RESOURCES,
99
100
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
102};
103
104
105
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107
108
109
110
111
112
113
114
115enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
117 PCI_INTERRUPT_INTA,
118 PCI_INTERRUPT_INTB,
119 PCI_INTERRUPT_INTC,
120 PCI_INTERRUPT_INTD,
121};
122
123
124#define PCI_NUM_INTX 4
125
126
127
128
129
130typedef int __bitwise pci_power_t;
131
132#define PCI_D0 ((pci_power_t __force) 0)
133#define PCI_D1 ((pci_power_t __force) 1)
134#define PCI_D2 ((pci_power_t __force) 2)
135#define PCI_D3hot ((pci_power_t __force) 3)
136#define PCI_D3cold ((pci_power_t __force) 4)
137#define PCI_UNKNOWN ((pci_power_t __force) 5)
138#define PCI_POWER_ERROR ((pci_power_t __force) -1)
139
140
141extern const char *pci_power_names[];
142
143static inline const char *pci_power_name(pci_power_t state)
144{
145 return pci_power_names[1 + (__force int) state];
146}
147
148#define PCI_PM_D2_DELAY 200
149#define PCI_PM_D3_WAIT 10
150#define PCI_PM_D3COLD_WAIT 100
151#define PCI_PM_BUS_WAIT 50
152
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158
159
160typedef unsigned int __bitwise pci_channel_state_t;
161
162enum pci_channel_state {
163
164 pci_channel_io_normal = (__force pci_channel_state_t) 1,
165
166
167 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
168
169
170 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
171};
172
173typedef unsigned int __bitwise pcie_reset_state_t;
174
175enum pcie_reset_state {
176
177 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
178
179
180 pcie_warm_reset = (__force pcie_reset_state_t) 2,
181
182
183 pcie_hot_reset = (__force pcie_reset_state_t) 3
184};
185
186typedef unsigned short __bitwise pci_dev_flags_t;
187enum pci_dev_flags {
188
189 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
190
191 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
192
193 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
194
195 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
196
197 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
198
199 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
200
201 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
202
203 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
204
205 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
206
207 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
208
209 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
210};
211
212enum pci_irq_reroute_variant {
213 INTEL_IRQ_REROUTE_VARIANT = 1,
214 MAX_IRQ_REROUTE_VARIANTS = 3
215};
216
217typedef unsigned short __bitwise pci_bus_flags_t;
218enum pci_bus_flags {
219 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
220 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
221 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
222 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
223};
224
225
226enum pcie_link_width {
227 PCIE_LNK_WIDTH_RESRV = 0x00,
228 PCIE_LNK_X1 = 0x01,
229 PCIE_LNK_X2 = 0x02,
230 PCIE_LNK_X4 = 0x04,
231 PCIE_LNK_X8 = 0x08,
232 PCIE_LNK_X12 = 0x0c,
233 PCIE_LNK_X16 = 0x10,
234 PCIE_LNK_X32 = 0x20,
235 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
236};
237
238
239enum pci_bus_speed {
240 PCI_SPEED_33MHz = 0x00,
241 PCI_SPEED_66MHz = 0x01,
242 PCI_SPEED_66MHz_PCIX = 0x02,
243 PCI_SPEED_100MHz_PCIX = 0x03,
244 PCI_SPEED_133MHz_PCIX = 0x04,
245 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
246 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
247 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
248 PCI_SPEED_66MHz_PCIX_266 = 0x09,
249 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
250 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
251 AGP_UNKNOWN = 0x0c,
252 AGP_1X = 0x0d,
253 AGP_2X = 0x0e,
254 AGP_4X = 0x0f,
255 AGP_8X = 0x10,
256 PCI_SPEED_66MHz_PCIX_533 = 0x11,
257 PCI_SPEED_100MHz_PCIX_533 = 0x12,
258 PCI_SPEED_133MHz_PCIX_533 = 0x13,
259 PCIE_SPEED_2_5GT = 0x14,
260 PCIE_SPEED_5_0GT = 0x15,
261 PCIE_SPEED_8_0GT = 0x16,
262 PCIE_SPEED_16_0GT = 0x17,
263 PCIE_SPEED_32_0GT = 0x18,
264 PCI_SPEED_UNKNOWN = 0xff,
265};
266
267enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
268enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
269
270struct pci_cap_saved_data {
271 u16 cap_nr;
272 bool cap_extended;
273 unsigned int size;
274 u32 data[0];
275};
276
277struct pci_cap_saved_state {
278 struct hlist_node next;
279 struct pci_cap_saved_data cap;
280};
281
282struct irq_affinity;
283struct pcie_link_state;
284struct pci_vpd;
285struct pci_sriov;
286struct pci_ats;
287struct pci_p2pdma;
288
289
290struct pci_dev {
291 struct list_head bus_list;
292 struct pci_bus *bus;
293 struct pci_bus *subordinate;
294
295 void *sysdata;
296 struct proc_dir_entry *procent;
297 struct pci_slot *slot;
298
299 unsigned int devfn;
300 unsigned short vendor;
301 unsigned short device;
302 unsigned short subsystem_vendor;
303 unsigned short subsystem_device;
304 unsigned int class;
305 u8 revision;
306 u8 hdr_type;
307#ifdef CONFIG_PCIEAER
308 u16 aer_cap;
309 struct aer_stats *aer_stats;
310#endif
311 u8 pcie_cap;
312 u8 msi_cap;
313 u8 msix_cap;
314 u8 pcie_mpss:3;
315 u8 rom_base_reg;
316 u8 pin;
317 u16 pcie_flags_reg;
318 unsigned long *dma_alias_mask;
319
320 struct pci_driver *driver;
321 u64 dma_mask;
322
323
324
325
326
327 struct device_dma_parameters dma_parms;
328
329 pci_power_t current_state;
330
331
332 unsigned int imm_ready:1;
333 u8 pm_cap;
334 unsigned int pme_support:5;
335
336 unsigned int pme_poll:1;
337 unsigned int d1_support:1;
338 unsigned int d2_support:1;
339 unsigned int no_d1d2:1;
340 unsigned int no_d3cold:1;
341 unsigned int bridge_d3:1;
342 unsigned int d3cold_allowed:1;
343 unsigned int mmio_always_on:1;
344
345 unsigned int wakeup_prepared:1;
346 unsigned int runtime_d3cold:1;
347
348
349
350 unsigned int skip_bus_pm:1;
351 unsigned int ignore_hotplug:1;
352 unsigned int hotplug_user_indicators:1;
353
354
355 unsigned int clear_retrain_link:1;
356
357 unsigned int d3_delay;
358 unsigned int d3cold_delay;
359
360#ifdef CONFIG_PCIEASPM
361 struct pcie_link_state *link_state;
362 unsigned int ltr_path:1;
363
364#endif
365 unsigned int eetlp_prefix_path:1;
366
367 pci_channel_state_t error_state;
368 struct device dev;
369
370 int cfg_size;
371
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373
374
375
376 unsigned int irq;
377 struct resource resource[DEVICE_COUNT_RESOURCE];
378
379 bool match_driver;
380
381 unsigned int transparent:1;
382 unsigned int io_window:1;
383 unsigned int pref_window:1;
384 unsigned int pref_64_window:1;
385 unsigned int multifunction:1;
386
387 unsigned int is_busmaster:1;
388 unsigned int no_msi:1;
389 unsigned int no_64bit_msi:1;
390 unsigned int block_cfg_access:1;
391 unsigned int broken_parity_status:1;
392 unsigned int irq_reroute_variant:2;
393 unsigned int msi_enabled:1;
394 unsigned int msix_enabled:1;
395 unsigned int ari_enabled:1;
396 unsigned int ats_enabled:1;
397 unsigned int pasid_enabled:1;
398 unsigned int pri_enabled:1;
399 unsigned int is_managed:1;
400 unsigned int needs_freset:1;
401 unsigned int state_saved:1;
402 unsigned int is_physfn:1;
403 unsigned int is_virtfn:1;
404 unsigned int reset_fn:1;
405 unsigned int is_hotplug_bridge:1;
406 unsigned int shpc_managed:1;
407 unsigned int is_thunderbolt:1;
408
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414
415 unsigned int untrusted:1;
416 unsigned int __aer_firmware_first_valid:1;
417 unsigned int __aer_firmware_first:1;
418 unsigned int broken_intx_masking:1;
419 unsigned int io_window_1k:1;
420 unsigned int irq_managed:1;
421 unsigned int has_secondary_link:1;
422 unsigned int non_compliant_bars:1;
423 unsigned int is_probed:1;
424 unsigned int link_active_reporting:1;
425 unsigned int no_vf_scan:1;
426 pci_dev_flags_t dev_flags;
427 atomic_t enable_cnt;
428
429 u32 saved_config_space[16];
430 struct hlist_head saved_cap_space;
431 struct bin_attribute *rom_attr;
432 int rom_attr_enabled;
433 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
434 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
435
436#ifdef CONFIG_HOTPLUG_PCI_PCIE
437 unsigned int broken_cmd_compl:1;
438#endif
439#ifdef CONFIG_PCIE_PTM
440 unsigned int ptm_root:1;
441 unsigned int ptm_enabled:1;
442 u8 ptm_granularity;
443#endif
444#ifdef CONFIG_PCI_MSI
445 const struct attribute_group **msi_irq_groups;
446#endif
447 struct pci_vpd *vpd;
448#ifdef CONFIG_PCI_ATS
449 union {
450 struct pci_sriov *sriov;
451 struct pci_dev *physfn;
452 };
453 u16 ats_cap;
454 u8 ats_stu;
455 atomic_t ats_ref_cnt;
456#endif
457#ifdef CONFIG_PCI_PRI
458 u32 pri_reqs_alloc;
459#endif
460#ifdef CONFIG_PCI_PASID
461 u16 pasid_features;
462#endif
463#ifdef CONFIG_PCI_P2PDMA
464 struct pci_p2pdma *p2pdma;
465#endif
466 phys_addr_t rom;
467 size_t romlen;
468 char *driver_override;
469
470 unsigned long priv_flags;
471};
472
473static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
474{
475#ifdef CONFIG_PCI_IOV
476 if (dev->is_virtfn)
477 dev = dev->physfn;
478#endif
479 return dev;
480}
481
482struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
483
484#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
485#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
486
487static inline int pci_channel_offline(struct pci_dev *pdev)
488{
489 return (pdev->error_state != pci_channel_io_normal);
490}
491
492struct pci_host_bridge {
493 struct device dev;
494 struct pci_bus *bus;
495 struct pci_ops *ops;
496 void *sysdata;
497 int busnr;
498 struct list_head windows;
499 struct list_head dma_ranges;
500 u8 (*swizzle_irq)(struct pci_dev *, u8 *);
501 int (*map_irq)(const struct pci_dev *, u8, u8);
502 void (*release_fn)(struct pci_host_bridge *);
503 void *release_data;
504 struct msi_controller *msi;
505 unsigned int ignore_reset_delay:1;
506 unsigned int no_ext_tags:1;
507 unsigned int native_aer:1;
508 unsigned int native_pcie_hotplug:1;
509 unsigned int native_shpc_hotplug:1;
510 unsigned int native_pme:1;
511 unsigned int native_ltr:1;
512 unsigned int preserve_config:1;
513
514
515 resource_size_t (*align_resource)(struct pci_dev *dev,
516 const struct resource *res,
517 resource_size_t start,
518 resource_size_t size,
519 resource_size_t align);
520 unsigned long private[0] ____cacheline_aligned;
521};
522
523#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
524
525static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
526{
527 return (void *)bridge->private;
528}
529
530static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
531{
532 return container_of(priv, struct pci_host_bridge, private);
533}
534
535struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
536struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
537 size_t priv);
538void pci_free_host_bridge(struct pci_host_bridge *bridge);
539struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
540
541void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
542 void (*release_fn)(struct pci_host_bridge *),
543 void *release_data);
544
545int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
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559
560#define PCI_SUBTRACTIVE_DECODE 0x1
561
562struct pci_bus_resource {
563 struct list_head list;
564 struct resource *res;
565 unsigned int flags;
566};
567
568#define PCI_REGION_FLAG_MASK 0x0fU
569
570struct pci_bus {
571 struct list_head node;
572 struct pci_bus *parent;
573 struct list_head children;
574 struct list_head devices;
575 struct pci_dev *self;
576 struct list_head slots;
577
578 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
579 struct list_head resources;
580 struct resource busn_res;
581
582 struct pci_ops *ops;
583 struct msi_controller *msi;
584 void *sysdata;
585 struct proc_dir_entry *procdir;
586
587 unsigned char number;
588 unsigned char primary;
589 unsigned char max_bus_speed;
590 unsigned char cur_bus_speed;
591#ifdef CONFIG_PCI_DOMAINS_GENERIC
592 int domain_nr;
593#endif
594
595 char name[48];
596
597 unsigned short bridge_ctl;
598 pci_bus_flags_t bus_flags;
599 struct device *bridge;
600 struct device dev;
601 struct bin_attribute *legacy_io;
602 struct bin_attribute *legacy_mem;
603 unsigned int is_added:1;
604};
605
606#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
607
608static inline u16 pci_dev_id(struct pci_dev *dev)
609{
610 return PCI_DEVID(dev->bus->number, dev->devfn);
611}
612
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621static inline bool pci_is_root_bus(struct pci_bus *pbus)
622{
623 return !(pbus->parent);
624}
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632
633static inline bool pci_is_bridge(struct pci_dev *dev)
634{
635 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
636 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
637}
638
639#define for_each_pci_bridge(dev, bus) \
640 list_for_each_entry(dev, &bus->devices, bus_list) \
641 if (!pci_is_bridge(dev)) {} else
642
643static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
644{
645 dev = pci_physfn(dev);
646 if (pci_is_root_bus(dev->bus))
647 return NULL;
648
649 return dev->bus->self;
650}
651
652struct device *pci_get_host_bridge_device(struct pci_dev *dev);
653void pci_put_host_bridge_device(struct device *dev);
654
655#ifdef CONFIG_PCI_MSI
656static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
657{
658 return pci_dev->msi_enabled || pci_dev->msix_enabled;
659}
660#else
661static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
662#endif
663
664
665#define PCIBIOS_SUCCESSFUL 0x00
666#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
667#define PCIBIOS_BAD_VENDOR_ID 0x83
668#define PCIBIOS_DEVICE_NOT_FOUND 0x86
669#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
670#define PCIBIOS_SET_FAILED 0x88
671#define PCIBIOS_BUFFER_TOO_SMALL 0x89
672
673
674static inline int pcibios_err_to_errno(int err)
675{
676 if (err <= PCIBIOS_SUCCESSFUL)
677 return err;
678
679 switch (err) {
680 case PCIBIOS_FUNC_NOT_SUPPORTED:
681 return -ENOENT;
682 case PCIBIOS_BAD_VENDOR_ID:
683 return -ENOTTY;
684 case PCIBIOS_DEVICE_NOT_FOUND:
685 return -ENODEV;
686 case PCIBIOS_BAD_REGISTER_NUMBER:
687 return -EFAULT;
688 case PCIBIOS_SET_FAILED:
689 return -EIO;
690 case PCIBIOS_BUFFER_TOO_SMALL:
691 return -ENOSPC;
692 }
693
694 return -ERANGE;
695}
696
697
698
699struct pci_ops {
700 int (*add_bus)(struct pci_bus *bus);
701 void (*remove_bus)(struct pci_bus *bus);
702 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
703 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
704 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
705};
706
707
708
709
710
711int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
712 int reg, int len, u32 *val);
713int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
714 int reg, int len, u32 val);
715
716#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
717typedef u64 pci_bus_addr_t;
718#else
719typedef u32 pci_bus_addr_t;
720#endif
721
722struct pci_bus_region {
723 pci_bus_addr_t start;
724 pci_bus_addr_t end;
725};
726
727struct pci_dynids {
728 spinlock_t lock;
729 struct list_head list;
730};
731
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739
740typedef unsigned int __bitwise pci_ers_result_t;
741
742enum pci_ers_result {
743
744 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
745
746
747 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
748
749
750 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
751
752
753 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
754
755
756 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
757
758
759 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
760};
761
762
763struct pci_error_handlers {
764
765 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
766 enum pci_channel_state error);
767
768
769 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
770
771
772 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
773
774
775 void (*reset_prepare)(struct pci_dev *dev);
776 void (*reset_done)(struct pci_dev *dev);
777
778
779 void (*resume)(struct pci_dev *dev);
780};
781
782
783struct module;
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828struct pci_driver {
829 struct list_head node;
830 const char *name;
831 const struct pci_device_id *id_table;
832 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
833 void (*remove)(struct pci_dev *dev);
834 int (*suspend)(struct pci_dev *dev, pm_message_t state);
835 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
836 int (*resume_early)(struct pci_dev *dev);
837 int (*resume)(struct pci_dev *dev);
838 void (*shutdown)(struct pci_dev *dev);
839 int (*sriov_configure)(struct pci_dev *dev, int num_vfs);
840 const struct pci_error_handlers *err_handler;
841 const struct attribute_group **groups;
842 struct device_driver driver;
843 struct pci_dynids dynids;
844};
845
846#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
847
848
849
850
851
852
853
854
855
856
857#define PCI_DEVICE(vend,dev) \
858 .vendor = (vend), .device = (dev), \
859 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
860
861
862
863
864
865
866
867
868
869
870
871#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
872 .vendor = (vend), .device = (dev), \
873 .subvendor = (subvend), .subdevice = (subdev)
874
875
876
877
878
879
880
881
882
883
884#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
885 .class = (dev_class), .class_mask = (dev_class_mask), \
886 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
887 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
888
889
890
891
892
893
894
895
896
897
898
899#define PCI_VDEVICE(vend, dev) \
900 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
901 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
902
903
904
905
906
907
908
909
910
911
912
913#define PCI_DEVICE_DATA(vend, dev, data) \
914 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
915 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
916 .driver_data = (kernel_ulong_t)(data)
917
918enum {
919 PCI_REASSIGN_ALL_RSRC = 0x00000001,
920 PCI_REASSIGN_ALL_BUS = 0x00000002,
921 PCI_PROBE_ONLY = 0x00000004,
922 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
923 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
924 PCI_COMPAT_DOMAIN_0 = 0x00000020,
925 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
926};
927
928
929#ifdef CONFIG_PCI
930
931extern unsigned int pci_flags;
932
933static inline void pci_set_flags(int flags) { pci_flags = flags; }
934static inline void pci_add_flags(int flags) { pci_flags |= flags; }
935static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
936static inline int pci_has_flag(int flag) { return pci_flags & flag; }
937
938void pcie_bus_configure_settings(struct pci_bus *bus);
939
940enum pcie_bus_config_types {
941 PCIE_BUS_TUNE_OFF,
942 PCIE_BUS_DEFAULT,
943 PCIE_BUS_SAFE,
944 PCIE_BUS_PERFORMANCE,
945 PCIE_BUS_PEER2PEER,
946};
947
948extern enum pcie_bus_config_types pcie_bus_config;
949
950extern struct bus_type pci_bus_type;
951
952
953
954extern struct list_head pci_root_buses;
955
956int no_pci_devices(void);
957
958void pcibios_resource_survey_bus(struct pci_bus *bus);
959void pcibios_bus_add_device(struct pci_dev *pdev);
960void pcibios_add_bus(struct pci_bus *bus);
961void pcibios_remove_bus(struct pci_bus *bus);
962void pcibios_fixup_bus(struct pci_bus *);
963int __must_check pcibios_enable_device(struct pci_dev *, int mask);
964
965char *pcibios_setup(char *str);
966
967
968resource_size_t pcibios_align_resource(void *, const struct resource *,
969 resource_size_t,
970 resource_size_t);
971
972
973void pci_fixup_cardbus(struct pci_bus *);
974
975
976
977void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
978 struct resource *res);
979void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
980 struct pci_bus_region *region);
981void pcibios_scan_specific_bus(int busn);
982struct pci_bus *pci_find_bus(int domain, int busnr);
983void pci_bus_add_devices(const struct pci_bus *bus);
984struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
985struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
986 struct pci_ops *ops, void *sysdata,
987 struct list_head *resources);
988int pci_host_probe(struct pci_host_bridge *bridge);
989int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
990int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
991void pci_bus_release_busn_res(struct pci_bus *b);
992struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
993 struct pci_ops *ops, void *sysdata,
994 struct list_head *resources);
995int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
996struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
997 int busnr);
998void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
999struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1000 const char *name,
1001 struct hotplug_slot *hotplug);
1002void pci_destroy_slot(struct pci_slot *slot);
1003#ifdef CONFIG_SYSFS
1004void pci_dev_assign_slot(struct pci_dev *dev);
1005#else
1006static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1007#endif
1008int pci_scan_slot(struct pci_bus *bus, int devfn);
1009struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1010void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1011unsigned int pci_scan_child_bus(struct pci_bus *bus);
1012void pci_bus_add_device(struct pci_dev *dev);
1013void pci_read_bridge_bases(struct pci_bus *child);
1014struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1015 struct resource *res);
1016struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
1017u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1018int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1019u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1020struct pci_dev *pci_dev_get(struct pci_dev *dev);
1021void pci_dev_put(struct pci_dev *dev);
1022void pci_remove_bus(struct pci_bus *b);
1023void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1024void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1025void pci_stop_root_bus(struct pci_bus *bus);
1026void pci_remove_root_bus(struct pci_bus *bus);
1027void pci_setup_cardbus(struct pci_bus *bus);
1028void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1029void pci_sort_breadthfirst(void);
1030#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1031#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1032
1033
1034
1035enum pci_lost_interrupt_reason {
1036 PCI_LOST_IRQ_NO_INFORMATION = 0,
1037 PCI_LOST_IRQ_DISABLE_MSI,
1038 PCI_LOST_IRQ_DISABLE_MSIX,
1039 PCI_LOST_IRQ_DISABLE_ACPI,
1040};
1041enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
1042int pci_find_capability(struct pci_dev *dev, int cap);
1043int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1044int pci_find_ext_capability(struct pci_dev *dev, int cap);
1045int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1046int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1047int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1048struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1049
1050struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1051 struct pci_dev *from);
1052struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1053 unsigned int ss_vendor, unsigned int ss_device,
1054 struct pci_dev *from);
1055struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1056struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1057 unsigned int devfn);
1058struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1059int pci_dev_present(const struct pci_device_id *ids);
1060
1061int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1062 int where, u8 *val);
1063int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1064 int where, u16 *val);
1065int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1066 int where, u32 *val);
1067int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1068 int where, u8 val);
1069int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1070 int where, u16 val);
1071int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1072 int where, u32 val);
1073
1074int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1075 int where, int size, u32 *val);
1076int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1077 int where, int size, u32 val);
1078int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1079 int where, int size, u32 *val);
1080int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1081 int where, int size, u32 val);
1082
1083struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1084
1085int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1086int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1087int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1088int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1089int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1090int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1091
1092int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1093int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1094int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1095int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1096int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1097 u16 clear, u16 set);
1098int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1099 u32 clear, u32 set);
1100
1101static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1102 u16 set)
1103{
1104 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1105}
1106
1107static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1108 u32 set)
1109{
1110 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1111}
1112
1113static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1114 u16 clear)
1115{
1116 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1117}
1118
1119static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1120 u32 clear)
1121{
1122 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1123}
1124
1125
1126int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1127int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1128int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1129int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1130int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1131int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1132
1133int __must_check pci_enable_device(struct pci_dev *dev);
1134int __must_check pci_enable_device_io(struct pci_dev *dev);
1135int __must_check pci_enable_device_mem(struct pci_dev *dev);
1136int __must_check pci_reenable_device(struct pci_dev *);
1137int __must_check pcim_enable_device(struct pci_dev *pdev);
1138void pcim_pin_device(struct pci_dev *pdev);
1139
1140static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1141{
1142
1143
1144
1145
1146 return !pdev->broken_intx_masking;
1147}
1148
1149static inline int pci_is_enabled(struct pci_dev *pdev)
1150{
1151 return (atomic_read(&pdev->enable_cnt) > 0);
1152}
1153
1154static inline int pci_is_managed(struct pci_dev *pdev)
1155{
1156 return pdev->is_managed;
1157}
1158
1159void pci_disable_device(struct pci_dev *dev);
1160
1161extern unsigned int pcibios_max_latency;
1162void pci_set_master(struct pci_dev *dev);
1163void pci_clear_master(struct pci_dev *dev);
1164
1165int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1166int pci_set_cacheline_size(struct pci_dev *dev);
1167#define HAVE_PCI_SET_MWI
1168int __must_check pci_set_mwi(struct pci_dev *dev);
1169int __must_check pcim_set_mwi(struct pci_dev *dev);
1170int pci_try_set_mwi(struct pci_dev *dev);
1171void pci_clear_mwi(struct pci_dev *dev);
1172void pci_intx(struct pci_dev *dev, int enable);
1173bool pci_check_and_mask_intx(struct pci_dev *dev);
1174bool pci_check_and_unmask_intx(struct pci_dev *dev);
1175int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1176int pci_wait_for_pending_transaction(struct pci_dev *dev);
1177int pcix_get_max_mmrbc(struct pci_dev *dev);
1178int pcix_get_mmrbc(struct pci_dev *dev);
1179int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1180int pcie_get_readrq(struct pci_dev *dev);
1181int pcie_set_readrq(struct pci_dev *dev, int rq);
1182int pcie_get_mps(struct pci_dev *dev);
1183int pcie_set_mps(struct pci_dev *dev, int mps);
1184u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1185 enum pci_bus_speed *speed,
1186 enum pcie_link_width *width);
1187void pcie_print_link_status(struct pci_dev *dev);
1188bool pcie_has_flr(struct pci_dev *dev);
1189int pcie_flr(struct pci_dev *dev);
1190int __pci_reset_function_locked(struct pci_dev *dev);
1191int pci_reset_function(struct pci_dev *dev);
1192int pci_reset_function_locked(struct pci_dev *dev);
1193int pci_try_reset_function(struct pci_dev *dev);
1194int pci_probe_reset_slot(struct pci_slot *slot);
1195int pci_probe_reset_bus(struct pci_bus *bus);
1196int pci_reset_bus(struct pci_dev *dev);
1197void pci_reset_secondary_bus(struct pci_dev *dev);
1198void pcibios_reset_secondary_bus(struct pci_dev *dev);
1199void pci_update_resource(struct pci_dev *dev, int resno);
1200int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1201int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1202void pci_release_resource(struct pci_dev *dev, int resno);
1203int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1204int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1205bool pci_device_is_present(struct pci_dev *pdev);
1206void pci_ignore_hotplug(struct pci_dev *dev);
1207
1208int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1209 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1210 const char *fmt, ...);
1211void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1212
1213
1214int pci_enable_rom(struct pci_dev *pdev);
1215void pci_disable_rom(struct pci_dev *pdev);
1216void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1217void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1218void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1219
1220
1221int pci_save_state(struct pci_dev *dev);
1222void pci_restore_state(struct pci_dev *dev);
1223struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1224int pci_load_saved_state(struct pci_dev *dev,
1225 struct pci_saved_state *state);
1226int pci_load_and_free_saved_state(struct pci_dev *dev,
1227 struct pci_saved_state **state);
1228struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1229struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1230 u16 cap);
1231int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1232int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1233 u16 cap, unsigned int size);
1234int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1235int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1236pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1237bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1238void pci_pme_active(struct pci_dev *dev, bool enable);
1239int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1240int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1241int pci_prepare_to_sleep(struct pci_dev *dev);
1242int pci_back_from_sleep(struct pci_dev *dev);
1243bool pci_dev_run_wake(struct pci_dev *dev);
1244bool pci_check_pme_status(struct pci_dev *dev);
1245void pci_pme_wakeup_bus(struct pci_bus *bus);
1246void pci_d3cold_enable(struct pci_dev *dev);
1247void pci_d3cold_disable(struct pci_dev *dev);
1248bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1249void pci_wakeup_bus(struct pci_bus *bus);
1250void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1251
1252
1253int pci_save_vc_state(struct pci_dev *dev);
1254void pci_restore_vc_state(struct pci_dev *dev);
1255void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1256
1257
1258void set_pcie_port_type(struct pci_dev *pdev);
1259void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1260
1261
1262int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1263unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1264unsigned int pci_rescan_bus(struct pci_bus *bus);
1265void pci_lock_rescan_remove(void);
1266void pci_unlock_rescan_remove(void);
1267
1268
1269ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1270ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1271int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1272
1273
1274resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1275void pci_bus_assign_resources(const struct pci_bus *bus);
1276void pci_bus_claim_resources(struct pci_bus *bus);
1277void pci_bus_size_bridges(struct pci_bus *bus);
1278int pci_claim_resource(struct pci_dev *, int);
1279int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1280void pci_assign_unassigned_resources(void);
1281void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1282void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1283void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1284int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1285void pdev_enable_device(struct pci_dev *);
1286int pci_enable_resources(struct pci_dev *, int mask);
1287void pci_assign_irq(struct pci_dev *dev);
1288struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1289#define HAVE_PCI_REQ_REGIONS 2
1290int __must_check pci_request_regions(struct pci_dev *, const char *);
1291int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1292void pci_release_regions(struct pci_dev *);
1293int __must_check pci_request_region(struct pci_dev *, int, const char *);
1294void pci_release_region(struct pci_dev *, int);
1295int pci_request_selected_regions(struct pci_dev *, int, const char *);
1296int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1297void pci_release_selected_regions(struct pci_dev *, int);
1298
1299
1300struct pci_bus *pci_bus_get(struct pci_bus *bus);
1301void pci_bus_put(struct pci_bus *bus);
1302void pci_add_resource(struct list_head *resources, struct resource *res);
1303void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1304 resource_size_t offset);
1305void pci_free_resource_list(struct list_head *resources);
1306void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1307 unsigned int flags);
1308struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1309void pci_bus_remove_resources(struct pci_bus *bus);
1310int devm_request_pci_bus_resources(struct device *dev,
1311 struct list_head *resources);
1312
1313
1314int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1315
1316#define pci_bus_for_each_resource(bus, res, i) \
1317 for (i = 0; \
1318 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1319 i++)
1320
1321int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1322 struct resource *res, resource_size_t size,
1323 resource_size_t align, resource_size_t min,
1324 unsigned long type_mask,
1325 resource_size_t (*alignf)(void *,
1326 const struct resource *,
1327 resource_size_t,
1328 resource_size_t),
1329 void *alignf_data);
1330
1331
1332int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1333 resource_size_t size);
1334unsigned long pci_address_to_pio(phys_addr_t addr);
1335phys_addr_t pci_pio_to_address(unsigned long pio);
1336int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1337int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1338 phys_addr_t phys_addr);
1339void pci_unmap_iospace(struct resource *res);
1340void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1341 resource_size_t offset,
1342 resource_size_t size);
1343void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1344 struct resource *res);
1345
1346static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1347{
1348 struct pci_bus_region region;
1349
1350 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1351 return region.start;
1352}
1353
1354
1355int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1356 const char *mod_name);
1357
1358
1359#define pci_register_driver(driver) \
1360 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1361
1362void pci_unregister_driver(struct pci_driver *dev);
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372#define module_pci_driver(__pci_driver) \
1373 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383#define builtin_pci_driver(__pci_driver) \
1384 builtin_driver(__pci_driver, pci_register_driver)
1385
1386struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1387int pci_add_dynid(struct pci_driver *drv,
1388 unsigned int vendor, unsigned int device,
1389 unsigned int subvendor, unsigned int subdevice,
1390 unsigned int class, unsigned int class_mask,
1391 unsigned long driver_data);
1392const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1393 struct pci_dev *dev);
1394int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1395 int pass);
1396
1397void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1398 void *userdata);
1399int pci_cfg_space_size(struct pci_dev *dev);
1400unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1401void pci_setup_bridge(struct pci_bus *bus);
1402resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1403 unsigned long type);
1404
1405#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1406#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1407
1408int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1409 unsigned int command_bits, u32 flags);
1410
1411#define PCI_IRQ_LEGACY (1 << 0)
1412#define PCI_IRQ_MSI (1 << 1)
1413#define PCI_IRQ_MSIX (1 << 2)
1414#define PCI_IRQ_AFFINITY (1 << 3)
1415
1416
1417
1418
1419
1420
1421
1422#define PCI_IRQ_VIRTUAL (1 << 4)
1423
1424#define PCI_IRQ_ALL_TYPES \
1425 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1426
1427
1428
1429#include <linux/dmapool.h>
1430
1431#define pci_pool dma_pool
1432#define pci_pool_create(name, pdev, size, align, allocation) \
1433 dma_pool_create(name, &pdev->dev, size, align, allocation)
1434#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1435#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1436#define pci_pool_zalloc(pool, flags, handle) \
1437 dma_pool_zalloc(pool, flags, handle)
1438#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1439
1440struct msix_entry {
1441 u32 vector;
1442 u16 entry;
1443};
1444
1445#ifdef CONFIG_PCI_MSI
1446int pci_msi_vec_count(struct pci_dev *dev);
1447void pci_disable_msi(struct pci_dev *dev);
1448int pci_msix_vec_count(struct pci_dev *dev);
1449void pci_disable_msix(struct pci_dev *dev);
1450void pci_restore_msi_state(struct pci_dev *dev);
1451int pci_msi_enabled(void);
1452int pci_enable_msi(struct pci_dev *dev);
1453int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1454 int minvec, int maxvec);
1455static inline int pci_enable_msix_exact(struct pci_dev *dev,
1456 struct msix_entry *entries, int nvec)
1457{
1458 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1459 if (rc < 0)
1460 return rc;
1461 return 0;
1462}
1463int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1464 unsigned int max_vecs, unsigned int flags,
1465 struct irq_affinity *affd);
1466
1467void pci_free_irq_vectors(struct pci_dev *dev);
1468int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1469const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1470int pci_irq_get_node(struct pci_dev *pdev, int vec);
1471
1472#else
1473static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1474static inline void pci_disable_msi(struct pci_dev *dev) { }
1475static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1476static inline void pci_disable_msix(struct pci_dev *dev) { }
1477static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1478static inline int pci_msi_enabled(void) { return 0; }
1479static inline int pci_enable_msi(struct pci_dev *dev)
1480{ return -ENOSYS; }
1481static inline int pci_enable_msix_range(struct pci_dev *dev,
1482 struct msix_entry *entries, int minvec, int maxvec)
1483{ return -ENOSYS; }
1484static inline int pci_enable_msix_exact(struct pci_dev *dev,
1485 struct msix_entry *entries, int nvec)
1486{ return -ENOSYS; }
1487
1488static inline int
1489pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1490 unsigned int max_vecs, unsigned int flags,
1491 struct irq_affinity *aff_desc)
1492{
1493 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1494 return 1;
1495 return -ENOSPC;
1496}
1497
1498static inline void pci_free_irq_vectors(struct pci_dev *dev)
1499{
1500}
1501
1502static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1503{
1504 if (WARN_ON_ONCE(nr > 0))
1505 return -EINVAL;
1506 return dev->irq;
1507}
1508static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1509 int vec)
1510{
1511 return cpu_possible_mask;
1512}
1513
1514static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1515{
1516 return first_online_node;
1517}
1518#endif
1519
1520static inline int
1521pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1522 unsigned int max_vecs, unsigned int flags)
1523{
1524 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1525 NULL);
1526}
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1545 struct device_node *node,
1546 const u32 *intspec,
1547 unsigned int intsize,
1548 unsigned long *out_hwirq,
1549 unsigned int *out_type)
1550{
1551 const u32 intx = intspec[0];
1552
1553 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1554 return -EINVAL;
1555
1556 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1557 return 0;
1558}
1559
1560#ifdef CONFIG_PCIEPORTBUS
1561extern bool pcie_ports_disabled;
1562extern bool pcie_ports_native;
1563#else
1564#define pcie_ports_disabled true
1565#define pcie_ports_native false
1566#endif
1567
1568#ifdef CONFIG_PCIEASPM
1569bool pcie_aspm_support_enabled(void);
1570bool pcie_aspm_enabled(struct pci_dev *pdev);
1571#else
1572static inline bool pcie_aspm_support_enabled(void) { return false; }
1573static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1574#endif
1575
1576#ifdef CONFIG_PCIEAER
1577bool pci_aer_available(void);
1578#else
1579static inline bool pci_aer_available(void) { return false; }
1580#endif
1581
1582#ifdef CONFIG_PCIE_ECRC
1583void pcie_set_ecrc_checking(struct pci_dev *dev);
1584void pcie_ecrc_get_policy(char *str);
1585#else
1586static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1587static inline void pcie_ecrc_get_policy(char *str) { }
1588#endif
1589
1590bool pci_ats_disabled(void);
1591
1592#ifdef CONFIG_PCIE_PTM
1593int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1594#else
1595static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1596{ return -EINVAL; }
1597#endif
1598
1599void pci_cfg_access_lock(struct pci_dev *dev);
1600bool pci_cfg_access_trylock(struct pci_dev *dev);
1601void pci_cfg_access_unlock(struct pci_dev *dev);
1602
1603
1604
1605
1606
1607
1608#ifdef CONFIG_PCI_DOMAINS
1609extern int pci_domains_supported;
1610#else
1611enum { pci_domains_supported = 0 };
1612static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1613static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1614#endif
1615
1616
1617
1618
1619
1620
1621#ifdef CONFIG_PCI_DOMAINS_GENERIC
1622static inline int pci_domain_nr(struct pci_bus *bus)
1623{
1624 return bus->domain_nr;
1625}
1626#ifdef CONFIG_ACPI
1627int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1628#else
1629static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1630{ return 0; }
1631#endif
1632int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1633#endif
1634
1635
1636typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1637 unsigned int command_bits, u32 flags);
1638void pci_register_set_vga_state(arch_set_vga_state_t func);
1639
1640static inline int
1641pci_request_io_regions(struct pci_dev *pdev, const char *name)
1642{
1643 return pci_request_selected_regions(pdev,
1644 pci_select_bars(pdev, IORESOURCE_IO), name);
1645}
1646
1647static inline void
1648pci_release_io_regions(struct pci_dev *pdev)
1649{
1650 return pci_release_selected_regions(pdev,
1651 pci_select_bars(pdev, IORESOURCE_IO));
1652}
1653
1654static inline int
1655pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1656{
1657 return pci_request_selected_regions(pdev,
1658 pci_select_bars(pdev, IORESOURCE_MEM), name);
1659}
1660
1661static inline void
1662pci_release_mem_regions(struct pci_dev *pdev)
1663{
1664 return pci_release_selected_regions(pdev,
1665 pci_select_bars(pdev, IORESOURCE_MEM));
1666}
1667
1668#else
1669
1670static inline void pci_set_flags(int flags) { }
1671static inline void pci_add_flags(int flags) { }
1672static inline void pci_clear_flags(int flags) { }
1673static inline int pci_has_flag(int flag) { return 0; }
1674
1675
1676
1677
1678
1679#define _PCI_NOP(o, s, t) \
1680 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1681 int where, t val) \
1682 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1683
1684#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1685 _PCI_NOP(o, word, u16 x) \
1686 _PCI_NOP(o, dword, u32 x)
1687_PCI_NOP_ALL(read, *)
1688_PCI_NOP_ALL(write,)
1689
1690static inline struct pci_dev *pci_get_device(unsigned int vendor,
1691 unsigned int device,
1692 struct pci_dev *from)
1693{ return NULL; }
1694
1695static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1696 unsigned int device,
1697 unsigned int ss_vendor,
1698 unsigned int ss_device,
1699 struct pci_dev *from)
1700{ return NULL; }
1701
1702static inline struct pci_dev *pci_get_class(unsigned int class,
1703 struct pci_dev *from)
1704{ return NULL; }
1705
1706#define pci_dev_present(ids) (0)
1707#define no_pci_devices() (1)
1708#define pci_dev_put(dev) do { } while (0)
1709
1710static inline void pci_set_master(struct pci_dev *dev) { }
1711static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1712static inline void pci_disable_device(struct pci_dev *dev) { }
1713static inline int pci_assign_resource(struct pci_dev *dev, int i)
1714{ return -EBUSY; }
1715static inline int __pci_register_driver(struct pci_driver *drv,
1716 struct module *owner)
1717{ return 0; }
1718static inline int pci_register_driver(struct pci_driver *drv)
1719{ return 0; }
1720static inline void pci_unregister_driver(struct pci_driver *drv) { }
1721static inline int pci_find_capability(struct pci_dev *dev, int cap)
1722{ return 0; }
1723static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1724 int cap)
1725{ return 0; }
1726static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1727{ return 0; }
1728
1729
1730static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1731static inline void pci_restore_state(struct pci_dev *dev) { }
1732static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1733{ return 0; }
1734static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1735{ return 0; }
1736static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1737 pm_message_t state)
1738{ return PCI_D0; }
1739static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1740 int enable)
1741{ return 0; }
1742
1743static inline struct resource *pci_find_resource(struct pci_dev *dev,
1744 struct resource *res)
1745{ return NULL; }
1746static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1747{ return -EIO; }
1748static inline void pci_release_regions(struct pci_dev *dev) { }
1749
1750static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1751
1752static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1753static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1754{ return 0; }
1755static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1756
1757static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1758{ return NULL; }
1759static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1760 unsigned int devfn)
1761{ return NULL; }
1762static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1763 unsigned int bus, unsigned int devfn)
1764{ return NULL; }
1765
1766static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1767static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1768
1769#define dev_is_pci(d) (false)
1770#define dev_is_pf(d) (false)
1771static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1772{ return false; }
1773static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1774 struct device_node *node,
1775 const u32 *intspec,
1776 unsigned int intsize,
1777 unsigned long *out_hwirq,
1778 unsigned int *out_type)
1779{ return -EINVAL; }
1780
1781static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1782 struct pci_dev *dev)
1783{ return NULL; }
1784static inline bool pci_ats_disabled(void) { return true; }
1785#endif
1786
1787#ifdef CONFIG_PCI_ATS
1788
1789void pci_ats_init(struct pci_dev *dev);
1790int pci_enable_ats(struct pci_dev *dev, int ps);
1791void pci_disable_ats(struct pci_dev *dev);
1792int pci_ats_queue_depth(struct pci_dev *dev);
1793int pci_ats_page_aligned(struct pci_dev *dev);
1794#else
1795static inline void pci_ats_init(struct pci_dev *d) { }
1796static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1797static inline void pci_disable_ats(struct pci_dev *d) { }
1798static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1799static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; }
1800#endif
1801
1802
1803
1804#include <asm/pci.h>
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1819 struct vm_area_struct *vma,
1820 enum pci_mmap_state mmap_state, int write_combine);
1821int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1822 struct vm_area_struct *vma,
1823 enum pci_mmap_state mmap_state, int write_combine);
1824
1825#ifndef arch_can_pci_mmap_wc
1826#define arch_can_pci_mmap_wc() 0
1827#endif
1828
1829#ifndef arch_can_pci_mmap_io
1830#define arch_can_pci_mmap_io() 0
1831#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1832#else
1833int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1834#endif
1835
1836#ifndef pci_root_bus_fwnode
1837#define pci_root_bus_fwnode(bus) NULL
1838#endif
1839
1840
1841
1842
1843
1844#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1845#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1846#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1847#define pci_resource_len(dev,bar) \
1848 ((pci_resource_start((dev), (bar)) == 0 && \
1849 pci_resource_end((dev), (bar)) == \
1850 pci_resource_start((dev), (bar))) ? 0 : \
1851 \
1852 (pci_resource_end((dev), (bar)) - \
1853 pci_resource_start((dev), (bar)) + 1))
1854
1855
1856
1857
1858
1859
1860static inline void *pci_get_drvdata(struct pci_dev *pdev)
1861{
1862 return dev_get_drvdata(&pdev->dev);
1863}
1864
1865static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1866{
1867 dev_set_drvdata(&pdev->dev, data);
1868}
1869
1870static inline const char *pci_name(const struct pci_dev *pdev)
1871{
1872 return dev_name(&pdev->dev);
1873}
1874
1875
1876
1877
1878
1879
1880#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1881void pci_resource_to_user(const struct pci_dev *dev, int bar,
1882 const struct resource *rsrc,
1883 resource_size_t *start, resource_size_t *end);
1884#else
1885static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1886 const struct resource *rsrc, resource_size_t *start,
1887 resource_size_t *end)
1888{
1889 *start = rsrc->start;
1890 *end = rsrc->end;
1891}
1892#endif
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902struct pci_fixup {
1903 u16 vendor;
1904 u16 device;
1905 u32 class;
1906 unsigned int class_shift;
1907#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1908 int hook_offset;
1909#else
1910 void (*hook)(struct pci_dev *dev);
1911#endif
1912};
1913
1914enum pci_fixup_pass {
1915 pci_fixup_early,
1916 pci_fixup_header,
1917 pci_fixup_final,
1918 pci_fixup_enable,
1919 pci_fixup_resume,
1920 pci_fixup_suspend,
1921 pci_fixup_resume_early,
1922 pci_fixup_suspend_late,
1923};
1924
1925#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1926#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1927 class_shift, hook) \
1928 __ADDRESSABLE(hook) \
1929 asm(".section " #sec ", \"a\" \n" \
1930 ".balign 16 \n" \
1931 ".short " #vendor ", " #device " \n" \
1932 ".long " #class ", " #class_shift " \n" \
1933 ".long " #hook " - . \n" \
1934 ".previous \n");
1935#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1936 class_shift, hook) \
1937 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1938 class_shift, hook)
1939#else
1940
1941#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1942 class_shift, hook) \
1943 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1944 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1945 = { vendor, device, class, class_shift, hook };
1946#endif
1947
1948#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1949 class_shift, hook) \
1950 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1951 hook, vendor, device, class, class_shift, hook)
1952#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1953 class_shift, hook) \
1954 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1955 hook, vendor, device, class, class_shift, hook)
1956#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1957 class_shift, hook) \
1958 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1959 hook, vendor, device, class, class_shift, hook)
1960#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1961 class_shift, hook) \
1962 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1963 hook, vendor, device, class, class_shift, hook)
1964#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1965 class_shift, hook) \
1966 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1967 resume##hook, vendor, device, class, class_shift, hook)
1968#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1969 class_shift, hook) \
1970 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1971 resume_early##hook, vendor, device, class, class_shift, hook)
1972#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1973 class_shift, hook) \
1974 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1975 suspend##hook, vendor, device, class, class_shift, hook)
1976#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1977 class_shift, hook) \
1978 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1979 suspend_late##hook, vendor, device, class, class_shift, hook)
1980
1981#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1982 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1983 hook, vendor, device, PCI_ANY_ID, 0, hook)
1984#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1985 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1986 hook, vendor, device, PCI_ANY_ID, 0, hook)
1987#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1988 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1989 hook, vendor, device, PCI_ANY_ID, 0, hook)
1990#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1991 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1992 hook, vendor, device, PCI_ANY_ID, 0, hook)
1993#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1994 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1995 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1996#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1997 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1998 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1999#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2000 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2001 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2002#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2003 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2004 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2005
2006#ifdef CONFIG_PCI_QUIRKS
2007void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2008#else
2009static inline void pci_fixup_device(enum pci_fixup_pass pass,
2010 struct pci_dev *dev) { }
2011#endif
2012
2013void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2014void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2015void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2016int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2017int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2018 const char *name);
2019void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2020
2021extern int pci_pci_problems;
2022#define PCIPCI_FAIL 1
2023#define PCIPCI_TRITON 2
2024#define PCIPCI_NATOMA 4
2025#define PCIPCI_VIAETBF 8
2026#define PCIPCI_VSFX 16
2027#define PCIPCI_ALIMAGIK 32
2028#define PCIAGP_FAIL 64
2029
2030extern unsigned long pci_cardbus_io_size;
2031extern unsigned long pci_cardbus_mem_size;
2032extern u8 pci_dfl_cache_line_size;
2033extern u8 pci_cache_line_size;
2034
2035extern unsigned long pci_hotplug_io_size;
2036extern unsigned long pci_hotplug_mem_size;
2037extern unsigned long pci_hotplug_bus_size;
2038
2039
2040void pcibios_disable_device(struct pci_dev *dev);
2041void pcibios_set_master(struct pci_dev *dev);
2042int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2043 enum pcie_reset_state state);
2044int pcibios_add_device(struct pci_dev *dev);
2045void pcibios_release_device(struct pci_dev *dev);
2046#ifdef CONFIG_PCI
2047void pcibios_penalize_isa_irq(int irq, int active);
2048#else
2049static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2050#endif
2051int pcibios_alloc_irq(struct pci_dev *dev);
2052void pcibios_free_irq(struct pci_dev *dev);
2053resource_size_t pcibios_default_alignment(void);
2054
2055#ifdef CONFIG_HIBERNATE_CALLBACKS
2056extern struct dev_pm_ops pcibios_pm_ops;
2057#endif
2058
2059#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2060void __init pci_mmcfg_early_init(void);
2061void __init pci_mmcfg_late_init(void);
2062#else
2063static inline void pci_mmcfg_early_init(void) { }
2064static inline void pci_mmcfg_late_init(void) { }
2065#endif
2066
2067int pci_ext_cfg_avail(void);
2068
2069void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2070void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2071
2072#ifdef CONFIG_PCI_IOV
2073int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2074int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2075
2076int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2077void pci_disable_sriov(struct pci_dev *dev);
2078int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2079void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2080int pci_num_vf(struct pci_dev *dev);
2081int pci_vfs_assigned(struct pci_dev *dev);
2082int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2083int pci_sriov_get_totalvfs(struct pci_dev *dev);
2084int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2085resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2086void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2087
2088
2089int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2090int pcibios_sriov_disable(struct pci_dev *pdev);
2091resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2092#else
2093static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2094{
2095 return -ENOSYS;
2096}
2097static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2098{
2099 return -ENOSYS;
2100}
2101static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2102{ return -ENODEV; }
2103static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2104{
2105 return -ENOSYS;
2106}
2107static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2108 int id) { }
2109static inline void pci_disable_sriov(struct pci_dev *dev) { }
2110static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2111static inline int pci_vfs_assigned(struct pci_dev *dev)
2112{ return 0; }
2113static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2114{ return 0; }
2115static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2116{ return 0; }
2117#define pci_sriov_configure_simple NULL
2118static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2119{ return 0; }
2120static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2121#endif
2122
2123#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2124void pci_hp_create_module_link(struct pci_slot *pci_slot);
2125void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2126#endif
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139static inline int pci_pcie_cap(struct pci_dev *dev)
2140{
2141 return dev->pcie_cap;
2142}
2143
2144
2145
2146
2147
2148
2149
2150static inline bool pci_is_pcie(struct pci_dev *dev)
2151{
2152 return pci_pcie_cap(dev);
2153}
2154
2155
2156
2157
2158
2159static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2160{
2161 return dev->pcie_flags_reg;
2162}
2163
2164
2165
2166
2167
2168static inline int pci_pcie_type(const struct pci_dev *dev)
2169{
2170 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2171}
2172
2173static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2174{
2175 while (1) {
2176 if (!pci_is_pcie(dev))
2177 break;
2178 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2179 return dev;
2180 if (!dev->bus->self)
2181 break;
2182 dev = dev->bus->self;
2183 }
2184 return NULL;
2185}
2186
2187void pci_request_acs(void);
2188bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2189bool pci_acs_path_enabled(struct pci_dev *start,
2190 struct pci_dev *end, u16 acs_flags);
2191int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2192
2193#define PCI_VPD_LRDT 0x80
2194#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2195
2196
2197#define PCI_VPD_LTIN_ID_STRING 0x02
2198#define PCI_VPD_LTIN_RO_DATA 0x10
2199#define PCI_VPD_LTIN_RW_DATA 0x11
2200
2201#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2202#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2203#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2204
2205
2206#define PCI_VPD_STIN_END 0x0f
2207
2208#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2209
2210#define PCI_VPD_SRDT_TIN_MASK 0x78
2211#define PCI_VPD_SRDT_LEN_MASK 0x07
2212#define PCI_VPD_LRDT_TIN_MASK 0x7f
2213
2214#define PCI_VPD_LRDT_TAG_SIZE 3
2215#define PCI_VPD_SRDT_TAG_SIZE 1
2216
2217#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2218
2219#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2220#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2221#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2222#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2223
2224
2225
2226
2227
2228
2229
2230static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2231{
2232 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2233}
2234
2235
2236
2237
2238
2239
2240
2241static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2242{
2243 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2244}
2245
2246
2247
2248
2249
2250
2251
2252static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2253{
2254 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2255}
2256
2257
2258
2259
2260
2261
2262
2263static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2264{
2265 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2266}
2267
2268
2269
2270
2271
2272
2273
2274static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2275{
2276 return info_field[2];
2277}
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2302 unsigned int len, const char *kw);
2303
2304
2305#ifdef CONFIG_OF
2306struct device_node;
2307struct irq_domain;
2308void pci_set_of_node(struct pci_dev *dev);
2309void pci_release_of_node(struct pci_dev *dev);
2310void pci_set_bus_of_node(struct pci_bus *bus);
2311void pci_release_bus_of_node(struct pci_bus *bus);
2312struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2313int pci_parse_request_of_pci_ranges(struct device *dev,
2314 struct list_head *resources,
2315 struct resource **bus_range);
2316
2317
2318struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2319
2320#else
2321static inline void pci_set_of_node(struct pci_dev *dev) { }
2322static inline void pci_release_of_node(struct pci_dev *dev) { }
2323static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2324static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2325static inline struct irq_domain *
2326pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2327static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2328 struct list_head *resources,
2329 struct resource **bus_range)
2330{
2331 return -EINVAL;
2332}
2333#endif
2334
2335static inline struct device_node *
2336pci_device_to_OF_node(const struct pci_dev *pdev)
2337{
2338 return pdev ? pdev->dev.of_node : NULL;
2339}
2340
2341static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2342{
2343 return bus ? bus->dev.of_node : NULL;
2344}
2345
2346#ifdef CONFIG_ACPI
2347struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2348
2349void
2350pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2351#else
2352static inline struct irq_domain *
2353pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2354#endif
2355
2356#ifdef CONFIG_EEH
2357static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2358{
2359 return pdev->dev.archdata.edev;
2360}
2361#endif
2362
2363void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2364bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2365int pci_for_each_dma_alias(struct pci_dev *pdev,
2366 int (*fn)(struct pci_dev *pdev,
2367 u16 alias, void *data), void *data);
2368
2369
2370static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2371{
2372 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2373}
2374static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2375{
2376 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2377}
2378static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2379{
2380 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2381}
2382
2383
2384
2385
2386
2387
2388
2389static inline bool pci_ari_enabled(struct pci_bus *bus)
2390{
2391 return bus->self && bus->self->ari_enabled;
2392}
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2403{
2404 struct pci_dev *parent = pdev;
2405
2406 if (pdev->is_thunderbolt)
2407 return true;
2408
2409 while ((parent = pci_upstream_bridge(parent)))
2410 if (parent->is_thunderbolt)
2411 return true;
2412
2413 return false;
2414}
2415
2416#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2417void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2418#endif
2419
2420
2421#include <linux/pci-dma-compat.h>
2422
2423#define pci_printk(level, pdev, fmt, arg...) \
2424 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2425
2426#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2427#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2428#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2429#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2430#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2431#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2432#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2433#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2434
2435#define pci_notice_ratelimited(pdev, fmt, arg...) \
2436 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2437
2438#endif
2439