LXR linux/include/linux/platform

   1#ifndef __TI_SYSC_DATA_H__
   2#define __TI_SYSC_DATA_H__
   3
   4enum ti_sysc_module_type {
   5        TI_SYSC_OMAP2,
   6        TI_SYSC_OMAP2_TIMER,
   7        TI_SYSC_OMAP3_SHAM,
   8        TI_SYSC_OMAP3_AES,
   9        TI_SYSC_OMAP4,
  10        TI_SYSC_OMAP4_TIMER,
  11        TI_SYSC_OMAP4_SIMPLE,
  12        TI_SYSC_OMAP34XX_SR,
  13        TI_SYSC_OMAP36XX_SR,
  14        TI_SYSC_OMAP4_SR,
  15        TI_SYSC_OMAP4_MCASP,
  16        TI_SYSC_OMAP4_USB_HOST_FS,
  17        TI_SYSC_DRA7_MCAN,
  18};
  19
  20struct ti_sysc_cookie {
  21        void *data;
  22        void *clkdm;
  23};
  24
  25/**
  26 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
  27 * @midle_shift: Offset of the midle bit
  28 * @clkact_shift: Offset of the clockactivity bit
  29 * @sidle_shift: Offset of the sidle bit
  30 * @enwkup_shift: Offset of the enawakeup bit
  31 * @srst_shift: Offset of the softreset bit
  32 * @autoidle_shift: Offset of the autoidle bit
  33 * @dmadisable_shift: Offset of the dmadisable bit
  34 * @emufree_shift; Offset of the emufree bit
  35 *
  36 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a
  37 * feature is not available.
  38 */
  39struct sysc_regbits {
  40        s8 midle_shift;
  41        s8 clkact_shift;
  42        s8 sidle_shift;
  43        s8 enwkup_shift;
  44        s8 srst_shift;
  45        s8 autoidle_shift;
  46        s8 dmadisable_shift;
  47        s8 emufree_shift;
  48};
  49
  50#define SYSC_MODULE_QUIRK_HDQ1W         BIT(17)
  51#define SYSC_MODULE_QUIRK_I2C           BIT(16)
  52#define SYSC_MODULE_QUIRK_WDT           BIT(15)
  53#define SYSS_QUIRK_RESETDONE_INVERTED   BIT(14)
  54#define SYSC_QUIRK_SWSUP_MSTANDBY       BIT(13)
  55#define SYSC_QUIRK_SWSUP_SIDLE_ACT      BIT(12)
  56#define SYSC_QUIRK_SWSUP_SIDLE          BIT(11)
  57#define SYSC_QUIRK_EXT_OPT_CLOCK        BIT(10)
  58#define SYSC_QUIRK_LEGACY_IDLE          BIT(9)
  59#define SYSC_QUIRK_RESET_STATUS         BIT(8)
  60#define SYSC_QUIRK_NO_IDLE              BIT(7)
  61#define SYSC_QUIRK_NO_IDLE_ON_INIT      BIT(6)
  62#define SYSC_QUIRK_NO_RESET_ON_INIT     BIT(5)
  63#define SYSC_QUIRK_OPT_CLKS_NEEDED      BIT(4)
  64#define SYSC_QUIRK_OPT_CLKS_IN_RESET    BIT(3)
  65#define SYSC_QUIRK_16BIT                BIT(2)
  66#define SYSC_QUIRK_UNCACHED             BIT(1)
  67#define SYSC_QUIRK_USE_CLOCKACT         BIT(0)
  68
  69#define SYSC_NR_IDLEMODES               4
  70
  71/**
  72 * struct sysc_capabilities - capabilities for an interconnect target module
  73 *
  74 * @sysc_mask: bitmask of supported SYSCONFIG register bits
  75 * @regbits: bitmask of SYSCONFIG register bits
  76 * @mod_quirks: bitmask of module specific quirks
  77 */
  78struct sysc_capabilities {
  79        const enum ti_sysc_module_type type;
  80        const u32 sysc_mask;
  81        const struct sysc_regbits *regbits;
  82        const u32 mod_quirks;
  83};
  84
  85/**
  86 * struct sysc_config - configuration for an interconnect target module
  87 * @sysc_val: configured value for sysc register
  88 * @midlemodes: bitmask of supported master idle modes
  89 * @sidlemodes: bitmask of supported master idle modes
  90 * @srst_udelay: optional delay needed after OCP soft reset
  91 * @quirks: bitmask of enabled quirks
  92 */
  93struct sysc_config {
  94        u32 sysc_val;
  95        u32 syss_mask;
  96        u8 midlemodes;
  97        u8 sidlemodes;
  98        u8 srst_udelay;
  99        u32 quirks;
 100};
 101
 102enum sysc_registers {
 103        SYSC_REVISION,
 104        SYSC_SYSCONFIG,
 105        SYSC_SYSSTATUS,
 106        SYSC_MAX_REGS,
 107};
 108
 109/**
 110 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module
 111 * @name: legacy "ti,hwmods" module name
 112 * @module_pa: physical address of the interconnect target module
 113 * @module_size: size of the interconnect target module
 114 * @offsets: array of register offsets as listed in enum sysc_registers
 115 * @nr_offsets: number of registers
 116 * @cap: interconnect target module capabilities
 117 * @cfg: interconnect target module configuration
 118 *
 119 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig
 120 * based on device tree data parsed by ti-sysc driver.
 121 */
 122struct ti_sysc_module_data {
 123        const char *name;
 124        u64 module_pa;
 125        u32 module_size;
 126        int *offsets;
 127        int nr_offsets;
 128        const struct sysc_capabilities *cap;
 129        struct sysc_config *cfg;
 130};
 131
 132struct device;
 133struct clk;
 134
 135struct ti_sysc_platform_data {
 136        struct of_dev_auxdata *auxdata;
 137        int (*init_clockdomain)(struct device *dev, struct clk *fck,
 138                                struct clk *ick, struct ti_sysc_cookie *cookie);
 139        void (*clkdm_deny_idle)(struct device *dev,
 140                                const struct ti_sysc_cookie *cookie);
 141        void (*clkdm_allow_idle)(struct device *dev,
 142                                 const struct ti_sysc_cookie *cookie);
 143        int (*init_module)(struct device *dev,
 144                           const struct ti_sysc_module_data *data,
 145                           struct ti_sysc_cookie *cookie);
 146        int (*enable_module)(struct device *dev,
 147                             const struct ti_sysc_cookie *cookie);
 148        int (*idle_module)(struct device *dev,
 149                           const struct ti_sysc_cookie *cookie);
 150        int (*shutdown_module)(struct device *dev,
 151                               const struct ti_sysc_cookie *cookie);
 152};
 153
 154#endif  /* __TI_SYSC_DATA_H__ */
 155