linux/include/soc/tegra/mc.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2014 NVIDIA Corporation
   4 */
   5
   6#ifndef __SOC_TEGRA_MC_H__
   7#define __SOC_TEGRA_MC_H__
   8
   9#include <linux/err.h>
  10#include <linux/reset-controller.h>
  11#include <linux/types.h>
  12
  13struct clk;
  14struct device;
  15struct page;
  16
  17struct tegra_smmu_enable {
  18        unsigned int reg;
  19        unsigned int bit;
  20};
  21
  22struct tegra_mc_timing {
  23        unsigned long rate;
  24
  25        u32 *emem_data;
  26};
  27
  28/* latency allowance */
  29struct tegra_mc_la {
  30        unsigned int reg;
  31        unsigned int shift;
  32        unsigned int mask;
  33        unsigned int def;
  34};
  35
  36struct tegra_mc_client {
  37        unsigned int id;
  38        const char *name;
  39        unsigned int swgroup;
  40
  41        unsigned int fifo_size;
  42
  43        struct tegra_smmu_enable smmu;
  44        struct tegra_mc_la la;
  45};
  46
  47struct tegra_smmu_swgroup {
  48        const char *name;
  49        unsigned int swgroup;
  50        unsigned int reg;
  51};
  52
  53struct tegra_smmu_group_soc {
  54        const char *name;
  55        const unsigned int *swgroups;
  56        unsigned int num_swgroups;
  57};
  58
  59struct tegra_smmu_soc {
  60        const struct tegra_mc_client *clients;
  61        unsigned int num_clients;
  62
  63        const struct tegra_smmu_swgroup *swgroups;
  64        unsigned int num_swgroups;
  65
  66        const struct tegra_smmu_group_soc *groups;
  67        unsigned int num_groups;
  68
  69        bool supports_round_robin_arbitration;
  70        bool supports_request_limit;
  71
  72        unsigned int num_tlb_lines;
  73        unsigned int num_asids;
  74};
  75
  76struct tegra_mc;
  77struct tegra_smmu;
  78struct gart_device;
  79
  80#ifdef CONFIG_TEGRA_IOMMU_SMMU
  81struct tegra_smmu *tegra_smmu_probe(struct device *dev,
  82                                    const struct tegra_smmu_soc *soc,
  83                                    struct tegra_mc *mc);
  84void tegra_smmu_remove(struct tegra_smmu *smmu);
  85#else
  86static inline struct tegra_smmu *
  87tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
  88                 struct tegra_mc *mc)
  89{
  90        return NULL;
  91}
  92
  93static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
  94{
  95}
  96#endif
  97
  98#ifdef CONFIG_TEGRA_IOMMU_GART
  99struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc);
 100int tegra_gart_suspend(struct gart_device *gart);
 101int tegra_gart_resume(struct gart_device *gart);
 102#else
 103static inline struct gart_device *
 104tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
 105{
 106        return ERR_PTR(-ENODEV);
 107}
 108
 109static inline int tegra_gart_suspend(struct gart_device *gart)
 110{
 111        return -ENODEV;
 112}
 113
 114static inline int tegra_gart_resume(struct gart_device *gart)
 115{
 116        return -ENODEV;
 117}
 118#endif
 119
 120struct tegra_mc_reset {
 121        const char *name;
 122        unsigned long id;
 123        unsigned int control;
 124        unsigned int status;
 125        unsigned int reset;
 126        unsigned int bit;
 127};
 128
 129struct tegra_mc_reset_ops {
 130        int (*hotreset_assert)(struct tegra_mc *mc,
 131                               const struct tegra_mc_reset *rst);
 132        int (*hotreset_deassert)(struct tegra_mc *mc,
 133                                 const struct tegra_mc_reset *rst);
 134        int (*block_dma)(struct tegra_mc *mc,
 135                         const struct tegra_mc_reset *rst);
 136        bool (*dma_idling)(struct tegra_mc *mc,
 137                           const struct tegra_mc_reset *rst);
 138        int (*unblock_dma)(struct tegra_mc *mc,
 139                           const struct tegra_mc_reset *rst);
 140        int (*reset_status)(struct tegra_mc *mc,
 141                            const struct tegra_mc_reset *rst);
 142};
 143
 144struct tegra_mc_soc {
 145        const struct tegra_mc_client *clients;
 146        unsigned int num_clients;
 147
 148        const unsigned long *emem_regs;
 149        unsigned int num_emem_regs;
 150
 151        unsigned int num_address_bits;
 152        unsigned int atom_size;
 153
 154        u8 client_id_mask;
 155
 156        const struct tegra_smmu_soc *smmu;
 157
 158        u32 intmask;
 159
 160        const struct tegra_mc_reset_ops *reset_ops;
 161        const struct tegra_mc_reset *resets;
 162        unsigned int num_resets;
 163};
 164
 165struct tegra_mc {
 166        struct device *dev;
 167        struct tegra_smmu *smmu;
 168        struct gart_device *gart;
 169        void __iomem *regs;
 170        struct clk *clk;
 171        int irq;
 172
 173        const struct tegra_mc_soc *soc;
 174        unsigned long tick;
 175
 176        struct tegra_mc_timing *timings;
 177        unsigned int num_timings;
 178
 179        struct reset_controller_dev reset;
 180
 181        spinlock_t lock;
 182};
 183
 184void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
 185unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
 186
 187#endif /* __SOC_TEGRA_MC_H__ */
 188