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11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/interrupt.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/module.h>
18#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/ac97_codec.h>
21#include <sound/info.h>
22#include <sound/initval.h>
23
24MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
25MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "
26 "SiS 7013; NVidia MCP/2/2S/3 modems");
27MODULE_LICENSE("GPL");
28MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
29 "{Intel,82901AB-ICH0},"
30 "{Intel,82801BA-ICH2},"
31 "{Intel,82801CA-ICH3},"
32 "{Intel,82801DB-ICH4},"
33 "{Intel,ICH5},"
34 "{Intel,ICH6},"
35 "{Intel,ICH7},"
36 "{Intel,MX440},"
37 "{SiS,7013},"
38 "{NVidia,NForce Modem},"
39 "{NVidia,NForce2 Modem},"
40 "{NVidia,NForce2s Modem},"
41 "{NVidia,NForce3 Modem},"
42 "{AMD,AMD768}}");
43
44static int index = -2;
45static char *id = SNDRV_DEFAULT_STR1;
46static int ac97_clock;
47
48module_param(index, int, 0444);
49MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
50module_param(id, charp, 0444);
51MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
52module_param(ac97_clock, int, 0444);
53MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
54
55
56static bool enable;
57module_param(enable, bool, 0444);
58
59
60
61
62enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
63
64#define ICHREG(x) ICH_REG_##x
65
66#define DEFINE_REGSET(name,base) \
67enum { \
68 ICH_REG_##name##_BDBAR = base + 0x0, \
69 ICH_REG_##name##_CIV = base + 0x04, \
70 ICH_REG_##name##_LVI = base + 0x05, \
71 ICH_REG_##name##_SR = base + 0x06, \
72 ICH_REG_##name##_PICB = base + 0x08, \
73 ICH_REG_##name##_PIV = base + 0x0a, \
74 ICH_REG_##name##_CR = base + 0x0b, \
75};
76
77
78DEFINE_REGSET(OFF, 0);
79
80
81
82
83#define ICH_REG_LVI_MASK 0x1f
84
85
86#define ICH_FIFOE 0x10
87#define ICH_BCIS 0x08
88#define ICH_LVBCI 0x04
89#define ICH_CELV 0x02
90#define ICH_DCH 0x01
91
92
93#define ICH_REG_PIV_MASK 0x1f
94
95
96#define ICH_IOCE 0x10
97#define ICH_FEIE 0x08
98#define ICH_LVBIE 0x04
99#define ICH_RESETREGS 0x02
100#define ICH_STARTBM 0x01
101
102
103
104#define ICH_REG_GLOB_CNT 0x3c
105#define ICH_TRIE 0x00000040
106#define ICH_SRIE 0x00000020
107#define ICH_PRIE 0x00000010
108#define ICH_ACLINK 0x00000008
109#define ICH_AC97WARM 0x00000004
110#define ICH_AC97COLD 0x00000002
111#define ICH_GIE 0x00000001
112#define ICH_REG_GLOB_STA 0x40
113#define ICH_TRI 0x20000000
114#define ICH_TCR 0x10000000
115#define ICH_BCS 0x08000000
116#define ICH_SPINT 0x04000000
117#define ICH_P2INT 0x02000000
118#define ICH_M2INT 0x01000000
119#define ICH_SAMPLE_CAP 0x00c00000
120#define ICH_MULTICHAN_CAP 0x00300000
121#define ICH_MD3 0x00020000
122#define ICH_AD3 0x00010000
123#define ICH_RCS 0x00008000
124#define ICH_BIT3 0x00004000
125#define ICH_BIT2 0x00002000
126#define ICH_BIT1 0x00001000
127#define ICH_SRI 0x00000800
128#define ICH_PRI 0x00000400
129#define ICH_SCR 0x00000200
130#define ICH_PCR 0x00000100
131#define ICH_MCINT 0x00000080
132#define ICH_POINT 0x00000040
133#define ICH_PIINT 0x00000020
134#define ICH_NVSPINT 0x00000010
135#define ICH_MOINT 0x00000004
136#define ICH_MIINT 0x00000002
137#define ICH_GSCI 0x00000001
138#define ICH_REG_ACC_SEMA 0x44
139#define ICH_CAS 0x01
140
141#define ICH_MAX_FRAGS 32
142
143
144
145
146
147
148enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
149enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
150
151#define get_ichdev(substream) (substream->runtime->private_data)
152
153struct ichdev {
154 unsigned int ichd;
155 unsigned long reg_offset;
156 __le32 *bdbar;
157 unsigned int bdbar_addr;
158 struct snd_pcm_substream *substream;
159 unsigned int physbuf;
160 unsigned int size;
161 unsigned int fragsize;
162 unsigned int fragsize1;
163 unsigned int position;
164 int frags;
165 int lvi;
166 int lvi_frag;
167 int civ;
168 int ack;
169 int ack_reload;
170 unsigned int ack_bit;
171 unsigned int roff_sr;
172 unsigned int roff_picb;
173 unsigned int int_sta_mask;
174 unsigned int ali_slot;
175 struct snd_ac97 *ac97;
176};
177
178struct intel8x0m {
179 unsigned int device_type;
180
181 int irq;
182
183 void __iomem *addr;
184 void __iomem *bmaddr;
185
186 struct pci_dev *pci;
187 struct snd_card *card;
188
189 int pcm_devs;
190 struct snd_pcm *pcm[2];
191 struct ichdev ichd[2];
192
193 unsigned int in_ac97_init: 1;
194
195 struct snd_ac97_bus *ac97_bus;
196 struct snd_ac97 *ac97;
197
198 spinlock_t reg_lock;
199
200 struct snd_dma_buffer bdbars;
201 u32 bdbars_count;
202 u32 int_sta_reg;
203 u32 int_sta_mask;
204 unsigned int pcm_pos_shift;
205};
206
207static const struct pci_device_id snd_intel8x0m_ids[] = {
208 { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL },
209 { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL },
210 { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL },
211 { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL },
212 { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL },
213 { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL },
214 { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL },
215 { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL },
216 { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL },
217 { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL },
218 { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS },
219 { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE },
220 { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE },
221 { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE },
222 { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE },
223 { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL },
224#if 0
225 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },
226#endif
227 { 0, }
228};
229
230MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
231
232
233
234
235
236static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)
237{
238 return ioread8(chip->bmaddr + offset);
239}
240
241static inline u16 igetword(struct intel8x0m *chip, u32 offset)
242{
243 return ioread16(chip->bmaddr + offset);
244}
245
246static inline u32 igetdword(struct intel8x0m *chip, u32 offset)
247{
248 return ioread32(chip->bmaddr + offset);
249}
250
251static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)
252{
253 iowrite8(val, chip->bmaddr + offset);
254}
255
256static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)
257{
258 iowrite16(val, chip->bmaddr + offset);
259}
260
261static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)
262{
263 iowrite32(val, chip->bmaddr + offset);
264}
265
266
267
268
269
270static inline u16 iagetword(struct intel8x0m *chip, u32 offset)
271{
272 return ioread16(chip->addr + offset);
273}
274
275static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
276{
277 iowrite16(val, chip->addr + offset);
278}
279
280
281
282
283
284
285
286
287
288
289static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)
290{
291 static unsigned int codec_bit[3] = {
292 ICH_PCR, ICH_SCR, ICH_TCR
293 };
294 if (snd_BUG_ON(codec >= 3))
295 return ICH_PCR;
296 return codec_bit[codec];
297}
298
299static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)
300{
301 int time;
302
303 if (codec > 1)
304 return -EIO;
305 codec = get_ich_codec_bit(chip, codec);
306
307
308 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
309 return -EIO;
310
311
312 time = 100;
313 do {
314 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
315 return 0;
316 udelay(10);
317 } while (time--);
318
319
320
321
322 dev_err(chip->card->dev,
323 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
324 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
325 iagetword(chip, 0);
326
327 return -EBUSY;
328}
329
330static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97,
331 unsigned short reg,
332 unsigned short val)
333{
334 struct intel8x0m *chip = ac97->private_data;
335
336 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
337 if (! chip->in_ac97_init)
338 dev_err(chip->card->dev,
339 "codec_write %d: semaphore is not ready for register 0x%x\n",
340 ac97->num, reg);
341 }
342 iaputword(chip, reg + ac97->num * 0x80, val);
343}
344
345static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97,
346 unsigned short reg)
347{
348 struct intel8x0m *chip = ac97->private_data;
349 unsigned short res;
350 unsigned int tmp;
351
352 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
353 if (! chip->in_ac97_init)
354 dev_err(chip->card->dev,
355 "codec_read %d: semaphore is not ready for register 0x%x\n",
356 ac97->num, reg);
357 res = 0xffff;
358 } else {
359 res = iagetword(chip, reg + ac97->num * 0x80);
360 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
361
362 iputdword(chip, ICHREG(GLOB_STA),
363 tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
364 if (! chip->in_ac97_init)
365 dev_err(chip->card->dev,
366 "codec_read %d: read timeout for register 0x%x\n",
367 ac97->num, reg);
368 res = 0xffff;
369 }
370 }
371 if (reg == AC97_GPIO_STATUS)
372 iagetword(chip, 0);
373 return res;
374}
375
376
377
378
379
380static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)
381{
382 int idx;
383 __le32 *bdbar = ichdev->bdbar;
384 unsigned long port = ichdev->reg_offset;
385
386 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
387 if (ichdev->size == ichdev->fragsize) {
388 ichdev->ack_reload = ichdev->ack = 2;
389 ichdev->fragsize1 = ichdev->fragsize >> 1;
390 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
391 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
392 bdbar[idx + 1] = cpu_to_le32(0x80000000 |
393 ichdev->fragsize1 >> chip->pcm_pos_shift);
394 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
395 bdbar[idx + 3] = cpu_to_le32(0x80000000 |
396 ichdev->fragsize1 >> chip->pcm_pos_shift);
397 }
398 ichdev->frags = 2;
399 } else {
400 ichdev->ack_reload = ichdev->ack = 1;
401 ichdev->fragsize1 = ichdev->fragsize;
402 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
403 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
404 bdbar[idx + 1] = cpu_to_le32(0x80000000 |
405 ichdev->fragsize >> chip->pcm_pos_shift);
406
407
408
409
410 }
411 ichdev->frags = ichdev->size / ichdev->fragsize;
412 }
413 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
414 ichdev->civ = 0;
415 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
416 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
417 ichdev->position = 0;
418#if 0
419 dev_dbg(chip->card->dev,
420 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
421 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
422 ichdev->fragsize1);
423#endif
424
425 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
426}
427
428
429
430
431
432static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev)
433{
434 unsigned long port = ichdev->reg_offset;
435 int civ, i, step;
436 int ack = 0;
437
438 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
439 if (civ == ichdev->civ) {
440
441 step = 1;
442 ichdev->civ++;
443 ichdev->civ &= ICH_REG_LVI_MASK;
444 } else {
445 step = civ - ichdev->civ;
446 if (step < 0)
447 step += ICH_REG_LVI_MASK + 1;
448
449
450 ichdev->civ = civ;
451 }
452
453 ichdev->position += step * ichdev->fragsize1;
454 ichdev->position %= ichdev->size;
455 ichdev->lvi += step;
456 ichdev->lvi &= ICH_REG_LVI_MASK;
457 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
458 for (i = 0; i < step; i++) {
459 ichdev->lvi_frag++;
460 ichdev->lvi_frag %= ichdev->frags;
461 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +
462 ichdev->lvi_frag *
463 ichdev->fragsize1);
464#if 0
465 dev_dbg(chip->card->dev,
466 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
467 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
468 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
469 inl(port + 4), inb(port + ICH_REG_OFF_CR));
470#endif
471 if (--ichdev->ack == 0) {
472 ichdev->ack = ichdev->ack_reload;
473 ack = 1;
474 }
475 }
476 if (ack && ichdev->substream) {
477 spin_unlock(&chip->reg_lock);
478 snd_pcm_period_elapsed(ichdev->substream);
479 spin_lock(&chip->reg_lock);
480 }
481 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
482}
483
484static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id)
485{
486 struct intel8x0m *chip = dev_id;
487 struct ichdev *ichdev;
488 unsigned int status;
489 unsigned int i;
490
491 spin_lock(&chip->reg_lock);
492 status = igetdword(chip, chip->int_sta_reg);
493 if (status == 0xffffffff) {
494 spin_unlock(&chip->reg_lock);
495 return IRQ_NONE;
496 }
497 if ((status & chip->int_sta_mask) == 0) {
498 if (status)
499 iputdword(chip, chip->int_sta_reg, status);
500 spin_unlock(&chip->reg_lock);
501 return IRQ_NONE;
502 }
503
504 for (i = 0; i < chip->bdbars_count; i++) {
505 ichdev = &chip->ichd[i];
506 if (status & ichdev->int_sta_mask)
507 snd_intel8x0m_update(chip, ichdev);
508 }
509
510
511 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
512 spin_unlock(&chip->reg_lock);
513
514 return IRQ_HANDLED;
515}
516
517
518
519
520
521static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
522{
523 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
524 struct ichdev *ichdev = get_ichdev(substream);
525 unsigned char val = 0;
526 unsigned long port = ichdev->reg_offset;
527
528 switch (cmd) {
529 case SNDRV_PCM_TRIGGER_START:
530 case SNDRV_PCM_TRIGGER_RESUME:
531 val = ICH_IOCE | ICH_STARTBM;
532 break;
533 case SNDRV_PCM_TRIGGER_STOP:
534 case SNDRV_PCM_TRIGGER_SUSPEND:
535 val = 0;
536 break;
537 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
538 val = ICH_IOCE;
539 break;
540 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
541 val = ICH_IOCE | ICH_STARTBM;
542 break;
543 default:
544 return -EINVAL;
545 }
546 iputbyte(chip, port + ICH_REG_OFF_CR, val);
547 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
548
549 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
550
551 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
552 }
553 return 0;
554}
555
556static int snd_intel8x0m_hw_params(struct snd_pcm_substream *substream,
557 struct snd_pcm_hw_params *hw_params)
558{
559 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
560}
561
562static int snd_intel8x0m_hw_free(struct snd_pcm_substream *substream)
563{
564 return snd_pcm_lib_free_pages(substream);
565}
566
567static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream)
568{
569 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
570 struct ichdev *ichdev = get_ichdev(substream);
571 size_t ptr1, ptr;
572
573 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
574 if (ptr1 != 0)
575 ptr = ichdev->fragsize1 - ptr1;
576 else
577 ptr = 0;
578 ptr += ichdev->position;
579 if (ptr >= ichdev->size)
580 return 0;
581 return bytes_to_frames(substream->runtime, ptr);
582}
583
584static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)
585{
586 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
587 struct snd_pcm_runtime *runtime = substream->runtime;
588 struct ichdev *ichdev = get_ichdev(substream);
589
590 ichdev->physbuf = runtime->dma_addr;
591 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
592 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
593 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
594 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
595 snd_intel8x0m_setup_periods(chip, ichdev);
596 return 0;
597}
598
599static const struct snd_pcm_hardware snd_intel8x0m_stream =
600{
601 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
602 SNDRV_PCM_INFO_BLOCK_TRANSFER |
603 SNDRV_PCM_INFO_MMAP_VALID |
604 SNDRV_PCM_INFO_PAUSE |
605 SNDRV_PCM_INFO_RESUME),
606 .formats = SNDRV_PCM_FMTBIT_S16_LE,
607 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
608 .rate_min = 8000,
609 .rate_max = 16000,
610 .channels_min = 1,
611 .channels_max = 1,
612 .buffer_bytes_max = 64 * 1024,
613 .period_bytes_min = 32,
614 .period_bytes_max = 64 * 1024,
615 .periods_min = 1,
616 .periods_max = 1024,
617 .fifo_size = 0,
618};
619
620
621static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
622{
623 static const unsigned int rates[] = { 8000, 9600, 12000, 16000 };
624 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
625 .count = ARRAY_SIZE(rates),
626 .list = rates,
627 .mask = 0,
628 };
629 struct snd_pcm_runtime *runtime = substream->runtime;
630 int err;
631
632 ichdev->substream = substream;
633 runtime->hw = snd_intel8x0m_stream;
634 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
635 &hw_constraints_rates);
636 if ( err < 0 )
637 return err;
638 runtime->private_data = ichdev;
639 return 0;
640}
641
642static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)
643{
644 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
645
646 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
647}
648
649static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)
650{
651 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
652
653 chip->ichd[ICHD_MDMOUT].substream = NULL;
654 return 0;
655}
656
657static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)
658{
659 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
660
661 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
662}
663
664static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)
665{
666 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
667
668 chip->ichd[ICHD_MDMIN].substream = NULL;
669 return 0;
670}
671
672
673static const struct snd_pcm_ops snd_intel8x0m_playback_ops = {
674 .open = snd_intel8x0m_playback_open,
675 .close = snd_intel8x0m_playback_close,
676 .ioctl = snd_pcm_lib_ioctl,
677 .hw_params = snd_intel8x0m_hw_params,
678 .hw_free = snd_intel8x0m_hw_free,
679 .prepare = snd_intel8x0m_pcm_prepare,
680 .trigger = snd_intel8x0m_pcm_trigger,
681 .pointer = snd_intel8x0m_pcm_pointer,
682};
683
684static const struct snd_pcm_ops snd_intel8x0m_capture_ops = {
685 .open = snd_intel8x0m_capture_open,
686 .close = snd_intel8x0m_capture_close,
687 .ioctl = snd_pcm_lib_ioctl,
688 .hw_params = snd_intel8x0m_hw_params,
689 .hw_free = snd_intel8x0m_hw_free,
690 .prepare = snd_intel8x0m_pcm_prepare,
691 .trigger = snd_intel8x0m_pcm_trigger,
692 .pointer = snd_intel8x0m_pcm_pointer,
693};
694
695
696struct ich_pcm_table {
697 char *suffix;
698 const struct snd_pcm_ops *playback_ops;
699 const struct snd_pcm_ops *capture_ops;
700 size_t prealloc_size;
701 size_t prealloc_max_size;
702 int ac97_idx;
703};
704
705static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device,
706 struct ich_pcm_table *rec)
707{
708 struct snd_pcm *pcm;
709 int err;
710 char name[32];
711
712 if (rec->suffix)
713 sprintf(name, "Intel ICH - %s", rec->suffix);
714 else
715 strcpy(name, "Intel ICH");
716 err = snd_pcm_new(chip->card, name, device,
717 rec->playback_ops ? 1 : 0,
718 rec->capture_ops ? 1 : 0, &pcm);
719 if (err < 0)
720 return err;
721
722 if (rec->playback_ops)
723 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
724 if (rec->capture_ops)
725 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
726
727 pcm->private_data = chip;
728 pcm->info_flags = 0;
729 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
730 if (rec->suffix)
731 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
732 else
733 strcpy(pcm->name, chip->card->shortname);
734 chip->pcm[device] = pcm;
735
736 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
737 snd_dma_pci_data(chip->pci),
738 rec->prealloc_size,
739 rec->prealloc_max_size);
740
741 return 0;
742}
743
744static struct ich_pcm_table intel_pcms[] = {
745 {
746 .suffix = "Modem",
747 .playback_ops = &snd_intel8x0m_playback_ops,
748 .capture_ops = &snd_intel8x0m_capture_ops,
749 .prealloc_size = 32 * 1024,
750 .prealloc_max_size = 64 * 1024,
751 },
752};
753
754static int snd_intel8x0m_pcm(struct intel8x0m *chip)
755{
756 int i, tblsize, device, err;
757 struct ich_pcm_table *tbl, *rec;
758
759#if 1
760 tbl = intel_pcms;
761 tblsize = 1;
762#else
763 switch (chip->device_type) {
764 case DEVICE_NFORCE:
765 tbl = nforce_pcms;
766 tblsize = ARRAY_SIZE(nforce_pcms);
767 break;
768 case DEVICE_ALI:
769 tbl = ali_pcms;
770 tblsize = ARRAY_SIZE(ali_pcms);
771 break;
772 default:
773 tbl = intel_pcms;
774 tblsize = 2;
775 break;
776 }
777#endif
778 device = 0;
779 for (i = 0; i < tblsize; i++) {
780 rec = tbl + i;
781 if (i > 0 && rec->ac97_idx) {
782
783 if (! chip->ichd[rec->ac97_idx].ac97)
784 continue;
785 }
786 err = snd_intel8x0m_pcm1(chip, device, rec);
787 if (err < 0)
788 return err;
789 device++;
790 }
791
792 chip->pcm_devs = device;
793 return 0;
794}
795
796
797
798
799
800
801static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
802{
803 struct intel8x0m *chip = bus->private_data;
804 chip->ac97_bus = NULL;
805}
806
807static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97)
808{
809 struct intel8x0m *chip = ac97->private_data;
810 chip->ac97 = NULL;
811}
812
813
814static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock)
815{
816 struct snd_ac97_bus *pbus;
817 struct snd_ac97_template ac97;
818 struct snd_ac97 *x97;
819 int err;
820 unsigned int glob_sta = 0;
821 static struct snd_ac97_bus_ops ops = {
822 .write = snd_intel8x0m_codec_write,
823 .read = snd_intel8x0m_codec_read,
824 };
825
826 chip->in_ac97_init = 1;
827
828 memset(&ac97, 0, sizeof(ac97));
829 ac97.private_data = chip;
830 ac97.private_free = snd_intel8x0m_mixer_free_ac97;
831 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
832
833 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
834
835 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
836 goto __err;
837 pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus;
838 if (ac97_clock >= 8000 && ac97_clock <= 48000)
839 pbus->clock = ac97_clock;
840 chip->ac97_bus = pbus;
841
842 ac97.pci = chip->pci;
843 ac97.num = glob_sta & ICH_SCR ? 1 : 0;
844 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
845 dev_err(chip->card->dev,
846 "Unable to initialize codec #%d\n", ac97.num);
847 if (ac97.num == 0)
848 goto __err;
849 return err;
850 }
851 chip->ac97 = x97;
852 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
853 chip->ichd[ICHD_MDMIN].ac97 = x97;
854 chip->ichd[ICHD_MDMOUT].ac97 = x97;
855 }
856
857 chip->in_ac97_init = 0;
858 return 0;
859
860 __err:
861
862 if (chip->device_type != DEVICE_ALI)
863 iputdword(chip, ICHREG(GLOB_CNT),
864 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
865 return err;
866}
867
868
869
870
871
872
873static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)
874{
875 unsigned long end_time;
876 unsigned int cnt, status, nstatus;
877
878
879
880 status = ICH_RCS | ICH_MIINT | ICH_MOINT;
881 cnt = igetdword(chip, ICHREG(GLOB_STA));
882 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
883
884
885 cnt = igetdword(chip, ICHREG(GLOB_CNT));
886 cnt &= ~(ICH_ACLINK);
887
888 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
889 iputdword(chip, ICHREG(GLOB_CNT), cnt);
890 usleep_range(500, 1000);
891 end_time = jiffies + HZ / 4;
892 do {
893 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
894 goto __ok;
895 schedule_timeout_uninterruptible(1);
896 } while (time_after_eq(end_time, jiffies));
897 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
898 igetdword(chip, ICHREG(GLOB_CNT)));
899 return -EIO;
900
901 __ok:
902 if (probing) {
903
904
905
906
907 end_time = jiffies + HZ;
908 do {
909 status = igetdword(chip, ICHREG(GLOB_STA)) &
910 (ICH_PCR | ICH_SCR | ICH_TCR);
911 if (status)
912 break;
913 schedule_timeout_uninterruptible(1);
914 } while (time_after_eq(end_time, jiffies));
915 if (! status) {
916
917 dev_err(chip->card->dev,
918 "codec_ready: codec is not ready [0x%x]\n",
919 igetdword(chip, ICHREG(GLOB_STA)));
920 return -EIO;
921 }
922
923
924 nstatus = ICH_PCR | ICH_SCR;
925
926
927 end_time = jiffies + HZ / 4;
928 while (status != nstatus && time_after_eq(end_time, jiffies)) {
929 schedule_timeout_uninterruptible(1);
930 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
931 }
932
933 } else {
934
935 status = 0;
936 if (chip->ac97)
937 status |= get_ich_codec_bit(chip, chip->ac97->num);
938
939 end_time = jiffies + HZ;
940 do {
941 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
942 (ICH_PCR | ICH_SCR | ICH_TCR);
943 if (status == nstatus)
944 break;
945 schedule_timeout_uninterruptible(1);
946 } while (time_after_eq(end_time, jiffies));
947 }
948
949 if (chip->device_type == DEVICE_SIS) {
950
951 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
952 }
953
954 return 0;
955}
956
957static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing)
958{
959 unsigned int i;
960 int err;
961
962 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
963 return err;
964 iagetword(chip, 0);
965
966
967 for (i = 0; i < chip->bdbars_count; i++)
968 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
969
970 for (i = 0; i < chip->bdbars_count; i++)
971 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
972
973 for (i = 0; i < chip->bdbars_count; i++)
974 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
975 return 0;
976}
977
978static int snd_intel8x0m_free(struct intel8x0m *chip)
979{
980 unsigned int i;
981
982 if (chip->irq < 0)
983 goto __hw_end;
984
985 for (i = 0; i < chip->bdbars_count; i++)
986 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
987
988 for (i = 0; i < chip->bdbars_count; i++)
989 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
990 __hw_end:
991 if (chip->irq >= 0)
992 free_irq(chip->irq, chip);
993 if (chip->bdbars.area)
994 snd_dma_free_pages(&chip->bdbars);
995 if (chip->addr)
996 pci_iounmap(chip->pci, chip->addr);
997 if (chip->bmaddr)
998 pci_iounmap(chip->pci, chip->bmaddr);
999 pci_release_regions(chip->pci);
1000 pci_disable_device(chip->pci);
1001 kfree(chip);
1002 return 0;
1003}
1004
1005#ifdef CONFIG_PM_SLEEP
1006
1007
1008
1009static int intel8x0m_suspend(struct device *dev)
1010{
1011 struct snd_card *card = dev_get_drvdata(dev);
1012 struct intel8x0m *chip = card->private_data;
1013
1014 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1015 snd_ac97_suspend(chip->ac97);
1016 if (chip->irq >= 0) {
1017 free_irq(chip->irq, chip);
1018 chip->irq = -1;
1019 }
1020 return 0;
1021}
1022
1023static int intel8x0m_resume(struct device *dev)
1024{
1025 struct pci_dev *pci = to_pci_dev(dev);
1026 struct snd_card *card = dev_get_drvdata(dev);
1027 struct intel8x0m *chip = card->private_data;
1028
1029 if (request_irq(pci->irq, snd_intel8x0m_interrupt,
1030 IRQF_SHARED, KBUILD_MODNAME, chip)) {
1031 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
1032 pci->irq);
1033 snd_card_disconnect(card);
1034 return -EIO;
1035 }
1036 chip->irq = pci->irq;
1037 snd_intel8x0m_chip_init(chip, 0);
1038 snd_ac97_resume(chip->ac97);
1039
1040 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1041 return 0;
1042}
1043
1044static SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume);
1045#define INTEL8X0M_PM_OPS &intel8x0m_pm
1046#else
1047#define INTEL8X0M_PM_OPS NULL
1048#endif
1049
1050static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,
1051 struct snd_info_buffer *buffer)
1052{
1053 struct intel8x0m *chip = entry->private_data;
1054 unsigned int tmp;
1055
1056 snd_iprintf(buffer, "Intel8x0m\n\n");
1057 if (chip->device_type == DEVICE_ALI)
1058 return;
1059 tmp = igetdword(chip, ICHREG(GLOB_STA));
1060 snd_iprintf(buffer, "Global control : 0x%08x\n",
1061 igetdword(chip, ICHREG(GLOB_CNT)));
1062 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
1063 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
1064 tmp & ICH_PCR ? " primary" : "",
1065 tmp & ICH_SCR ? " secondary" : "",
1066 tmp & ICH_TCR ? " tertiary" : "",
1067 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1068}
1069
1070static void snd_intel8x0m_proc_init(struct intel8x0m *chip)
1071{
1072 snd_card_ro_proc_new(chip->card, "intel8x0m", chip,
1073 snd_intel8x0m_proc_read);
1074}
1075
1076static int snd_intel8x0m_dev_free(struct snd_device *device)
1077{
1078 struct intel8x0m *chip = device->device_data;
1079 return snd_intel8x0m_free(chip);
1080}
1081
1082struct ich_reg_info {
1083 unsigned int int_sta_mask;
1084 unsigned int offset;
1085};
1086
1087static int snd_intel8x0m_create(struct snd_card *card,
1088 struct pci_dev *pci,
1089 unsigned long device_type,
1090 struct intel8x0m **r_intel8x0m)
1091{
1092 struct intel8x0m *chip;
1093 int err;
1094 unsigned int i;
1095 unsigned int int_sta_masks;
1096 struct ichdev *ichdev;
1097 static struct snd_device_ops ops = {
1098 .dev_free = snd_intel8x0m_dev_free,
1099 };
1100 static struct ich_reg_info intel_regs[2] = {
1101 { ICH_MIINT, 0 },
1102 { ICH_MOINT, 0x10 },
1103 };
1104 struct ich_reg_info *tbl;
1105
1106 *r_intel8x0m = NULL;
1107
1108 if ((err = pci_enable_device(pci)) < 0)
1109 return err;
1110
1111 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1112 if (chip == NULL) {
1113 pci_disable_device(pci);
1114 return -ENOMEM;
1115 }
1116 spin_lock_init(&chip->reg_lock);
1117 chip->device_type = device_type;
1118 chip->card = card;
1119 chip->pci = pci;
1120 chip->irq = -1;
1121
1122 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
1123 kfree(chip);
1124 pci_disable_device(pci);
1125 return err;
1126 }
1127
1128 if (device_type == DEVICE_ALI) {
1129
1130 chip->bmaddr = pci_iomap(pci, 0, 0);
1131 goto port_inited;
1132 }
1133
1134 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM)
1135 chip->addr = pci_iomap(pci, 2, 0);
1136 else
1137 chip->addr = pci_iomap(pci, 0, 0);
1138 if (!chip->addr) {
1139 dev_err(card->dev, "AC'97 space ioremap problem\n");
1140 snd_intel8x0m_free(chip);
1141 return -EIO;
1142 }
1143 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM)
1144 chip->bmaddr = pci_iomap(pci, 3, 0);
1145 else
1146 chip->bmaddr = pci_iomap(pci, 1, 0);
1147 if (!chip->bmaddr) {
1148 dev_err(card->dev, "Controller space ioremap problem\n");
1149 snd_intel8x0m_free(chip);
1150 return -EIO;
1151 }
1152
1153 port_inited:
1154
1155 chip->bdbars_count = 2;
1156 tbl = intel_regs;
1157
1158 for (i = 0; i < chip->bdbars_count; i++) {
1159 ichdev = &chip->ichd[i];
1160 ichdev->ichd = i;
1161 ichdev->reg_offset = tbl[i].offset;
1162 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1163 if (device_type == DEVICE_SIS) {
1164
1165 ichdev->roff_sr = ICH_REG_OFF_PICB;
1166 ichdev->roff_picb = ICH_REG_OFF_SR;
1167 } else {
1168 ichdev->roff_sr = ICH_REG_OFF_SR;
1169 ichdev->roff_picb = ICH_REG_OFF_PICB;
1170 }
1171 if (device_type == DEVICE_ALI)
1172 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1173 }
1174
1175 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1176
1177
1178
1179 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1180 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
1181 &chip->bdbars) < 0) {
1182 snd_intel8x0m_free(chip);
1183 return -ENOMEM;
1184 }
1185
1186
1187 int_sta_masks = 0;
1188 for (i = 0; i < chip->bdbars_count; i++) {
1189 ichdev = &chip->ichd[i];
1190 ichdev->bdbar = ((__le32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1191 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1192 int_sta_masks |= ichdev->int_sta_mask;
1193 }
1194 chip->int_sta_reg = ICH_REG_GLOB_STA;
1195 chip->int_sta_mask = int_sta_masks;
1196
1197 pci_set_master(pci);
1198
1199 if ((err = snd_intel8x0m_chip_init(chip, 1)) < 0) {
1200 snd_intel8x0m_free(chip);
1201 return err;
1202 }
1203
1204 if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED,
1205 KBUILD_MODNAME, chip)) {
1206 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1207 snd_intel8x0m_free(chip);
1208 return -EBUSY;
1209 }
1210 chip->irq = pci->irq;
1211
1212 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1213 snd_intel8x0m_free(chip);
1214 return err;
1215 }
1216
1217 *r_intel8x0m = chip;
1218 return 0;
1219}
1220
1221static struct shortname_table {
1222 unsigned int id;
1223 const char *s;
1224} shortnames[] = {
1225 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
1226 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
1227 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1228 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1229 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
1230 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
1231 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
1232 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
1233 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
1234 { 0x7446, "AMD AMD768" },
1235 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1236 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
1237 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1238 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1239 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1240 { 0x746e, "AMD AMD8111" },
1241#if 0
1242 { 0x5455, "ALi M5455" },
1243#endif
1244 { 0 },
1245};
1246
1247static int snd_intel8x0m_probe(struct pci_dev *pci,
1248 const struct pci_device_id *pci_id)
1249{
1250 struct snd_card *card;
1251 struct intel8x0m *chip;
1252 int err;
1253 struct shortname_table *name;
1254
1255 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
1256 if (err < 0)
1257 return err;
1258
1259 strcpy(card->driver, "ICH-MODEM");
1260 strcpy(card->shortname, "Intel ICH");
1261 for (name = shortnames; name->id; name++) {
1262 if (pci->device == name->id) {
1263 strcpy(card->shortname, name->s);
1264 break;
1265 }
1266 }
1267 strcat(card->shortname," Modem");
1268
1269 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1270 snd_card_free(card);
1271 return err;
1272 }
1273 card->private_data = chip;
1274
1275 if ((err = snd_intel8x0m_mixer(chip, ac97_clock)) < 0) {
1276 snd_card_free(card);
1277 return err;
1278 }
1279 if ((err = snd_intel8x0m_pcm(chip)) < 0) {
1280 snd_card_free(card);
1281 return err;
1282 }
1283
1284 snd_intel8x0m_proc_init(chip);
1285
1286 sprintf(card->longname, "%s at irq %i",
1287 card->shortname, chip->irq);
1288
1289 if ((err = snd_card_register(card)) < 0) {
1290 snd_card_free(card);
1291 return err;
1292 }
1293 pci_set_drvdata(pci, card);
1294 return 0;
1295}
1296
1297static void snd_intel8x0m_remove(struct pci_dev *pci)
1298{
1299 snd_card_free(pci_get_drvdata(pci));
1300}
1301
1302static struct pci_driver intel8x0m_driver = {
1303 .name = KBUILD_MODNAME,
1304 .id_table = snd_intel8x0m_ids,
1305 .probe = snd_intel8x0m_probe,
1306 .remove = snd_intel8x0m_remove,
1307 .driver = {
1308 .pm = INTEL8X0M_PM_OPS,
1309 },
1310};
1311
1312module_pci_driver(intel8x0m_driver);
1313
