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8#include <linux/pci.h>
9#include <sound/control.h>
10#include <sound/core.h>
11#include <sound/pcm.h>
12#include <sound/pcm_params.h>
13#include "oxygen.h"
14
15
16#define BUFFER_BYTES_MAX ((1 << 16) * 4)
17
18#define BUFFER_BYTES_MAX_MULTICH ((1 << 24) * 4)
19
20#define FIFO_BYTES 256
21#define FIFO_BYTES_MULTICH 1024
22
23#define PERIOD_BYTES_MIN 64
24
25#define DEFAULT_BUFFER_BYTES (BUFFER_BYTES_MAX / 2)
26#define DEFAULT_BUFFER_BYTES_MULTICH (1024 * 1024)
27
28static const struct snd_pcm_hardware oxygen_stereo_hardware = {
29 .info = SNDRV_PCM_INFO_MMAP |
30 SNDRV_PCM_INFO_MMAP_VALID |
31 SNDRV_PCM_INFO_INTERLEAVED |
32 SNDRV_PCM_INFO_PAUSE |
33 SNDRV_PCM_INFO_SYNC_START |
34 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
35 .formats = SNDRV_PCM_FMTBIT_S16_LE |
36 SNDRV_PCM_FMTBIT_S32_LE,
37 .rates = SNDRV_PCM_RATE_32000 |
38 SNDRV_PCM_RATE_44100 |
39 SNDRV_PCM_RATE_48000 |
40 SNDRV_PCM_RATE_64000 |
41 SNDRV_PCM_RATE_88200 |
42 SNDRV_PCM_RATE_96000 |
43 SNDRV_PCM_RATE_176400 |
44 SNDRV_PCM_RATE_192000,
45 .rate_min = 32000,
46 .rate_max = 192000,
47 .channels_min = 2,
48 .channels_max = 2,
49 .buffer_bytes_max = BUFFER_BYTES_MAX,
50 .period_bytes_min = PERIOD_BYTES_MIN,
51 .period_bytes_max = BUFFER_BYTES_MAX,
52 .periods_min = 1,
53 .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
54 .fifo_size = FIFO_BYTES,
55};
56static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
57 .info = SNDRV_PCM_INFO_MMAP |
58 SNDRV_PCM_INFO_MMAP_VALID |
59 SNDRV_PCM_INFO_INTERLEAVED |
60 SNDRV_PCM_INFO_PAUSE |
61 SNDRV_PCM_INFO_SYNC_START |
62 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
63 .formats = SNDRV_PCM_FMTBIT_S16_LE |
64 SNDRV_PCM_FMTBIT_S32_LE,
65 .rates = SNDRV_PCM_RATE_32000 |
66 SNDRV_PCM_RATE_44100 |
67 SNDRV_PCM_RATE_48000 |
68 SNDRV_PCM_RATE_64000 |
69 SNDRV_PCM_RATE_88200 |
70 SNDRV_PCM_RATE_96000 |
71 SNDRV_PCM_RATE_176400 |
72 SNDRV_PCM_RATE_192000,
73 .rate_min = 32000,
74 .rate_max = 192000,
75 .channels_min = 2,
76 .channels_max = 8,
77 .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
78 .period_bytes_min = PERIOD_BYTES_MIN,
79 .period_bytes_max = BUFFER_BYTES_MAX_MULTICH,
80 .periods_min = 1,
81 .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
82 .fifo_size = FIFO_BYTES_MULTICH,
83};
84static const struct snd_pcm_hardware oxygen_ac97_hardware = {
85 .info = SNDRV_PCM_INFO_MMAP |
86 SNDRV_PCM_INFO_MMAP_VALID |
87 SNDRV_PCM_INFO_INTERLEAVED |
88 SNDRV_PCM_INFO_PAUSE |
89 SNDRV_PCM_INFO_SYNC_START |
90 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
91 .formats = SNDRV_PCM_FMTBIT_S16_LE,
92 .rates = SNDRV_PCM_RATE_48000,
93 .rate_min = 48000,
94 .rate_max = 48000,
95 .channels_min = 2,
96 .channels_max = 2,
97 .buffer_bytes_max = BUFFER_BYTES_MAX,
98 .period_bytes_min = PERIOD_BYTES_MIN,
99 .period_bytes_max = BUFFER_BYTES_MAX,
100 .periods_min = 1,
101 .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
102 .fifo_size = FIFO_BYTES,
103};
104
105static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
106 [PCM_A] = &oxygen_stereo_hardware,
107 [PCM_B] = &oxygen_stereo_hardware,
108 [PCM_C] = &oxygen_stereo_hardware,
109 [PCM_SPDIF] = &oxygen_stereo_hardware,
110 [PCM_MULTICH] = &oxygen_multichannel_hardware,
111 [PCM_AC97] = &oxygen_ac97_hardware,
112};
113
114static inline unsigned int
115oxygen_substream_channel(struct snd_pcm_substream *substream)
116{
117 return (unsigned int)(uintptr_t)substream->runtime->private_data;
118}
119
120static int oxygen_open(struct snd_pcm_substream *substream,
121 unsigned int channel)
122{
123 struct oxygen *chip = snd_pcm_substream_chip(substream);
124 struct snd_pcm_runtime *runtime = substream->runtime;
125 int err;
126
127 runtime->private_data = (void *)(uintptr_t)channel;
128 if (channel == PCM_B && chip->has_ac97_1 &&
129 (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
130 runtime->hw = oxygen_ac97_hardware;
131 else
132 runtime->hw = *oxygen_hardware[channel];
133 switch (channel) {
134 case PCM_C:
135 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) {
136 runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
137 SNDRV_PCM_RATE_64000);
138 runtime->hw.rate_min = 44100;
139 }
140
141 case PCM_A:
142 case PCM_B:
143 runtime->hw.fifo_size = 0;
144 break;
145 case PCM_MULTICH:
146 runtime->hw.channels_max = chip->model.dac_channels_pcm;
147 break;
148 }
149 if (chip->model.pcm_hardware_filter)
150 chip->model.pcm_hardware_filter(channel, &runtime->hw);
151 err = snd_pcm_hw_constraint_step(runtime, 0,
152 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
153 if (err < 0)
154 return err;
155 err = snd_pcm_hw_constraint_step(runtime, 0,
156 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
157 if (err < 0)
158 return err;
159 if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
160 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
161 if (err < 0)
162 return err;
163 }
164 if (runtime->hw.channels_max > 2) {
165 err = snd_pcm_hw_constraint_step(runtime, 0,
166 SNDRV_PCM_HW_PARAM_CHANNELS,
167 2);
168 if (err < 0)
169 return err;
170 }
171 snd_pcm_set_sync(substream);
172 chip->streams[channel] = substream;
173
174 mutex_lock(&chip->mutex);
175 chip->pcm_active |= 1 << channel;
176 if (channel == PCM_SPDIF) {
177 chip->spdif_pcm_bits = chip->spdif_bits;
178 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
179 ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
180 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
181 SNDRV_CTL_EVENT_MASK_INFO,
182 &chip->controls[CONTROL_SPDIF_PCM]->id);
183 }
184 mutex_unlock(&chip->mutex);
185
186 return 0;
187}
188
189static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
190{
191 return oxygen_open(substream, PCM_A);
192}
193
194static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
195{
196 return oxygen_open(substream, PCM_B);
197}
198
199static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
200{
201 return oxygen_open(substream, PCM_C);
202}
203
204static int oxygen_spdif_open(struct snd_pcm_substream *substream)
205{
206 return oxygen_open(substream, PCM_SPDIF);
207}
208
209static int oxygen_multich_open(struct snd_pcm_substream *substream)
210{
211 return oxygen_open(substream, PCM_MULTICH);
212}
213
214static int oxygen_ac97_open(struct snd_pcm_substream *substream)
215{
216 return oxygen_open(substream, PCM_AC97);
217}
218
219static int oxygen_close(struct snd_pcm_substream *substream)
220{
221 struct oxygen *chip = snd_pcm_substream_chip(substream);
222 unsigned int channel = oxygen_substream_channel(substream);
223
224 mutex_lock(&chip->mutex);
225 chip->pcm_active &= ~(1 << channel);
226 if (channel == PCM_SPDIF) {
227 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
228 SNDRV_CTL_ELEM_ACCESS_INACTIVE;
229 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
230 SNDRV_CTL_EVENT_MASK_INFO,
231 &chip->controls[CONTROL_SPDIF_PCM]->id);
232 }
233 if (channel == PCM_SPDIF || channel == PCM_MULTICH)
234 oxygen_update_spdif_source(chip);
235 mutex_unlock(&chip->mutex);
236
237 chip->streams[channel] = NULL;
238 return 0;
239}
240
241static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
242{
243 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
244 return OXYGEN_FORMAT_24;
245 else
246 return OXYGEN_FORMAT_16;
247}
248
249static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
250{
251 switch (params_rate(hw_params)) {
252 case 32000:
253 return OXYGEN_RATE_32000;
254 case 44100:
255 return OXYGEN_RATE_44100;
256 default:
257 return OXYGEN_RATE_48000;
258 case 64000:
259 return OXYGEN_RATE_64000;
260 case 88200:
261 return OXYGEN_RATE_88200;
262 case 96000:
263 return OXYGEN_RATE_96000;
264 case 176400:
265 return OXYGEN_RATE_176400;
266 case 192000:
267 return OXYGEN_RATE_192000;
268 }
269}
270
271static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
272{
273 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
274 return OXYGEN_I2S_BITS_24;
275 else
276 return OXYGEN_I2S_BITS_16;
277}
278
279static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
280{
281 switch (params_channels(hw_params)) {
282 default:
283 return OXYGEN_PLAY_CHANNELS_2;
284 case 4:
285 return OXYGEN_PLAY_CHANNELS_4;
286 case 6:
287 return OXYGEN_PLAY_CHANNELS_6;
288 case 8:
289 return OXYGEN_PLAY_CHANNELS_8;
290 }
291}
292
293static const unsigned int channel_base_registers[PCM_COUNT] = {
294 [PCM_A] = OXYGEN_DMA_A_ADDRESS,
295 [PCM_B] = OXYGEN_DMA_B_ADDRESS,
296 [PCM_C] = OXYGEN_DMA_C_ADDRESS,
297 [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
298 [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
299 [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
300};
301
302static int oxygen_hw_params(struct snd_pcm_substream *substream,
303 struct snd_pcm_hw_params *hw_params)
304{
305 struct oxygen *chip = snd_pcm_substream_chip(substream);
306 unsigned int channel = oxygen_substream_channel(substream);
307 int err;
308
309 err = snd_pcm_lib_malloc_pages(substream,
310 params_buffer_bytes(hw_params));
311 if (err < 0)
312 return err;
313
314 oxygen_write32(chip, channel_base_registers[channel],
315 (u32)substream->runtime->dma_addr);
316 if (channel == PCM_MULTICH) {
317 oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
318 params_buffer_bytes(hw_params) / 4 - 1);
319 oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
320 params_period_bytes(hw_params) / 4 - 1);
321 } else {
322 oxygen_write16(chip, channel_base_registers[channel] + 4,
323 params_buffer_bytes(hw_params) / 4 - 1);
324 oxygen_write16(chip, channel_base_registers[channel] + 6,
325 params_period_bytes(hw_params) / 4 - 1);
326 }
327 return 0;
328}
329
330static u16 get_mclk(struct oxygen *chip, unsigned int channel,
331 struct snd_pcm_hw_params *params)
332{
333 unsigned int mclks, shift;
334
335 if (channel == PCM_MULTICH)
336 mclks = chip->model.dac_mclks;
337 else
338 mclks = chip->model.adc_mclks;
339
340 if (params_rate(params) <= 48000)
341 shift = 0;
342 else if (params_rate(params) <= 96000)
343 shift = 2;
344 else
345 shift = 4;
346
347 return OXYGEN_I2S_MCLK(mclks >> shift);
348}
349
350static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
351 struct snd_pcm_hw_params *hw_params)
352{
353 struct oxygen *chip = snd_pcm_substream_chip(substream);
354 int err;
355
356 err = oxygen_hw_params(substream, hw_params);
357 if (err < 0)
358 return err;
359
360 spin_lock_irq(&chip->reg_lock);
361 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
362 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
363 OXYGEN_REC_FORMAT_A_MASK);
364 oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
365 oxygen_rate(hw_params) |
366 chip->model.adc_i2s_format |
367 get_mclk(chip, PCM_A, hw_params) |
368 oxygen_i2s_bits(hw_params),
369 OXYGEN_I2S_RATE_MASK |
370 OXYGEN_I2S_FORMAT_MASK |
371 OXYGEN_I2S_MCLK_MASK |
372 OXYGEN_I2S_BITS_MASK);
373 spin_unlock_irq(&chip->reg_lock);
374
375 mutex_lock(&chip->mutex);
376 chip->model.set_adc_params(chip, hw_params);
377 mutex_unlock(&chip->mutex);
378 return 0;
379}
380
381static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
382 struct snd_pcm_hw_params *hw_params)
383{
384 struct oxygen *chip = snd_pcm_substream_chip(substream);
385 int is_ac97;
386 int err;
387
388 err = oxygen_hw_params(substream, hw_params);
389 if (err < 0)
390 return err;
391
392 is_ac97 = chip->has_ac97_1 &&
393 (chip->model.device_config & CAPTURE_2_FROM_AC97_1);
394
395 spin_lock_irq(&chip->reg_lock);
396 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
397 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
398 OXYGEN_REC_FORMAT_B_MASK);
399 if (!is_ac97)
400 oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
401 oxygen_rate(hw_params) |
402 chip->model.adc_i2s_format |
403 get_mclk(chip, PCM_B, hw_params) |
404 oxygen_i2s_bits(hw_params),
405 OXYGEN_I2S_RATE_MASK |
406 OXYGEN_I2S_FORMAT_MASK |
407 OXYGEN_I2S_MCLK_MASK |
408 OXYGEN_I2S_BITS_MASK);
409 spin_unlock_irq(&chip->reg_lock);
410
411 if (!is_ac97) {
412 mutex_lock(&chip->mutex);
413 chip->model.set_adc_params(chip, hw_params);
414 mutex_unlock(&chip->mutex);
415 }
416 return 0;
417}
418
419static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
420 struct snd_pcm_hw_params *hw_params)
421{
422 struct oxygen *chip = snd_pcm_substream_chip(substream);
423 bool is_spdif;
424 int err;
425
426 err = oxygen_hw_params(substream, hw_params);
427 if (err < 0)
428 return err;
429
430 is_spdif = chip->model.device_config & CAPTURE_1_FROM_SPDIF;
431
432 spin_lock_irq(&chip->reg_lock);
433 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
434 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
435 OXYGEN_REC_FORMAT_C_MASK);
436 if (!is_spdif)
437 oxygen_write16_masked(chip, OXYGEN_I2S_C_FORMAT,
438 oxygen_rate(hw_params) |
439 chip->model.adc_i2s_format |
440 get_mclk(chip, PCM_B, hw_params) |
441 oxygen_i2s_bits(hw_params),
442 OXYGEN_I2S_RATE_MASK |
443 OXYGEN_I2S_FORMAT_MASK |
444 OXYGEN_I2S_MCLK_MASK |
445 OXYGEN_I2S_BITS_MASK);
446 spin_unlock_irq(&chip->reg_lock);
447
448 if (!is_spdif) {
449 mutex_lock(&chip->mutex);
450 chip->model.set_adc_params(chip, hw_params);
451 mutex_unlock(&chip->mutex);
452 }
453 return 0;
454}
455
456static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
457 struct snd_pcm_hw_params *hw_params)
458{
459 struct oxygen *chip = snd_pcm_substream_chip(substream);
460 int err;
461
462 err = oxygen_hw_params(substream, hw_params);
463 if (err < 0)
464 return err;
465
466 mutex_lock(&chip->mutex);
467 spin_lock_irq(&chip->reg_lock);
468 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
469 OXYGEN_SPDIF_OUT_ENABLE);
470 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
471 oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
472 OXYGEN_SPDIF_FORMAT_MASK);
473 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
474 oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
475 OXYGEN_SPDIF_OUT_RATE_MASK);
476 oxygen_update_spdif_source(chip);
477 spin_unlock_irq(&chip->reg_lock);
478 mutex_unlock(&chip->mutex);
479 return 0;
480}
481
482static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
483 struct snd_pcm_hw_params *hw_params)
484{
485 struct oxygen *chip = snd_pcm_substream_chip(substream);
486 int err;
487
488 err = oxygen_hw_params(substream, hw_params);
489 if (err < 0)
490 return err;
491
492 mutex_lock(&chip->mutex);
493 spin_lock_irq(&chip->reg_lock);
494 oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
495 oxygen_play_channels(hw_params),
496 OXYGEN_PLAY_CHANNELS_MASK);
497 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
498 oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
499 OXYGEN_MULTICH_FORMAT_MASK);
500 oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
501 oxygen_rate(hw_params) |
502 chip->model.dac_i2s_format |
503 get_mclk(chip, PCM_MULTICH, hw_params) |
504 oxygen_i2s_bits(hw_params),
505 OXYGEN_I2S_RATE_MASK |
506 OXYGEN_I2S_FORMAT_MASK |
507 OXYGEN_I2S_MCLK_MASK |
508 OXYGEN_I2S_BITS_MASK);
509 oxygen_update_spdif_source(chip);
510 spin_unlock_irq(&chip->reg_lock);
511
512 chip->model.set_dac_params(chip, hw_params);
513 oxygen_update_dac_routing(chip);
514 mutex_unlock(&chip->mutex);
515 return 0;
516}
517
518static int oxygen_hw_free(struct snd_pcm_substream *substream)
519{
520 struct oxygen *chip = snd_pcm_substream_chip(substream);
521 unsigned int channel = oxygen_substream_channel(substream);
522 unsigned int channel_mask = 1 << channel;
523
524 spin_lock_irq(&chip->reg_lock);
525 chip->interrupt_mask &= ~channel_mask;
526 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
527
528 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
529 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
530 spin_unlock_irq(&chip->reg_lock);
531
532 return snd_pcm_lib_free_pages(substream);
533}
534
535static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
536{
537 struct oxygen *chip = snd_pcm_substream_chip(substream);
538
539 spin_lock_irq(&chip->reg_lock);
540 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
541 OXYGEN_SPDIF_OUT_ENABLE);
542 spin_unlock_irq(&chip->reg_lock);
543 return oxygen_hw_free(substream);
544}
545
546static int oxygen_prepare(struct snd_pcm_substream *substream)
547{
548 struct oxygen *chip = snd_pcm_substream_chip(substream);
549 unsigned int channel = oxygen_substream_channel(substream);
550 unsigned int channel_mask = 1 << channel;
551
552 spin_lock_irq(&chip->reg_lock);
553 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
554 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
555
556 if (substream->runtime->no_period_wakeup)
557 chip->interrupt_mask &= ~channel_mask;
558 else
559 chip->interrupt_mask |= channel_mask;
560 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
561 spin_unlock_irq(&chip->reg_lock);
562 return 0;
563}
564
565static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
566{
567 struct oxygen *chip = snd_pcm_substream_chip(substream);
568 struct snd_pcm_substream *s;
569 unsigned int mask = 0;
570 int pausing;
571
572 switch (cmd) {
573 case SNDRV_PCM_TRIGGER_STOP:
574 case SNDRV_PCM_TRIGGER_START:
575 case SNDRV_PCM_TRIGGER_SUSPEND:
576 pausing = 0;
577 break;
578 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
579 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
580 pausing = 1;
581 break;
582 default:
583 return -EINVAL;
584 }
585
586 snd_pcm_group_for_each_entry(s, substream) {
587 if (snd_pcm_substream_chip(s) == chip) {
588 mask |= 1 << oxygen_substream_channel(s);
589 snd_pcm_trigger_done(s, substream);
590 }
591 }
592
593 spin_lock(&chip->reg_lock);
594 if (!pausing) {
595 if (cmd == SNDRV_PCM_TRIGGER_START)
596 chip->pcm_running |= mask;
597 else
598 chip->pcm_running &= ~mask;
599 oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
600 } else {
601 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
602 oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
603 else
604 oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
605 }
606 spin_unlock(&chip->reg_lock);
607 return 0;
608}
609
610static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
611{
612 struct oxygen *chip = snd_pcm_substream_chip(substream);
613 struct snd_pcm_runtime *runtime = substream->runtime;
614 unsigned int channel = oxygen_substream_channel(substream);
615 u32 curr_addr;
616
617
618 curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
619 return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
620}
621
622static const struct snd_pcm_ops oxygen_rec_a_ops = {
623 .open = oxygen_rec_a_open,
624 .close = oxygen_close,
625 .ioctl = snd_pcm_lib_ioctl,
626 .hw_params = oxygen_rec_a_hw_params,
627 .hw_free = oxygen_hw_free,
628 .prepare = oxygen_prepare,
629 .trigger = oxygen_trigger,
630 .pointer = oxygen_pointer,
631};
632
633static const struct snd_pcm_ops oxygen_rec_b_ops = {
634 .open = oxygen_rec_b_open,
635 .close = oxygen_close,
636 .ioctl = snd_pcm_lib_ioctl,
637 .hw_params = oxygen_rec_b_hw_params,
638 .hw_free = oxygen_hw_free,
639 .prepare = oxygen_prepare,
640 .trigger = oxygen_trigger,
641 .pointer = oxygen_pointer,
642};
643
644static const struct snd_pcm_ops oxygen_rec_c_ops = {
645 .open = oxygen_rec_c_open,
646 .close = oxygen_close,
647 .ioctl = snd_pcm_lib_ioctl,
648 .hw_params = oxygen_rec_c_hw_params,
649 .hw_free = oxygen_hw_free,
650 .prepare = oxygen_prepare,
651 .trigger = oxygen_trigger,
652 .pointer = oxygen_pointer,
653};
654
655static const struct snd_pcm_ops oxygen_spdif_ops = {
656 .open = oxygen_spdif_open,
657 .close = oxygen_close,
658 .ioctl = snd_pcm_lib_ioctl,
659 .hw_params = oxygen_spdif_hw_params,
660 .hw_free = oxygen_spdif_hw_free,
661 .prepare = oxygen_prepare,
662 .trigger = oxygen_trigger,
663 .pointer = oxygen_pointer,
664};
665
666static const struct snd_pcm_ops oxygen_multich_ops = {
667 .open = oxygen_multich_open,
668 .close = oxygen_close,
669 .ioctl = snd_pcm_lib_ioctl,
670 .hw_params = oxygen_multich_hw_params,
671 .hw_free = oxygen_hw_free,
672 .prepare = oxygen_prepare,
673 .trigger = oxygen_trigger,
674 .pointer = oxygen_pointer,
675};
676
677static const struct snd_pcm_ops oxygen_ac97_ops = {
678 .open = oxygen_ac97_open,
679 .close = oxygen_close,
680 .ioctl = snd_pcm_lib_ioctl,
681 .hw_params = oxygen_hw_params,
682 .hw_free = oxygen_hw_free,
683 .prepare = oxygen_prepare,
684 .trigger = oxygen_trigger,
685 .pointer = oxygen_pointer,
686};
687
688int oxygen_pcm_init(struct oxygen *chip)
689{
690 struct snd_pcm *pcm;
691 int outs, ins;
692 int err;
693
694 outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
695 ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
696 CAPTURE_0_FROM_I2S_2));
697 if (outs | ins) {
698 err = snd_pcm_new(chip->card, "Multichannel",
699 0, outs, ins, &pcm);
700 if (err < 0)
701 return err;
702 if (outs)
703 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
704 &oxygen_multich_ops);
705 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
706 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
707 &oxygen_rec_a_ops);
708 else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
709 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
710 &oxygen_rec_b_ops);
711 pcm->private_data = chip;
712 strcpy(pcm->name, "Multichannel");
713 if (outs)
714 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
715 SNDRV_DMA_TYPE_DEV,
716 snd_dma_pci_data(chip->pci),
717 DEFAULT_BUFFER_BYTES_MULTICH,
718 BUFFER_BYTES_MAX_MULTICH);
719 if (ins)
720 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
721 SNDRV_DMA_TYPE_DEV,
722 snd_dma_pci_data(chip->pci),
723 DEFAULT_BUFFER_BYTES,
724 BUFFER_BYTES_MAX);
725 }
726
727 outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
728 ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
729 if (outs | ins) {
730 err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
731 if (err < 0)
732 return err;
733 if (outs)
734 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
735 &oxygen_spdif_ops);
736 if (ins)
737 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
738 &oxygen_rec_c_ops);
739 pcm->private_data = chip;
740 strcpy(pcm->name, "Digital");
741 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
742 snd_dma_pci_data(chip->pci),
743 DEFAULT_BUFFER_BYTES,
744 BUFFER_BYTES_MAX);
745 }
746
747 if (chip->has_ac97_1) {
748 outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
749 ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
750 } else {
751 outs = 0;
752 ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
753 }
754 if (outs | ins) {
755 err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
756 2, outs, ins, &pcm);
757 if (err < 0)
758 return err;
759 if (outs) {
760 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
761 &oxygen_ac97_ops);
762 oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
763 OXYGEN_REC_B_ROUTE_AC97_1,
764 OXYGEN_REC_B_ROUTE_MASK);
765 }
766 if (ins)
767 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
768 &oxygen_rec_b_ops);
769 pcm->private_data = chip;
770 strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
771 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
772 snd_dma_pci_data(chip->pci),
773 DEFAULT_BUFFER_BYTES,
774 BUFFER_BYTES_MAX);
775 }
776
777 ins = !!(chip->model.device_config & CAPTURE_3_FROM_I2S_3);
778 if (ins) {
779 err = snd_pcm_new(chip->card, "Analog3", 3, 0, ins, &pcm);
780 if (err < 0)
781 return err;
782 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
783 &oxygen_rec_c_ops);
784 oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
785 OXYGEN_REC_C_ROUTE_I2S_ADC_3,
786 OXYGEN_REC_C_ROUTE_MASK);
787 pcm->private_data = chip;
788 strcpy(pcm->name, "Analog 3");
789 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
790 snd_dma_pci_data(chip->pci),
791 DEFAULT_BUFFER_BYTES,
792 BUFFER_BYTES_MAX);
793 }
794 return 0;
795}
796
