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10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/i2c.h>
16#include <linux/slab.h>
17#include <linux/workqueue.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/regulator/machine.h>
21#include <linux/pm_runtime.h>
22#include <linux/of_device.h>
23#include <linux/of_gpio.h>
24#include <linux/of_irq.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <linux/gpio.h>
31#include <linux/gpio/consumer.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34#include <sound/cs35l34.h>
35
36#include "cs35l34.h"
37
38#define PDN_DONE_ATTEMPTS 10
39#define CS35L34_START_DELAY 50
40
41struct cs35l34_private {
42 struct snd_soc_component *component;
43 struct cs35l34_platform_data pdata;
44 struct regmap *regmap;
45 struct regulator_bulk_data core_supplies[2];
46 int num_core_supplies;
47 int mclk_int;
48 bool tdm_mode;
49 struct gpio_desc *reset_gpio;
50};
51
52static const struct reg_default cs35l34_reg[] = {
53 {CS35L34_PWRCTL1, 0x01},
54 {CS35L34_PWRCTL2, 0x19},
55 {CS35L34_PWRCTL3, 0x01},
56 {CS35L34_ADSP_CLK_CTL, 0x08},
57 {CS35L34_MCLK_CTL, 0x11},
58 {CS35L34_AMP_INP_DRV_CTL, 0x01},
59 {CS35L34_AMP_DIG_VOL_CTL, 0x12},
60 {CS35L34_AMP_DIG_VOL, 0x00},
61 {CS35L34_AMP_ANLG_GAIN_CTL, 0x0F},
62 {CS35L34_PROTECT_CTL, 0x06},
63 {CS35L34_AMP_KEEP_ALIVE_CTL, 0x04},
64 {CS35L34_BST_CVTR_V_CTL, 0x00},
65 {CS35L34_BST_PEAK_I, 0x10},
66 {CS35L34_BST_RAMP_CTL, 0x87},
67 {CS35L34_BST_CONV_COEF_1, 0x24},
68 {CS35L34_BST_CONV_COEF_2, 0x24},
69 {CS35L34_BST_CONV_SLOPE_COMP, 0x4E},
70 {CS35L34_BST_CONV_SW_FREQ, 0x08},
71 {CS35L34_CLASS_H_CTL, 0x0D},
72 {CS35L34_CLASS_H_HEADRM_CTL, 0x0D},
73 {CS35L34_CLASS_H_RELEASE_RATE, 0x08},
74 {CS35L34_CLASS_H_FET_DRIVE_CTL, 0x41},
75 {CS35L34_CLASS_H_STATUS, 0x05},
76 {CS35L34_VPBR_CTL, 0x0A},
77 {CS35L34_VPBR_VOL_CTL, 0x90},
78 {CS35L34_VPBR_TIMING_CTL, 0x6A},
79 {CS35L34_PRED_MAX_ATTEN_SPK_LOAD, 0x95},
80 {CS35L34_PRED_BROWNOUT_THRESH, 0x1C},
81 {CS35L34_PRED_BROWNOUT_VOL_CTL, 0x00},
82 {CS35L34_PRED_BROWNOUT_RATE_CTL, 0x10},
83 {CS35L34_PRED_WAIT_CTL, 0x10},
84 {CS35L34_PRED_ZVP_INIT_IMP_CTL, 0x08},
85 {CS35L34_PRED_MAN_SAFE_VPI_CTL, 0x80},
86 {CS35L34_VPBR_ATTEN_STATUS, 0x00},
87 {CS35L34_PRED_BRWNOUT_ATT_STATUS, 0x00},
88 {CS35L34_SPKR_MON_CTL, 0xC6},
89 {CS35L34_ADSP_I2S_CTL, 0x00},
90 {CS35L34_ADSP_TDM_CTL, 0x00},
91 {CS35L34_TDM_TX_CTL_1_VMON, 0x00},
92 {CS35L34_TDM_TX_CTL_2_IMON, 0x04},
93 {CS35L34_TDM_TX_CTL_3_VPMON, 0x03},
94 {CS35L34_TDM_TX_CTL_4_VBSTMON, 0x07},
95 {CS35L34_TDM_TX_CTL_5_FLAG1, 0x08},
96 {CS35L34_TDM_TX_CTL_6_FLAG2, 0x09},
97 {CS35L34_TDM_TX_SLOT_EN_1, 0x00},
98 {CS35L34_TDM_TX_SLOT_EN_2, 0x00},
99 {CS35L34_TDM_TX_SLOT_EN_3, 0x00},
100 {CS35L34_TDM_TX_SLOT_EN_4, 0x00},
101 {CS35L34_TDM_RX_CTL_1_AUDIN, 0x40},
102 {CS35L34_TDM_RX_CTL_3_ALIVE, 0x04},
103 {CS35L34_MULT_DEV_SYNCH1, 0x00},
104 {CS35L34_MULT_DEV_SYNCH2, 0x80},
105 {CS35L34_PROT_RELEASE_CTL, 0x00},
106 {CS35L34_DIAG_MODE_REG_LOCK, 0x00},
107 {CS35L34_DIAG_MODE_CTL_1, 0x00},
108 {CS35L34_DIAG_MODE_CTL_2, 0x00},
109 {CS35L34_INT_MASK_1, 0xFF},
110 {CS35L34_INT_MASK_2, 0xFF},
111 {CS35L34_INT_MASK_3, 0xFF},
112 {CS35L34_INT_MASK_4, 0xFF},
113 {CS35L34_INT_STATUS_1, 0x30},
114 {CS35L34_INT_STATUS_2, 0x05},
115 {CS35L34_INT_STATUS_3, 0x00},
116 {CS35L34_INT_STATUS_4, 0x00},
117 {CS35L34_OTP_TRIM_STATUS, 0x00},
118};
119
120static bool cs35l34_volatile_register(struct device *dev, unsigned int reg)
121{
122 switch (reg) {
123 case CS35L34_DEVID_AB:
124 case CS35L34_DEVID_CD:
125 case CS35L34_DEVID_E:
126 case CS35L34_FAB_ID:
127 case CS35L34_REV_ID:
128 case CS35L34_INT_STATUS_1:
129 case CS35L34_INT_STATUS_2:
130 case CS35L34_INT_STATUS_3:
131 case CS35L34_INT_STATUS_4:
132 case CS35L34_CLASS_H_STATUS:
133 case CS35L34_VPBR_ATTEN_STATUS:
134 case CS35L34_OTP_TRIM_STATUS:
135 return true;
136 default:
137 return false;
138 }
139}
140
141static bool cs35l34_readable_register(struct device *dev, unsigned int reg)
142{
143 switch (reg) {
144 case CS35L34_DEVID_AB:
145 case CS35L34_DEVID_CD:
146 case CS35L34_DEVID_E:
147 case CS35L34_FAB_ID:
148 case CS35L34_REV_ID:
149 case CS35L34_PWRCTL1:
150 case CS35L34_PWRCTL2:
151 case CS35L34_PWRCTL3:
152 case CS35L34_ADSP_CLK_CTL:
153 case CS35L34_MCLK_CTL:
154 case CS35L34_AMP_INP_DRV_CTL:
155 case CS35L34_AMP_DIG_VOL_CTL:
156 case CS35L34_AMP_DIG_VOL:
157 case CS35L34_AMP_ANLG_GAIN_CTL:
158 case CS35L34_PROTECT_CTL:
159 case CS35L34_AMP_KEEP_ALIVE_CTL:
160 case CS35L34_BST_CVTR_V_CTL:
161 case CS35L34_BST_PEAK_I:
162 case CS35L34_BST_RAMP_CTL:
163 case CS35L34_BST_CONV_COEF_1:
164 case CS35L34_BST_CONV_COEF_2:
165 case CS35L34_BST_CONV_SLOPE_COMP:
166 case CS35L34_BST_CONV_SW_FREQ:
167 case CS35L34_CLASS_H_CTL:
168 case CS35L34_CLASS_H_HEADRM_CTL:
169 case CS35L34_CLASS_H_RELEASE_RATE:
170 case CS35L34_CLASS_H_FET_DRIVE_CTL:
171 case CS35L34_CLASS_H_STATUS:
172 case CS35L34_VPBR_CTL:
173 case CS35L34_VPBR_VOL_CTL:
174 case CS35L34_VPBR_TIMING_CTL:
175 case CS35L34_PRED_MAX_ATTEN_SPK_LOAD:
176 case CS35L34_PRED_BROWNOUT_THRESH:
177 case CS35L34_PRED_BROWNOUT_VOL_CTL:
178 case CS35L34_PRED_BROWNOUT_RATE_CTL:
179 case CS35L34_PRED_WAIT_CTL:
180 case CS35L34_PRED_ZVP_INIT_IMP_CTL:
181 case CS35L34_PRED_MAN_SAFE_VPI_CTL:
182 case CS35L34_VPBR_ATTEN_STATUS:
183 case CS35L34_PRED_BRWNOUT_ATT_STATUS:
184 case CS35L34_SPKR_MON_CTL:
185 case CS35L34_ADSP_I2S_CTL:
186 case CS35L34_ADSP_TDM_CTL:
187 case CS35L34_TDM_TX_CTL_1_VMON:
188 case CS35L34_TDM_TX_CTL_2_IMON:
189 case CS35L34_TDM_TX_CTL_3_VPMON:
190 case CS35L34_TDM_TX_CTL_4_VBSTMON:
191 case CS35L34_TDM_TX_CTL_5_FLAG1:
192 case CS35L34_TDM_TX_CTL_6_FLAG2:
193 case CS35L34_TDM_TX_SLOT_EN_1:
194 case CS35L34_TDM_TX_SLOT_EN_2:
195 case CS35L34_TDM_TX_SLOT_EN_3:
196 case CS35L34_TDM_TX_SLOT_EN_4:
197 case CS35L34_TDM_RX_CTL_1_AUDIN:
198 case CS35L34_TDM_RX_CTL_3_ALIVE:
199 case CS35L34_MULT_DEV_SYNCH1:
200 case CS35L34_MULT_DEV_SYNCH2:
201 case CS35L34_PROT_RELEASE_CTL:
202 case CS35L34_DIAG_MODE_REG_LOCK:
203 case CS35L34_DIAG_MODE_CTL_1:
204 case CS35L34_DIAG_MODE_CTL_2:
205 case CS35L34_INT_MASK_1:
206 case CS35L34_INT_MASK_2:
207 case CS35L34_INT_MASK_3:
208 case CS35L34_INT_MASK_4:
209 case CS35L34_INT_STATUS_1:
210 case CS35L34_INT_STATUS_2:
211 case CS35L34_INT_STATUS_3:
212 case CS35L34_INT_STATUS_4:
213 case CS35L34_OTP_TRIM_STATUS:
214 return true;
215 default:
216 return false;
217 }
218}
219
220static bool cs35l34_precious_register(struct device *dev, unsigned int reg)
221{
222 switch (reg) {
223 case CS35L34_INT_STATUS_1:
224 case CS35L34_INT_STATUS_2:
225 case CS35L34_INT_STATUS_3:
226 case CS35L34_INT_STATUS_4:
227 return true;
228 default:
229 return false;
230 }
231}
232
233static int cs35l34_sdin_event(struct snd_soc_dapm_widget *w,
234 struct snd_kcontrol *kcontrol, int event)
235{
236 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
237 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
238 int ret;
239
240 switch (event) {
241 case SND_SOC_DAPM_PRE_PMU:
242 if (priv->tdm_mode)
243 regmap_update_bits(priv->regmap, CS35L34_PWRCTL3,
244 CS35L34_PDN_TDM, 0x00);
245
246 ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
247 CS35L34_PDN_ALL, 0);
248 if (ret < 0) {
249 dev_err(component->dev, "Cannot set Power bits %d\n", ret);
250 return ret;
251 }
252 usleep_range(5000, 5100);
253 break;
254 case SND_SOC_DAPM_POST_PMD:
255 if (priv->tdm_mode) {
256 regmap_update_bits(priv->regmap, CS35L34_PWRCTL3,
257 CS35L34_PDN_TDM, CS35L34_PDN_TDM);
258 }
259 ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
260 CS35L34_PDN_ALL, CS35L34_PDN_ALL);
261 break;
262 default:
263 pr_err("Invalid event = 0x%x\n", event);
264 }
265 return 0;
266}
267
268static int cs35l34_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
269 unsigned int rx_mask, int slots, int slot_width)
270{
271 struct snd_soc_component *component = dai->component;
272 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
273 unsigned int reg, bit_pos;
274 int slot, slot_num;
275
276 if (slot_width != 8)
277 return -EINVAL;
278
279 priv->tdm_mode = true;
280
281 slot = ffs(rx_mask) - 1;
282 if (slot >= 0)
283 snd_soc_component_update_bits(component, CS35L34_TDM_RX_CTL_1_AUDIN,
284 CS35L34_X_LOC, slot);
285
286
287
288
289 slot = ffs(tx_mask) - 1;
290 slot_num = 0;
291
292
293 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON,
294 CS35L34_X_STATE | CS35L34_X_LOC,
295 CS35L34_X_STATE | CS35L34_X_LOC);
296 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_4_VBSTMON,
297 CS35L34_X_STATE | CS35L34_X_LOC,
298 CS35L34_X_STATE | CS35L34_X_LOC);
299
300
301 while (slot >= 0) {
302
303 if (slot_num == 0)
304 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_1_VMON,
305 CS35L34_X_STATE | CS35L34_X_LOC, slot);
306
307
308 if (slot_num == 4) {
309 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_2_IMON,
310 CS35L34_X_STATE | CS35L34_X_LOC, slot);
311 }
312
313 if (slot_num == 3) {
314 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON,
315 CS35L34_X_STATE | CS35L34_X_LOC, slot);
316 }
317
318 if (slot_num == 7) {
319 snd_soc_component_update_bits(component,
320 CS35L34_TDM_TX_CTL_4_VBSTMON,
321 CS35L34_X_STATE | CS35L34_X_LOC, slot);
322 }
323
324
325 reg = CS35L34_TDM_TX_SLOT_EN_4 - (slot/8);
326 bit_pos = slot - ((slot / 8) * (8));
327 snd_soc_component_update_bits(component, reg,
328 1 << bit_pos, 1 << bit_pos);
329
330 tx_mask &= ~(1 << slot);
331 slot = ffs(tx_mask) - 1;
332 slot_num++;
333 }
334
335 return 0;
336}
337
338static int cs35l34_main_amp_event(struct snd_soc_dapm_widget *w,
339 struct snd_kcontrol *kcontrol, int event)
340{
341 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
342 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
343
344 switch (event) {
345 case SND_SOC_DAPM_POST_PMU:
346 regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL,
347 CS35L34_BST_CVTL_MASK, priv->pdata.boost_vtge);
348 usleep_range(5000, 5100);
349 regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL,
350 CS35L34_MUTE, 0);
351 break;
352 case SND_SOC_DAPM_POST_PMD:
353 regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL,
354 CS35L34_BST_CVTL_MASK, 0);
355 regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL,
356 CS35L34_MUTE, CS35L34_MUTE);
357 usleep_range(5000, 5100);
358 break;
359 default:
360 pr_err("Invalid event = 0x%x\n", event);
361 }
362 return 0;
363}
364
365static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
366
367static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 300, 100, 0);
368
369
370static const struct snd_kcontrol_new cs35l34_snd_controls[] = {
371 SOC_SINGLE_SX_TLV("Digital Volume", CS35L34_AMP_DIG_VOL,
372 0, 0x34, 0xE4, dig_vol_tlv),
373 SOC_SINGLE_TLV("Amp Gain Volume", CS35L34_AMP_ANLG_GAIN_CTL,
374 0, 0xF, 0, amp_gain_tlv),
375};
376
377
378static int cs35l34_mclk_event(struct snd_soc_dapm_widget *w,
379 struct snd_kcontrol *kcontrol, int event)
380{
381 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
382 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
383 int ret, i;
384 unsigned int reg;
385
386 switch (event) {
387 case SND_SOC_DAPM_PRE_PMD:
388 ret = regmap_read(priv->regmap, CS35L34_AMP_DIG_VOL_CTL,
389 ®);
390 if (ret != 0) {
391 pr_err("%s regmap read failure %d\n", __func__, ret);
392 return ret;
393 }
394 if (reg & CS35L34_AMP_DIGSFT)
395 msleep(40);
396 else
397 usleep_range(2000, 2100);
398
399 for (i = 0; i < PDN_DONE_ATTEMPTS; i++) {
400 ret = regmap_read(priv->regmap, CS35L34_INT_STATUS_2,
401 ®);
402 if (ret != 0) {
403 pr_err("%s regmap read failure %d\n",
404 __func__, ret);
405 return ret;
406 }
407 if (reg & CS35L34_PDN_DONE)
408 break;
409
410 usleep_range(5000, 5100);
411 }
412 if (i == PDN_DONE_ATTEMPTS)
413 pr_err("%s Device did not power down properly\n",
414 __func__);
415 break;
416 default:
417 pr_err("Invalid event = 0x%x\n", event);
418 break;
419 }
420 return 0;
421}
422
423static const struct snd_soc_dapm_widget cs35l34_dapm_widgets[] = {
424 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L34_PWRCTL3,
425 1, 1, cs35l34_sdin_event,
426 SND_SOC_DAPM_PRE_PMU |
427 SND_SOC_DAPM_POST_PMD),
428 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L34_PWRCTL3, 2, 1),
429
430 SND_SOC_DAPM_SUPPLY("EXTCLK", CS35L34_PWRCTL3, 7, 1,
431 cs35l34_mclk_event, SND_SOC_DAPM_PRE_PMD),
432
433 SND_SOC_DAPM_OUTPUT("SPK"),
434
435 SND_SOC_DAPM_INPUT("VP"),
436 SND_SOC_DAPM_INPUT("VPST"),
437 SND_SOC_DAPM_INPUT("ISENSE"),
438 SND_SOC_DAPM_INPUT("VSENSE"),
439
440 SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L34_PWRCTL2, 7, 1),
441 SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L34_PWRCTL2, 6, 1),
442 SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L34_PWRCTL3, 3, 1),
443 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L34_PWRCTL3, 4, 1),
444 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L34_PWRCTL2, 5, 1),
445 SND_SOC_DAPM_ADC("BOOST", NULL, CS35L34_PWRCTL2, 2, 1),
446
447 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L34_PWRCTL2, 0, 1, NULL, 0,
448 cs35l34_main_amp_event, SND_SOC_DAPM_POST_PMU |
449 SND_SOC_DAPM_POST_PMD),
450};
451
452static const struct snd_soc_dapm_route cs35l34_audio_map[] = {
453 {"SDIN", NULL, "AMP Playback"},
454 {"BOOST", NULL, "SDIN"},
455 {"CLASS H", NULL, "BOOST"},
456 {"Main AMP", NULL, "CLASS H"},
457 {"SPK", NULL, "Main AMP"},
458
459 {"VPMON ADC", NULL, "CLASS H"},
460 {"VBSTMON ADC", NULL, "CLASS H"},
461 {"SPK", NULL, "VPMON ADC"},
462 {"SPK", NULL, "VBSTMON ADC"},
463
464 {"IMON ADC", NULL, "ISENSE"},
465 {"VMON ADC", NULL, "VSENSE"},
466 {"SDOUT", NULL, "IMON ADC"},
467 {"SDOUT", NULL, "VMON ADC"},
468 {"AMP Capture", NULL, "SDOUT"},
469
470 {"SDIN", NULL, "EXTCLK"},
471 {"SDOUT", NULL, "EXTCLK"},
472};
473
474struct cs35l34_mclk_div {
475 int mclk;
476 int srate;
477 u8 adsp_rate;
478};
479
480static struct cs35l34_mclk_div cs35l34_mclk_coeffs[] = {
481
482
483
484 {5644800, 11025, 0x1},
485 {5644800, 22050, 0x4},
486 {5644800, 44100, 0x7},
487
488 {6000000, 8000, 0x0},
489 {6000000, 11025, 0x1},
490 {6000000, 12000, 0x2},
491 {6000000, 16000, 0x3},
492 {6000000, 22050, 0x4},
493 {6000000, 24000, 0x5},
494 {6000000, 32000, 0x6},
495 {6000000, 44100, 0x7},
496 {6000000, 48000, 0x8},
497
498 {6144000, 8000, 0x0},
499 {6144000, 11025, 0x1},
500 {6144000, 12000, 0x2},
501 {6144000, 16000, 0x3},
502 {6144000, 22050, 0x4},
503 {6144000, 24000, 0x5},
504 {6144000, 32000, 0x6},
505 {6144000, 44100, 0x7},
506 {6144000, 48000, 0x8},
507};
508
509static int cs35l34_get_mclk_coeff(int mclk, int srate)
510{
511 int i;
512
513 for (i = 0; i < ARRAY_SIZE(cs35l34_mclk_coeffs); i++) {
514 if (cs35l34_mclk_coeffs[i].mclk == mclk &&
515 cs35l34_mclk_coeffs[i].srate == srate)
516 return i;
517 }
518 return -EINVAL;
519}
520
521static int cs35l34_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
522{
523 struct snd_soc_component *component = codec_dai->component;
524 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
525
526 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
527 case SND_SOC_DAIFMT_CBM_CFM:
528 regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
529 0x80, 0x80);
530 break;
531 case SND_SOC_DAIFMT_CBS_CFS:
532 regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
533 0x80, 0x00);
534 break;
535 default:
536 return -EINVAL;
537 }
538 return 0;
539}
540
541static int cs35l34_pcm_hw_params(struct snd_pcm_substream *substream,
542 struct snd_pcm_hw_params *params,
543 struct snd_soc_dai *dai)
544{
545 struct snd_soc_component *component = dai->component;
546 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
547 int srate = params_rate(params);
548 int ret;
549
550 int coeff = cs35l34_get_mclk_coeff(priv->mclk_int, srate);
551
552 if (coeff < 0) {
553 dev_err(component->dev, "ERROR: Invalid mclk %d and/or srate %d\n",
554 priv->mclk_int, srate);
555 return coeff;
556 }
557
558 ret = regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
559 CS35L34_ADSP_RATE, cs35l34_mclk_coeffs[coeff].adsp_rate);
560 if (ret != 0)
561 dev_err(component->dev, "Failed to set clock state %d\n", ret);
562
563 return ret;
564}
565
566static const unsigned int cs35l34_src_rates[] = {
567 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
568};
569
570
571static const struct snd_pcm_hw_constraint_list cs35l34_constraints = {
572 .count = ARRAY_SIZE(cs35l34_src_rates),
573 .list = cs35l34_src_rates,
574};
575
576static int cs35l34_pcm_startup(struct snd_pcm_substream *substream,
577 struct snd_soc_dai *dai)
578{
579
580 snd_pcm_hw_constraint_list(substream->runtime, 0,
581 SNDRV_PCM_HW_PARAM_RATE, &cs35l34_constraints);
582 return 0;
583}
584
585
586static int cs35l34_set_tristate(struct snd_soc_dai *dai, int tristate)
587{
588
589 struct snd_soc_component *component = dai->component;
590
591 if (tristate)
592 snd_soc_component_update_bits(component, CS35L34_PWRCTL3,
593 CS35L34_PDN_SDOUT, CS35L34_PDN_SDOUT);
594 else
595 snd_soc_component_update_bits(component, CS35L34_PWRCTL3,
596 CS35L34_PDN_SDOUT, 0);
597 return 0;
598}
599
600static int cs35l34_dai_set_sysclk(struct snd_soc_dai *dai,
601 int clk_id, unsigned int freq, int dir)
602{
603 struct snd_soc_component *component = dai->component;
604 struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component);
605 unsigned int value;
606
607 switch (freq) {
608 case CS35L34_MCLK_5644:
609 value = CS35L34_MCLK_RATE_5P6448;
610 cs35l34->mclk_int = freq;
611 break;
612 case CS35L34_MCLK_6:
613 value = CS35L34_MCLK_RATE_6P0000;
614 cs35l34->mclk_int = freq;
615 break;
616 case CS35L34_MCLK_6144:
617 value = CS35L34_MCLK_RATE_6P1440;
618 cs35l34->mclk_int = freq;
619 break;
620 case CS35L34_MCLK_11289:
621 value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_5P6448;
622 cs35l34->mclk_int = freq / 2;
623 break;
624 case CS35L34_MCLK_12:
625 value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P0000;
626 cs35l34->mclk_int = freq / 2;
627 break;
628 case CS35L34_MCLK_12288:
629 value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P1440;
630 cs35l34->mclk_int = freq / 2;
631 break;
632 default:
633 dev_err(component->dev, "ERROR: Invalid Frequency %d\n", freq);
634 cs35l34->mclk_int = 0;
635 return -EINVAL;
636 }
637 regmap_update_bits(cs35l34->regmap, CS35L34_MCLK_CTL,
638 CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_MASK, value);
639 return 0;
640}
641
642static const struct snd_soc_dai_ops cs35l34_ops = {
643 .startup = cs35l34_pcm_startup,
644 .set_tristate = cs35l34_set_tristate,
645 .set_fmt = cs35l34_set_dai_fmt,
646 .hw_params = cs35l34_pcm_hw_params,
647 .set_sysclk = cs35l34_dai_set_sysclk,
648 .set_tdm_slot = cs35l34_set_tdm_slot,
649};
650
651static struct snd_soc_dai_driver cs35l34_dai = {
652 .name = "cs35l34",
653 .id = 0,
654 .playback = {
655 .stream_name = "AMP Playback",
656 .channels_min = 1,
657 .channels_max = 8,
658 .rates = CS35L34_RATES,
659 .formats = CS35L34_FORMATS,
660 },
661 .capture = {
662 .stream_name = "AMP Capture",
663 .channels_min = 1,
664 .channels_max = 8,
665 .rates = CS35L34_RATES,
666 .formats = CS35L34_FORMATS,
667 },
668 .ops = &cs35l34_ops,
669 .symmetric_rates = 1,
670};
671
672static int cs35l34_boost_inductor(struct cs35l34_private *cs35l34,
673 unsigned int inductor)
674{
675 struct snd_soc_component *component = cs35l34->component;
676
677 switch (inductor) {
678 case 1000:
679 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x24);
680 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x24);
681 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
682 0x4E);
683 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 0);
684 break;
685 case 1200:
686 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20);
687 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20);
688 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
689 0x47);
690 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 1);
691 break;
692 case 1500:
693 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20);
694 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20);
695 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
696 0x3C);
697 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 2);
698 break;
699 case 2200:
700 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x19);
701 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x25);
702 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
703 0x23);
704 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 3);
705 break;
706 default:
707 dev_err(component->dev, "%s Invalid Inductor Value %d uH\n",
708 __func__, inductor);
709 return -EINVAL;
710 }
711 return 0;
712}
713
714static int cs35l34_probe(struct snd_soc_component *component)
715{
716 int ret = 0;
717 struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component);
718
719 pm_runtime_get_sync(component->dev);
720
721
722 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
723 CS35L34_OTW_ATTN_MASK, 0x8);
724
725
726
727
728 regmap_write(cs35l34->regmap, CS35L34_PWRCTL2, 0xFD);
729 regmap_write(cs35l34->regmap, CS35L34_PWRCTL3, 0x1F);
730
731
732 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
733 CS35L34_MUTE, CS35L34_MUTE);
734
735
736 if (cs35l34->pdata.boost_peak)
737 regmap_update_bits(cs35l34->regmap, CS35L34_BST_PEAK_I,
738 CS35L34_BST_PEAK_MASK,
739 cs35l34->pdata.boost_peak);
740
741 if (cs35l34->pdata.gain_zc_disable)
742 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
743 CS35L34_GAIN_ZC_MASK, 0);
744 else
745 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
746 CS35L34_GAIN_ZC_MASK, CS35L34_GAIN_ZC_MASK);
747
748 if (cs35l34->pdata.aif_half_drv)
749 regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_CLK_CTL,
750 CS35L34_ADSP_DRIVE, 0);
751
752 if (cs35l34->pdata.digsft_disable)
753 regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL,
754 CS35L34_AMP_DIGSFT, 0);
755
756 if (cs35l34->pdata.amp_inv)
757 regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL,
758 CS35L34_INV, CS35L34_INV);
759
760 if (cs35l34->pdata.boost_ind)
761 ret = cs35l34_boost_inductor(cs35l34, cs35l34->pdata.boost_ind);
762
763 if (cs35l34->pdata.i2s_sdinloc)
764 regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_I2S_CTL,
765 CS35L34_I2S_LOC_MASK,
766 cs35l34->pdata.i2s_sdinloc << CS35L34_I2S_LOC_SHIFT);
767
768 if (cs35l34->pdata.tdm_rising_edge)
769 regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_TDM_CTL,
770 1, 1);
771
772 pm_runtime_put_sync(component->dev);
773
774 return ret;
775}
776
777
778static const struct snd_soc_component_driver soc_component_dev_cs35l34 = {
779 .probe = cs35l34_probe,
780 .dapm_widgets = cs35l34_dapm_widgets,
781 .num_dapm_widgets = ARRAY_SIZE(cs35l34_dapm_widgets),
782 .dapm_routes = cs35l34_audio_map,
783 .num_dapm_routes = ARRAY_SIZE(cs35l34_audio_map),
784 .controls = cs35l34_snd_controls,
785 .num_controls = ARRAY_SIZE(cs35l34_snd_controls),
786 .idle_bias_on = 1,
787 .use_pmdown_time = 1,
788 .endianness = 1,
789 .non_legacy_dai_naming = 1,
790};
791
792static struct regmap_config cs35l34_regmap = {
793 .reg_bits = 8,
794 .val_bits = 8,
795
796 .max_register = CS35L34_MAX_REGISTER,
797 .reg_defaults = cs35l34_reg,
798 .num_reg_defaults = ARRAY_SIZE(cs35l34_reg),
799 .volatile_reg = cs35l34_volatile_register,
800 .readable_reg = cs35l34_readable_register,
801 .precious_reg = cs35l34_precious_register,
802 .cache_type = REGCACHE_RBTREE,
803};
804
805static int cs35l34_handle_of_data(struct i2c_client *i2c_client,
806 struct cs35l34_platform_data *pdata)
807{
808 struct device_node *np = i2c_client->dev.of_node;
809 unsigned int val;
810
811 if (of_property_read_u32(np, "cirrus,boost-vtge-millivolt",
812 &val) >= 0) {
813
814 if (val > 8000 || (val < 3300 && val > 0)) {
815 dev_err(&i2c_client->dev,
816 "Invalid Boost Voltage %d mV\n", val);
817 return -EINVAL;
818 }
819 if (val == 0)
820 pdata->boost_vtge = 0;
821 else
822 pdata->boost_vtge = ((val - 3300)/100) + 1;
823 } else {
824 dev_warn(&i2c_client->dev,
825 "Boost Voltage not specified. Using VP\n");
826 }
827
828 if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
829 pdata->boost_ind = val;
830 } else {
831 dev_err(&i2c_client->dev, "Inductor not specified.\n");
832 return -EINVAL;
833 }
834
835 if (of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val) >= 0) {
836 if (val > 3840 || val < 1200) {
837 dev_err(&i2c_client->dev,
838 "Invalid Boost Peak Current %d mA\n", val);
839 return -EINVAL;
840 }
841 pdata->boost_peak = ((val - 1200)/80) + 1;
842 }
843
844 pdata->aif_half_drv = of_property_read_bool(np,
845 "cirrus,aif-half-drv");
846 pdata->digsft_disable = of_property_read_bool(np,
847 "cirrus,digsft-disable");
848
849 pdata->gain_zc_disable = of_property_read_bool(np,
850 "cirrus,gain-zc-disable");
851 pdata->amp_inv = of_property_read_bool(np, "cirrus,amp-inv");
852
853 if (of_property_read_u32(np, "cirrus,i2s-sdinloc", &val) >= 0)
854 pdata->i2s_sdinloc = val;
855 if (of_property_read_u32(np, "cirrus,tdm-rising-edge", &val) >= 0)
856 pdata->tdm_rising_edge = val;
857
858 return 0;
859}
860
861static irqreturn_t cs35l34_irq_thread(int irq, void *data)
862{
863 struct cs35l34_private *cs35l34 = data;
864 struct snd_soc_component *component = cs35l34->component;
865 unsigned int sticky1, sticky2, sticky3, sticky4;
866 unsigned int mask1, mask2, mask3, mask4, current1;
867
868
869
870 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_4, &sticky4);
871 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_3, &sticky3);
872 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_2, &sticky2);
873 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, &sticky1);
874
875 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_4, &mask4);
876 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_3, &mask3);
877 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_2, &mask2);
878 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_1, &mask1);
879
880 if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
881 && !(sticky4 & ~mask4))
882 return IRQ_NONE;
883
884 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, ¤t1);
885
886 if (sticky1 & CS35L34_CAL_ERR) {
887 dev_err(component->dev, "Cal error\n");
888
889
890 if (!(current1 & CS35L34_CAL_ERR)) {
891 dev_dbg(component->dev, "Cal error release\n");
892 regmap_update_bits(cs35l34->regmap,
893 CS35L34_PROT_RELEASE_CTL,
894 CS35L34_CAL_ERR_RLS, 0);
895 regmap_update_bits(cs35l34->regmap,
896 CS35L34_PROT_RELEASE_CTL,
897 CS35L34_CAL_ERR_RLS,
898 CS35L34_CAL_ERR_RLS);
899 regmap_update_bits(cs35l34->regmap,
900 CS35L34_PROT_RELEASE_CTL,
901 CS35L34_CAL_ERR_RLS, 0);
902
903 }
904 }
905
906 if (sticky1 & CS35L34_ALIVE_ERR)
907 dev_err(component->dev, "Alive error\n");
908
909 if (sticky1 & CS35L34_AMP_SHORT) {
910 dev_crit(component->dev, "Amp short error\n");
911
912
913 if (!(current1 & CS35L34_AMP_SHORT)) {
914 dev_dbg(component->dev,
915 "Amp short error release\n");
916 regmap_update_bits(cs35l34->regmap,
917 CS35L34_PROT_RELEASE_CTL,
918 CS35L34_SHORT_RLS, 0);
919 regmap_update_bits(cs35l34->regmap,
920 CS35L34_PROT_RELEASE_CTL,
921 CS35L34_SHORT_RLS,
922 CS35L34_SHORT_RLS);
923 regmap_update_bits(cs35l34->regmap,
924 CS35L34_PROT_RELEASE_CTL,
925 CS35L34_SHORT_RLS, 0);
926 }
927 }
928
929 if (sticky1 & CS35L34_OTW) {
930 dev_crit(component->dev, "Over temperature warning\n");
931
932
933 if (!(current1 & CS35L34_OTW)) {
934 dev_dbg(component->dev,
935 "Over temperature warning release\n");
936 regmap_update_bits(cs35l34->regmap,
937 CS35L34_PROT_RELEASE_CTL,
938 CS35L34_OTW_RLS, 0);
939 regmap_update_bits(cs35l34->regmap,
940 CS35L34_PROT_RELEASE_CTL,
941 CS35L34_OTW_RLS,
942 CS35L34_OTW_RLS);
943 regmap_update_bits(cs35l34->regmap,
944 CS35L34_PROT_RELEASE_CTL,
945 CS35L34_OTW_RLS, 0);
946 }
947 }
948
949 if (sticky1 & CS35L34_OTE) {
950 dev_crit(component->dev, "Over temperature error\n");
951
952
953 if (!(current1 & CS35L34_OTE)) {
954 dev_dbg(component->dev,
955 "Over temperature error release\n");
956 regmap_update_bits(cs35l34->regmap,
957 CS35L34_PROT_RELEASE_CTL,
958 CS35L34_OTE_RLS, 0);
959 regmap_update_bits(cs35l34->regmap,
960 CS35L34_PROT_RELEASE_CTL,
961 CS35L34_OTE_RLS,
962 CS35L34_OTE_RLS);
963 regmap_update_bits(cs35l34->regmap,
964 CS35L34_PROT_RELEASE_CTL,
965 CS35L34_OTE_RLS, 0);
966 }
967 }
968
969 if (sticky3 & CS35L34_BST_HIGH) {
970 dev_crit(component->dev, "VBST too high error; powering off!\n");
971 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2,
972 CS35L34_PDN_AMP, CS35L34_PDN_AMP);
973 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1,
974 CS35L34_PDN_ALL, CS35L34_PDN_ALL);
975 }
976
977 if (sticky3 & CS35L34_LBST_SHORT) {
978 dev_crit(component->dev, "LBST short error; powering off!\n");
979 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2,
980 CS35L34_PDN_AMP, CS35L34_PDN_AMP);
981 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1,
982 CS35L34_PDN_ALL, CS35L34_PDN_ALL);
983 }
984
985 return IRQ_HANDLED;
986}
987
988static const char * const cs35l34_core_supplies[] = {
989 "VA",
990 "VP",
991};
992
993static int cs35l34_i2c_probe(struct i2c_client *i2c_client,
994 const struct i2c_device_id *id)
995{
996 struct cs35l34_private *cs35l34;
997 struct cs35l34_platform_data *pdata =
998 dev_get_platdata(&i2c_client->dev);
999 int i;
1000 int ret;
1001 unsigned int devid = 0;
1002 unsigned int reg;
1003
1004 cs35l34 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l34), GFP_KERNEL);
1005 if (!cs35l34)
1006 return -ENOMEM;
1007
1008 i2c_set_clientdata(i2c_client, cs35l34);
1009 cs35l34->regmap = devm_regmap_init_i2c(i2c_client, &cs35l34_regmap);
1010 if (IS_ERR(cs35l34->regmap)) {
1011 ret = PTR_ERR(cs35l34->regmap);
1012 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1013 return ret;
1014 }
1015
1016 cs35l34->num_core_supplies = ARRAY_SIZE(cs35l34_core_supplies);
1017 for (i = 0; i < ARRAY_SIZE(cs35l34_core_supplies); i++)
1018 cs35l34->core_supplies[i].supply = cs35l34_core_supplies[i];
1019
1020 ret = devm_regulator_bulk_get(&i2c_client->dev,
1021 cs35l34->num_core_supplies,
1022 cs35l34->core_supplies);
1023 if (ret != 0) {
1024 dev_err(&i2c_client->dev,
1025 "Failed to request core supplies %d\n", ret);
1026 return ret;
1027 }
1028
1029 ret = regulator_bulk_enable(cs35l34->num_core_supplies,
1030 cs35l34->core_supplies);
1031 if (ret != 0) {
1032 dev_err(&i2c_client->dev,
1033 "Failed to enable core supplies: %d\n", ret);
1034 return ret;
1035 }
1036
1037 if (pdata) {
1038 cs35l34->pdata = *pdata;
1039 } else {
1040 pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
1041 GFP_KERNEL);
1042 if (!pdata)
1043 return -ENOMEM;
1044
1045 if (i2c_client->dev.of_node) {
1046 ret = cs35l34_handle_of_data(i2c_client, pdata);
1047 if (ret != 0)
1048 return ret;
1049
1050 }
1051 cs35l34->pdata = *pdata;
1052 }
1053
1054 ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
1055 cs35l34_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1056 "cs35l34", cs35l34);
1057 if (ret != 0)
1058 dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
1059
1060 cs35l34->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1061 "reset-gpios", GPIOD_OUT_LOW);
1062 if (IS_ERR(cs35l34->reset_gpio))
1063 return PTR_ERR(cs35l34->reset_gpio);
1064
1065 gpiod_set_value_cansleep(cs35l34->reset_gpio, 1);
1066
1067 msleep(CS35L34_START_DELAY);
1068
1069 ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_AB, ®);
1070
1071 devid = (reg & 0xFF) << 12;
1072 ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_CD, ®);
1073 devid |= (reg & 0xFF) << 4;
1074 ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_E, ®);
1075 devid |= (reg & 0xF0) >> 4;
1076
1077 if (devid != CS35L34_CHIP_ID) {
1078 dev_err(&i2c_client->dev,
1079 "CS35l34 Device ID (%X). Expected ID %X\n",
1080 devid, CS35L34_CHIP_ID);
1081 ret = -ENODEV;
1082 goto err_regulator;
1083 }
1084
1085 ret = regmap_read(cs35l34->regmap, CS35L34_REV_ID, ®);
1086 if (ret < 0) {
1087 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1088 goto err_regulator;
1089 }
1090
1091 dev_info(&i2c_client->dev,
1092 "Cirrus Logic CS35l34 (%x), Revision: %02X\n", devid,
1093 reg & 0xFF);
1094
1095
1096 regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_1,
1097 CS35L34_M_CAL_ERR | CS35L34_M_ALIVE_ERR |
1098 CS35L34_M_AMP_SHORT | CS35L34_M_OTW |
1099 CS35L34_M_OTE, 0);
1100 regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_3,
1101 CS35L34_M_BST_HIGH | CS35L34_M_LBST_SHORT, 0);
1102
1103 pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
1104 pm_runtime_use_autosuspend(&i2c_client->dev);
1105 pm_runtime_set_active(&i2c_client->dev);
1106 pm_runtime_enable(&i2c_client->dev);
1107
1108 ret = devm_snd_soc_register_component(&i2c_client->dev,
1109 &soc_component_dev_cs35l34, &cs35l34_dai, 1);
1110 if (ret < 0) {
1111 dev_err(&i2c_client->dev,
1112 "%s: Register component failed\n", __func__);
1113 goto err_regulator;
1114 }
1115
1116 return 0;
1117
1118err_regulator:
1119 regulator_bulk_disable(cs35l34->num_core_supplies,
1120 cs35l34->core_supplies);
1121
1122 return ret;
1123}
1124
1125static int cs35l34_i2c_remove(struct i2c_client *client)
1126{
1127 struct cs35l34_private *cs35l34 = i2c_get_clientdata(client);
1128
1129 gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
1130
1131 pm_runtime_disable(&client->dev);
1132 regulator_bulk_disable(cs35l34->num_core_supplies,
1133 cs35l34->core_supplies);
1134
1135 return 0;
1136}
1137
1138static int __maybe_unused cs35l34_runtime_resume(struct device *dev)
1139{
1140 struct cs35l34_private *cs35l34 = dev_get_drvdata(dev);
1141 int ret;
1142
1143 ret = regulator_bulk_enable(cs35l34->num_core_supplies,
1144 cs35l34->core_supplies);
1145
1146 if (ret != 0) {
1147 dev_err(dev, "Failed to enable core supplies: %d\n",
1148 ret);
1149 return ret;
1150 }
1151
1152 regcache_cache_only(cs35l34->regmap, false);
1153
1154 gpiod_set_value_cansleep(cs35l34->reset_gpio, 1);
1155 msleep(CS35L34_START_DELAY);
1156
1157 ret = regcache_sync(cs35l34->regmap);
1158 if (ret != 0) {
1159 dev_err(dev, "Failed to restore register cache\n");
1160 goto err;
1161 }
1162 return 0;
1163err:
1164 regcache_cache_only(cs35l34->regmap, true);
1165 regulator_bulk_disable(cs35l34->num_core_supplies,
1166 cs35l34->core_supplies);
1167
1168 return ret;
1169}
1170
1171static int __maybe_unused cs35l34_runtime_suspend(struct device *dev)
1172{
1173 struct cs35l34_private *cs35l34 = dev_get_drvdata(dev);
1174
1175 regcache_cache_only(cs35l34->regmap, true);
1176 regcache_mark_dirty(cs35l34->regmap);
1177
1178 gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
1179
1180 regulator_bulk_disable(cs35l34->num_core_supplies,
1181 cs35l34->core_supplies);
1182
1183 return 0;
1184}
1185
1186static const struct dev_pm_ops cs35l34_pm_ops = {
1187 SET_RUNTIME_PM_OPS(cs35l34_runtime_suspend,
1188 cs35l34_runtime_resume,
1189 NULL)
1190};
1191
1192static const struct of_device_id cs35l34_of_match[] = {
1193 {.compatible = "cirrus,cs35l34"},
1194 {},
1195};
1196MODULE_DEVICE_TABLE(of, cs35l34_of_match);
1197
1198static const struct i2c_device_id cs35l34_id[] = {
1199 {"cs35l34", 0},
1200 {}
1201};
1202MODULE_DEVICE_TABLE(i2c, cs35l34_id);
1203
1204static struct i2c_driver cs35l34_i2c_driver = {
1205 .driver = {
1206 .name = "cs35l34",
1207 .pm = &cs35l34_pm_ops,
1208 .of_match_table = cs35l34_of_match,
1209
1210 },
1211 .id_table = cs35l34_id,
1212 .probe = cs35l34_i2c_probe,
1213 .remove = cs35l34_i2c_remove,
1214
1215};
1216
1217static int __init cs35l34_modinit(void)
1218{
1219 int ret;
1220
1221 ret = i2c_add_driver(&cs35l34_i2c_driver);
1222 if (ret != 0) {
1223 pr_err("Failed to register CS35l34 I2C driver: %d\n", ret);
1224 return ret;
1225 }
1226 return 0;
1227}
1228module_init(cs35l34_modinit);
1229
1230static void __exit cs35l34_exit(void)
1231{
1232 i2c_del_driver(&cs35l34_i2c_driver);
1233}
1234module_exit(cs35l34_exit);
1235
1236MODULE_DESCRIPTION("ASoC CS35l34 driver");
1237MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan@cirrus.com>");
1238MODULE_LICENSE("GPL");
1239
