1
2
3
4
5
6#include <linux/module.h>
7#include <linux/moduleparam.h>
8#include <linux/init.h>
9#include <linux/delay.h>
10#include <linux/pm.h>
11#include <linux/i2c.h>
12#include <linux/slab.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15#include <sound/core.h>
16#include <sound/pcm.h>
17#include <sound/pcm_params.h>
18#include <sound/soc.h>
19#include <sound/tlv.h>
20#include "ml26124.h"
21
22#define DVOL_CTL_DVMUTE_ON BIT(4)
23#define DVOL_CTL_DVMUTE_OFF 0
24#define ML26124_SAI_NO_DELAY BIT(1)
25#define ML26124_SAI_FRAME_SYNC (BIT(5) | BIT(0))
26#define ML26134_CACHESIZE 212
27#define ML26124_VMID BIT(1)
28#define ML26124_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 |\
29 SNDRV_PCM_RATE_48000)
30#define ML26124_FORMATS (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |\
31 SNDRV_PCM_FMTBIT_S32_LE)
32#define ML26124_NUM_REGISTER ML26134_CACHESIZE
33
34struct ml26124_priv {
35 u32 mclk;
36 u32 rate;
37 struct regmap *regmap;
38 int clk_in;
39 struct snd_pcm_substream *substream;
40};
41
42struct clk_coeff {
43 u32 mclk;
44 u32 rate;
45 u8 pllnl;
46 u8 pllnh;
47 u8 pllml;
48 u8 pllmh;
49 u8 plldiv;
50};
51
52
53static const DECLARE_TLV_DB_SCALE(digital_tlv, -7150, 50, 0);
54
55static const DECLARE_TLV_DB_SCALE(alclvl, -2250, 150, 0);
56static const DECLARE_TLV_DB_SCALE(mingain, -1200, 600, 0);
57static const DECLARE_TLV_DB_SCALE(maxgain, -675, 600, 0);
58static const DECLARE_TLV_DB_SCALE(boost_vol, -1200, 75, 0);
59static const DECLARE_TLV_DB_SCALE(ngth, -7650, 150, 0);
60
61static const char * const ml26124_companding[] = {"16bit PCM", "u-law",
62 "A-law"};
63
64static SOC_ENUM_SINGLE_DECL(ml26124_adc_companding_enum,
65 ML26124_SAI_TRANS_CTL, 6, ml26124_companding);
66
67static SOC_ENUM_SINGLE_DECL(ml26124_dac_companding_enum,
68 ML26124_SAI_RCV_CTL, 6, ml26124_companding);
69
70static const struct snd_kcontrol_new ml26124_snd_controls[] = {
71 SOC_SINGLE_TLV("Capture Digital Volume", ML26124_RECORD_DIG_VOL, 0,
72 0xff, 1, digital_tlv),
73 SOC_SINGLE_TLV("Playback Digital Volume", ML26124_PLBAK_DIG_VOL, 0,
74 0xff, 1, digital_tlv),
75 SOC_SINGLE_TLV("Digital Boost Volume", ML26124_DIGI_BOOST_VOL, 0,
76 0x3f, 0, boost_vol),
77 SOC_SINGLE_TLV("EQ Band0 Volume", ML26124_EQ_GAIN_BRAND0, 0,
78 0xff, 1, digital_tlv),
79 SOC_SINGLE_TLV("EQ Band1 Volume", ML26124_EQ_GAIN_BRAND1, 0,
80 0xff, 1, digital_tlv),
81 SOC_SINGLE_TLV("EQ Band2 Volume", ML26124_EQ_GAIN_BRAND2, 0,
82 0xff, 1, digital_tlv),
83 SOC_SINGLE_TLV("EQ Band3 Volume", ML26124_EQ_GAIN_BRAND3, 0,
84 0xff, 1, digital_tlv),
85 SOC_SINGLE_TLV("EQ Band4 Volume", ML26124_EQ_GAIN_BRAND4, 0,
86 0xff, 1, digital_tlv),
87 SOC_SINGLE_TLV("ALC Target Level", ML26124_ALC_TARGET_LEV, 0,
88 0xf, 1, alclvl),
89 SOC_SINGLE_TLV("ALC Min Input Volume", ML26124_ALC_MAXMIN_GAIN, 0,
90 7, 0, mingain),
91 SOC_SINGLE_TLV("ALC Max Input Volume", ML26124_ALC_MAXMIN_GAIN, 4,
92 7, 1, maxgain),
93 SOC_SINGLE_TLV("Playback Limiter Min Input Volume",
94 ML26124_PL_MAXMIN_GAIN, 0, 7, 0, mingain),
95 SOC_SINGLE_TLV("Playback Limiter Max Input Volume",
96 ML26124_PL_MAXMIN_GAIN, 4, 7, 1, maxgain),
97 SOC_SINGLE_TLV("Playback Boost Volume", ML26124_PLYBAK_BOST_VOL, 0,
98 0x3f, 0, boost_vol),
99 SOC_SINGLE("DC High Pass Filter Switch", ML26124_FILTER_EN, 0, 1, 0),
100 SOC_SINGLE("Noise High Pass Filter Switch", ML26124_FILTER_EN, 1, 1, 0),
101 SOC_SINGLE("ZC Switch", ML26124_PW_ZCCMP_PW_MNG, 1,
102 1, 0),
103 SOC_SINGLE("EQ Band0 Switch", ML26124_FILTER_EN, 2, 1, 0),
104 SOC_SINGLE("EQ Band1 Switch", ML26124_FILTER_EN, 3, 1, 0),
105 SOC_SINGLE("EQ Band2 Switch", ML26124_FILTER_EN, 4, 1, 0),
106 SOC_SINGLE("EQ Band3 Switch", ML26124_FILTER_EN, 5, 1, 0),
107 SOC_SINGLE("EQ Band4 Switch", ML26124_FILTER_EN, 6, 1, 0),
108 SOC_SINGLE("Play Limiter", ML26124_DVOL_CTL, 0, 1, 0),
109 SOC_SINGLE("Capture Limiter", ML26124_DVOL_CTL, 1, 1, 0),
110 SOC_SINGLE("Digital Volume Fade Switch", ML26124_DVOL_CTL, 3, 1, 0),
111 SOC_SINGLE("Digital Switch", ML26124_DVOL_CTL, 4, 1, 0),
112 SOC_ENUM("DAC Companding", ml26124_dac_companding_enum),
113 SOC_ENUM("ADC Companding", ml26124_adc_companding_enum),
114};
115
116static const struct snd_kcontrol_new ml26124_output_mixer_controls[] = {
117 SOC_DAPM_SINGLE("DAC Switch", ML26124_SPK_AMP_OUT, 1, 1, 0),
118 SOC_DAPM_SINGLE("Line in loopback Switch", ML26124_SPK_AMP_OUT, 3, 1,
119 0),
120 SOC_DAPM_SINGLE("PGA Switch", ML26124_SPK_AMP_OUT, 5, 1, 0),
121};
122
123
124static const char * const ml26124_input_select[] = {"Analog MIC SingleEnded in",
125 "Digital MIC in", "Analog MIC Differential in"};
126
127static SOC_ENUM_SINGLE_DECL(ml26124_insel_enum,
128 ML26124_MIC_IF_CTL, 0, ml26124_input_select);
129
130static const struct snd_kcontrol_new ml26124_input_mux_controls =
131 SOC_DAPM_ENUM("Input Select", ml26124_insel_enum);
132
133static const struct snd_kcontrol_new ml26124_line_control =
134 SOC_DAPM_SINGLE("Switch", ML26124_PW_LOUT_PW_MNG, 1, 1, 0);
135
136static const struct snd_soc_dapm_widget ml26124_dapm_widgets[] = {
137 SND_SOC_DAPM_SUPPLY("MCLKEN", ML26124_CLK_EN, 0, 0, NULL, 0),
138 SND_SOC_DAPM_SUPPLY("PLLEN", ML26124_CLK_EN, 1, 0, NULL, 0),
139 SND_SOC_DAPM_SUPPLY("PLLOE", ML26124_CLK_EN, 2, 0, NULL, 0),
140 SND_SOC_DAPM_SUPPLY("MICBIAS", ML26124_PW_REF_PW_MNG, 2, 0, NULL, 0),
141 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
142 &ml26124_output_mixer_controls[0],
143 ARRAY_SIZE(ml26124_output_mixer_controls)),
144 SND_SOC_DAPM_DAC("DAC", "Playback", ML26124_PW_DAC_PW_MNG, 1, 0),
145 SND_SOC_DAPM_ADC("ADC", "Capture", ML26124_PW_IN_PW_MNG, 1, 0),
146 SND_SOC_DAPM_PGA("PGA", ML26124_PW_IN_PW_MNG, 3, 0, NULL, 0),
147 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
148 &ml26124_input_mux_controls),
149 SND_SOC_DAPM_SWITCH("Line Out Enable", SND_SOC_NOPM, 0, 0,
150 &ml26124_line_control),
151 SND_SOC_DAPM_INPUT("MDIN"),
152 SND_SOC_DAPM_INPUT("MIN"),
153 SND_SOC_DAPM_INPUT("LIN"),
154 SND_SOC_DAPM_OUTPUT("SPOUT"),
155 SND_SOC_DAPM_OUTPUT("LOUT"),
156};
157
158static const struct snd_soc_dapm_route ml26124_intercon[] = {
159
160 {"DAC", NULL, "MCLKEN"},
161 {"ADC", NULL, "MCLKEN"},
162 {"DAC", NULL, "PLLEN"},
163 {"ADC", NULL, "PLLEN"},
164 {"DAC", NULL, "PLLOE"},
165 {"ADC", NULL, "PLLOE"},
166
167
168 {"Output Mixer", "DAC Switch", "DAC"},
169 {"Output Mixer", "Line in loopback Switch", "LIN"},
170
171
172 {"LOUT", NULL, "Output Mixer"},
173 {"SPOUT", NULL, "Output Mixer"},
174 {"Line Out Enable", NULL, "LOUT"},
175
176
177 {"ADC", NULL, "Input Mux"},
178 {"Input Mux", "Analog MIC SingleEnded in", "PGA"},
179 {"Input Mux", "Analog MIC Differential in", "PGA"},
180 {"PGA", NULL, "MIN"},
181};
182
183
184static const struct clk_coeff coeff_div[] = {
185 {12288000, 16000, 0xc, 0x0, 0x20, 0x0, 0x4},
186 {12288000, 32000, 0xc, 0x0, 0x20, 0x0, 0x4},
187 {12288000, 48000, 0xc, 0x0, 0x30, 0x0, 0x4},
188};
189
190static const struct reg_default ml26124_reg[] = {
191
192 {0x00, 0x00 },
193 {0x02, 0x00},
194 {0x04, 0x00},
195 {0x06, 0x00},
196 {0x08, 0x00},
197 {0x0a, 0x00},
198 {0x0c, 0x00},
199 {0x0e, 0x00},
200
201
202 {0x10, 0x00},
203 {0x12, 0x00},
204 {0x14, 0x00},
205
206
207 {0x20, 0x00},
208 {0x22, 0x00},
209 {0x24, 0x00},
210 {0x26, 0x00},
211 {0x28, 0x00},
212 {0x2a, 0x00},
213 {0x2e, 0x00},
214
215
216 {0x30, 0x04},
217
218
219 {0x32, 0x10},
220 {0x38, 0x00},
221 {0x3a, 0x33},
222 {0x48, 0x00},
223 {0x4a, 0x00},
224
225
226 {0x54, 0x00},
227 {0x5a, 0x00},
228 {0xe8, 0x01},
229
230
231 {0x60, 0x00},
232 {0x62, 0x00},
233 {0x64, 0x00},
234
235
236 {0x66, 0x01},
237 {0x68, 0x00},
238 {0x6A, 0x00},
239 {0x6C, 0xff},
240 {0x70, 0xff},
241 {0x72, 0x10},
242 {0x74, 0xe7},
243 {0x76, 0xe7},
244 {0x78, 0xe7},
245 {0x7A, 0xe7},
246 {0x7C, 0xe7},
247 {0x7E, 0x00},
248 {0x80, 0x00},
249 {0x82, 0x00},
250 {0x84, 0x00},
251 {0x86, 0x00},
252 {0x88, 0x00},
253 {0x8A, 0x00},
254 {0x8C, 0x00},
255 {0x8E, 0x00},
256 {0x90, 0x00},
257 {0x92, 0x00},
258 {0x94, 0x00},
259 {0x96, 0x00},
260 {0x98, 0x00},
261 {0x9A, 0x00},
262 {0x9C, 0x00},
263 {0x9E, 0x00},
264 {0xA0, 0x00},
265 {0xA2, 0x00},
266 {0xA4, 0x00},
267 {0xA6, 0x00},
268
269
270 {0xb0, 0x00},
271 {0xb2, 0x02},
272 {0xb4, 0x03},
273 {0xb6, 0x00},
274 {0xb8, 0x0b},
275 {0xba, 0x70},
276 {0xbc, 0x00},
277 {0xbe, 0x00},
278
279
280 {0xc0, 0x04},
281 {0xc2, 0x05},
282 {0xc4, 0x0d},
283 {0xc6, 0x70},
284 {0xc8, 0x10},
285 {0xca, 0x00},
286
287
288 {0xd0, 0x01},
289 {0xd2, 0x01},
290 {0xd4, 0x01},
291};
292
293
294static inline int get_srate(int rate)
295{
296 int srate;
297
298 switch (rate) {
299 case 16000:
300 srate = 3;
301 break;
302 case 32000:
303 srate = 6;
304 break;
305 case 48000:
306 srate = 8;
307 break;
308 default:
309 return -EINVAL;
310 }
311 return srate;
312}
313
314static inline int get_coeff(int mclk, int rate)
315{
316 int i;
317
318 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
319 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
320 return i;
321 }
322 return -EINVAL;
323}
324
325static int ml26124_hw_params(struct snd_pcm_substream *substream,
326 struct snd_pcm_hw_params *hw_params,
327 struct snd_soc_dai *dai)
328{
329 struct snd_soc_component *component = dai->component;
330 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
331 int i = get_coeff(priv->mclk, params_rate(hw_params));
332 int srate;
333
334 if (i < 0)
335 return i;
336 priv->substream = substream;
337 priv->rate = params_rate(hw_params);
338
339 if (priv->clk_in) {
340 switch (priv->mclk / params_rate(hw_params)) {
341 case 256:
342 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
343 BIT(0) | BIT(1), 1);
344 break;
345 case 512:
346 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
347 BIT(0) | BIT(1), 2);
348 break;
349 case 1024:
350 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
351 BIT(0) | BIT(1), 3);
352 break;
353 default:
354 dev_err(component->dev, "Unsupported MCLKI\n");
355 break;
356 }
357 } else {
358 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
359 BIT(0) | BIT(1), 0);
360 }
361
362 srate = get_srate(params_rate(hw_params));
363 if (srate < 0)
364 return srate;
365
366 snd_soc_component_update_bits(component, ML26124_SMPLING_RATE, 0xf, srate);
367 snd_soc_component_update_bits(component, ML26124_PLLNL, 0xff, coeff_div[i].pllnl);
368 snd_soc_component_update_bits(component, ML26124_PLLNH, 0x1, coeff_div[i].pllnh);
369 snd_soc_component_update_bits(component, ML26124_PLLML, 0xff, coeff_div[i].pllml);
370 snd_soc_component_update_bits(component, ML26124_PLLMH, 0x3f, coeff_div[i].pllmh);
371 snd_soc_component_update_bits(component, ML26124_PLLDIV, 0x1f, coeff_div[i].plldiv);
372
373 return 0;
374}
375
376static int ml26124_mute(struct snd_soc_dai *dai, int mute)
377{
378 struct snd_soc_component *component = dai->component;
379 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
380
381 switch (priv->substream->stream) {
382 case SNDRV_PCM_STREAM_CAPTURE:
383 snd_soc_component_update_bits(component, ML26124_REC_PLYBAK_RUN, BIT(0), 1);
384 break;
385 case SNDRV_PCM_STREAM_PLAYBACK:
386 snd_soc_component_update_bits(component, ML26124_REC_PLYBAK_RUN, BIT(1), 2);
387 break;
388 }
389
390 if (mute)
391 snd_soc_component_update_bits(component, ML26124_DVOL_CTL, BIT(4),
392 DVOL_CTL_DVMUTE_ON);
393 else
394 snd_soc_component_update_bits(component, ML26124_DVOL_CTL, BIT(4),
395 DVOL_CTL_DVMUTE_OFF);
396
397 return 0;
398}
399
400static int ml26124_set_dai_fmt(struct snd_soc_dai *codec_dai,
401 unsigned int fmt)
402{
403 unsigned char mode;
404 struct snd_soc_component *component = codec_dai->component;
405
406
407 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
408 case SND_SOC_DAIFMT_CBM_CFM:
409 mode = 1;
410 break;
411 case SND_SOC_DAIFMT_CBS_CFS:
412 mode = 0;
413 break;
414 default:
415 return -EINVAL;
416 }
417 snd_soc_component_update_bits(component, ML26124_SAI_MODE_SEL, BIT(0), mode);
418
419
420 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
421 case SND_SOC_DAIFMT_I2S:
422 break;
423 default:
424 return -EINVAL;
425 }
426
427
428 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
429 case SND_SOC_DAIFMT_NB_NF:
430 break;
431 default:
432 return -EINVAL;
433 }
434
435 return 0;
436}
437
438static int ml26124_set_dai_sysclk(struct snd_soc_dai *codec_dai,
439 int clk_id, unsigned int freq, int dir)
440{
441 struct snd_soc_component *component = codec_dai->component;
442 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
443
444 switch (clk_id) {
445 case ML26124_USE_PLLOUT:
446 priv->clk_in = ML26124_USE_PLLOUT;
447 break;
448 case ML26124_USE_MCLKI:
449 priv->clk_in = ML26124_USE_MCLKI;
450 break;
451 default:
452 return -EINVAL;
453 }
454
455 priv->mclk = freq;
456
457 return 0;
458}
459
460static int ml26124_set_bias_level(struct snd_soc_component *component,
461 enum snd_soc_bias_level level)
462{
463 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
464
465 switch (level) {
466 case SND_SOC_BIAS_ON:
467 snd_soc_component_update_bits(component, ML26124_PW_SPAMP_PW_MNG,
468 ML26124_R26_MASK, ML26124_BLT_PREAMP_ON);
469 msleep(100);
470 snd_soc_component_update_bits(component, ML26124_PW_SPAMP_PW_MNG,
471 ML26124_R26_MASK,
472 ML26124_MICBEN_ON | ML26124_BLT_ALL_ON);
473 break;
474 case SND_SOC_BIAS_PREPARE:
475 break;
476 case SND_SOC_BIAS_STANDBY:
477
478 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
479 snd_soc_component_update_bits(component, ML26124_PW_REF_PW_MNG,
480 ML26124_VMID, ML26124_VMID);
481 msleep(500);
482 regcache_sync(priv->regmap);
483 }
484 break;
485 case SND_SOC_BIAS_OFF:
486
487 snd_soc_component_update_bits(component, ML26124_PW_REF_PW_MNG,
488 ML26124_VMID, 0);
489 break;
490 }
491 return 0;
492}
493
494static const struct snd_soc_dai_ops ml26124_dai_ops = {
495 .hw_params = ml26124_hw_params,
496 .digital_mute = ml26124_mute,
497 .set_fmt = ml26124_set_dai_fmt,
498 .set_sysclk = ml26124_set_dai_sysclk,
499};
500
501static struct snd_soc_dai_driver ml26124_dai = {
502 .name = "ml26124-hifi",
503 .playback = {
504 .stream_name = "Playback",
505 .channels_min = 1,
506 .channels_max = 2,
507 .rates = ML26124_RATES,
508 .formats = ML26124_FORMATS,},
509 .capture = {
510 .stream_name = "Capture",
511 .channels_min = 1,
512 .channels_max = 2,
513 .rates = ML26124_RATES,
514 .formats = ML26124_FORMATS,},
515 .ops = &ml26124_dai_ops,
516 .symmetric_rates = 1,
517};
518
519static int ml26124_probe(struct snd_soc_component *component)
520{
521
522 snd_soc_component_update_bits(component, ML26124_SW_RST, 0x01, 1);
523 snd_soc_component_update_bits(component, ML26124_SW_RST, 0x01, 0);
524
525 return 0;
526}
527
528static const struct snd_soc_component_driver soc_component_dev_ml26124 = {
529 .probe = ml26124_probe,
530 .set_bias_level = ml26124_set_bias_level,
531 .controls = ml26124_snd_controls,
532 .num_controls = ARRAY_SIZE(ml26124_snd_controls),
533 .dapm_widgets = ml26124_dapm_widgets,
534 .num_dapm_widgets = ARRAY_SIZE(ml26124_dapm_widgets),
535 .dapm_routes = ml26124_intercon,
536 .num_dapm_routes = ARRAY_SIZE(ml26124_intercon),
537 .suspend_bias_off = 1,
538 .idle_bias_on = 1,
539 .use_pmdown_time = 1,
540 .endianness = 1,
541 .non_legacy_dai_naming = 1,
542};
543
544static const struct regmap_config ml26124_i2c_regmap = {
545 .val_bits = 8,
546 .reg_bits = 8,
547 .max_register = ML26124_NUM_REGISTER,
548 .reg_defaults = ml26124_reg,
549 .num_reg_defaults = ARRAY_SIZE(ml26124_reg),
550 .cache_type = REGCACHE_RBTREE,
551 .write_flag_mask = 0x01,
552};
553
554static int ml26124_i2c_probe(struct i2c_client *i2c,
555 const struct i2c_device_id *id)
556{
557 struct ml26124_priv *priv;
558 int ret;
559
560 priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
561 if (!priv)
562 return -ENOMEM;
563
564 i2c_set_clientdata(i2c, priv);
565
566 priv->regmap = devm_regmap_init_i2c(i2c, &ml26124_i2c_regmap);
567 if (IS_ERR(priv->regmap)) {
568 ret = PTR_ERR(priv->regmap);
569 dev_err(&i2c->dev, "regmap_init_i2c() failed: %d\n", ret);
570 return ret;
571 }
572
573 return devm_snd_soc_register_component(&i2c->dev,
574 &soc_component_dev_ml26124, &ml26124_dai, 1);
575}
576
577static const struct i2c_device_id ml26124_i2c_id[] = {
578 { "ml26124", 0 },
579 { }
580};
581MODULE_DEVICE_TABLE(i2c, ml26124_i2c_id);
582
583static struct i2c_driver ml26124_i2c_driver = {
584 .driver = {
585 .name = "ml26124",
586 },
587 .probe = ml26124_i2c_probe,
588 .id_table = ml26124_i2c_id,
589};
590
591module_i2c_driver(ml26124_i2c_driver);
592
593MODULE_AUTHOR("Tomoya MORINAGA <tomoya.rohm@gmail.com>");
594MODULE_DESCRIPTION("LAPIS Semiconductor ML26124 ALSA SoC codec driver");
595MODULE_LICENSE("GPL");
596