LXR linux/sound/soc/intel/baytrail/sst-baytrail-dsp.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Intel Baytrail SST DSP driver
   4 * Copyright (c) 2014, Intel Corporation.
   5 */
   6
   7#include <linux/delay.h>
   8#include <linux/fs.h>
   9#include <linux/slab.h>
  10#include <linux/device.h>
  11#include <linux/interrupt.h>
  12#include <linux/module.h>
  13#include <linux/dma-mapping.h>
  14#include <linux/platform_device.h>
  15#include <linux/firmware.h>
  16
  17#include "../common/sst-dsp.h"
  18#include "../common/sst-dsp-priv.h"
  19#include "sst-baytrail-ipc.h"
  20
  21#define SST_BYT_FW_SIGNATURE_SIZE       4
  22#define SST_BYT_FW_SIGN                 "$SST"
  23
  24#define SST_BYT_IRAM_OFFSET     0xC0000
  25#define SST_BYT_DRAM_OFFSET     0x100000
  26#define SST_BYT_SHIM_OFFSET     0x140000
  27
  28enum sst_ram_type {
  29        SST_BYT_IRAM    = 1,
  30        SST_BYT_DRAM    = 2,
  31        SST_BYT_CACHE   = 3,
  32};
  33
  34struct dma_block_info {
  35        enum sst_ram_type       type;   /* IRAM/DRAM */
  36        u32                     size;   /* Bytes */
  37        u32                     ram_offset; /* Offset in I/DRAM */
  38        u32                     rsvd;   /* Reserved field */
  39};
  40
  41struct fw_header {
  42        unsigned char signature[SST_BYT_FW_SIGNATURE_SIZE];
  43        u32 file_size; /* size of fw minus this header */
  44        u32 modules; /*  # of modules */
  45        u32 file_format; /* version of header format */
  46        u32 reserved[4];
  47};
  48
  49struct sst_byt_fw_module_header {
  50        unsigned char signature[SST_BYT_FW_SIGNATURE_SIZE];
  51        u32 mod_size; /* size of module */
  52        u32 blocks; /* # of blocks */
  53        u32 type; /* codec type, pp lib */
  54        u32 entry_point;
  55};
  56
  57static int sst_byt_parse_module(struct sst_dsp *dsp, struct sst_fw *fw,
  58                                struct sst_byt_fw_module_header *module)
  59{
  60        struct dma_block_info *block;
  61        struct sst_module *mod;
  62        struct sst_module_template template;
  63        int count;
  64
  65        memset(&template, 0, sizeof(template));
  66        template.id = module->type;
  67        template.entry = module->entry_point;
  68
  69        mod = sst_module_new(fw, &template, NULL);
  70        if (mod == NULL)
  71                return -ENOMEM;
  72
  73        block = (void *)module + sizeof(*module);
  74
  75        for (count = 0; count < module->blocks; count++) {
  76
  77                if (block->size <= 0) {
  78                        dev_err(dsp->dev, "block %d size invalid\n", count);
  79                        return -EINVAL;
  80                }
  81
  82                switch (block->type) {
  83                case SST_BYT_IRAM:
  84                        mod->offset = block->ram_offset +
  85                                            dsp->addr.iram_offset;
  86                        mod->type = SST_MEM_IRAM;
  87                        break;
  88                case SST_BYT_DRAM:
  89                        mod->offset = block->ram_offset +
  90                                            dsp->addr.dram_offset;
  91                        mod->type = SST_MEM_DRAM;
  92                        break;
  93                case SST_BYT_CACHE:
  94                        mod->offset = block->ram_offset +
  95                                            (dsp->addr.fw_ext - dsp->addr.lpe);
  96                        mod->type = SST_MEM_CACHE;
  97                        break;
  98                default:
  99                        dev_err(dsp->dev, "wrong ram type 0x%x in block0x%x\n",
 100                                block->type, count);
 101                        return -EINVAL;
 102                }
 103
 104                mod->size = block->size;
 105                mod->data = (void *)block + sizeof(*block);
 106
 107                sst_module_alloc_blocks(mod);
 108
 109                block = (void *)block + sizeof(*block) + block->size;
 110        }
 111        return 0;
 112}
 113
 114static int sst_byt_parse_fw_image(struct sst_fw *sst_fw)
 115{
 116        struct fw_header *header;
 117        struct sst_byt_fw_module_header *module;
 118        struct sst_dsp *dsp = sst_fw->dsp;
 119        int ret, count;
 120
 121        /* Read the header information from the data pointer */
 122        header = (struct fw_header *)sst_fw->dma_buf;
 123
 124        /* verify FW */
 125        if ((strncmp(header->signature, SST_BYT_FW_SIGN, 4) != 0) ||
 126            (sst_fw->size != header->file_size + sizeof(*header))) {
 127                /* Invalid FW signature */
 128                dev_err(dsp->dev, "Invalid FW sign/filesize mismatch\n");
 129                return -EINVAL;
 130        }
 131
 132        dev_dbg(dsp->dev,
 133                "header sign=%4s size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
 134                header->signature, header->file_size, header->modules,
 135                header->file_format, sizeof(*header));
 136
 137        module = (void *)sst_fw->dma_buf + sizeof(*header);
 138        for (count = 0; count < header->modules; count++) {
 139                /* module */
 140                ret = sst_byt_parse_module(dsp, sst_fw, module);
 141                if (ret < 0) {
 142                        dev_err(dsp->dev, "invalid module %d\n", count);
 143                        return ret;
 144                }
 145                module = (void *)module + sizeof(*module) + module->mod_size;
 146        }
 147
 148        return 0;
 149}
 150
 151static void sst_byt_dump_shim(struct sst_dsp *sst)
 152{
 153        int i;
 154        u64 reg;
 155
 156        for (i = 0; i <= 0xF0; i += 8) {
 157                reg = sst_dsp_shim_read64_unlocked(sst, i);
 158                if (reg)
 159                        dev_dbg(sst->dev, "shim 0x%2.2x value 0x%16.16llx\n",
 160                                i, reg);
 161        }
 162
 163        for (i = 0x00; i <= 0xff; i += 4) {
 164                reg = readl(sst->addr.pci_cfg + i);
 165                if (reg)
 166                        dev_dbg(sst->dev, "pci 0x%2.2x value 0x%8.8x\n",
 167                                i, (u32)reg);
 168        }
 169}
 170
 171static irqreturn_t sst_byt_irq(int irq, void *context)
 172{
 173        struct sst_dsp *sst = (struct sst_dsp *) context;
 174        u64 isrx;
 175        irqreturn_t ret = IRQ_NONE;
 176
 177        spin_lock(&sst->spinlock);
 178
 179        isrx = sst_dsp_shim_read64_unlocked(sst, SST_ISRX);
 180        if (isrx & SST_ISRX_DONE) {
 181                /* ADSP has processed the message request from IA */
 182                sst_dsp_shim_update_bits64_unlocked(sst, SST_IPCX,
 183                                                    SST_BYT_IPCX_DONE, 0);
 184                ret = IRQ_WAKE_THREAD;
 185        }
 186        if (isrx & SST_BYT_ISRX_REQUEST) {
 187                /* mask message request from ADSP and do processing later */
 188                sst_dsp_shim_update_bits64_unlocked(sst, SST_IMRX,
 189                                                    SST_BYT_IMRX_REQUEST,
 190                                                    SST_BYT_IMRX_REQUEST);
 191                ret = IRQ_WAKE_THREAD;
 192        }
 193
 194        spin_unlock(&sst->spinlock);
 195
 196        return ret;
 197}
 198
 199static void sst_byt_boot(struct sst_dsp *sst)
 200{
 201        int tries = 10;
 202
 203        /*
 204         * save the physical address of extended firmware block in the first
 205         * 4 bytes of the mailbox
 206         */
 207        memcpy_toio(sst->addr.lpe + SST_BYT_MAILBOX_OFFSET,
 208               &sst->pdata->fw_base, sizeof(u32));
 209
 210        /* release stall and wait to unstall */
 211        sst_dsp_shim_update_bits64(sst, SST_CSR, SST_BYT_CSR_STALL, 0x0);
 212        while (tries--) {
 213                if (!(sst_dsp_shim_read64(sst, SST_CSR) &
 214                      SST_BYT_CSR_PWAITMODE))
 215                        break;
 216                msleep(100);
 217        }
 218        if (tries < 0) {
 219                dev_err(sst->dev, "unable to start DSP\n");
 220                sst_byt_dump_shim(sst);
 221        }
 222}
 223
 224static void sst_byt_reset(struct sst_dsp *sst)
 225{
 226        /* put DSP into reset, set reset vector and stall */
 227        sst_dsp_shim_update_bits64(sst, SST_CSR,
 228                SST_BYT_CSR_RST | SST_BYT_CSR_VECTOR_SEL | SST_BYT_CSR_STALL,
 229                SST_BYT_CSR_RST | SST_BYT_CSR_VECTOR_SEL | SST_BYT_CSR_STALL);
 230
 231        udelay(10);
 232
 233        /* take DSP out of reset and keep stalled for FW loading */
 234        sst_dsp_shim_update_bits64(sst, SST_CSR, SST_BYT_CSR_RST, 0);
 235}
 236
 237struct sst_adsp_memregion {
 238        u32 start;
 239        u32 end;
 240        int blocks;
 241        enum sst_mem_type type;
 242};
 243
 244/* BYT test stuff */
 245static const struct sst_adsp_memregion byt_region[] = {
 246        {0xC0000, 0x100000, 8, SST_MEM_IRAM}, /* I-SRAM - 8 * 32kB */
 247        {0x100000, 0x140000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
 248};
 249
 250static int sst_byt_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
 251{
 252        sst->addr.lpe_base = pdata->lpe_base;
 253        sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
 254        if (!sst->addr.lpe)
 255                return -ENODEV;
 256
 257        /* ADSP PCI MMIO config space */
 258        sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
 259        if (!sst->addr.pci_cfg) {
 260                iounmap(sst->addr.lpe);
 261                return -ENODEV;
 262        }
 263
 264        /* SST Extended FW allocation */
 265        sst->addr.fw_ext = ioremap(pdata->fw_base, pdata->fw_size);
 266        if (!sst->addr.fw_ext) {
 267                iounmap(sst->addr.pci_cfg);
 268                iounmap(sst->addr.lpe);
 269                return -ENODEV;
 270        }
 271
 272        /* SST Shim */
 273        sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
 274
 275        sst_dsp_mailbox_init(sst, SST_BYT_MAILBOX_OFFSET + 0x204,
 276                             SST_BYT_IPC_MAX_PAYLOAD_SIZE,
 277                             SST_BYT_MAILBOX_OFFSET,
 278                             SST_BYT_IPC_MAX_PAYLOAD_SIZE);
 279
 280        sst->irq = pdata->irq;
 281
 282        return 0;
 283}
 284
 285static int sst_byt_init(struct sst_dsp *sst, struct sst_pdata *pdata)
 286{
 287        const struct sst_adsp_memregion *region;
 288        struct device *dev;
 289        int ret = -ENODEV, i, j, region_count;
 290        u32 offset, size;
 291
 292        dev = sst->dev;
 293
 294        switch (sst->id) {
 295        case SST_DEV_ID_BYT:
 296                region = byt_region;
 297                region_count = ARRAY_SIZE(byt_region);
 298                sst->addr.iram_offset = SST_BYT_IRAM_OFFSET;
 299                sst->addr.dram_offset = SST_BYT_DRAM_OFFSET;
 300                sst->addr.shim_offset = SST_BYT_SHIM_OFFSET;
 301                break;
 302        default:
 303                dev_err(dev, "failed to get mem resources\n");
 304                return ret;
 305        }
 306
 307        ret = sst_byt_resource_map(sst, pdata);
 308        if (ret < 0) {
 309                dev_err(dev, "failed to map resources\n");
 310                return ret;
 311        }
 312
 313        ret = dma_coerce_mask_and_coherent(sst->dma_dev, DMA_BIT_MASK(32));
 314        if (ret)
 315                return ret;
 316
 317        /* enable Interrupt from both sides */
 318        sst_dsp_shim_update_bits64(sst, SST_IMRX, 0x3, 0x0);
 319        sst_dsp_shim_update_bits64(sst, SST_IMRD, 0x3, 0x0);
 320
 321        /* register DSP memory blocks - ideally we should get this from ACPI */
 322        for (i = 0; i < region_count; i++) {
 323                offset = region[i].start;
 324                size = (region[i].end - region[i].start) / region[i].blocks;
 325
 326                /* register individual memory blocks */
 327                for (j = 0; j < region[i].blocks; j++) {
 328                        sst_mem_block_register(sst, offset, size,
 329                                               region[i].type, NULL, j, sst);
 330                        offset += size;
 331                }
 332        }
 333
 334        return 0;
 335}
 336
 337static void sst_byt_free(struct sst_dsp *sst)
 338{
 339        sst_mem_block_unregister_all(sst);
 340        iounmap(sst->addr.lpe);
 341        iounmap(sst->addr.pci_cfg);
 342        iounmap(sst->addr.fw_ext);
 343}
 344
 345struct sst_ops sst_byt_ops = {
 346        .reset = sst_byt_reset,
 347        .boot = sst_byt_boot,
 348        .write = sst_shim32_write,
 349        .read = sst_shim32_read,
 350        .write64 = sst_shim32_write64,
 351        .read64 = sst_shim32_read64,
 352        .ram_read = sst_memcpy_fromio_32,
 353        .ram_write = sst_memcpy_toio_32,
 354        .irq_handler = sst_byt_irq,
 355        .init = sst_byt_init,
 356        .free = sst_byt_free,
 357        .parse_fw = sst_byt_parse_fw_image,
 358};
 359