linux/sound/soc/intel/boards/cht_bsw_rt5672.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *  cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms
   4 *                     Cherrytrail and Braswell, with RT5672 codec.
   5 *
   6 *  Copyright (C) 2014 Intel Corp
   7 *  Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
   8 *          Mengdong Lin <mengdong.lin@intel.com>
   9 */
  10
  11#include <linux/input.h>
  12#include <linux/module.h>
  13#include <linux/platform_device.h>
  14#include <linux/slab.h>
  15#include <linux/clk.h>
  16#include <sound/pcm.h>
  17#include <sound/pcm_params.h>
  18#include <sound/soc.h>
  19#include <sound/jack.h>
  20#include <sound/soc-acpi.h>
  21#include "../../codecs/rt5670.h"
  22#include "../atom/sst-atom-controls.h"
  23
  24
  25/* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
  26#define CHT_PLAT_CLK_3_HZ       19200000
  27#define CHT_CODEC_DAI   "rt5670-aif1"
  28
  29struct cht_mc_private {
  30        struct snd_soc_jack headset;
  31        char codec_name[SND_ACPI_I2C_ID_LEN];
  32        struct clk *mclk;
  33};
  34
  35/* Headset jack detection DAPM pins */
  36static struct snd_soc_jack_pin cht_bsw_headset_pins[] = {
  37        {
  38                .pin = "Headset Mic",
  39                .mask = SND_JACK_MICROPHONE,
  40        },
  41        {
  42                .pin = "Headphone",
  43                .mask = SND_JACK_HEADPHONE,
  44        },
  45};
  46
  47static int platform_clock_control(struct snd_soc_dapm_widget *w,
  48                struct snd_kcontrol *k, int  event)
  49{
  50        struct snd_soc_dapm_context *dapm = w->dapm;
  51        struct snd_soc_card *card = dapm->card;
  52        struct snd_soc_dai *codec_dai;
  53        struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card);
  54        int ret;
  55
  56        codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI);
  57        if (!codec_dai) {
  58                dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n");
  59                return -EIO;
  60        }
  61
  62        if (SND_SOC_DAPM_EVENT_ON(event)) {
  63                if (ctx->mclk) {
  64                        ret = clk_prepare_enable(ctx->mclk);
  65                        if (ret < 0) {
  66                                dev_err(card->dev,
  67                                        "could not configure MCLK state");
  68                                return ret;
  69                        }
  70                }
  71
  72                /* set codec PLL source to the 19.2MHz platform clock (MCLK) */
  73                ret = snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_MCLK,
  74                                CHT_PLAT_CLK_3_HZ, 48000 * 512);
  75                if (ret < 0) {
  76                        dev_err(card->dev, "can't set codec pll: %d\n", ret);
  77                        return ret;
  78                }
  79
  80                /* set codec sysclk source to PLL */
  81                ret = snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_PLL1,
  82                        48000 * 512, SND_SOC_CLOCK_IN);
  83                if (ret < 0) {
  84                        dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
  85                        return ret;
  86                }
  87        } else {
  88                /* Set codec sysclk source to its internal clock because codec
  89                 * PLL will be off when idle and MCLK will also be off by ACPI
  90                 * when codec is runtime suspended. Codec needs clock for jack
  91                 * detection and button press.
  92                 */
  93                snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_RCCLK,
  94                                       48000 * 512, SND_SOC_CLOCK_IN);
  95
  96                if (ctx->mclk)
  97                        clk_disable_unprepare(ctx->mclk);
  98        }
  99        return 0;
 100}
 101
 102static const struct snd_soc_dapm_widget cht_dapm_widgets[] = {
 103        SND_SOC_DAPM_HP("Headphone", NULL),
 104        SND_SOC_DAPM_MIC("Headset Mic", NULL),
 105        SND_SOC_DAPM_MIC("Int Mic", NULL),
 106        SND_SOC_DAPM_SPK("Ext Spk", NULL),
 107        SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
 108                        platform_clock_control, SND_SOC_DAPM_PRE_PMU |
 109                        SND_SOC_DAPM_POST_PMD),
 110};
 111
 112static const struct snd_soc_dapm_route cht_audio_map[] = {
 113        {"IN1P", NULL, "Headset Mic"},
 114        {"IN1N", NULL, "Headset Mic"},
 115        {"DMIC L1", NULL, "Int Mic"},
 116        {"DMIC R1", NULL, "Int Mic"},
 117        {"Headphone", NULL, "HPOL"},
 118        {"Headphone", NULL, "HPOR"},
 119        {"Ext Spk", NULL, "SPOLP"},
 120        {"Ext Spk", NULL, "SPOLN"},
 121        {"Ext Spk", NULL, "SPORP"},
 122        {"Ext Spk", NULL, "SPORN"},
 123        {"AIF1 Playback", NULL, "ssp2 Tx"},
 124        {"ssp2 Tx", NULL, "codec_out0"},
 125        {"ssp2 Tx", NULL, "codec_out1"},
 126        {"codec_in0", NULL, "ssp2 Rx"},
 127        {"codec_in1", NULL, "ssp2 Rx"},
 128        {"ssp2 Rx", NULL, "AIF1 Capture"},
 129        {"Headphone", NULL, "Platform Clock"},
 130        {"Headset Mic", NULL, "Platform Clock"},
 131        {"Int Mic", NULL, "Platform Clock"},
 132        {"Ext Spk", NULL, "Platform Clock"},
 133};
 134
 135static const struct snd_kcontrol_new cht_mc_controls[] = {
 136        SOC_DAPM_PIN_SWITCH("Headphone"),
 137        SOC_DAPM_PIN_SWITCH("Headset Mic"),
 138        SOC_DAPM_PIN_SWITCH("Int Mic"),
 139        SOC_DAPM_PIN_SWITCH("Ext Spk"),
 140};
 141
 142static int cht_aif1_hw_params(struct snd_pcm_substream *substream,
 143                                        struct snd_pcm_hw_params *params)
 144{
 145        struct snd_soc_pcm_runtime *rtd = substream->private_data;
 146        struct snd_soc_dai *codec_dai = rtd->codec_dai;
 147        int ret;
 148
 149        /* set codec PLL source to the 19.2MHz platform clock (MCLK) */
 150        ret = snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_MCLK,
 151                                  CHT_PLAT_CLK_3_HZ, params_rate(params) * 512);
 152        if (ret < 0) {
 153                dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
 154                return ret;
 155        }
 156
 157        /* set codec sysclk source to PLL */
 158        ret = snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_PLL1,
 159                                     params_rate(params) * 512,
 160                                     SND_SOC_CLOCK_IN);
 161        if (ret < 0) {
 162                dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
 163                return ret;
 164        }
 165        return 0;
 166}
 167
 168static const struct acpi_gpio_params headset_gpios = { 0, 0, false };
 169
 170static const struct acpi_gpio_mapping cht_rt5672_gpios[] = {
 171        { "headset-gpios", &headset_gpios, 1 },
 172        {},
 173};
 174
 175static int cht_codec_init(struct snd_soc_pcm_runtime *runtime)
 176{
 177        int ret;
 178        struct snd_soc_dai *codec_dai = runtime->codec_dai;
 179        struct snd_soc_component *component = codec_dai->component;
 180        struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card);
 181
 182        if (devm_acpi_dev_add_driver_gpios(component->dev, cht_rt5672_gpios))
 183                dev_warn(runtime->dev, "Unable to add GPIO mapping table\n");
 184
 185        /* Select codec ASRC clock source to track I2S1 clock, because codec
 186         * is in slave mode and 100fs I2S format (BCLK = 100 * LRCLK) cannot
 187         * be supported by RT5672. Otherwise, ASRC will be disabled and cause
 188         * noise.
 189         */
 190        rt5670_sel_asrc_clk_src(component,
 191                                RT5670_DA_STEREO_FILTER
 192                                | RT5670_DA_MONO_L_FILTER
 193                                | RT5670_DA_MONO_R_FILTER
 194                                | RT5670_AD_STEREO_FILTER
 195                                | RT5670_AD_MONO_L_FILTER
 196                                | RT5670_AD_MONO_R_FILTER,
 197                                RT5670_CLK_SEL_I2S1_ASRC);
 198
 199        ret = snd_soc_card_jack_new(runtime->card, "Headset",
 200                                    SND_JACK_HEADSET | SND_JACK_BTN_0 |
 201                                    SND_JACK_BTN_1 | SND_JACK_BTN_2,
 202                                    &ctx->headset,
 203                                    cht_bsw_headset_pins,
 204                                    ARRAY_SIZE(cht_bsw_headset_pins));
 205        if (ret)
 206                return ret;
 207
 208        snd_jack_set_key(ctx->headset.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
 209        snd_jack_set_key(ctx->headset.jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
 210        snd_jack_set_key(ctx->headset.jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
 211
 212        rt5670_set_jack_detect(component, &ctx->headset);
 213        if (ctx->mclk) {
 214                /*
 215                 * The firmware might enable the clock at
 216                 * boot (this information may or may not
 217                 * be reflected in the enable clock register).
 218                 * To change the rate we must disable the clock
 219                 * first to cover these cases. Due to common
 220                 * clock framework restrictions that do not allow
 221                 * to disable a clock that has not been enabled,
 222                 * we need to enable the clock first.
 223                 */
 224                ret = clk_prepare_enable(ctx->mclk);
 225                if (!ret)
 226                        clk_disable_unprepare(ctx->mclk);
 227
 228                ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
 229
 230                if (ret) {
 231                        dev_err(runtime->dev, "unable to set MCLK rate\n");
 232                        return ret;
 233                }
 234        }
 235        return 0;
 236}
 237
 238static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd,
 239                            struct snd_pcm_hw_params *params)
 240{
 241        struct snd_interval *rate = hw_param_interval(params,
 242                        SNDRV_PCM_HW_PARAM_RATE);
 243        struct snd_interval *channels = hw_param_interval(params,
 244                                                SNDRV_PCM_HW_PARAM_CHANNELS);
 245        int ret;
 246
 247        /* The DSP will covert the FE rate to 48k, stereo, 24bits */
 248        rate->min = rate->max = 48000;
 249        channels->min = channels->max = 2;
 250
 251        /* set SSP2 to 24-bit */
 252        params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
 253
 254        /*
 255         * Default mode for SSP configuration is TDM 4 slot
 256         */
 257        ret = snd_soc_dai_set_fmt(rtd->codec_dai,
 258                                  SND_SOC_DAIFMT_DSP_B |
 259                                  SND_SOC_DAIFMT_IB_NF |
 260                                  SND_SOC_DAIFMT_CBS_CFS);
 261        if (ret < 0) {
 262                dev_err(rtd->dev, "can't set format to TDM %d\n", ret);
 263                return ret;
 264        }
 265
 266        /* TDM 4 slots 24 bit, set Rx & Tx bitmask to 4 active slots */
 267        ret = snd_soc_dai_set_tdm_slot(rtd->codec_dai, 0xF, 0xF, 4, 24);
 268        if (ret < 0) {
 269                dev_err(rtd->dev, "can't set codec TDM slot %d\n", ret);
 270                return ret;
 271        }
 272
 273        return 0;
 274}
 275
 276static int cht_aif1_startup(struct snd_pcm_substream *substream)
 277{
 278        return snd_pcm_hw_constraint_single(substream->runtime,
 279                        SNDRV_PCM_HW_PARAM_RATE, 48000);
 280}
 281
 282static const struct snd_soc_ops cht_aif1_ops = {
 283        .startup = cht_aif1_startup,
 284};
 285
 286static const struct snd_soc_ops cht_be_ssp2_ops = {
 287        .hw_params = cht_aif1_hw_params,
 288};
 289
 290SND_SOC_DAILINK_DEF(dummy,
 291        DAILINK_COMP_ARRAY(COMP_DUMMY()));
 292
 293SND_SOC_DAILINK_DEF(media,
 294        DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
 295
 296SND_SOC_DAILINK_DEF(deepbuffer,
 297        DAILINK_COMP_ARRAY(COMP_CPU("deepbuffer-cpu-dai")));
 298
 299SND_SOC_DAILINK_DEF(ssp2_port,
 300        DAILINK_COMP_ARRAY(COMP_CPU("ssp2-port")));
 301SND_SOC_DAILINK_DEF(ssp2_codec,
 302        DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5670:00",
 303                                      "rt5670-aif1")));
 304
 305SND_SOC_DAILINK_DEF(platform,
 306        DAILINK_COMP_ARRAY(COMP_PLATFORM("sst-mfld-platform")));
 307
 308static struct snd_soc_dai_link cht_dailink[] = {
 309        /* Front End DAI links */
 310        [MERR_DPCM_AUDIO] = {
 311                .name = "Audio Port",
 312                .stream_name = "Audio",
 313                .nonatomic = true,
 314                .dynamic = 1,
 315                .dpcm_playback = 1,
 316                .dpcm_capture = 1,
 317                .ops = &cht_aif1_ops,
 318                SND_SOC_DAILINK_REG(media, dummy, platform),
 319        },
 320        [MERR_DPCM_DEEP_BUFFER] = {
 321                .name = "Deep-Buffer Audio Port",
 322                .stream_name = "Deep-Buffer Audio",
 323                .nonatomic = true,
 324                .dynamic = 1,
 325                .dpcm_playback = 1,
 326                .ops = &cht_aif1_ops,
 327                SND_SOC_DAILINK_REG(deepbuffer, dummy, platform),
 328        },
 329
 330        /* Back End DAI links */
 331        {
 332                /* SSP2 - Codec */
 333                .name = "SSP2-Codec",
 334                .id = 0,
 335                .no_pcm = 1,
 336                .nonatomic = true,
 337                .init = cht_codec_init,
 338                .be_hw_params_fixup = cht_codec_fixup,
 339                .dpcm_playback = 1,
 340                .dpcm_capture = 1,
 341                .ops = &cht_be_ssp2_ops,
 342                SND_SOC_DAILINK_REG(ssp2_port, ssp2_codec, platform),
 343        },
 344};
 345
 346static int cht_suspend_pre(struct snd_soc_card *card)
 347{
 348        struct snd_soc_component *component;
 349        struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card);
 350
 351        for_each_card_components(card, component) {
 352                if (!strncmp(component->name,
 353                             ctx->codec_name, sizeof(ctx->codec_name))) {
 354
 355                        dev_dbg(component->dev, "disabling jack detect before going to suspend.\n");
 356                        rt5670_jack_suspend(component);
 357                        break;
 358                }
 359        }
 360        return 0;
 361}
 362
 363static int cht_resume_post(struct snd_soc_card *card)
 364{
 365        struct snd_soc_component *component;
 366        struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card);
 367
 368        for_each_card_components(card, component) {
 369                if (!strncmp(component->name,
 370                             ctx->codec_name, sizeof(ctx->codec_name))) {
 371
 372                        dev_dbg(component->dev, "enabling jack detect for resume.\n");
 373                        rt5670_jack_resume(component);
 374                        break;
 375                }
 376        }
 377
 378        return 0;
 379}
 380
 381/* SoC card */
 382static struct snd_soc_card snd_soc_card_cht = {
 383        .name = "cht-bsw-rt5672",
 384        .owner = THIS_MODULE,
 385        .dai_link = cht_dailink,
 386        .num_links = ARRAY_SIZE(cht_dailink),
 387        .dapm_widgets = cht_dapm_widgets,
 388        .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets),
 389        .dapm_routes = cht_audio_map,
 390        .num_dapm_routes = ARRAY_SIZE(cht_audio_map),
 391        .controls = cht_mc_controls,
 392        .num_controls = ARRAY_SIZE(cht_mc_controls),
 393        .suspend_pre = cht_suspend_pre,
 394        .resume_post = cht_resume_post,
 395};
 396
 397#define RT5672_I2C_DEFAULT      "i2c-10EC5670:00"
 398
 399static int snd_cht_mc_probe(struct platform_device *pdev)
 400{
 401        int ret_val = 0;
 402        struct cht_mc_private *drv;
 403        struct snd_soc_acpi_mach *mach = pdev->dev.platform_data;
 404        const char *platform_name;
 405        struct acpi_device *adev;
 406        int i;
 407
 408        drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
 409        if (!drv)
 410                return -ENOMEM;
 411
 412        strcpy(drv->codec_name, RT5672_I2C_DEFAULT);
 413
 414        /* fixup codec name based on HID */
 415        adev = acpi_dev_get_first_match_dev(mach->id, NULL, -1);
 416        if (adev) {
 417                snprintf(drv->codec_name, sizeof(drv->codec_name),
 418                         "i2c-%s", acpi_dev_name(adev));
 419                put_device(&adev->dev);
 420                for (i = 0; i < ARRAY_SIZE(cht_dailink); i++) {
 421                        if (!strcmp(cht_dailink[i].codecs->name,
 422                                    RT5672_I2C_DEFAULT)) {
 423                                cht_dailink[i].codecs->name = drv->codec_name;
 424                                break;
 425                        }
 426                }
 427        }
 428
 429        /* override plaform name, if required */
 430        snd_soc_card_cht.dev = &pdev->dev;
 431        platform_name = mach->mach_params.platform;
 432
 433        ret_val = snd_soc_fixup_dai_links_platform_name(&snd_soc_card_cht,
 434                                                        platform_name);
 435        if (ret_val)
 436                return ret_val;
 437
 438        drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");
 439        if (IS_ERR(drv->mclk)) {
 440                dev_err(&pdev->dev,
 441                        "Failed to get MCLK from pmc_plt_clk_3: %ld\n",
 442                        PTR_ERR(drv->mclk));
 443                return PTR_ERR(drv->mclk);
 444        }
 445        snd_soc_card_set_drvdata(&snd_soc_card_cht, drv);
 446
 447        /* register the soc card */
 448        ret_val = devm_snd_soc_register_card(&pdev->dev, &snd_soc_card_cht);
 449        if (ret_val) {
 450                dev_err(&pdev->dev,
 451                        "snd_soc_register_card failed %d\n", ret_val);
 452                return ret_val;
 453        }
 454        platform_set_drvdata(pdev, &snd_soc_card_cht);
 455        return ret_val;
 456}
 457
 458static struct platform_driver snd_cht_mc_driver = {
 459        .driver = {
 460                .name = "cht-bsw-rt5672",
 461        },
 462        .probe = snd_cht_mc_probe,
 463};
 464
 465module_platform_driver(snd_cht_mc_driver);
 466
 467MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver");
 468MODULE_AUTHOR("Subhransu S. Prusty, Mengdong Lin");
 469MODULE_LICENSE("GPL v2");
 470MODULE_ALIAS("platform:cht-bsw-rt5672");
 471