LXR linux/sound/soc/intel/common/sst-dsp.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Intel Smart Sound Technology (SST) Core
   4 *
   5 * Copyright (C) 2013, Intel Corporation. All rights reserved.
   6 */
   7
   8#ifndef __SOUND_SOC_SST_DSP_H
   9#define __SOUND_SOC_SST_DSP_H
  10
  11#include <linux/kernel.h>
  12#include <linux/types.h>
  13#include <linux/interrupt.h>
  14
  15/* SST Device IDs  */
  16#define SST_DEV_ID_LYNX_POINT           0x33C8
  17#define SST_DEV_ID_WILDCAT_POINT        0x3438
  18#define SST_DEV_ID_BYT                  0x0F28
  19
  20/* Supported SST DMA Devices */
  21#define SST_DMA_TYPE_DW         1
  22
  23/* autosuspend delay 5s*/
  24#define SST_RUNTIME_SUSPEND_DELAY       (5 * 1000)
  25
  26/* SST Shim register map
  27 * The register naming can differ between products. Some products also
  28 * contain extra functionality.
  29 */
  30#define SST_CSR                 0x00
  31#define SST_PISR                0x08
  32#define SST_PIMR                0x10
  33#define SST_ISRX                0x18
  34#define SST_ISRD                0x20
  35#define SST_IMRX                0x28
  36#define SST_IMRD                0x30
  37#define SST_IPCX                0x38 /* IPC IA -> SST */
  38#define SST_IPCD                0x40 /* IPC SST -> IA */
  39#define SST_ISRSC               0x48
  40#define SST_ISRLPESC            0x50
  41#define SST_IMRSC               0x58
  42#define SST_IMRLPESC            0x60
  43#define SST_IPCSC               0x68
  44#define SST_IPCLPESC            0x70
  45#define SST_CLKCTL              0x78
  46#define SST_CSR2                0x80
  47#define SST_LTRC                0xE0
  48#define SST_HMDC                0xE8
  49
  50#define SST_SHIM_BEGIN          SST_CSR
  51#define SST_SHIM_END            SST_HDMC
  52
  53#define SST_DBGO                0xF0
  54
  55#define SST_SHIM_SIZE           0x100
  56#define SST_PWMCTRL             0x1000
  57
  58/* SST Shim Register bits
  59 * The register bit naming can differ between products. Some products also
  60 * contain extra functionality.
  61 */
  62
  63/* CSR / CS */
  64#define SST_CSR_RST             (0x1 << 1)
  65#define SST_CSR_SBCS0           (0x1 << 2)
  66#define SST_CSR_SBCS1           (0x1 << 3)
  67#define SST_CSR_DCS(x)          (x << 4)
  68#define SST_CSR_DCS_MASK        (0x7 << 4)
  69#define SST_CSR_STALL           (0x1 << 10)
  70#define SST_CSR_S0IOCS          (0x1 << 21)
  71#define SST_CSR_S1IOCS          (0x1 << 23)
  72#define SST_CSR_LPCS            (0x1 << 31)
  73#define SST_CSR_24MHZ_LPCS      (SST_CSR_SBCS0 | SST_CSR_SBCS1 | SST_CSR_LPCS)
  74#define SST_CSR_24MHZ_NO_LPCS   (SST_CSR_SBCS0 | SST_CSR_SBCS1)
  75#define SST_BYT_CSR_RST         (0x1 << 0)
  76#define SST_BYT_CSR_VECTOR_SEL  (0x1 << 1)
  77#define SST_BYT_CSR_STALL       (0x1 << 2)
  78#define SST_BYT_CSR_PWAITMODE   (0x1 << 3)
  79
  80/*  ISRX / ISC */
  81#define SST_ISRX_BUSY           (0x1 << 1)
  82#define SST_ISRX_DONE           (0x1 << 0)
  83#define SST_BYT_ISRX_REQUEST    (0x1 << 1)
  84
  85/*  ISRD / ISD */
  86#define SST_ISRD_BUSY           (0x1 << 1)
  87#define SST_ISRD_DONE           (0x1 << 0)
  88
  89/* IMRX / IMC */
  90#define SST_IMRX_BUSY           (0x1 << 1)
  91#define SST_IMRX_DONE           (0x1 << 0)
  92#define SST_BYT_IMRX_REQUEST    (0x1 << 1)
  93
  94/* IMRD / IMD */
  95#define SST_IMRD_DONE           (0x1 << 0)
  96#define SST_IMRD_BUSY           (0x1 << 1)
  97#define SST_IMRD_SSP0           (0x1 << 16)
  98#define SST_IMRD_DMAC0          (0x1 << 21)
  99#define SST_IMRD_DMAC1          (0x1 << 22)
 100#define SST_IMRD_DMAC           (SST_IMRD_DMAC0 | SST_IMRD_DMAC1)
 101
 102/*  IPCX / IPCC */
 103#define SST_IPCX_DONE           (0x1 << 30)
 104#define SST_IPCX_BUSY           (0x1 << 31)
 105#define SST_BYT_IPCX_DONE       ((u64)0x1 << 62)
 106#define SST_BYT_IPCX_BUSY       ((u64)0x1 << 63)
 107
 108/*  IPCD */
 109#define SST_IPCD_DONE           (0x1 << 30)
 110#define SST_IPCD_BUSY           (0x1 << 31)
 111#define SST_BYT_IPCD_DONE       ((u64)0x1 << 62)
 112#define SST_BYT_IPCD_BUSY       ((u64)0x1 << 63)
 113
 114/* CLKCTL */
 115#define SST_CLKCTL_SMOS(x)      (x << 24)
 116#define SST_CLKCTL_MASK         (3 << 24)
 117#define SST_CLKCTL_DCPLCG       (1 << 18)
 118#define SST_CLKCTL_SCOE1        (1 << 17)
 119#define SST_CLKCTL_SCOE0        (1 << 16)
 120
 121/* CSR2 / CS2 */
 122#define SST_CSR2_SDFD_SSP0      (1 << 1)
 123#define SST_CSR2_SDFD_SSP1      (1 << 2)
 124
 125/* LTRC */
 126#define SST_LTRC_VAL(x)         (x << 0)
 127
 128/* HMDC */
 129#define SST_HMDC_HDDA0(x)       (x << 0)
 130#define SST_HMDC_HDDA1(x)       (x << 7)
 131#define SST_HMDC_HDDA_E0_CH0    1
 132#define SST_HMDC_HDDA_E0_CH1    2
 133#define SST_HMDC_HDDA_E0_CH2    4
 134#define SST_HMDC_HDDA_E0_CH3    8
 135#define SST_HMDC_HDDA_E1_CH0    SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH0)
 136#define SST_HMDC_HDDA_E1_CH1    SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH1)
 137#define SST_HMDC_HDDA_E1_CH2    SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH2)
 138#define SST_HMDC_HDDA_E1_CH3    SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH3)
 139#define SST_HMDC_HDDA_E0_ALLCH  (SST_HMDC_HDDA_E0_CH0 | SST_HMDC_HDDA_E0_CH1 | \
 140                                 SST_HMDC_HDDA_E0_CH2 | SST_HMDC_HDDA_E0_CH3)
 141#define SST_HMDC_HDDA_E1_ALLCH  (SST_HMDC_HDDA_E1_CH0 | SST_HMDC_HDDA_E1_CH1 | \
 142                                 SST_HMDC_HDDA_E1_CH2 | SST_HMDC_HDDA_E1_CH3)
 143
 144
 145/* SST Vendor Defined Registers and bits */
 146#define SST_VDRTCTL0            0xa0
 147#define SST_VDRTCTL1            0xa4
 148#define SST_VDRTCTL2            0xa8
 149#define SST_VDRTCTL3            0xaC
 150
 151/* VDRTCTL0 */
 152#define SST_VDRTCL0_D3PGD               (1 << 0)
 153#define SST_VDRTCL0_D3SRAMPGD           (1 << 1)
 154#define SST_VDRTCL0_DSRAMPGE_SHIFT      12
 155#define SST_VDRTCL0_DSRAMPGE_MASK       (0xfffff << SST_VDRTCL0_DSRAMPGE_SHIFT)
 156#define SST_VDRTCL0_ISRAMPGE_SHIFT      2
 157#define SST_VDRTCL0_ISRAMPGE_MASK       (0x3ff << SST_VDRTCL0_ISRAMPGE_SHIFT)
 158
 159/* VDRTCTL2 */
 160#define SST_VDRTCL2_DCLCGE              (1 << 1)
 161#define SST_VDRTCL2_DTCGE               (1 << 10)
 162#define SST_VDRTCL2_APLLSE_MASK         (1 << 31)
 163
 164/* PMCS */
 165#define SST_PMCS                0x84
 166#define SST_PMCS_PS_MASK        0x3
 167
 168struct sst_dsp;
 169
 170/*
 171 * SST Device.
 172 *
 173 * This structure is populated by the SST core driver.
 174 */
 175struct sst_dsp_device {
 176        /* Mandatory fields */
 177        struct sst_ops *ops;
 178        irqreturn_t (*thread)(int irq, void *context);
 179        void *thread_context;
 180};
 181
 182/*
 183 * SST Platform Data.
 184 */
 185struct sst_pdata {
 186        /* ACPI data */
 187        u32 lpe_base;
 188        u32 lpe_size;
 189        u32 pcicfg_base;
 190        u32 pcicfg_size;
 191        u32 fw_base;
 192        u32 fw_size;
 193        int irq;
 194
 195        /* Firmware */
 196        const struct firmware *fw;
 197
 198        /* DMA */
 199        int resindex_dma_base; /* other fields invalid if equals to -1 */
 200        u32 dma_base;
 201        u32 dma_size;
 202        int dma_engine;
 203        struct device *dma_dev;
 204
 205        /* DSP */
 206        u32 id;
 207        void *dsp;
 208};
 209
 210#if IS_ENABLED(CONFIG_DW_DMAC_CORE)
 211/* Initialization */
 212struct sst_dsp *sst_dsp_new(struct device *dev,
 213        struct sst_dsp_device *sst_dev, struct sst_pdata *pdata);
 214void sst_dsp_free(struct sst_dsp *sst);
 215#endif
 216
 217/* SHIM Read / Write */
 218void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value);
 219u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset);
 220int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
 221                                u32 mask, u32 value);
 222void sst_dsp_shim_write64(struct sst_dsp *sst, u32 offset, u64 value);
 223u64 sst_dsp_shim_read64(struct sst_dsp *sst, u32 offset);
 224int sst_dsp_shim_update_bits64(struct sst_dsp *sst, u32 offset,
 225                                u64 mask, u64 value);
 226void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
 227                                u32 mask, u32 value);
 228
 229/* SHIM Read / Write Unlocked for callers already holding sst lock */
 230void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value);
 231u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset);
 232int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
 233                                u32 mask, u32 value);
 234void sst_dsp_shim_write64_unlocked(struct sst_dsp *sst, u32 offset, u64 value);
 235u64 sst_dsp_shim_read64_unlocked(struct sst_dsp *sst, u32 offset);
 236int sst_dsp_shim_update_bits64_unlocked(struct sst_dsp *sst, u32 offset,
 237                                        u64 mask, u64 value);
 238void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
 239                                u32 mask, u32 value);
 240
 241/* Internal generic low-level SST IO functions - can be overidden */
 242void sst_shim32_write(void __iomem *addr, u32 offset, u32 value);
 243u32 sst_shim32_read(void __iomem *addr, u32 offset);
 244void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value);
 245u64 sst_shim32_read64(void __iomem *addr, u32 offset);
 246void sst_memcpy_toio_32(struct sst_dsp *sst,
 247                        void __iomem *dest, void *src, size_t bytes);
 248void sst_memcpy_fromio_32(struct sst_dsp *sst,
 249                          void *dest, void __iomem *src, size_t bytes);
 250
 251/* DSP reset & boot */
 252void sst_dsp_reset(struct sst_dsp *sst);
 253int sst_dsp_boot(struct sst_dsp *sst);
 254int sst_dsp_wake(struct sst_dsp *sst);
 255void sst_dsp_sleep(struct sst_dsp *sst);
 256void sst_dsp_stall(struct sst_dsp *sst);
 257
 258/* DMA */
 259int sst_dsp_dma_get_channel(struct sst_dsp *dsp, int chan_id);
 260void sst_dsp_dma_put_channel(struct sst_dsp *dsp);
 261int sst_dsp_dma_copyfrom(struct sst_dsp *sst, dma_addr_t dest_addr,
 262        dma_addr_t src_addr, size_t size);
 263int sst_dsp_dma_copyto(struct sst_dsp *sst, dma_addr_t dest_addr,
 264        dma_addr_t src_addr, size_t size);
 265
 266/* Msg IO */
 267void sst_dsp_ipc_msg_tx(struct sst_dsp *dsp, u32 msg);
 268u32 sst_dsp_ipc_msg_rx(struct sst_dsp *dsp);
 269
 270/* Mailbox management */
 271int sst_dsp_mailbox_init(struct sst_dsp *dsp, u32 inbox_offset,
 272        size_t inbox_size, u32 outbox_offset, size_t outbox_size);
 273void sst_dsp_inbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
 274void sst_dsp_inbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
 275void sst_dsp_outbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
 276void sst_dsp_outbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
 277void sst_dsp_mailbox_dump(struct sst_dsp *dsp, size_t bytes);
 278int sst_dsp_register_poll(struct sst_dsp  *dsp, u32 offset, u32 mask,
 279                 u32 expected_value, u32 timeout, char *operation);
 280
 281/* Debug */
 282void sst_dsp_dump(struct sst_dsp *sst);
 283
 284#endif
 285