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18#include <linux/module.h>
19#include <linux/delay.h>
20#include <linux/firmware.h>
21#include <linux/device.h>
22
23#include "../common/sst-dsp.h"
24#include "../common/sst-dsp-priv.h"
25#include "../common/sst-ipc.h"
26#include "cnl-sst-dsp.h"
27#include "skl-sst-dsp.h"
28#include "skl-sst-ipc.h"
29
30#define CNL_FW_ROM_INIT 0x1
31#define CNL_FW_INIT 0x5
32#define CNL_IPC_PURGE 0x01004000
33#define CNL_INIT_TIMEOUT 300
34#define CNL_BASEFW_TIMEOUT 3000
35
36#define CNL_ADSP_SRAM0_BASE 0x80000
37
38
39#define CNL_ADSP_FW_STATUS CNL_ADSP_SRAM0_BASE
40#define CNL_ADSP_ERROR_CODE (CNL_ADSP_FW_STATUS + 0x4)
41
42#define CNL_INSTANCE_ID 0
43#define CNL_BASE_FW_MODULE_ID 0
44#define CNL_ADSP_FW_HDR_OFFSET 0x2000
45#define CNL_ROM_CTRL_DMA_ID 0x9
46
47static int cnl_prepare_fw(struct sst_dsp *ctx, const void *fwdata, u32 fwsize)
48{
49
50 int ret, stream_tag;
51
52 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
53 if (stream_tag <= 0) {
54 dev_err(ctx->dev, "dma prepare failed: 0%#x\n", stream_tag);
55 return stream_tag;
56 }
57
58 ctx->dsp_ops.stream_tag = stream_tag;
59 memcpy(ctx->dmab.area, fwdata, fwsize);
60
61
62 sst_dsp_shim_write(ctx, CNL_ADSP_REG_HIPCIDR,
63 CNL_ADSP_REG_HIPCIDR_BUSY | (CNL_IPC_PURGE |
64 ((stream_tag - 1) << CNL_ROM_CTRL_DMA_ID)));
65
66 ret = cnl_dsp_enable_core(ctx, SKL_DSP_CORE0_MASK);
67 if (ret < 0) {
68 dev_err(ctx->dev, "dsp boot core failed ret: %d\n", ret);
69 ret = -EIO;
70 goto base_fw_load_failed;
71 }
72
73
74 cnl_ipc_int_enable(ctx);
75 cnl_ipc_op_int_enable(ctx);
76
77 ret = sst_dsp_register_poll(ctx, CNL_ADSP_FW_STATUS, CNL_FW_STS_MASK,
78 CNL_FW_ROM_INIT, CNL_INIT_TIMEOUT,
79 "rom load");
80 if (ret < 0) {
81 dev_err(ctx->dev, "rom init timeout, ret: %d\n", ret);
82 goto base_fw_load_failed;
83 }
84
85 return 0;
86
87base_fw_load_failed:
88 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
89 cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
90
91 return ret;
92}
93
94static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
95{
96 int ret;
97
98 ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
99 ret = sst_dsp_register_poll(ctx, CNL_ADSP_FW_STATUS, CNL_FW_STS_MASK,
100 CNL_FW_INIT, CNL_BASEFW_TIMEOUT,
101 "firmware boot");
102
103 ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
104 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
105
106 return ret;
107}
108
109static int cnl_load_base_firmware(struct sst_dsp *ctx)
110{
111 struct firmware stripped_fw;
112 struct skl_sst *cnl = ctx->thread_context;
113 int ret;
114
115 if (!ctx->fw) {
116 ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
117 if (ret < 0) {
118 dev_err(ctx->dev, "request firmware failed: %d\n", ret);
119 goto cnl_load_base_firmware_failed;
120 }
121 }
122
123
124 if (cnl->is_first_boot) {
125 ret = snd_skl_parse_uuids(ctx, ctx->fw,
126 CNL_ADSP_FW_HDR_OFFSET, 0);
127 if (ret < 0)
128 goto cnl_load_base_firmware_failed;
129 }
130
131 stripped_fw.data = ctx->fw->data;
132 stripped_fw.size = ctx->fw->size;
133 skl_dsp_strip_extended_manifest(&stripped_fw);
134
135 ret = cnl_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
136 if (ret < 0) {
137 dev_err(ctx->dev, "prepare firmware failed: %d\n", ret);
138 goto cnl_load_base_firmware_failed;
139 }
140
141 ret = sst_transfer_fw_host_dma(ctx);
142 if (ret < 0) {
143 dev_err(ctx->dev, "transfer firmware failed: %d\n", ret);
144 cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
145 goto cnl_load_base_firmware_failed;
146 }
147
148 ret = wait_event_timeout(cnl->boot_wait, cnl->boot_complete,
149 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
150 if (ret == 0) {
151 dev_err(ctx->dev, "FW ready timed-out\n");
152 cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
153 ret = -EIO;
154 goto cnl_load_base_firmware_failed;
155 }
156
157 cnl->fw_loaded = true;
158
159 return 0;
160
161cnl_load_base_firmware_failed:
162 release_firmware(ctx->fw);
163 ctx->fw = NULL;
164
165 return ret;
166}
167
168static int cnl_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
169{
170 struct skl_sst *cnl = ctx->thread_context;
171 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
172 struct skl_ipc_dxstate_info dx;
173 int ret;
174
175 if (!cnl->fw_loaded) {
176 cnl->boot_complete = false;
177 ret = cnl_load_base_firmware(ctx);
178 if (ret < 0) {
179 dev_err(ctx->dev, "fw reload failed: %d\n", ret);
180 return ret;
181 }
182
183 cnl->cores.state[core_id] = SKL_DSP_RUNNING;
184 return ret;
185 }
186
187 ret = cnl_dsp_enable_core(ctx, core_mask);
188 if (ret < 0) {
189 dev_err(ctx->dev, "enable dsp core %d failed: %d\n",
190 core_id, ret);
191 goto err;
192 }
193
194 if (core_id == SKL_DSP_CORE0_ID) {
195
196 cnl_ipc_int_enable(ctx);
197 cnl_ipc_op_int_enable(ctx);
198 cnl->boot_complete = false;
199
200 ret = wait_event_timeout(cnl->boot_wait, cnl->boot_complete,
201 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
202 if (ret == 0) {
203 dev_err(ctx->dev,
204 "dsp boot timeout, status=%#x error=%#x\n",
205 sst_dsp_shim_read(ctx, CNL_ADSP_FW_STATUS),
206 sst_dsp_shim_read(ctx, CNL_ADSP_ERROR_CODE));
207 goto err;
208 }
209 } else {
210 dx.core_mask = core_mask;
211 dx.dx_mask = core_mask;
212
213 ret = skl_ipc_set_dx(&cnl->ipc, CNL_INSTANCE_ID,
214 CNL_BASE_FW_MODULE_ID, &dx);
215 if (ret < 0) {
216 dev_err(ctx->dev, "set_dx failed, core: %d ret: %d\n",
217 core_id, ret);
218 goto err;
219 }
220 }
221 cnl->cores.state[core_id] = SKL_DSP_RUNNING;
222
223 return 0;
224err:
225 cnl_dsp_disable_core(ctx, core_mask);
226
227 return ret;
228}
229
230static int cnl_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
231{
232 struct skl_sst *cnl = ctx->thread_context;
233 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
234 struct skl_ipc_dxstate_info dx;
235 int ret;
236
237 dx.core_mask = core_mask;
238 dx.dx_mask = SKL_IPC_D3_MASK;
239
240 ret = skl_ipc_set_dx(&cnl->ipc, CNL_INSTANCE_ID,
241 CNL_BASE_FW_MODULE_ID, &dx);
242 if (ret < 0) {
243 dev_err(ctx->dev,
244 "dsp core %d to d3 failed; continue reset\n",
245 core_id);
246 cnl->fw_loaded = false;
247 }
248
249
250 if (core_id == SKL_DSP_CORE0_ID) {
251 skl_ipc_op_int_disable(ctx);
252 skl_ipc_int_disable(ctx);
253 }
254
255 ret = cnl_dsp_disable_core(ctx, core_mask);
256 if (ret < 0) {
257 dev_err(ctx->dev, "disable dsp core %d failed: %d\n",
258 core_id, ret);
259 return ret;
260 }
261
262 cnl->cores.state[core_id] = SKL_DSP_RESET;
263
264 return ret;
265}
266
267static unsigned int cnl_get_errno(struct sst_dsp *ctx)
268{
269 return sst_dsp_shim_read(ctx, CNL_ADSP_ERROR_CODE);
270}
271
272static const struct skl_dsp_fw_ops cnl_fw_ops = {
273 .set_state_D0 = cnl_set_dsp_D0,
274 .set_state_D3 = cnl_set_dsp_D3,
275 .load_fw = cnl_load_base_firmware,
276 .get_fw_errcode = cnl_get_errno,
277};
278
279static struct sst_ops cnl_ops = {
280 .irq_handler = cnl_dsp_sst_interrupt,
281 .write = sst_shim32_write,
282 .read = sst_shim32_read,
283 .ram_read = sst_memcpy_fromio_32,
284 .ram_write = sst_memcpy_toio_32,
285 .free = cnl_dsp_free,
286};
287
288#define CNL_IPC_GLB_NOTIFY_RSP_SHIFT 29
289#define CNL_IPC_GLB_NOTIFY_RSP_MASK 0x1
290#define CNL_IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> CNL_IPC_GLB_NOTIFY_RSP_SHIFT) \
291 & CNL_IPC_GLB_NOTIFY_RSP_MASK)
292
293static irqreturn_t cnl_dsp_irq_thread_handler(int irq, void *context)
294{
295 struct sst_dsp *dsp = context;
296 struct skl_sst *cnl = sst_dsp_get_thread_context(dsp);
297 struct sst_generic_ipc *ipc = &cnl->ipc;
298 struct skl_ipc_header header = {0};
299 u32 hipcida, hipctdr, hipctdd;
300 int ipc_irq = 0;
301
302
303 if (!(dsp->intr_status & CNL_ADSPIS_IPC))
304 return IRQ_NONE;
305
306 hipcida = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDA);
307 hipctdr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDR);
308 hipctdd = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDD);
309
310
311 if (hipcida & CNL_ADSP_REG_HIPCIDA_DONE) {
312 sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL,
313 CNL_ADSP_REG_HIPCCTL_DONE, 0);
314
315
316 sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCIDA,
317 CNL_ADSP_REG_HIPCIDA_DONE, CNL_ADSP_REG_HIPCIDA_DONE);
318
319 ipc_irq = 1;
320
321
322 sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL,
323 CNL_ADSP_REG_HIPCCTL_DONE, CNL_ADSP_REG_HIPCCTL_DONE);
324 }
325
326
327 if (hipctdr & CNL_ADSP_REG_HIPCTDR_BUSY) {
328 header.primary = hipctdr;
329 header.extension = hipctdd;
330 dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x",
331 header.primary);
332 dev_dbg(dsp->dev, "IPC irq: Firmware respond extension:%x",
333 header.extension);
334
335 if (CNL_IPC_GLB_NOTIFY_RSP_TYPE(header.primary)) {
336
337 skl_ipc_process_reply(ipc, header);
338 } else {
339 dev_dbg(dsp->dev, "IPC irq: Notification from firmware\n");
340 skl_ipc_process_notification(ipc, header);
341 }
342
343 sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCTDR,
344 CNL_ADSP_REG_HIPCTDR_BUSY, CNL_ADSP_REG_HIPCTDR_BUSY);
345
346
347 sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCTDA,
348 CNL_ADSP_REG_HIPCTDA_DONE, CNL_ADSP_REG_HIPCTDA_DONE);
349 ipc_irq = 1;
350 }
351
352 if (ipc_irq == 0)
353 return IRQ_NONE;
354
355 cnl_ipc_int_enable(dsp);
356
357
358 schedule_work(&ipc->kwork);
359
360 return IRQ_HANDLED;
361}
362
363static struct sst_dsp_device cnl_dev = {
364 .thread = cnl_dsp_irq_thread_handler,
365 .ops = &cnl_ops,
366};
367
368static void cnl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
369{
370 struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->header);
371
372 if (msg->tx_size)
373 sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
374 sst_dsp_shim_write_unlocked(ipc->dsp, CNL_ADSP_REG_HIPCIDD,
375 header->extension);
376 sst_dsp_shim_write_unlocked(ipc->dsp, CNL_ADSP_REG_HIPCIDR,
377 header->primary | CNL_ADSP_REG_HIPCIDR_BUSY);
378}
379
380static bool cnl_ipc_is_dsp_busy(struct sst_dsp *dsp)
381{
382 u32 hipcidr;
383
384 hipcidr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDR);
385
386 return (hipcidr & CNL_ADSP_REG_HIPCIDR_BUSY);
387}
388
389static int cnl_ipc_init(struct device *dev, struct skl_sst *cnl)
390{
391 struct sst_generic_ipc *ipc;
392 int err;
393
394 ipc = &cnl->ipc;
395 ipc->dsp = cnl->dsp;
396 ipc->dev = dev;
397
398 ipc->tx_data_max_size = CNL_ADSP_W1_SZ;
399 ipc->rx_data_max_size = CNL_ADSP_W0_UP_SZ;
400
401 err = sst_ipc_init(ipc);
402 if (err)
403 return err;
404
405
406
407
408
409 ipc->ops.tx_msg = cnl_ipc_tx_msg;
410 ipc->ops.tx_data_copy = skl_ipc_tx_data_copy;
411 ipc->ops.is_dsp_busy = cnl_ipc_is_dsp_busy;
412
413 return 0;
414}
415
416int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
417 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
418 struct skl_sst **dsp)
419{
420 struct skl_sst *cnl;
421 struct sst_dsp *sst;
422 int ret;
423
424 ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &cnl_dev);
425 if (ret < 0) {
426 dev_err(dev, "%s: no device\n", __func__);
427 return ret;
428 }
429
430 cnl = *dsp;
431 sst = cnl->dsp;
432 sst->fw_ops = cnl_fw_ops;
433 sst->addr.lpe = mmio_base;
434 sst->addr.shim = mmio_base;
435 sst->addr.sram0_base = CNL_ADSP_SRAM0_BASE;
436 sst->addr.sram1_base = CNL_ADSP_SRAM1_BASE;
437 sst->addr.w0_stat_sz = CNL_ADSP_W0_STAT_SZ;
438 sst->addr.w0_up_sz = CNL_ADSP_W0_UP_SZ;
439
440 sst_dsp_mailbox_init(sst, (CNL_ADSP_SRAM0_BASE + CNL_ADSP_W0_STAT_SZ),
441 CNL_ADSP_W0_UP_SZ, CNL_ADSP_SRAM1_BASE,
442 CNL_ADSP_W1_SZ);
443
444 ret = cnl_ipc_init(dev, cnl);
445 if (ret) {
446 skl_dsp_free(sst);
447 return ret;
448 }
449
450 cnl->boot_complete = false;
451 init_waitqueue_head(&cnl->boot_wait);
452
453 return skl_dsp_acquire_irq(sst);
454}
455EXPORT_SYMBOL_GPL(cnl_sst_dsp_init);
456
457int cnl_sst_init_fw(struct device *dev, struct skl_sst *ctx)
458{
459 int ret;
460 struct sst_dsp *sst = ctx->dsp;
461
462 ret = ctx->dsp->fw_ops.load_fw(sst);
463 if (ret < 0) {
464 dev_err(dev, "load base fw failed: %d", ret);
465 return ret;
466 }
467
468 skl_dsp_init_core_state(sst);
469
470 ctx->is_first_boot = false;
471
472 return 0;
473}
474EXPORT_SYMBOL_GPL(cnl_sst_init_fw);
475
476void cnl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
477{
478 if (ctx->dsp->fw)
479 release_firmware(ctx->dsp->fw);
480
481 skl_freeup_uuid_list(ctx);
482 cnl_ipc_free(&ctx->ipc);
483
484 ctx->dsp->ops->free(ctx->dsp);
485}
486EXPORT_SYMBOL_GPL(cnl_sst_dsp_cleanup);
487
488MODULE_LICENSE("GPL v2");
489MODULE_DESCRIPTION("Intel Cannonlake IPC driver");
490
