LXR linux/sound/soc/intel/skylake/skl-sst-dsp.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Skylake SST DSP Support
   4 *
   5 * Copyright (C) 2014-15, Intel Corporation.
   6 */
   7
   8#ifndef __SKL_SST_DSP_H__
   9#define __SKL_SST_DSP_H__
  10
  11#include <linux/interrupt.h>
  12#include <linux/uuid.h>
  13#include <linux/firmware.h>
  14#include <sound/memalloc.h>
  15#include "skl-sst-cldma.h"
  16
  17struct sst_dsp;
  18struct skl_sst;
  19struct sst_dsp_device;
  20struct skl_lib_info;
  21
  22/* Intel HD Audio General DSP Registers */
  23#define SKL_ADSP_GEN_BASE               0x0
  24#define SKL_ADSP_REG_ADSPCS             (SKL_ADSP_GEN_BASE + 0x04)
  25#define SKL_ADSP_REG_ADSPIC             (SKL_ADSP_GEN_BASE + 0x08)
  26#define SKL_ADSP_REG_ADSPIS             (SKL_ADSP_GEN_BASE + 0x0C)
  27#define SKL_ADSP_REG_ADSPIC2            (SKL_ADSP_GEN_BASE + 0x10)
  28#define SKL_ADSP_REG_ADSPIS2            (SKL_ADSP_GEN_BASE + 0x14)
  29
  30/* Intel HD Audio Inter-Processor Communication Registers */
  31#define SKL_ADSP_IPC_BASE               0x40
  32#define SKL_ADSP_REG_HIPCT              (SKL_ADSP_IPC_BASE + 0x00)
  33#define SKL_ADSP_REG_HIPCTE             (SKL_ADSP_IPC_BASE + 0x04)
  34#define SKL_ADSP_REG_HIPCI              (SKL_ADSP_IPC_BASE + 0x08)
  35#define SKL_ADSP_REG_HIPCIE             (SKL_ADSP_IPC_BASE + 0x0C)
  36#define SKL_ADSP_REG_HIPCCTL            (SKL_ADSP_IPC_BASE + 0x10)
  37
  38/*  HIPCI */
  39#define SKL_ADSP_REG_HIPCI_BUSY         BIT(31)
  40
  41/* HIPCIE */
  42#define SKL_ADSP_REG_HIPCIE_DONE        BIT(30)
  43
  44/* HIPCCTL */
  45#define SKL_ADSP_REG_HIPCCTL_DONE       BIT(1)
  46#define SKL_ADSP_REG_HIPCCTL_BUSY       BIT(0)
  47
  48/* HIPCT */
  49#define SKL_ADSP_REG_HIPCT_BUSY         BIT(31)
  50
  51/* FW base IDs */
  52#define SKL_INSTANCE_ID                 0
  53#define SKL_BASE_FW_MODULE_ID           0
  54
  55/* Intel HD Audio SRAM Window 1 */
  56#define SKL_ADSP_SRAM1_BASE             0xA000
  57
  58#define SKL_ADSP_MMIO_LEN               0x10000
  59
  60#define SKL_ADSP_W0_STAT_SZ             0x1000
  61
  62#define SKL_ADSP_W0_UP_SZ               0x1000
  63
  64#define SKL_ADSP_W1_SZ                  0x1000
  65
  66#define SKL_FW_STS_MASK                 0xf
  67
  68#define SKL_FW_INIT                     0x1
  69#define SKL_FW_RFW_START                0xf
  70
  71#define SKL_ADSPIC_IPC                  1
  72#define SKL_ADSPIS_IPC                  1
  73
  74/* Core ID of core0 */
  75#define SKL_DSP_CORE0_ID                0
  76
  77/* Mask for a given core index, c = 0.. number of supported cores - 1 */
  78#define SKL_DSP_CORE_MASK(c)            BIT(c)
  79
  80/*
  81 * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately
  82 * since Core0 is primary core and it is used often
  83 */
  84#define SKL_DSP_CORE0_MASK              BIT(0)
  85
  86/*
  87 * Mask for a given number of cores
  88 * nc = number of supported cores
  89 */
  90#define SKL_DSP_CORES_MASK(nc)  GENMASK((nc - 1), 0)
  91
  92/* ADSPCS - Audio DSP Control & Status */
  93
  94/*
  95 * Core Reset - asserted high
  96 * CRST Mask for a given core mask pattern, cm
  97 */
  98#define SKL_ADSPCS_CRST_SHIFT           0
  99#define SKL_ADSPCS_CRST_MASK(cm)        ((cm) << SKL_ADSPCS_CRST_SHIFT)
 100
 101/*
 102 * Core run/stall - when set to '1' core is stalled
 103 * CSTALL Mask for a given core mask pattern, cm
 104 */
 105#define SKL_ADSPCS_CSTALL_SHIFT         8
 106#define SKL_ADSPCS_CSTALL_MASK(cm)      ((cm) << SKL_ADSPCS_CSTALL_SHIFT)
 107
 108/*
 109 * Set Power Active - when set to '1' turn cores on
 110 * SPA Mask for a given core mask pattern, cm
 111 */
 112#define SKL_ADSPCS_SPA_SHIFT            16
 113#define SKL_ADSPCS_SPA_MASK(cm)         ((cm) << SKL_ADSPCS_SPA_SHIFT)
 114
 115/*
 116 * Current Power Active - power status of cores, set by hardware
 117 * CPA Mask for a given core mask pattern, cm
 118 */
 119#define SKL_ADSPCS_CPA_SHIFT            24
 120#define SKL_ADSPCS_CPA_MASK(cm)         ((cm) << SKL_ADSPCS_CPA_SHIFT)
 121
 122/* DSP Core state */
 123enum skl_dsp_states {
 124        SKL_DSP_RUNNING = 1,
 125        /* Running in D0i3 state; can be in streaming or non-streaming D0i3 */
 126        SKL_DSP_RUNNING_D0I3, /* Running in D0i3 state*/
 127        SKL_DSP_RESET,
 128};
 129
 130/* D0i3 substates */
 131enum skl_dsp_d0i3_states {
 132        SKL_DSP_D0I3_NONE = -1, /* No D0i3 */
 133        SKL_DSP_D0I3_NON_STREAMING = 0,
 134        SKL_DSP_D0I3_STREAMING = 1,
 135};
 136
 137struct skl_dsp_fw_ops {
 138        int (*load_fw)(struct sst_dsp  *ctx);
 139        /* FW module parser/loader */
 140        int (*load_library)(struct sst_dsp *ctx,
 141                struct skl_lib_info *linfo, int lib_count);
 142        int (*parse_fw)(struct sst_dsp *ctx);
 143        int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id);
 144        int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id);
 145        int (*set_state_D0i3)(struct sst_dsp *ctx);
 146        int (*set_state_D0i0)(struct sst_dsp *ctx);
 147        unsigned int (*get_fw_errcode)(struct sst_dsp *ctx);
 148        int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name);
 149        int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id);
 150
 151};
 152
 153struct skl_dsp_loader_ops {
 154        int stream_tag;
 155
 156        int (*alloc_dma_buf)(struct device *dev,
 157                struct snd_dma_buffer *dmab, size_t size);
 158        int (*free_dma_buf)(struct device *dev,
 159                struct snd_dma_buffer *dmab);
 160        int (*prepare)(struct device *dev, unsigned int format,
 161                                unsigned int byte_size,
 162                                struct snd_dma_buffer *bufp);
 163        int (*trigger)(struct device *dev, bool start, int stream_tag);
 164
 165        int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab,
 166                                 int stream_tag);
 167};
 168
 169#define MAX_INSTANCE_BUFF 2
 170
 171struct uuid_module {
 172        guid_t uuid;
 173        int id;
 174        int is_loadable;
 175        int max_instance;
 176        u64 pvt_id[MAX_INSTANCE_BUFF];
 177        int *instance_id;
 178
 179        struct list_head list;
 180};
 181
 182struct skl_load_module_info {
 183        u16 mod_id;
 184        const struct firmware *fw;
 185};
 186
 187struct skl_module_table {
 188        struct skl_load_module_info *mod_info;
 189        unsigned int usage_cnt;
 190        struct list_head list;
 191};
 192
 193void skl_cldma_process_intr(struct sst_dsp *ctx);
 194void skl_cldma_int_disable(struct sst_dsp *ctx);
 195int skl_cldma_prepare(struct sst_dsp *ctx);
 196int skl_cldma_wait_interruptible(struct sst_dsp *ctx);
 197
 198void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state);
 199struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
 200                struct sst_dsp_device *sst_dev, int irq);
 201int skl_dsp_acquire_irq(struct sst_dsp *sst);
 202bool is_skl_dsp_running(struct sst_dsp *ctx);
 203
 204unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx);
 205void skl_dsp_init_core_state(struct sst_dsp *ctx);
 206int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask);
 207int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask);
 208int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask);
 209int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask);
 210int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx,
 211                                        unsigned int core_mask);
 212int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask);
 213
 214irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id);
 215int skl_dsp_wake(struct sst_dsp *ctx);
 216int skl_dsp_sleep(struct sst_dsp *ctx);
 217void skl_dsp_free(struct sst_dsp *dsp);
 218
 219int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id);
 220int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id);
 221
 222int skl_dsp_boot(struct sst_dsp *ctx);
 223int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 224                const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 225                struct skl_sst **dsp);
 226int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 227                const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 228                struct skl_sst **dsp);
 229int skl_sst_init_fw(struct device *dev, struct skl_sst *ctx);
 230int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx);
 231void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
 232void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
 233
 234int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw,
 235                                unsigned int offset, int index);
 236int skl_get_pvt_id(struct skl_sst *ctx, guid_t *uuid_mod, int instance_id);
 237int skl_put_pvt_id(struct skl_sst *ctx, guid_t *uuid_mod, int *pvt_id);
 238int skl_get_pvt_instance_id_map(struct skl_sst *ctx,
 239                                int module_id, int instance_id);
 240void skl_freeup_uuid_list(struct skl_sst *ctx);
 241
 242int skl_dsp_strip_extended_manifest(struct firmware *fw);
 243void skl_dsp_enable_notification(struct skl_sst *ctx, bool enable);
 244
 245void skl_dsp_set_astate_cfg(struct skl_sst *ctx, u32 cnt, void *data);
 246
 247int skl_sst_ctx_init(struct device *dev, int irq, const char *fw_name,
 248                struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp,
 249                struct sst_dsp_device *skl_dev);
 250int skl_prepare_lib_load(struct skl_sst *skl, struct skl_lib_info *linfo,
 251                        struct firmware *stripped_fw,
 252                        unsigned int hdr_offset, int index);
 253void skl_release_library(struct skl_lib_info *linfo, int lib_count);
 254
 255#endif /*__SKL_SST_DSP_H__*/
 256