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8#include <linux/regmap.h>
9#include <sound/pcm_params.h>
10#include "mt8183-afe-clk.h"
11#include "mt8183-afe-common.h"
12#include "mt8183-interconnection.h"
13#include "mt8183-reg.h"
14
15struct mtk_afe_tdm_priv {
16 int bck_id;
17 int bck_rate;
18
19 int mclk_id;
20 int mclk_multiple;
21 int mclk_rate;
22 int mclk_apll;
23};
24
25enum {
26 TDM_WLEN_16_BIT = 1,
27 TDM_WLEN_32_BIT = 2,
28};
29
30enum {
31 TDM_CHANNEL_BCK_16 = 0,
32 TDM_CHANNEL_BCK_24 = 1,
33 TDM_CHANNEL_BCK_32 = 2,
34};
35
36enum {
37 TDM_CHANNEL_NUM_2 = 0,
38 TDM_CHANNEL_NUM_4 = 1,
39 TDM_CHANNEL_NUM_8 = 2,
40};
41
42enum {
43 TDM_CH_START_O30_O31 = 0,
44 TDM_CH_START_O32_O33,
45 TDM_CH_START_O34_O35,
46 TDM_CH_START_O36_O37,
47 TDM_CH_ZERO,
48};
49
50enum {
51 HDMI_BIT_WIDTH_16_BIT = 0,
52 HDMI_BIT_WIDTH_32_BIT = 1,
53};
54
55static unsigned int get_hdmi_wlen(snd_pcm_format_t format)
56{
57 return snd_pcm_format_physical_width(format) <= 16 ?
58 HDMI_BIT_WIDTH_16_BIT : HDMI_BIT_WIDTH_32_BIT;
59}
60
61static unsigned int get_tdm_wlen(snd_pcm_format_t format)
62{
63 return snd_pcm_format_physical_width(format) <= 16 ?
64 TDM_WLEN_16_BIT : TDM_WLEN_32_BIT;
65}
66
67static unsigned int get_tdm_channel_bck(snd_pcm_format_t format)
68{
69 return snd_pcm_format_physical_width(format) <= 16 ?
70 TDM_CHANNEL_BCK_16 : TDM_CHANNEL_BCK_32;
71}
72
73static unsigned int get_tdm_lrck_width(snd_pcm_format_t format)
74{
75 return snd_pcm_format_physical_width(format) - 1;
76}
77
78static unsigned int get_tdm_ch(unsigned int ch)
79{
80 switch (ch) {
81 case 1:
82 case 2:
83 return TDM_CHANNEL_NUM_2;
84 case 3:
85 case 4:
86 return TDM_CHANNEL_NUM_4;
87 case 5:
88 case 6:
89 case 7:
90 case 8:
91 default:
92 return TDM_CHANNEL_NUM_8;
93 }
94}
95
96
97enum {
98 HDMI_CONN_CH0 = 0,
99 HDMI_CONN_CH1,
100 HDMI_CONN_CH2,
101 HDMI_CONN_CH3,
102 HDMI_CONN_CH4,
103 HDMI_CONN_CH5,
104 HDMI_CONN_CH6,
105 HDMI_CONN_CH7,
106};
107
108static const char *const hdmi_conn_mux_map[] = {
109 "CH0", "CH1", "CH2", "CH3",
110 "CH4", "CH5", "CH6", "CH7",
111};
112
113static int hdmi_conn_mux_map_value[] = {
114 HDMI_CONN_CH0,
115 HDMI_CONN_CH1,
116 HDMI_CONN_CH2,
117 HDMI_CONN_CH3,
118 HDMI_CONN_CH4,
119 HDMI_CONN_CH5,
120 HDMI_CONN_CH6,
121 HDMI_CONN_CH7,
122};
123
124static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
125 AFE_HDMI_CONN0,
126 HDMI_O_0_SFT,
127 HDMI_O_0_MASK,
128 hdmi_conn_mux_map,
129 hdmi_conn_mux_map_value);
130
131static const struct snd_kcontrol_new hdmi_ch0_mux_control =
132 SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
133
134static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
135 AFE_HDMI_CONN0,
136 HDMI_O_1_SFT,
137 HDMI_O_1_MASK,
138 hdmi_conn_mux_map,
139 hdmi_conn_mux_map_value);
140
141static const struct snd_kcontrol_new hdmi_ch1_mux_control =
142 SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
143
144static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
145 AFE_HDMI_CONN0,
146 HDMI_O_2_SFT,
147 HDMI_O_2_MASK,
148 hdmi_conn_mux_map,
149 hdmi_conn_mux_map_value);
150
151static const struct snd_kcontrol_new hdmi_ch2_mux_control =
152 SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
153
154static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
155 AFE_HDMI_CONN0,
156 HDMI_O_3_SFT,
157 HDMI_O_3_MASK,
158 hdmi_conn_mux_map,
159 hdmi_conn_mux_map_value);
160
161static const struct snd_kcontrol_new hdmi_ch3_mux_control =
162 SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
163
164static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
165 AFE_HDMI_CONN0,
166 HDMI_O_4_SFT,
167 HDMI_O_4_MASK,
168 hdmi_conn_mux_map,
169 hdmi_conn_mux_map_value);
170
171static const struct snd_kcontrol_new hdmi_ch4_mux_control =
172 SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
173
174static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
175 AFE_HDMI_CONN0,
176 HDMI_O_5_SFT,
177 HDMI_O_5_MASK,
178 hdmi_conn_mux_map,
179 hdmi_conn_mux_map_value);
180
181static const struct snd_kcontrol_new hdmi_ch5_mux_control =
182 SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
183
184static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
185 AFE_HDMI_CONN0,
186 HDMI_O_6_SFT,
187 HDMI_O_6_MASK,
188 hdmi_conn_mux_map,
189 hdmi_conn_mux_map_value);
190
191static const struct snd_kcontrol_new hdmi_ch6_mux_control =
192 SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
193
194static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
195 AFE_HDMI_CONN0,
196 HDMI_O_7_SFT,
197 HDMI_O_7_MASK,
198 hdmi_conn_mux_map,
199 hdmi_conn_mux_map_value);
200
201static const struct snd_kcontrol_new hdmi_ch7_mux_control =
202 SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
203
204enum {
205 SUPPLY_SEQ_APLL,
206 SUPPLY_SEQ_TDM_MCK_EN,
207 SUPPLY_SEQ_TDM_BCK_EN,
208};
209
210static int mtk_tdm_bck_en_event(struct snd_soc_dapm_widget *w,
211 struct snd_kcontrol *kcontrol,
212 int event)
213{
214 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
215 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
216 struct mt8183_afe_private *afe_priv = afe->platform_priv;
217 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
218
219 dev_info(cmpnt->dev, "%s(), name %s, event 0x%x\n",
220 __func__, w->name, event);
221
222 switch (event) {
223 case SND_SOC_DAPM_PRE_PMU:
224 mt8183_mck_enable(afe, tdm_priv->bck_id, tdm_priv->bck_rate);
225 break;
226 case SND_SOC_DAPM_POST_PMD:
227 mt8183_mck_disable(afe, tdm_priv->bck_id);
228 break;
229 default:
230 break;
231 }
232
233 return 0;
234}
235
236static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w,
237 struct snd_kcontrol *kcontrol,
238 int event)
239{
240 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
241 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
242 struct mt8183_afe_private *afe_priv = afe->platform_priv;
243 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
244
245 dev_info(cmpnt->dev, "%s(), name %s, event 0x%x\n",
246 __func__, w->name, event);
247
248 switch (event) {
249 case SND_SOC_DAPM_PRE_PMU:
250 mt8183_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate);
251 break;
252 case SND_SOC_DAPM_POST_PMD:
253 tdm_priv->mclk_rate = 0;
254 mt8183_mck_disable(afe, tdm_priv->mclk_id);
255 break;
256 default:
257 break;
258 }
259
260 return 0;
261}
262
263static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = {
264 SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
265 &hdmi_ch0_mux_control),
266 SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
267 &hdmi_ch1_mux_control),
268 SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
269 &hdmi_ch2_mux_control),
270 SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
271 &hdmi_ch3_mux_control),
272 SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
273 &hdmi_ch4_mux_control),
274 SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
275 &hdmi_ch5_mux_control),
276 SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
277 &hdmi_ch6_mux_control),
278 SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
279 &hdmi_ch7_mux_control),
280
281 SND_SOC_DAPM_CLOCK_SUPPLY("aud_tdm_clk"),
282
283 SND_SOC_DAPM_SUPPLY_S("TDM_BCK", SUPPLY_SEQ_TDM_BCK_EN,
284 SND_SOC_NOPM, 0, 0,
285 mtk_tdm_bck_en_event,
286 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
287
288 SND_SOC_DAPM_SUPPLY_S("TDM_MCK", SUPPLY_SEQ_TDM_MCK_EN,
289 SND_SOC_NOPM, 0, 0,
290 mtk_tdm_mck_en_event,
291 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
292};
293
294static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source,
295 struct snd_soc_dapm_widget *sink)
296{
297 struct snd_soc_dapm_widget *w = sink;
298 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
299 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
300 struct mt8183_afe_private *afe_priv = afe->platform_priv;
301 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
302 int cur_apll;
303
304
305 cur_apll = mt8183_get_apll_by_name(afe, source->name);
306
307 return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0;
308}
309
310static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = {
311 {"HDMI_CH0_MUX", "CH0", "HDMI"},
312 {"HDMI_CH0_MUX", "CH1", "HDMI"},
313 {"HDMI_CH0_MUX", "CH2", "HDMI"},
314 {"HDMI_CH0_MUX", "CH3", "HDMI"},
315 {"HDMI_CH0_MUX", "CH4", "HDMI"},
316 {"HDMI_CH0_MUX", "CH5", "HDMI"},
317 {"HDMI_CH0_MUX", "CH6", "HDMI"},
318 {"HDMI_CH0_MUX", "CH7", "HDMI"},
319
320 {"HDMI_CH1_MUX", "CH0", "HDMI"},
321 {"HDMI_CH1_MUX", "CH1", "HDMI"},
322 {"HDMI_CH1_MUX", "CH2", "HDMI"},
323 {"HDMI_CH1_MUX", "CH3", "HDMI"},
324 {"HDMI_CH1_MUX", "CH4", "HDMI"},
325 {"HDMI_CH1_MUX", "CH5", "HDMI"},
326 {"HDMI_CH1_MUX", "CH6", "HDMI"},
327 {"HDMI_CH1_MUX", "CH7", "HDMI"},
328
329 {"HDMI_CH2_MUX", "CH0", "HDMI"},
330 {"HDMI_CH2_MUX", "CH1", "HDMI"},
331 {"HDMI_CH2_MUX", "CH2", "HDMI"},
332 {"HDMI_CH2_MUX", "CH3", "HDMI"},
333 {"HDMI_CH2_MUX", "CH4", "HDMI"},
334 {"HDMI_CH2_MUX", "CH5", "HDMI"},
335 {"HDMI_CH2_MUX", "CH6", "HDMI"},
336 {"HDMI_CH2_MUX", "CH7", "HDMI"},
337
338 {"HDMI_CH3_MUX", "CH0", "HDMI"},
339 {"HDMI_CH3_MUX", "CH1", "HDMI"},
340 {"HDMI_CH3_MUX", "CH2", "HDMI"},
341 {"HDMI_CH3_MUX", "CH3", "HDMI"},
342 {"HDMI_CH3_MUX", "CH4", "HDMI"},
343 {"HDMI_CH3_MUX", "CH5", "HDMI"},
344 {"HDMI_CH3_MUX", "CH6", "HDMI"},
345 {"HDMI_CH3_MUX", "CH7", "HDMI"},
346
347 {"HDMI_CH4_MUX", "CH0", "HDMI"},
348 {"HDMI_CH4_MUX", "CH1", "HDMI"},
349 {"HDMI_CH4_MUX", "CH2", "HDMI"},
350 {"HDMI_CH4_MUX", "CH3", "HDMI"},
351 {"HDMI_CH4_MUX", "CH4", "HDMI"},
352 {"HDMI_CH4_MUX", "CH5", "HDMI"},
353 {"HDMI_CH4_MUX", "CH6", "HDMI"},
354 {"HDMI_CH4_MUX", "CH7", "HDMI"},
355
356 {"HDMI_CH5_MUX", "CH0", "HDMI"},
357 {"HDMI_CH5_MUX", "CH1", "HDMI"},
358 {"HDMI_CH5_MUX", "CH2", "HDMI"},
359 {"HDMI_CH5_MUX", "CH3", "HDMI"},
360 {"HDMI_CH5_MUX", "CH4", "HDMI"},
361 {"HDMI_CH5_MUX", "CH5", "HDMI"},
362 {"HDMI_CH5_MUX", "CH6", "HDMI"},
363 {"HDMI_CH5_MUX", "CH7", "HDMI"},
364
365 {"HDMI_CH6_MUX", "CH0", "HDMI"},
366 {"HDMI_CH6_MUX", "CH1", "HDMI"},
367 {"HDMI_CH6_MUX", "CH2", "HDMI"},
368 {"HDMI_CH6_MUX", "CH3", "HDMI"},
369 {"HDMI_CH6_MUX", "CH4", "HDMI"},
370 {"HDMI_CH6_MUX", "CH5", "HDMI"},
371 {"HDMI_CH6_MUX", "CH6", "HDMI"},
372 {"HDMI_CH6_MUX", "CH7", "HDMI"},
373
374 {"HDMI_CH7_MUX", "CH0", "HDMI"},
375 {"HDMI_CH7_MUX", "CH1", "HDMI"},
376 {"HDMI_CH7_MUX", "CH2", "HDMI"},
377 {"HDMI_CH7_MUX", "CH3", "HDMI"},
378 {"HDMI_CH7_MUX", "CH4", "HDMI"},
379 {"HDMI_CH7_MUX", "CH5", "HDMI"},
380 {"HDMI_CH7_MUX", "CH6", "HDMI"},
381 {"HDMI_CH7_MUX", "CH7", "HDMI"},
382
383 {"TDM", NULL, "HDMI_CH0_MUX"},
384 {"TDM", NULL, "HDMI_CH1_MUX"},
385 {"TDM", NULL, "HDMI_CH2_MUX"},
386 {"TDM", NULL, "HDMI_CH3_MUX"},
387 {"TDM", NULL, "HDMI_CH4_MUX"},
388 {"TDM", NULL, "HDMI_CH5_MUX"},
389 {"TDM", NULL, "HDMI_CH6_MUX"},
390 {"TDM", NULL, "HDMI_CH7_MUX"},
391
392 {"TDM", NULL, "aud_tdm_clk"},
393 {"TDM", NULL, "TDM_BCK"},
394 {"TDM_BCK", NULL, "TDM_MCK"},
395 {"TDM_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},
396 {"TDM_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},
397};
398
399
400static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe,
401 struct mtk_afe_tdm_priv *tdm_priv,
402 int freq)
403{
404 int apll;
405 int apll_rate;
406
407 apll = mt8183_get_apll_by_rate(afe, freq);
408 apll_rate = mt8183_get_apll_rate(afe, apll);
409
410 if (!freq || freq > apll_rate) {
411 dev_warn(afe->dev,
412 "%s(), freq(%d Hz) invalid\n", __func__, freq);
413 return -EINVAL;
414 }
415
416 if (apll_rate % freq != 0) {
417 dev_warn(afe->dev,
418 "%s(), APLL cannot generate %d Hz", __func__, freq);
419 return -EINVAL;
420 }
421
422 tdm_priv->mclk_rate = freq;
423 tdm_priv->mclk_apll = apll;
424
425 return 0;
426}
427
428static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream,
429 struct snd_pcm_hw_params *params,
430 struct snd_soc_dai *dai)
431{
432 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
433 struct mt8183_afe_private *afe_priv = afe->platform_priv;
434 int tdm_id = dai->id;
435 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[tdm_id];
436 unsigned int rate = params_rate(params);
437 unsigned int channels = params_channels(params);
438 snd_pcm_format_t format = params_format(params);
439 unsigned int tdm_con = 0;
440
441
442 if (!tdm_priv->mclk_rate) {
443 tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple;
444 mtk_dai_tdm_cal_mclk(afe,
445 tdm_priv,
446 tdm_priv->mclk_rate);
447 }
448
449
450 tdm_priv->bck_rate = rate *
451 channels *
452 snd_pcm_format_physical_width(format);
453
454 if (tdm_priv->bck_rate > tdm_priv->mclk_rate)
455 dev_warn(afe->dev, "%s(), bck_rate > mclk_rate rate", __func__);
456
457 if (tdm_priv->mclk_rate % tdm_priv->bck_rate != 0)
458 dev_warn(afe->dev, "%s(), bck cannot generate", __func__);
459
460 dev_info(afe->dev, "%s(), id %d, rate %d, channels %d, format %d, mclk_rate %d, bck_rate %d\n",
461 __func__,
462 tdm_id, rate, channels, format,
463 tdm_priv->mclk_rate, tdm_priv->bck_rate);
464
465
466 tdm_con = 1 << BCK_INVERSE_SFT;
467 tdm_con |= 1 << LRCK_INVERSE_SFT;
468 tdm_con |= 1 << DELAY_DATA_SFT;
469 tdm_con |= 1 << LEFT_ALIGN_SFT;
470 tdm_con |= get_tdm_wlen(format) << WLEN_SFT;
471 tdm_con |= get_tdm_ch(channels) << CHANNEL_NUM_SFT;
472 tdm_con |= get_tdm_channel_bck(format) << CHANNEL_BCK_CYCLES_SFT;
473 tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT;
474 regmap_write(afe->regmap, AFE_TDM_CON1, tdm_con);
475
476 switch (channels) {
477 case 1:
478 case 2:
479 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
480 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;
481 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
482 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
483 break;
484 case 3:
485 case 4:
486 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
487 tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
488 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
489 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
490 break;
491 case 5:
492 case 6:
493 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
494 tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
495 tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
496 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
497 break;
498 case 7:
499 case 8:
500 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
501 tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
502 tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
503 tdm_con |= TDM_CH_START_O36_O37 << ST_CH_PAIR_SOUT3_SFT;
504 break;
505 default:
506 tdm_con = 0;
507 }
508 regmap_write(afe->regmap, AFE_TDM_CON2, tdm_con);
509
510 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
511 AFE_HDMI_OUT_CH_NUM_MASK_SFT,
512 channels << AFE_HDMI_OUT_CH_NUM_SFT);
513
514 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
515 AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT,
516 get_hdmi_wlen(format) << AFE_HDMI_OUT_BIT_WIDTH_SFT);
517 return 0;
518}
519
520static int mtk_dai_tdm_trigger(struct snd_pcm_substream *substream,
521 int cmd,
522 struct snd_soc_dai *dai)
523{
524 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
525
526 switch (cmd) {
527 case SNDRV_PCM_TRIGGER_START:
528 case SNDRV_PCM_TRIGGER_RESUME:
529
530 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
531 AFE_HDMI_OUT_ON_MASK_SFT,
532 0x1 << AFE_HDMI_OUT_ON_SFT);
533
534 regmap_update_bits(afe->regmap, AFE_TDM_CON1,
535 TDM_EN_MASK_SFT, 0x1 << TDM_EN_SFT);
536 break;
537 case SNDRV_PCM_TRIGGER_STOP:
538 case SNDRV_PCM_TRIGGER_SUSPEND:
539
540 regmap_update_bits(afe->regmap, AFE_TDM_CON1,
541 TDM_EN_MASK_SFT, 0);
542
543 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
544 AFE_HDMI_OUT_ON_MASK_SFT,
545 0);
546 break;
547 default:
548 return -EINVAL;
549 }
550
551 return 0;
552}
553
554static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai,
555 int clk_id, unsigned int freq, int dir)
556{
557 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
558 struct mt8183_afe_private *afe_priv = afe->platform_priv;
559 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
560
561 if (!tdm_priv) {
562 dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
563 return -EINVAL;
564 }
565
566 if (dir != SND_SOC_CLOCK_OUT) {
567 dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
568 return -EINVAL;
569 }
570
571 dev_info(afe->dev, "%s(), freq %d\n", __func__, freq);
572
573 return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq);
574}
575
576static const struct snd_soc_dai_ops mtk_dai_tdm_ops = {
577 .hw_params = mtk_dai_tdm_hw_params,
578 .trigger = mtk_dai_tdm_trigger,
579 .set_sysclk = mtk_dai_tdm_set_sysclk,
580};
581
582
583#define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
584 SNDRV_PCM_RATE_88200 |\
585 SNDRV_PCM_RATE_96000 |\
586 SNDRV_PCM_RATE_176400 |\
587 SNDRV_PCM_RATE_192000)
588
589#define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
590 SNDRV_PCM_FMTBIT_S24_LE |\
591 SNDRV_PCM_FMTBIT_S32_LE)
592
593static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = {
594 {
595 .name = "TDM",
596 .id = MT8183_DAI_TDM,
597 .playback = {
598 .stream_name = "TDM",
599 .channels_min = 2,
600 .channels_max = 8,
601 .rates = MTK_TDM_RATES,
602 .formats = MTK_TDM_FORMATS,
603 },
604 .ops = &mtk_dai_tdm_ops,
605 },
606};
607
608int mt8183_dai_tdm_register(struct mtk_base_afe *afe)
609{
610 struct mt8183_afe_private *afe_priv = afe->platform_priv;
611 struct mtk_afe_tdm_priv *tdm_priv;
612 struct mtk_base_afe_dai *dai;
613
614 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
615 if (!dai)
616 return -ENOMEM;
617
618 list_add(&dai->list, &afe->sub_dais);
619
620 dai->dai_drivers = mtk_dai_tdm_driver;
621 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver);
622
623 dai->dapm_widgets = mtk_dai_tdm_widgets;
624 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets);
625 dai->dapm_routes = mtk_dai_tdm_routes;
626 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes);
627
628 tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv),
629 GFP_KERNEL);
630 if (!tdm_priv)
631 return -ENOMEM;
632
633 tdm_priv->mclk_multiple = 128;
634 tdm_priv->bck_id = MT8183_I2S4_BCK;
635 tdm_priv->mclk_id = MT8183_I2S4_MCK;
636
637 afe_priv->dai_priv[MT8183_DAI_TDM] = tdm_priv;
638 return 0;
639}
640
