LXR linux/sound/soc/nuc900/nuc900-audio.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2010 Nuvoton technology corporation.
   4 *
   5 * Wan ZongShun <mcuos.com@gmail.com>
   6 */
   7
   8#ifndef _NUC900_AUDIO_H
   9#define _NUC900_AUDIO_H
  10
  11#include <linux/io.h>
  12
  13/* Audio Control Registers */
  14#define ACTL_CON                0x00
  15#define ACTL_RESET              0x04
  16#define ACTL_RDSTB              0x08
  17#define ACTL_RDST_LENGTH        0x0C
  18#define ACTL_RDSTC              0x10
  19#define ACTL_RSR                0x14
  20#define ACTL_PDSTB              0x18
  21#define ACTL_PDST_LENGTH        0x1C
  22#define ACTL_PDSTC              0x20
  23#define ACTL_PSR                0x24
  24#define ACTL_IISCON             0x28
  25#define ACTL_ACCON              0x2C
  26#define ACTL_ACOS0              0x30
  27#define ACTL_ACOS1              0x34
  28#define ACTL_ACOS2              0x38
  29#define ACTL_ACIS0              0x3C
  30#define ACTL_ACIS1              0x40
  31#define ACTL_ACIS2              0x44
  32#define ACTL_COUNTER            0x48
  33
  34/* bit definition of REG_ACTL_CON register */
  35#define R_DMA_IRQ               0x1000
  36#define T_DMA_IRQ               0x0800
  37#define IIS_AC_PIN_SEL          0x0100
  38#define FIFO_TH                 0x0080
  39#define ADC_EN                  0x0010
  40#define M80_EN                  0x0008
  41#define ACLINK_EN               0x0004
  42#define IIS_EN                  0x0002
  43
  44/* bit definition of REG_ACTL_RESET register */
  45#define W5691_PLAY              0x20000
  46#define ACTL_RESET_BIT          0x10000
  47#define RECORD_RIGHT_CHNNEL     0x08000
  48#define RECORD_LEFT_CHNNEL      0x04000
  49#define PLAY_RIGHT_CHNNEL       0x02000
  50#define PLAY_LEFT_CHNNEL        0x01000
  51#define DAC_PLAY                0x00800
  52#define ADC_RECORD              0x00400
  53#define M80_PLAY                0x00200
  54#define AC_RECORD               0x00100
  55#define AC_PLAY                 0x00080
  56#define IIS_RECORD              0x00040
  57#define IIS_PLAY                0x00020
  58#define DAC_RESET               0x00010
  59#define ADC_RESET               0x00008
  60#define M80_RESET               0x00004
  61#define AC_RESET                0x00002
  62#define IIS_RESET               0x00001
  63
  64/* bit definition of REG_ACTL_ACCON register */
  65#define AC_BCLK_PU_EN           0x20
  66#define AC_R_FINISH             0x10
  67#define AC_W_FINISH             0x08
  68#define AC_W_RES                0x04
  69#define AC_C_RES                0x02
  70
  71/* bit definition of ACTL_RSR register */
  72#define R_FIFO_EMPTY            0x04
  73#define R_DMA_END_IRQ           0x02
  74#define R_DMA_MIDDLE_IRQ        0x01
  75
  76/* bit definition of ACTL_PSR register */
  77#define P_FIFO_EMPTY            0x04
  78#define P_DMA_END_IRQ           0x02
  79#define P_DMA_MIDDLE_IRQ        0x01
  80
  81/* bit definition of ACTL_ACOS0 register */
  82#define SLOT1_VALID             0x01
  83#define SLOT2_VALID             0x02
  84#define SLOT3_VALID             0x04
  85#define SLOT4_VALID             0x08
  86#define VALID_FRAME             0x10
  87
  88/* bit definition of ACTL_ACOS1 register */
  89#define R_WB                    0x80
  90
  91#define CODEC_READY             0x10
  92#define RESET_PRSR              0x00
  93#define AUDIO_WRITE(addr, val)  __raw_writel(val, addr)
  94#define AUDIO_READ(addr)        __raw_readl(addr)
  95
  96struct nuc900_audio {
  97        void __iomem *mmio;
  98        spinlock_t lock;
  99        unsigned long irq_num;
 100        struct resource *res;
 101        struct clk *clk;
 102        struct device *dev;
 103
 104};
 105
 106extern struct nuc900_audio *nuc900_ac97_data;
 107
 108#endif /*end _NUC900_AUDIO_H */
 109