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6#include <linux/irqchip/arm-gic-v3.h>
7#include <linux/kvm.h>
8#include <linux/kvm_host.h>
9#include <kvm/iodev.h>
10#include <kvm/arm_vgic.h>
11
12#include <asm/kvm_emulate.h>
13#include <asm/kvm_arm.h>
14#include <asm/kvm_mmu.h>
15
16#include "vgic.h"
17#include "vgic-mmio.h"
18
19
20unsigned long extract_bytes(u64 data, unsigned int offset,
21 unsigned int num)
22{
23 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
24}
25
26
27u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
28 unsigned long val)
29{
30 int lower = (offset & 4) * 8;
31 int upper = lower + 8 * len - 1;
32
33 reg &= ~GENMASK_ULL(upper, lower);
34 val &= GENMASK_ULL(len * 8 - 1, 0);
35
36 return reg | ((u64)val << lower);
37}
38
39bool vgic_has_its(struct kvm *kvm)
40{
41 struct vgic_dist *dist = &kvm->arch.vgic;
42
43 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
44 return false;
45
46 return dist->has_its;
47}
48
49bool vgic_supports_direct_msis(struct kvm *kvm)
50{
51 return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm);
52}
53
54
55
56
57
58
59
60
61static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
62 gpa_t addr, unsigned int len)
63{
64 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
65 u32 value = 0;
66
67 switch (addr & 0x0c) {
68 case GICD_CTLR:
69 if (vgic->enabled)
70 value |= GICD_CTLR_ENABLE_SS_G1;
71 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
72 break;
73 case GICD_TYPER:
74 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
75 value = (value >> 5) - 1;
76 if (vgic_has_its(vcpu->kvm)) {
77 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
78 value |= GICD_TYPER_LPIS;
79 } else {
80 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
81 }
82 break;
83 case GICD_IIDR:
84 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
85 (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
86 (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
87 break;
88 default:
89 return 0;
90 }
91
92 return value;
93}
94
95static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
96 gpa_t addr, unsigned int len,
97 unsigned long val)
98{
99 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
100 bool was_enabled = dist->enabled;
101
102 switch (addr & 0x0c) {
103 case GICD_CTLR:
104 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
105
106 if (!was_enabled && dist->enabled)
107 vgic_kick_vcpus(vcpu->kvm);
108 break;
109 case GICD_TYPER:
110 case GICD_IIDR:
111 return;
112 }
113}
114
115static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
116 gpa_t addr, unsigned int len,
117 unsigned long val)
118{
119 switch (addr & 0x0c) {
120 case GICD_IIDR:
121 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
122 return -EINVAL;
123 }
124
125 vgic_mmio_write_v3_misc(vcpu, addr, len, val);
126 return 0;
127}
128
129static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
130 gpa_t addr, unsigned int len)
131{
132 int intid = VGIC_ADDR_TO_INTID(addr, 64);
133 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
134 unsigned long ret = 0;
135
136 if (!irq)
137 return 0;
138
139
140 if (!(addr & 4))
141 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
142
143 vgic_put_irq(vcpu->kvm, irq);
144 return ret;
145}
146
147static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
148 gpa_t addr, unsigned int len,
149 unsigned long val)
150{
151 int intid = VGIC_ADDR_TO_INTID(addr, 64);
152 struct vgic_irq *irq;
153 unsigned long flags;
154
155
156 if (addr & 4)
157 return;
158
159 irq = vgic_get_irq(vcpu->kvm, NULL, intid);
160
161 if (!irq)
162 return;
163
164 raw_spin_lock_irqsave(&irq->irq_lock, flags);
165
166
167 irq->mpidr = val & GENMASK(23, 0);
168 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
169
170 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
171 vgic_put_irq(vcpu->kvm, irq);
172}
173
174static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
175 gpa_t addr, unsigned int len)
176{
177 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
178
179 return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
180}
181
182
183static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
184 gpa_t addr, unsigned int len,
185 unsigned long val)
186{
187 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
188 bool was_enabled = vgic_cpu->lpis_enabled;
189
190 if (!vgic_has_its(vcpu->kvm))
191 return;
192
193 vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
194
195 if (was_enabled && !vgic_cpu->lpis_enabled)
196 vgic_flush_pending_lpis(vcpu);
197
198 if (!was_enabled && vgic_cpu->lpis_enabled)
199 vgic_enable_lpis(vcpu);
200}
201
202static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
203 gpa_t addr, unsigned int len)
204{
205 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
206 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
207 struct vgic_redist_region *rdreg = vgic_cpu->rdreg;
208 int target_vcpu_id = vcpu->vcpu_id;
209 gpa_t last_rdist_typer = rdreg->base + GICR_TYPER +
210 (rdreg->free_index - 1) * KVM_VGIC_V3_REDIST_SIZE;
211 u64 value;
212
213 value = (u64)(mpidr & GENMASK(23, 0)) << 32;
214 value |= ((target_vcpu_id & 0xffff) << 8);
215
216 if (addr == last_rdist_typer)
217 value |= GICR_TYPER_LAST;
218 if (vgic_has_its(vcpu->kvm))
219 value |= GICR_TYPER_PLPIS;
220
221 return extract_bytes(value, addr & 7, len);
222}
223
224static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
225 gpa_t addr, unsigned int len)
226{
227 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
228}
229
230static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
231 gpa_t addr, unsigned int len)
232{
233 switch (addr & 0xffff) {
234 case GICD_PIDR2:
235
236 return 0x3b;
237 }
238
239 return 0;
240}
241
242static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
243 gpa_t addr, unsigned int len)
244{
245 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
246 u32 value = 0;
247 int i;
248
249
250
251
252
253
254
255
256 for (i = 0; i < len * 8; i++) {
257 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
258
259 if (irq->pending_latch)
260 value |= (1U << i);
261
262 vgic_put_irq(vcpu->kvm, irq);
263 }
264
265 return value;
266}
267
268static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
269 gpa_t addr, unsigned int len,
270 unsigned long val)
271{
272 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
273 int i;
274 unsigned long flags;
275
276 for (i = 0; i < len * 8; i++) {
277 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
278
279 raw_spin_lock_irqsave(&irq->irq_lock, flags);
280 if (test_bit(i, &val)) {
281
282
283
284
285
286 irq->pending_latch = true;
287 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
288 } else {
289 irq->pending_latch = false;
290 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
291 }
292
293 vgic_put_irq(vcpu->kvm, irq);
294 }
295
296 return 0;
297}
298
299
300u64 vgic_sanitise_shareability(u64 field)
301{
302 switch (field) {
303 case GIC_BASER_OuterShareable:
304 return GIC_BASER_InnerShareable;
305 default:
306 return field;
307 }
308}
309
310
311u64 vgic_sanitise_inner_cacheability(u64 field)
312{
313 switch (field) {
314 case GIC_BASER_CACHE_nCnB:
315 case GIC_BASER_CACHE_nC:
316 return GIC_BASER_CACHE_RaWb;
317 default:
318 return field;
319 }
320}
321
322
323u64 vgic_sanitise_outer_cacheability(u64 field)
324{
325 switch (field) {
326 case GIC_BASER_CACHE_SameAsInner:
327 case GIC_BASER_CACHE_nC:
328 return field;
329 default:
330 return GIC_BASER_CACHE_nC;
331 }
332}
333
334u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
335 u64 (*sanitise_fn)(u64))
336{
337 u64 field = (reg & field_mask) >> field_shift;
338
339 field = sanitise_fn(field) << field_shift;
340 return (reg & ~field_mask) | field;
341}
342
343#define PROPBASER_RES0_MASK \
344 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
345#define PENDBASER_RES0_MASK \
346 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \
347 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
348
349static u64 vgic_sanitise_pendbaser(u64 reg)
350{
351 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
352 GICR_PENDBASER_SHAREABILITY_SHIFT,
353 vgic_sanitise_shareability);
354 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
355 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
356 vgic_sanitise_inner_cacheability);
357 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
358 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
359 vgic_sanitise_outer_cacheability);
360
361 reg &= ~PENDBASER_RES0_MASK;
362
363 return reg;
364}
365
366static u64 vgic_sanitise_propbaser(u64 reg)
367{
368 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
369 GICR_PROPBASER_SHAREABILITY_SHIFT,
370 vgic_sanitise_shareability);
371 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
372 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
373 vgic_sanitise_inner_cacheability);
374 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
375 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
376 vgic_sanitise_outer_cacheability);
377
378 reg &= ~PROPBASER_RES0_MASK;
379 return reg;
380}
381
382static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
383 gpa_t addr, unsigned int len)
384{
385 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
386
387 return extract_bytes(dist->propbaser, addr & 7, len);
388}
389
390static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
391 gpa_t addr, unsigned int len,
392 unsigned long val)
393{
394 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
395 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
396 u64 old_propbaser, propbaser;
397
398
399 if (vgic_cpu->lpis_enabled)
400 return;
401
402 do {
403 old_propbaser = READ_ONCE(dist->propbaser);
404 propbaser = old_propbaser;
405 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
406 propbaser = vgic_sanitise_propbaser(propbaser);
407 } while (cmpxchg64(&dist->propbaser, old_propbaser,
408 propbaser) != old_propbaser);
409}
410
411static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
412 gpa_t addr, unsigned int len)
413{
414 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
415
416 return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
417}
418
419static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
420 gpa_t addr, unsigned int len,
421 unsigned long val)
422{
423 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
424 u64 old_pendbaser, pendbaser;
425
426
427 if (vgic_cpu->lpis_enabled)
428 return;
429
430 do {
431 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser);
432 pendbaser = old_pendbaser;
433 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
434 pendbaser = vgic_sanitise_pendbaser(pendbaser);
435 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
436 pendbaser) != old_pendbaser);
437}
438
439
440
441
442
443
444
445
446#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
447 { \
448 .reg_offset = off, \
449 .bits_per_irq = bpi, \
450 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
451 .access_flags = acc, \
452 .read = vgic_mmio_read_raz, \
453 .write = vgic_mmio_write_wi, \
454 }, { \
455 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
456 .bits_per_irq = bpi, \
457 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
458 .access_flags = acc, \
459 .read = rd, \
460 .write = wr, \
461 .uaccess_read = ur, \
462 .uaccess_write = uw, \
463 }
464
465static const struct vgic_register_region vgic_v3_dist_registers[] = {
466 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
467 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
468 NULL, vgic_mmio_uaccess_write_v3_misc,
469 16, VGIC_ACCESS_32bit),
470 REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
471 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
472 VGIC_ACCESS_32bit),
473 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
474 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1,
475 VGIC_ACCESS_32bit),
476 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
477 vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
478 VGIC_ACCESS_32bit),
479 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
480 vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
481 VGIC_ACCESS_32bit),
482 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
483 vgic_mmio_read_pending, vgic_mmio_write_spending,
484 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
485 VGIC_ACCESS_32bit),
486 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
487 vgic_mmio_read_pending, vgic_mmio_write_cpending,
488 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1,
489 VGIC_ACCESS_32bit),
490 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
491 vgic_mmio_read_active, vgic_mmio_write_sactive,
492 NULL, vgic_mmio_uaccess_write_sactive, 1,
493 VGIC_ACCESS_32bit),
494 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
495 vgic_mmio_read_active, vgic_mmio_write_cactive,
496 NULL, vgic_mmio_uaccess_write_cactive,
497 1, VGIC_ACCESS_32bit),
498 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
499 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
500 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
501 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
502 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
503 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
504 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
505 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
506 VGIC_ACCESS_32bit),
507 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
508 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
509 VGIC_ACCESS_32bit),
510 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
511 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
512 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
513 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
514 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
515 VGIC_ACCESS_32bit),
516};
517
518static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
519 REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
520 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
521 VGIC_ACCESS_32bit),
522 REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
523 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
524 VGIC_ACCESS_32bit),
525 REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
526 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
527 VGIC_ACCESS_32bit),
528 REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
529 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
530 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
531 REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
532 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
533 VGIC_ACCESS_32bit),
534 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
535 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
536 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
537 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
538 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
539 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
540 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
541 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
542 VGIC_ACCESS_32bit),
543};
544
545static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
546 REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
547 vgic_mmio_read_group, vgic_mmio_write_group, 4,
548 VGIC_ACCESS_32bit),
549 REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
550 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
551 VGIC_ACCESS_32bit),
552 REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
553 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
554 VGIC_ACCESS_32bit),
555 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
556 vgic_mmio_read_pending, vgic_mmio_write_spending,
557 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
558 VGIC_ACCESS_32bit),
559 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
560 vgic_mmio_read_pending, vgic_mmio_write_cpending,
561 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4,
562 VGIC_ACCESS_32bit),
563 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISACTIVER0,
564 vgic_mmio_read_active, vgic_mmio_write_sactive,
565 NULL, vgic_mmio_uaccess_write_sactive,
566 4, VGIC_ACCESS_32bit),
567 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICACTIVER0,
568 vgic_mmio_read_active, vgic_mmio_write_cactive,
569 NULL, vgic_mmio_uaccess_write_cactive,
570 4, VGIC_ACCESS_32bit),
571 REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
572 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
573 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
574 REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
575 vgic_mmio_read_config, vgic_mmio_write_config, 8,
576 VGIC_ACCESS_32bit),
577 REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
578 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
579 VGIC_ACCESS_32bit),
580 REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
581 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
582 VGIC_ACCESS_32bit),
583};
584
585unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
586{
587 dev->regions = vgic_v3_dist_registers;
588 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
589
590 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
591
592 return SZ_64K;
593}
594
595
596
597
598
599
600
601
602
603
604int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
605{
606 struct kvm *kvm = vcpu->kvm;
607 struct vgic_dist *vgic = &kvm->arch.vgic;
608 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
609 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
610 struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
611 struct vgic_redist_region *rdreg;
612 gpa_t rd_base, sgi_base;
613 int ret;
614
615 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
616 return 0;
617
618
619
620
621
622
623
624 rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
625 if (!rdreg)
626 return 0;
627
628 if (!vgic_v3_check_base(kvm))
629 return -EINVAL;
630
631 vgic_cpu->rdreg = rdreg;
632
633 rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
634 sgi_base = rd_base + SZ_64K;
635
636 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
637 rd_dev->base_addr = rd_base;
638 rd_dev->iodev_type = IODEV_REDIST;
639 rd_dev->regions = vgic_v3_rdbase_registers;
640 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
641 rd_dev->redist_vcpu = vcpu;
642
643 mutex_lock(&kvm->slots_lock);
644 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
645 SZ_64K, &rd_dev->dev);
646 mutex_unlock(&kvm->slots_lock);
647
648 if (ret)
649 return ret;
650
651 kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
652 sgi_dev->base_addr = sgi_base;
653 sgi_dev->iodev_type = IODEV_REDIST;
654 sgi_dev->regions = vgic_v3_sgibase_registers;
655 sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
656 sgi_dev->redist_vcpu = vcpu;
657
658 mutex_lock(&kvm->slots_lock);
659 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
660 SZ_64K, &sgi_dev->dev);
661 if (ret) {
662 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
663 &rd_dev->dev);
664 goto out;
665 }
666
667 rdreg->free_index++;
668out:
669 mutex_unlock(&kvm->slots_lock);
670 return ret;
671}
672
673static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
674{
675 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
676 struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
677
678 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
679 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &sgi_dev->dev);
680}
681
682static int vgic_register_all_redist_iodevs(struct kvm *kvm)
683{
684 struct kvm_vcpu *vcpu;
685 int c, ret = 0;
686
687 kvm_for_each_vcpu(c, vcpu, kvm) {
688 ret = vgic_register_redist_iodev(vcpu);
689 if (ret)
690 break;
691 }
692
693 if (ret) {
694
695 mutex_lock(&kvm->slots_lock);
696 for (c--; c >= 0; c--) {
697 vcpu = kvm_get_vcpu(kvm, c);
698 vgic_unregister_redist_iodev(vcpu);
699 }
700 mutex_unlock(&kvm->slots_lock);
701 }
702
703 return ret;
704}
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index,
722 gpa_t base, uint32_t count)
723{
724 struct vgic_dist *d = &kvm->arch.vgic;
725 struct vgic_redist_region *rdreg;
726 struct list_head *rd_regions = &d->rd_regions;
727 size_t size = count * KVM_VGIC_V3_REDIST_SIZE;
728 int ret;
729
730
731 if (!count && !list_empty(rd_regions))
732 return -EINVAL;
733
734
735 if (base + size < base)
736 return -EINVAL;
737
738 if (list_empty(rd_regions)) {
739 if (index != 0)
740 return -EINVAL;
741 } else {
742 rdreg = list_last_entry(rd_regions,
743 struct vgic_redist_region, list);
744 if (index != rdreg->index + 1)
745 return -EINVAL;
746
747
748 if (!rdreg->count)
749 return -EINVAL;
750 }
751
752
753
754
755
756
757 if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
758 vgic_dist_overlap(kvm, base, size))
759 return -EINVAL;
760
761
762 if (vgic_v3_rdist_overlap(kvm, base, size))
763 return -EINVAL;
764
765 rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL);
766 if (!rdreg)
767 return -ENOMEM;
768
769 rdreg->base = VGIC_ADDR_UNDEF;
770
771 ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K);
772 if (ret)
773 goto free;
774
775 rdreg->base = base;
776 rdreg->count = count;
777 rdreg->free_index = 0;
778 rdreg->index = index;
779
780 list_add_tail(&rdreg->list, rd_regions);
781 return 0;
782free:
783 kfree(rdreg);
784 return ret;
785}
786
787int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
788{
789 int ret;
790
791 ret = vgic_v3_insert_redist_region(kvm, index, addr, count);
792 if (ret)
793 return ret;
794
795
796
797
798
799 ret = vgic_register_all_redist_iodevs(kvm);
800 if (ret)
801 return ret;
802
803 return 0;
804}
805
806int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
807{
808 const struct vgic_register_region *region;
809 struct vgic_io_device iodev;
810 struct vgic_reg_attr reg_attr;
811 struct kvm_vcpu *vcpu;
812 gpa_t addr;
813 int ret;
814
815 ret = vgic_v3_parse_attr(dev, attr, ®_attr);
816 if (ret)
817 return ret;
818
819 vcpu = reg_attr.vcpu;
820 addr = reg_attr.addr;
821
822 switch (attr->group) {
823 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
824 iodev.regions = vgic_v3_dist_registers;
825 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
826 iodev.base_addr = 0;
827 break;
828 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
829 iodev.regions = vgic_v3_rdbase_registers;
830 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
831 iodev.base_addr = 0;
832 break;
833 }
834 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
835 u64 reg, id;
836
837 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
838 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, ®);
839 }
840 default:
841 return -ENXIO;
842 }
843
844
845 if (addr & 3)
846 return -ENXIO;
847
848 region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
849 if (!region)
850 return -ENXIO;
851
852 return 0;
853}
854
855
856
857
858
859
860static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
861{
862 unsigned long affinity;
863 int level0;
864
865
866
867
868
869 affinity = kvm_vcpu_get_mpidr_aff(vcpu);
870 level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
871 affinity &= ~MPIDR_LEVEL_MASK;
872
873
874 if (sgi_aff != affinity)
875 return -1;
876
877
878 if (!(sgi_cpu_mask & BIT(level0)))
879 return -1;
880
881 return level0;
882}
883
884
885
886
887
888
889#define SGI_AFFINITY_LEVEL(reg, level) \
890 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
891 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
908{
909 struct kvm *kvm = vcpu->kvm;
910 struct kvm_vcpu *c_vcpu;
911 u16 target_cpus;
912 u64 mpidr;
913 int sgi, c;
914 int vcpu_id = vcpu->vcpu_id;
915 bool broadcast;
916 unsigned long flags;
917
918 sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
919 broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
920 target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
921 mpidr = SGI_AFFINITY_LEVEL(reg, 3);
922 mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
923 mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
924
925
926
927
928
929
930
931 kvm_for_each_vcpu(c, c_vcpu, kvm) {
932 struct vgic_irq *irq;
933
934
935 if (!broadcast && target_cpus == 0)
936 break;
937
938
939 if (broadcast && c == vcpu_id)
940 continue;
941
942 if (!broadcast) {
943 int level0;
944
945 level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
946 if (level0 == -1)
947 continue;
948
949
950 target_cpus &= ~BIT(level0);
951 }
952
953 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
954
955 raw_spin_lock_irqsave(&irq->irq_lock, flags);
956
957
958
959
960
961
962 if (!irq->group || allow_group1) {
963 irq->pending_latch = true;
964 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
965 } else {
966 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
967 }
968
969 vgic_put_irq(vcpu->kvm, irq);
970 }
971}
972
973int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
974 int offset, u32 *val)
975{
976 struct vgic_io_device dev = {
977 .regions = vgic_v3_dist_registers,
978 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
979 };
980
981 return vgic_uaccess(vcpu, &dev, is_write, offset, val);
982}
983
984int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
985 int offset, u32 *val)
986{
987 struct vgic_io_device rd_dev = {
988 .regions = vgic_v3_rdbase_registers,
989 .nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers),
990 };
991
992 struct vgic_io_device sgi_dev = {
993 .regions = vgic_v3_sgibase_registers,
994 .nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers),
995 };
996
997
998 if (offset >= SZ_64K)
999 return vgic_uaccess(vcpu, &sgi_dev, is_write, offset - SZ_64K,
1000 val);
1001 else
1002 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
1003}
1004
1005int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1006 u32 intid, u64 *val)
1007{
1008 if (intid % 32)
1009 return -EINVAL;
1010
1011 if (is_write)
1012 vgic_write_irq_line_level_info(vcpu, intid, *val);
1013 else
1014 *val = vgic_read_irq_line_level_info(vcpu, intid);
1015
1016 return 0;
1017}
1018