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7#include <linux/cpu.h>
8#include <linux/init.h>
9#include <linux/sched.h>
10#include <linux/ioport.h>
11#include <linux/irq.h>
12#include <linux/of_fdt.h>
13#include <linux/pci.h>
14#include <linux/screen_info.h>
15#include <linux/time.h>
16
17#include <asm/dma-coherence.h>
18#include <asm/fw/fw.h>
19#include <asm/mach-malta/malta-dtshim.h>
20#include <asm/mips-cps.h>
21#include <asm/mips-boards/generic.h>
22#include <asm/mips-boards/malta.h>
23#include <asm/mips-boards/maltaint.h>
24#include <asm/dma.h>
25#include <asm/prom.h>
26#include <asm/traps.h>
27#ifdef CONFIG_VT
28#include <linux/console.h>
29#endif
30
31#define ROCIT_CONFIG_GEN0 0x1f403000
32#define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7)
33
34static struct resource standard_io_resources[] = {
35 {
36 .name = "dma1",
37 .start = 0x00,
38 .end = 0x1f,
39 .flags = IORESOURCE_IO | IORESOURCE_BUSY
40 },
41 {
42 .name = "timer",
43 .start = 0x40,
44 .end = 0x5f,
45 .flags = IORESOURCE_IO | IORESOURCE_BUSY
46 },
47 {
48 .name = "keyboard",
49 .start = 0x60,
50 .end = 0x6f,
51 .flags = IORESOURCE_IO | IORESOURCE_BUSY
52 },
53 {
54 .name = "dma page reg",
55 .start = 0x80,
56 .end = 0x8f,
57 .flags = IORESOURCE_IO | IORESOURCE_BUSY
58 },
59 {
60 .name = "dma2",
61 .start = 0xc0,
62 .end = 0xdf,
63 .flags = IORESOURCE_IO | IORESOURCE_BUSY
64 },
65};
66
67const char *get_system_type(void)
68{
69 return "MIPS Malta";
70}
71
72#ifdef CONFIG_BLK_DEV_FD
73static void __init fd_activate(void)
74{
75
76
77
78
79
80
81 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
82
83
84 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
85 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
86 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
87 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
88
89
90 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
91}
92#endif
93
94static int __init plat_enable_iocoherency(void)
95{
96 int supported = 0;
97 u32 cfg;
98
99 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
100 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
101 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
102 pr_info("Enabled Bonito CPU coherency\n");
103 supported = 1;
104 }
105 if (strstr(fw_getcmdline(), "iobcuncached")) {
106 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
107 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
108 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
109 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
110 pr_info("Disabled Bonito IOBC coherency\n");
111 } else {
112 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
113 BONITO_PCIMEMBASECFG |=
114 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
115 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
116 pr_info("Enabled Bonito IOBC coherency\n");
117 }
118 } else if (mips_cps_numiocu(0) != 0) {
119
120 pr_info("CMP IOCU detected\n");
121 cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
122 if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) {
123 pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
124 return 0;
125 }
126 supported = 1;
127 }
128 hw_coherentio = supported;
129 return supported;
130}
131
132static void __init plat_setup_iocoherency(void)
133{
134 if (plat_enable_iocoherency()) {
135 if (coherentio == IO_COHERENCE_DISABLED)
136 pr_info("Hardware DMA cache coherency disabled\n");
137 else
138 pr_info("Hardware DMA cache coherency enabled\n");
139 } else {
140 if (coherentio == IO_COHERENCE_ENABLED)
141 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
142 else
143 pr_info("Software DMA cache coherency enabled\n");
144 }
145}
146
147static void __init pci_clock_check(void)
148{
149 unsigned int __iomem *jmpr_p =
150 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
151 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
152 static const int pciclocks[] __initconst = {
153 33, 20, 25, 30, 12, 16, 37, 10
154 };
155 int pciclock = pciclocks[jmpr];
156 char *optptr, *argptr = fw_getcmdline();
157
158
159
160
161 optptr = strstr(argptr, "pci_clock=");
162 if (optptr && (optptr == argptr || optptr[-1] == ' '))
163 return;
164
165 if (pciclock != 33) {
166 pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
167 pciclock);
168 argptr += strlen(argptr);
169 sprintf(argptr, " pci_clock=%d", pciclock);
170 if (pciclock < 20 || pciclock > 66)
171 pr_warn("WARNING: IDE timing calculations will be "
172 "incorrect\n");
173 }
174}
175
176#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
177static void __init screen_info_setup(void)
178{
179 screen_info = (struct screen_info) {
180 .orig_x = 0,
181 .orig_y = 25,
182 .ext_mem_k = 0,
183 .orig_video_page = 0,
184 .orig_video_mode = 0,
185 .orig_video_cols = 80,
186 .unused2 = 0,
187 .orig_video_ega_bx = 0,
188 .unused3 = 0,
189 .orig_video_lines = 25,
190 .orig_video_isVGA = VIDEO_TYPE_VGAC,
191 .orig_video_points = 16
192 };
193}
194#endif
195
196static void __init bonito_quirks_setup(void)
197{
198 char *argptr;
199
200 argptr = fw_getcmdline();
201 if (strstr(argptr, "debug")) {
202 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
203 pr_info("Enabled Bonito debug mode\n");
204 } else
205 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
206}
207
208void __init *plat_get_fdt(void)
209{
210 return (void *)__dtb_start;
211}
212
213void __init plat_mem_setup(void)
214{
215 unsigned int i;
216 void *fdt = plat_get_fdt();
217
218 fdt = malta_dt_shim(fdt);
219 __dt_setup_arch(fdt);
220
221 if (IS_ENABLED(CONFIG_EVA))
222
223 pr_info("Enhanced Virtual Addressing (EVA) activated\n");
224
225 mips_pcibios_init();
226
227
228 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
229 request_resource(&ioport_resource, standard_io_resources+i);
230
231
232
233
234 enable_dma(4);
235
236 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
237 bonito_quirks_setup();
238
239 plat_setup_iocoherency();
240
241 pci_clock_check();
242
243#ifdef CONFIG_BLK_DEV_FD
244 fd_activate();
245#endif
246
247#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
248 screen_info_setup();
249#endif
250}
251
