LXR linux/arch/powerpc/include/asm/time.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Common time prototypes and such for all ppc machines.
   4 *
   5 * Written by Cort Dougan (cort@cs.nmt.edu) to merge
   6 * Paul Mackerras' version and mine for PReP and Pmac.
   7 */
   8
   9#ifndef __POWERPC_TIME_H
  10#define __POWERPC_TIME_H
  11
  12#ifdef __KERNEL__
  13#include <linux/types.h>
  14#include <linux/percpu.h>
  15
  16#include <asm/processor.h>
  17#include <asm/cpu_has_feature.h>
  18
  19/* time.c */
  20extern unsigned long tb_ticks_per_jiffy;
  21extern unsigned long tb_ticks_per_usec;
  22extern unsigned long tb_ticks_per_sec;
  23extern struct clock_event_device decrementer_clockevent;
  24
  25
  26extern void generic_calibrate_decr(void);
  27extern void hdec_interrupt(struct pt_regs *regs);
  28
  29/* Some sane defaults: 125 MHz timebase, 1GHz processor */
  30extern unsigned long ppc_proc_freq;
  31#define DEFAULT_PROC_FREQ       (DEFAULT_TB_FREQ * 8)
  32extern unsigned long ppc_tb_freq;
  33#define DEFAULT_TB_FREQ         125000000UL
  34
  35extern bool tb_invalid;
  36
  37struct div_result {
  38        u64 result_high;
  39        u64 result_low;
  40};
  41
  42/* Accessor functions for the timebase (RTC on 601) registers. */
  43/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
  44#define __USE_RTC()     (IS_ENABLED(CONFIG_PPC_BOOK3S_601))
  45
  46#ifdef CONFIG_PPC64
  47
  48/* For compatibility, get_tbl() is defined as get_tb() on ppc64 */
  49#define get_tbl         get_tb
  50
  51#else
  52
  53static inline unsigned long get_tbl(void)
  54{
  55#if defined(CONFIG_403GCX)
  56        unsigned long tbl;
  57        asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
  58        return tbl;
  59#else
  60        return mftbl();
  61#endif
  62}
  63
  64static inline unsigned int get_tbu(void)
  65{
  66#ifdef CONFIG_403GCX
  67        unsigned int tbu;
  68        asm volatile("mfspr %0, 0x3dc" : "=r" (tbu));
  69        return tbu;
  70#else
  71        return mftbu();
  72#endif
  73}
  74#endif /* !CONFIG_PPC64 */
  75
  76static inline unsigned int get_rtcl(void)
  77{
  78        unsigned int rtcl;
  79
  80        asm volatile("mfrtcl %0" : "=r" (rtcl));
  81        return rtcl;
  82}
  83
  84static inline u64 get_rtc(void)
  85{
  86        unsigned int hi, lo, hi2;
  87
  88        do {
  89                asm volatile("mfrtcu %0; mfrtcl %1; mfrtcu %2"
  90                             : "=r" (hi), "=r" (lo), "=r" (hi2));
  91        } while (hi2 != hi);
  92        return (u64)hi * 1000000000 + lo;
  93}
  94
  95static inline u64 get_vtb(void)
  96{
  97#ifdef CONFIG_PPC_BOOK3S_64
  98        if (cpu_has_feature(CPU_FTR_ARCH_207S))
  99                return mfspr(SPRN_VTB);
 100#endif
 101        return 0;
 102}
 103
 104#ifdef CONFIG_PPC64
 105static inline u64 get_tb(void)
 106{
 107        return mftb();
 108}
 109#else /* CONFIG_PPC64 */
 110static inline u64 get_tb(void)
 111{
 112        unsigned int tbhi, tblo, tbhi2;
 113
 114        do {
 115                tbhi = get_tbu();
 116                tblo = get_tbl();
 117                tbhi2 = get_tbu();
 118        } while (tbhi != tbhi2);
 119
 120        return ((u64)tbhi << 32) | tblo;
 121}
 122#endif /* !CONFIG_PPC64 */
 123
 124static inline u64 get_tb_or_rtc(void)
 125{
 126        return __USE_RTC() ? get_rtc() : get_tb();
 127}
 128
 129static inline void set_tb(unsigned int upper, unsigned int lower)
 130{
 131        mtspr(SPRN_TBWL, 0);
 132        mtspr(SPRN_TBWU, upper);
 133        mtspr(SPRN_TBWL, lower);
 134}
 135
 136/* Accessor functions for the decrementer register.
 137 * The 4xx doesn't even have a decrementer.  I tried to use the
 138 * generic timer interrupt code, which seems OK, with the 4xx PIT
 139 * in auto-reload mode.  The problem is PIT stops counting when it
 140 * hits zero.  If it would wrap, we could use it just like a decrementer.
 141 */
 142static inline u64 get_dec(void)
 143{
 144#if defined(CONFIG_40x)
 145        return (mfspr(SPRN_PIT));
 146#else
 147        return (mfspr(SPRN_DEC));
 148#endif
 149}
 150
 151/*
 152 * Note: Book E and 4xx processors differ from other PowerPC processors
 153 * in when the decrementer generates its interrupt: on the 1 to 0
 154 * transition for Book E/4xx, but on the 0 to -1 transition for others.
 155 */
 156static inline void set_dec(u64 val)
 157{
 158#if defined(CONFIG_40x)
 159        mtspr(SPRN_PIT, (u32) val);
 160#else
 161#ifndef CONFIG_BOOKE
 162        --val;
 163#endif
 164        mtspr(SPRN_DEC, val);
 165#endif /* not 40x */
 166}
 167
 168static inline unsigned long tb_ticks_since(unsigned long tstamp)
 169{
 170        if (__USE_RTC()) {
 171                int delta = get_rtcl() - (unsigned int) tstamp;
 172                return delta < 0 ? delta + 1000000000 : delta;
 173        }
 174        return get_tbl() - tstamp;
 175}
 176
 177#define mulhwu(x,y) \
 178({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
 179
 180#ifdef CONFIG_PPC64
 181#define mulhdu(x,y) \
 182({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
 183#else
 184extern u64 mulhdu(u64, u64);
 185#endif
 186
 187extern void div128_by_32(u64 dividend_high, u64 dividend_low,
 188                         unsigned divisor, struct div_result *dr);
 189
 190extern void secondary_cpu_time_init(void);
 191extern void __init time_init(void);
 192
 193DECLARE_PER_CPU(u64, decrementers_next_tb);
 194
 195/* Convert timebase ticks to nanoseconds */
 196unsigned long long tb_to_ns(unsigned long long tb_ticks);
 197
 198#endif /* __KERNEL__ */
 199#endif /* __POWERPC_TIME_H */
 200