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8
9#define DRV_MODULE_NAME "hlwd-pic"
10#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
11
12#include <linux/kernel.h>
13#include <linux/irq.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <asm/io.h>
18
19#include "hlwd-pic.h"
20
21#define HLWD_NR_IRQS 32
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30
31#define HW_BROADWAY_ICR 0x00
32#define HW_BROADWAY_IMR 0x04
33#define HW_STARLET_ICR 0x08
34#define HW_STARLET_IMR 0x0c
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40
41
42static void hlwd_pic_mask_and_ack(struct irq_data *d)
43{
44 int irq = irqd_to_hwirq(d);
45 void __iomem *io_base = irq_data_get_irq_chip_data(d);
46 u32 mask = 1 << irq;
47
48 clrbits32(io_base + HW_BROADWAY_IMR, mask);
49 out_be32(io_base + HW_BROADWAY_ICR, mask);
50}
51
52static void hlwd_pic_ack(struct irq_data *d)
53{
54 int irq = irqd_to_hwirq(d);
55 void __iomem *io_base = irq_data_get_irq_chip_data(d);
56
57 out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
58}
59
60static void hlwd_pic_mask(struct irq_data *d)
61{
62 int irq = irqd_to_hwirq(d);
63 void __iomem *io_base = irq_data_get_irq_chip_data(d);
64
65 clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
66}
67
68static void hlwd_pic_unmask(struct irq_data *d)
69{
70 int irq = irqd_to_hwirq(d);
71 void __iomem *io_base = irq_data_get_irq_chip_data(d);
72
73 setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
74
75
76 clrbits32(io_base + HW_STARLET_IMR, 1 << irq);
77}
78
79
80static struct irq_chip hlwd_pic = {
81 .name = "hlwd-pic",
82 .irq_ack = hlwd_pic_ack,
83 .irq_mask_ack = hlwd_pic_mask_and_ack,
84 .irq_mask = hlwd_pic_mask,
85 .irq_unmask = hlwd_pic_unmask,
86};
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92
93static struct irq_domain *hlwd_irq_host;
94
95static int hlwd_pic_map(struct irq_domain *h, unsigned int virq,
96 irq_hw_number_t hwirq)
97{
98 irq_set_chip_data(virq, h->host_data);
99 irq_set_status_flags(virq, IRQ_LEVEL);
100 irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
101 return 0;
102}
103
104static const struct irq_domain_ops hlwd_irq_domain_ops = {
105 .map = hlwd_pic_map,
106};
107
108static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
109{
110 void __iomem *io_base = h->host_data;
111 int irq;
112 u32 irq_status;
113
114 irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
115 in_be32(io_base + HW_BROADWAY_IMR);
116 if (irq_status == 0)
117 return 0;
118
119 irq = __ffs(irq_status);
120 return irq_linear_revmap(h, irq);
121}
122
123static void hlwd_pic_irq_cascade(struct irq_desc *desc)
124{
125 struct irq_chip *chip = irq_desc_get_chip(desc);
126 struct irq_domain *irq_domain = irq_desc_get_handler_data(desc);
127 unsigned int virq;
128
129 raw_spin_lock(&desc->lock);
130 chip->irq_mask(&desc->irq_data);
131 raw_spin_unlock(&desc->lock);
132
133 virq = __hlwd_pic_get_irq(irq_domain);
134 if (virq)
135 generic_handle_irq(virq);
136 else
137 pr_err("spurious interrupt!\n");
138
139 raw_spin_lock(&desc->lock);
140 chip->irq_ack(&desc->irq_data);
141 if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
142 chip->irq_unmask(&desc->irq_data);
143 raw_spin_unlock(&desc->lock);
144}
145
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149
150
151static void __hlwd_quiesce(void __iomem *io_base)
152{
153
154 out_be32(io_base + HW_BROADWAY_IMR, 0);
155 out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
156}
157
158static struct irq_domain *hlwd_pic_init(struct device_node *np)
159{
160 struct irq_domain *irq_domain;
161 struct resource res;
162 void __iomem *io_base;
163 int retval;
164
165 retval = of_address_to_resource(np, 0, &res);
166 if (retval) {
167 pr_err("no io memory range found\n");
168 return NULL;
169 }
170 io_base = ioremap(res.start, resource_size(&res));
171 if (!io_base) {
172 pr_err("ioremap failed\n");
173 return NULL;
174 }
175
176 pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
177
178 __hlwd_quiesce(io_base);
179
180 irq_domain = irq_domain_add_linear(np, HLWD_NR_IRQS,
181 &hlwd_irq_domain_ops, io_base);
182 if (!irq_domain) {
183 pr_err("failed to allocate irq_domain\n");
184 iounmap(io_base);
185 return NULL;
186 }
187
188 return irq_domain;
189}
190
191unsigned int hlwd_pic_get_irq(void)
192{
193 return __hlwd_pic_get_irq(hlwd_irq_host);
194}
195
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199
200
201void hlwd_pic_probe(void)
202{
203 struct irq_domain *host;
204 struct device_node *np;
205 const u32 *interrupts;
206 int cascade_virq;
207
208 for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") {
209 interrupts = of_get_property(np, "interrupts", NULL);
210 if (interrupts) {
211 host = hlwd_pic_init(np);
212 BUG_ON(!host);
213 cascade_virq = irq_of_parse_and_map(np, 0);
214 irq_set_handler_data(cascade_virq, host);
215 irq_set_chained_handler(cascade_virq,
216 hlwd_pic_irq_cascade);
217 hlwd_irq_host = host;
218 break;
219 }
220 }
221}
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227
228
229void hlwd_quiesce(void)
230{
231 void __iomem *io_base = hlwd_irq_host->host_data;
232
233 __hlwd_quiesce(io_base);
234}
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236