1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver. 4 * 5 * (c) 2006-2008 MSC Vertriebsges.m.b.H., 6 * Manuel Lauss <mano@roarinelk.homelinux.net> 7 * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 8 */ 9 10#ifndef _ASM_SH_SH7760FB_H 11#define _ASM_SH_SH7760FB_H 12 13/* 14 * some bits of the colormap registers should be written as zero. 15 * create a mask for that. 16 */ 17#define SH7760FB_PALETTE_MASK 0x00f8fcf8 18 19/* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */ 20#define SH7760FB_DMA_MASK 0x0C000000 21 22/* palette */ 23#define LDPR(x) (((x) << 2)) 24 25/* framebuffer registers and bits */ 26#define LDICKR 0x400 27#define LDMTR 0x402 28/* see sh7760fb.h for LDMTR bits */ 29#define LDDFR 0x404 30#define LDDFR_PABD (1 << 8) 31#define LDDFR_COLOR_MASK 0x7F 32#define LDSMR 0x406 33#define LDSMR_ROT (1 << 13) 34#define LDSARU 0x408 35#define LDSARL 0x40c 36#define LDLAOR 0x410 37#define LDPALCR 0x412 38#define LDPALCR_PALS (1 << 4) 39#define LDPALCR_PALEN (1 << 0) 40#define LDHCNR 0x414 41#define LDHSYNR 0x416 42#define LDVDLNR 0x418 43#define LDVTLNR 0x41a 44#define LDVSYNR 0x41c 45#define LDACLNR 0x41e 46#define LDINTR 0x420 47#define LDPMMR 0x424 48#define LDPSPR 0x426 49#define LDCNTR 0x428 50#define LDCNTR_DON (1 << 0) 51#define LDCNTR_DON2 (1 << 4) 52 53#ifdef CONFIG_CPU_SUBTYPE_SH7763 54# define LDLIRNR 0x440 55/* LDINTR bit */ 56# define LDINTR_MINTEN (1 << 15) 57# define LDINTR_FINTEN (1 << 14) 58# define LDINTR_VSINTEN (1 << 13) 59# define LDINTR_VEINTEN (1 << 12) 60# define LDINTR_MINTS (1 << 11) 61# define LDINTR_FINTS (1 << 10) 62# define LDINTR_VSINTS (1 << 9) 63# define LDINTR_VEINTS (1 << 8) 64# define VINT_START (LDINTR_VSINTEN) 65# define VINT_CHECK (LDINTR_VSINTS) 66#else 67/* LDINTR bit */ 68# define LDINTR_VINTSEL (1 << 12) 69# define LDINTR_VINTE (1 << 8) 70# define LDINTR_VINTS (1 << 0) 71# define VINT_START (LDINTR_VINTSEL) 72# define VINT_CHECK (LDINTR_VINTS) 73#endif 74 75/* HSYNC polarity inversion */ 76#define LDMTR_FLMPOL (1 << 15) 77 78/* VSYNC polarity inversion */ 79#define LDMTR_CL1POL (1 << 14) 80 81/* DISPLAY-ENABLE polarity inversion */ 82#define LDMTR_DISPEN_LOWACT (1 << 13) 83 84/* DISPLAY DATA BUS polarity inversion */ 85#define LDMTR_DPOL_LOWACT (1 << 12) 86 87/* AC modulation signal enable */ 88#define LDMTR_MCNT (1 << 10) 89 90/* Disable output of HSYNC during VSYNC period */ 91#define LDMTR_CL1CNT (1 << 9) 92 93/* Disable output of VSYNC during VSYNC period */ 94#define LDMTR_CL2CNT (1 << 8) 95 96/* Display types supported by the LCDC */ 97#define LDMTR_STN_MONO_4 0x00 98#define LDMTR_STN_MONO_8 0x01 99#define LDMTR_STN_COLOR_4 0x08 100#define LDMTR_STN_COLOR_8 0x09 101#define LDMTR_STN_COLOR_12 0x0A 102#define LDMTR_STN_COLOR_16 0x0B 103#define LDMTR_DSTN_MONO_8 0x11 104#define LDMTR_DSTN_MONO_16 0x13 105#define LDMTR_DSTN_COLOR_8 0x19 106#define LDMTR_DSTN_COLOR_12 0x1A 107#define LDMTR_DSTN_COLOR_16 0x1B 108#define LDMTR_TFT_COLOR_16 0x2B 109 110/* framebuffer color layout */ 111#define LDDFR_1BPP_MONO 0x00 112#define LDDFR_2BPP_MONO 0x01 113#define LDDFR_4BPP_MONO 0x02 114#define LDDFR_6BPP_MONO 0x04 115#define LDDFR_4BPP 0x0A 116#define LDDFR_8BPP 0x0C 117#define LDDFR_16BPP_RGB555 0x1D 118#define LDDFR_16BPP_RGB565 0x2D 119 120/* LCDC Pixclock sources */ 121#define LCDC_CLKSRC_BUSCLOCK 0 122#define LCDC_CLKSRC_PERIPHERAL 1 123#define LCDC_CLKSRC_EXTERNAL 2 124 125#define LDICKR_CLKSRC(x) \ 126 (((x) & 3) << 12) 127 128/* LCDC pixclock input divider. Set to 1 at a minimum! */ 129#define LDICKR_CLKDIV(x) \ 130 ((x) & 0x1f) 131 132struct sh7760fb_platdata { 133 134 /* Set this member to a valid fb_videmode for the display you 135 * wish to use. The following members must be initialized: 136 * xres, yres, hsync_len, vsync_len, sync, 137 * {left,right,upper,lower}_margin. 138 * The driver uses the above members to calculate register values 139 * and memory requirements. Other members are ignored but may 140 * be used by other framebuffer layer components. 141 */ 142 struct fb_videomode *def_mode; 143 144 /* LDMTR includes display type and signal polarity. The 145 * HSYNC/VSYNC polarities are derived from the fb_var_screeninfo 146 * data above; however the polarities of the following signals 147 * must be encoded in the ldmtr member: 148 * Display Enable signal (default high-active) DISPEN_LOWACT 149 * Display Data signals (default high-active) DPOL_LOWACT 150 * AC Modulation signal (default off) MCNT 151 * Hsync-During-Vsync suppression (default off) CL1CNT 152 * Vsync-during-vsync suppression (default off) CL2CNT 153 * NOTE: also set a display type! 154 * (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16}) 155 */ 156 u16 ldmtr; 157 158 /* LDDFR controls framebuffer image format (depth, organization) 159 * Use ONE of the LDDFR_?BPP_* macros! 160 */ 161 u16 lddfr; 162 163 /* LDPMMR and LDPSPR control the timing of the power signals 164 * for the display. Please read the SH7760 Hardware Manual, 165 * Chapters 30.3.17, 30.3.18 and 30.4.6! 166 */ 167 u16 ldpmmr; 168 u16 ldpspr; 169 170 /* LDACLNR contains the line numbers after which the AC modulation 171 * signal is to toggle. Set to ZERO for TFTs or displays which 172 * do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual). 173 */ 174 u16 ldaclnr; 175 176 /* LDICKR contains information on pixelclock source and config. 177 * Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros. 178 * minimal value for CLKDIV() must be 1!. 179 */ 180 u16 ldickr; 181 182 /* set this member to 1 if you wish to use the LCDC's hardware 183 * rotation function. This is limited to displays <= 320x200 184 * pixels resolution! 185 */ 186 int rotate; /* set to 1 to rotate 90 CCW */ 187 188 /* set this to 1 to suppress vsync irq use. */ 189 int novsync; 190 191 /* blanking hook for platform. Set this if your platform can do 192 * more than the LCDC in terms of blanking (e.g. disable clock 193 * generator / backlight power supply / etc. 194 */ 195 void (*blank) (int); 196}; 197 198#endif /* _ASM_SH_SH7760FB_H */ 199