1
2#ifndef _ASM_X86_APIC_H
3#define _ASM_X86_APIC_H
4
5#include <linux/cpumask.h>
6
7#include <asm/alternative.h>
8#include <asm/cpufeature.h>
9#include <asm/apicdef.h>
10#include <linux/atomic.h>
11#include <asm/fixmap.h>
12#include <asm/mpspec.h>
13#include <asm/msr.h>
14#include <asm/hardirq.h>
15
16#define ARCH_APICTIMER_STOPS_ON_C3 1
17
18
19
20
21#define APIC_QUIET 0
22#define APIC_VERBOSE 1
23#define APIC_DEBUG 2
24
25
26#define APIC_EXTNMI_BSP 0
27#define APIC_EXTNMI_ALL 1
28#define APIC_EXTNMI_NONE 2
29
30
31
32
33
34
35
36#define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
38 printk(s, ##a); \
39 } while (0)
40
41
42#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43extern void generic_apic_probe(void);
44#else
45static inline void generic_apic_probe(void)
46{
47}
48#endif
49
50#ifdef CONFIG_X86_LOCAL_APIC
51
52extern int apic_verbosity;
53extern int local_apic_timer_c2_ok;
54
55extern int disable_apic;
56extern unsigned int lapic_timer_period;
57
58extern enum apic_intr_mode_id apic_intr_mode;
59enum apic_intr_mode_id {
60 APIC_PIC,
61 APIC_VIRTUAL_WIRE,
62 APIC_VIRTUAL_WIRE_NO_CONFIG,
63 APIC_SYMMETRIC_IO,
64 APIC_SYMMETRIC_IO_NO_ROUTING
65};
66
67#ifdef CONFIG_SMP
68extern void __inquire_remote_apic(int apicid);
69#else
70static inline void __inquire_remote_apic(int apicid)
71{
72}
73#endif
74
75static inline void default_inquire_remote_apic(int apicid)
76{
77 if (apic_verbosity >= APIC_DEBUG)
78 __inquire_remote_apic(apicid);
79}
80
81
82
83
84
85
86
87
88
89static inline bool apic_from_smp_config(void)
90{
91 return smp_found_config && !disable_apic;
92}
93
94
95
96
97#ifdef CONFIG_PARAVIRT
98#include <asm/paravirt.h>
99#endif
100
101extern int setup_profiling_timer(unsigned int);
102
103static inline void native_apic_mem_write(u32 reg, u32 v)
104{
105 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
106
107 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
108 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
109 ASM_OUTPUT2("0" (v), "m" (*addr)));
110}
111
112static inline u32 native_apic_mem_read(u32 reg)
113{
114 return *((volatile u32 *)(APIC_BASE + reg));
115}
116
117extern void native_apic_wait_icr_idle(void);
118extern u32 native_safe_apic_wait_icr_idle(void);
119extern void native_apic_icr_write(u32 low, u32 id);
120extern u64 native_apic_icr_read(void);
121
122static inline bool apic_is_x2apic_enabled(void)
123{
124 u64 msr;
125
126 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
127 return false;
128 return msr & X2APIC_ENABLE;
129}
130
131extern void enable_IR_x2apic(void);
132
133extern int get_physical_broadcast(void);
134
135extern int lapic_get_maxlvt(void);
136extern void clear_local_APIC(void);
137extern void disconnect_bsp_APIC(int virt_wire_setup);
138extern void disable_local_APIC(void);
139extern void apic_soft_disable(void);
140extern void lapic_shutdown(void);
141extern void sync_Arb_IDs(void);
142extern void init_bsp_APIC(void);
143extern void apic_intr_mode_init(void);
144extern void init_apic_mappings(void);
145void register_lapic_address(unsigned long address);
146extern void setup_boot_APIC_clock(void);
147extern void setup_secondary_APIC_clock(void);
148extern void lapic_update_tsc_freq(void);
149
150#ifdef CONFIG_X86_64
151static inline int apic_force_enable(unsigned long addr)
152{
153 return -1;
154}
155#else
156extern int apic_force_enable(unsigned long addr);
157#endif
158
159extern void apic_ap_setup(void);
160
161
162
163
164#ifdef CONFIG_X86_64
165extern int apic_is_clustered_box(void);
166#else
167static inline int apic_is_clustered_box(void)
168{
169 return 0;
170}
171#endif
172
173extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
174extern void lapic_assign_system_vectors(void);
175extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
176extern void lapic_online(void);
177extern void lapic_offline(void);
178extern bool apic_needs_pit(void);
179
180extern void apic_send_IPI_allbutself(unsigned int vector);
181
182#else
183static inline void lapic_shutdown(void) { }
184#define local_apic_timer_c2_ok 1
185static inline void init_apic_mappings(void) { }
186static inline void disable_local_APIC(void) { }
187# define setup_boot_APIC_clock x86_init_noop
188# define setup_secondary_APIC_clock x86_init_noop
189static inline void lapic_update_tsc_freq(void) { }
190static inline void init_bsp_APIC(void) { }
191static inline void apic_intr_mode_init(void) { }
192static inline void lapic_assign_system_vectors(void) { }
193static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
194static inline bool apic_needs_pit(void) { return true; }
195#endif
196
197#ifdef CONFIG_X86_X2APIC
198
199
200
201
202
203static inline void x2apic_wrmsr_fence(void)
204{
205 asm volatile("mfence" : : : "memory");
206}
207
208static inline void native_apic_msr_write(u32 reg, u32 v)
209{
210 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
211 reg == APIC_LVR)
212 return;
213
214 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
215}
216
217static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
218{
219 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
220}
221
222static inline u32 native_apic_msr_read(u32 reg)
223{
224 u64 msr;
225
226 if (reg == APIC_DFR)
227 return -1;
228
229 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
230 return (u32)msr;
231}
232
233static inline void native_x2apic_wait_icr_idle(void)
234{
235
236 return;
237}
238
239static inline u32 native_safe_x2apic_wait_icr_idle(void)
240{
241
242 return 0;
243}
244
245static inline void native_x2apic_icr_write(u32 low, u32 id)
246{
247 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
248}
249
250static inline u64 native_x2apic_icr_read(void)
251{
252 unsigned long val;
253
254 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
255 return val;
256}
257
258extern int x2apic_mode;
259extern int x2apic_phys;
260extern void __init check_x2apic(void);
261extern void x2apic_setup(void);
262static inline int x2apic_enabled(void)
263{
264 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
265}
266
267#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
268#else
269static inline void check_x2apic(void) { }
270static inline void x2apic_setup(void) { }
271static inline int x2apic_enabled(void) { return 0; }
272
273#define x2apic_mode (0)
274#define x2apic_supported() (0)
275#endif
276
277struct irq_data;
278
279
280
281
282
283
284
285
286
287
288struct apic {
289
290 void (*eoi_write)(u32 reg, u32 v);
291 void (*native_eoi_write)(u32 reg, u32 v);
292 void (*write)(u32 reg, u32 v);
293 u32 (*read)(u32 reg);
294
295
296 void (*wait_icr_idle)(void);
297 u32 (*safe_wait_icr_idle)(void);
298
299 void (*send_IPI)(int cpu, int vector);
300 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
301 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
302 void (*send_IPI_allbutself)(int vector);
303 void (*send_IPI_all)(int vector);
304 void (*send_IPI_self)(int vector);
305
306
307 u32 dest_logical;
308 u32 disable_esr;
309 u32 irq_delivery_mode;
310 u32 irq_dest_mode;
311
312 u32 (*calc_dest_apicid)(unsigned int cpu);
313
314
315 u64 (*icr_read)(void);
316 void (*icr_write)(u32 low, u32 high);
317
318
319 int (*probe)(void);
320 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
321 int (*apic_id_valid)(u32 apicid);
322 int (*apic_id_registered)(void);
323
324 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
325 void (*init_apic_ldr)(void);
326 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
327 void (*setup_apic_routing)(void);
328 int (*cpu_present_to_apicid)(int mps_cpu);
329 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
330 int (*check_phys_apicid_present)(int phys_apicid);
331 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
332
333 u32 (*get_apic_id)(unsigned long x);
334 u32 (*set_apic_id)(unsigned int id);
335
336
337 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
338
339 void (*inquire_remote_apic)(int apicid);
340
341#ifdef CONFIG_X86_32
342
343
344
345
346
347
348
349
350
351
352 int (*x86_32_early_logical_apicid)(int cpu);
353#endif
354 char *name;
355};
356
357
358
359
360
361
362extern struct apic *apic;
363
364
365
366
367
368
369
370
371
372#define apic_driver(sym) \
373 static const struct apic *__apicdrivers_##sym __used \
374 __aligned(sizeof(struct apic *)) \
375 __section(.apicdrivers) = { &sym }
376
377#define apic_drivers(sym1, sym2) \
378 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
379 __aligned(sizeof(struct apic *)) \
380 __section(.apicdrivers) = { &sym1, &sym2 }
381
382extern struct apic *__apicdrivers[], *__apicdrivers_end[];
383
384
385
386
387#ifdef CONFIG_SMP
388extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
389extern int lapic_can_unplug_cpu(void);
390#endif
391
392#ifdef CONFIG_X86_LOCAL_APIC
393
394static inline u32 apic_read(u32 reg)
395{
396 return apic->read(reg);
397}
398
399static inline void apic_write(u32 reg, u32 val)
400{
401 apic->write(reg, val);
402}
403
404static inline void apic_eoi(void)
405{
406 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
407}
408
409static inline u64 apic_icr_read(void)
410{
411 return apic->icr_read();
412}
413
414static inline void apic_icr_write(u32 low, u32 high)
415{
416 apic->icr_write(low, high);
417}
418
419static inline void apic_wait_icr_idle(void)
420{
421 apic->wait_icr_idle();
422}
423
424static inline u32 safe_apic_wait_icr_idle(void)
425{
426 return apic->safe_wait_icr_idle();
427}
428
429extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
430
431#else
432
433static inline u32 apic_read(u32 reg) { return 0; }
434static inline void apic_write(u32 reg, u32 val) { }
435static inline void apic_eoi(void) { }
436static inline u64 apic_icr_read(void) { return 0; }
437static inline void apic_icr_write(u32 low, u32 high) { }
438static inline void apic_wait_icr_idle(void) { }
439static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
440static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
441
442#endif
443
444extern void apic_ack_irq(struct irq_data *data);
445
446static inline void ack_APIC_irq(void)
447{
448
449
450
451
452 apic_eoi();
453}
454
455static inline unsigned default_get_apic_id(unsigned long x)
456{
457 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
458
459 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
460 return (x >> 24) & 0xFF;
461 else
462 return (x >> 24) & 0x0F;
463}
464
465
466
467
468#define TRAMPOLINE_PHYS_LOW 0x467
469#define TRAMPOLINE_PHYS_HIGH 0x469
470
471extern void generic_bigsmp_probe(void);
472
473#ifdef CONFIG_X86_LOCAL_APIC
474
475#include <asm/smp.h>
476
477#define APIC_DFR_VALUE (APIC_DFR_FLAT)
478
479DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
480
481extern struct apic apic_noop;
482
483static inline unsigned int read_apic_id(void)
484{
485 unsigned int reg = apic_read(APIC_ID);
486
487 return apic->get_apic_id(reg);
488}
489
490extern int default_apic_id_valid(u32 apicid);
491extern int default_acpi_madt_oem_check(char *, char *);
492extern void default_setup_apic_routing(void);
493
494extern u32 apic_default_calc_apicid(unsigned int cpu);
495extern u32 apic_flat_calc_apicid(unsigned int cpu);
496
497extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
498extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
499extern int default_cpu_present_to_apicid(int mps_cpu);
500extern int default_check_phys_apicid_present(int phys_apicid);
501
502#endif
503
504#ifdef CONFIG_SMP
505bool apic_id_is_primary_thread(unsigned int id);
506void apic_smt_update(void);
507#else
508static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
509static inline void apic_smt_update(void) { }
510#endif
511
512extern void irq_enter(void);
513extern void irq_exit(void);
514
515static inline void entering_irq(void)
516{
517 irq_enter();
518 kvm_set_cpu_l1tf_flush_l1d();
519}
520
521static inline void entering_ack_irq(void)
522{
523 entering_irq();
524 ack_APIC_irq();
525}
526
527static inline void ipi_entering_ack_irq(void)
528{
529 irq_enter();
530 ack_APIC_irq();
531 kvm_set_cpu_l1tf_flush_l1d();
532}
533
534static inline void exiting_irq(void)
535{
536 irq_exit();
537}
538
539static inline void exiting_ack_irq(void)
540{
541 ack_APIC_irq();
542 irq_exit();
543}
544
545extern void ioapic_zap_locks(void);
546
547#endif
548