1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25#ifndef __DISPLAY_MODE_STRUCTS_H__ 26#define __DISPLAY_MODE_STRUCTS_H__ 27 28#define MAX_CLOCK_LIMIT_STATES 8 29 30typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st; 31typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st; 32typedef struct _vcs_dpi_ip_params_st ip_params_st; 33typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st; 34typedef struct _vcs_dpi_display_output_params_st display_output_params_st; 35typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st; 36typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st; 37typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st; 38typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st; 39typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st; 40typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st; 41typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st; 42typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st; 43typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st; 44typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st; 45typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st; 46typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st; 47typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st; 48typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st; 49typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st; 50typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st; 51typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; 52typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; 53typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; 54 55struct _vcs_dpi_voltage_scaling_st { 56 int state; 57 double dscclk_mhz; 58 double dcfclk_mhz; 59 double socclk_mhz; 60 double phyclk_d18_mhz; 61 double dram_speed_mts; 62 double fabricclk_mhz; 63 double dispclk_mhz; 64 double phyclk_mhz; 65 double dppclk_mhz; 66}; 67 68struct _vcs_dpi_soc_bounding_box_st { 69 double sr_exit_time_us; 70 double sr_enter_plus_exit_time_us; 71 double urgent_latency_us; 72 double urgent_latency_pixel_data_only_us; 73 double urgent_latency_pixel_mixed_with_vm_data_us; 74 double urgent_latency_vm_data_only_us; 75 double writeback_latency_us; 76 double ideal_dram_bw_after_urgent_percent; 77 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly 78 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 79 double pct_ideal_dram_sdp_bw_after_urgent_vm_only; 80 double max_avg_sdp_bw_use_normal_percent; 81 double max_avg_dram_bw_use_normal_percent; 82 unsigned int max_request_size_bytes; 83 double downspread_percent; 84 double dram_page_open_time_ns; 85 double dram_rw_turnaround_time_ns; 86 double dram_return_buffer_per_channel_bytes; 87 double dram_channel_width_bytes; 88 double fabric_datapath_to_dcn_data_return_bytes; 89 double dcn_downspread_percent; 90 double dispclk_dppclk_vco_speed_mhz; 91 double dfs_vco_period_ps; 92 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; 93 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 94 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; 95 unsigned int round_trip_ping_latency_dcfclk_cycles; 96 unsigned int urgent_out_of_order_return_per_channel_bytes; 97 unsigned int channel_interleave_bytes; 98 unsigned int num_banks; 99 unsigned int num_chans; 100 unsigned int vmm_page_size_bytes; 101 unsigned int hostvm_min_page_size_bytes; 102 double dram_clock_change_latency_us; 103 double dummy_pstate_latency_us; 104 double writeback_dram_clock_change_latency_us; 105 unsigned int return_bus_width_bytes; 106 unsigned int voltage_override; 107 double xfc_bus_transport_time_us; 108 double xfc_xbuf_latency_tolerance_us; 109 int use_urgent_burst_bw; 110 unsigned int num_states; 111 struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES]; 112 bool do_urgent_latency_adjustment; 113 double urgent_latency_adjustment_fabric_clock_component_us; 114 double urgent_latency_adjustment_fabric_clock_reference_mhz; 115}; 116 117struct _vcs_dpi_ip_params_st { 118 bool gpuvm_enable; 119 bool hostvm_enable; 120 unsigned int gpuvm_max_page_table_levels; 121 unsigned int hostvm_max_page_table_levels; 122 unsigned int hostvm_cached_page_table_levels; 123 unsigned int pte_group_size_bytes; 124 unsigned int max_inter_dcn_tile_repeaters; 125 unsigned int num_dsc; 126 unsigned int odm_capable; 127 unsigned int rob_buffer_size_kbytes; 128 unsigned int det_buffer_size_kbytes; 129 unsigned int dpte_buffer_size_in_pte_reqs_luma; 130 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 131 unsigned int pde_proc_buffer_size_64k_reqs; 132 unsigned int dpp_output_buffer_pixels; 133 unsigned int opp_output_buffer_lines; 134 unsigned int pixel_chunk_size_kbytes; 135 unsigned char pte_enable; 136 unsigned int pte_chunk_size_kbytes; 137 unsigned int meta_chunk_size_kbytes; 138 unsigned int writeback_chunk_size_kbytes; 139 unsigned int line_buffer_size_bits; 140 unsigned int max_line_buffer_lines; 141 unsigned int writeback_luma_buffer_size_kbytes; 142 unsigned int writeback_chroma_buffer_size_kbytes; 143 unsigned int writeback_chroma_line_buffer_width_pixels; 144 145 unsigned int writeback_interface_buffer_size_kbytes; 146 unsigned int writeback_line_buffer_buffer_size; 147 148#ifdef CONFIG_DRM_AMD_DC_DCN2_0 149 unsigned int writeback_10bpc420_supported; 150 double writeback_max_hscl_ratio; 151 double writeback_max_vscl_ratio; 152 double writeback_min_hscl_ratio; 153 double writeback_min_vscl_ratio; 154 unsigned int writeback_max_hscl_taps; 155 unsigned int writeback_max_vscl_taps; 156 unsigned int writeback_line_buffer_luma_buffer_size; 157 unsigned int writeback_line_buffer_chroma_buffer_size; 158#endif 159 160 unsigned int max_page_table_levels; 161 unsigned int max_num_dpp; 162 unsigned int max_num_otg; 163 unsigned int cursor_chunk_size; 164 unsigned int cursor_buffer_size; 165 unsigned int max_num_wb; 166 unsigned int max_dchub_pscl_bw_pix_per_clk; 167 unsigned int max_pscl_lb_bw_pix_per_clk; 168 unsigned int max_lb_vscl_bw_pix_per_clk; 169 unsigned int max_vscl_hscl_bw_pix_per_clk; 170 double max_hscl_ratio; 171 double max_vscl_ratio; 172 unsigned int hscl_mults; 173 unsigned int vscl_mults; 174 unsigned int max_hscl_taps; 175 unsigned int max_vscl_taps; 176 unsigned int xfc_supported; 177 unsigned int ptoi_supported; 178 unsigned int gfx7_compat_tiling_supported; 179 180 bool odm_combine_4to1_supported; 181 bool dynamic_metadata_vm_enabled; 182 unsigned int max_num_hdmi_frl_outputs; 183 184 unsigned int xfc_fill_constant_bytes; 185 double dispclk_ramp_margin_percent; 186 double xfc_fill_bw_overhead_percent; 187 double underscan_factor; 188 unsigned int min_vblank_lines; 189 unsigned int dppclk_delay_subtotal; 190 unsigned int dispclk_delay_subtotal; 191 unsigned int dcfclk_cstate_latency; 192 unsigned int dppclk_delay_scl; 193 unsigned int dppclk_delay_scl_lb_only; 194 unsigned int dppclk_delay_cnvc_formatter; 195 unsigned int dppclk_delay_cnvc_cursor; 196 unsigned int is_line_buffer_bpp_fixed; 197 unsigned int line_buffer_fixed_bpp; 198 unsigned int dcc_supported; 199 200 unsigned int IsLineBufferBppFixed; 201 unsigned int LineBufferFixedBpp; 202 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 203 unsigned int bug_forcing_LC_req_same_size_fixed; 204}; 205 206struct _vcs_dpi_display_xfc_params_st { 207 double xfc_tslv_vready_offset_us; 208 double xfc_tslv_vupdate_width_us; 209 double xfc_tslv_vupdate_offset_us; 210 int xfc_slv_chunk_size_bytes; 211}; 212 213struct _vcs_dpi_display_pipe_source_params_st { 214 int source_format; 215 unsigned char dcc; 216 unsigned int dcc_rate; 217 unsigned char dcc_use_global; 218 unsigned char vm; 219 bool gpuvm; // gpuvm enabled 220 bool hostvm; // hostvm enabled 221 bool gpuvm_levels_force_en; 222 unsigned int gpuvm_levels_force; 223 bool hostvm_levels_force_en; 224 unsigned int hostvm_levels_force; 225 int source_scan; 226 int sw_mode; 227 int macro_tile_size; 228 unsigned int viewport_width; 229 unsigned int viewport_height; 230 unsigned int viewport_y_y; 231 unsigned int viewport_y_c; 232 unsigned int viewport_width_c; 233 unsigned int viewport_height_c; 234 unsigned int data_pitch; 235 unsigned int data_pitch_c; 236 unsigned int meta_pitch; 237 unsigned int meta_pitch_c; 238 unsigned int cur0_src_width; 239 int cur0_bpp; 240 unsigned int cur1_src_width; 241 int cur1_bpp; 242 int num_cursors; 243 unsigned char is_hsplit; 244 unsigned char dynamic_metadata_enable; 245 unsigned int dynamic_metadata_lines_before_active; 246 unsigned int dynamic_metadata_xmit_bytes; 247 unsigned int hsplit_grp; 248 unsigned char xfc_enable; 249 unsigned char xfc_slave; 250 unsigned char immediate_flip; 251 struct _vcs_dpi_display_xfc_params_st xfc_params; 252 //for vstartuplines calculation freesync 253 unsigned char v_total_min; 254 unsigned char v_total_max; 255}; 256struct writeback_st { 257 int wb_src_height; 258 int wb_src_width; 259 int wb_dst_width; 260 int wb_dst_height; 261 int wb_pixel_format; 262 int wb_htaps_luma; 263 int wb_vtaps_luma; 264 int wb_htaps_chroma; 265 int wb_vtaps_chroma; 266 double wb_hratio; 267 double wb_vratio; 268}; 269 270struct _vcs_dpi_display_output_params_st { 271 int dp_lanes; 272 int output_bpp; 273 int dsc_enable; 274 int wb_enable; 275 int num_active_wb; 276 int output_bpc; 277 int output_type; 278 int output_format; 279 int dsc_slices; 280 struct writeback_st wb; 281}; 282 283struct _vcs_dpi_scaler_ratio_depth_st { 284 double hscl_ratio; 285 double vscl_ratio; 286 double hscl_ratio_c; 287 double vscl_ratio_c; 288 double vinit; 289 double vinit_c; 290 double vinit_bot; 291 double vinit_bot_c; 292 int lb_depth; 293 int scl_enable; 294}; 295 296struct _vcs_dpi_scaler_taps_st { 297 unsigned int htaps; 298 unsigned int vtaps; 299 unsigned int htaps_c; 300 unsigned int vtaps_c; 301}; 302 303struct _vcs_dpi_display_pipe_dest_params_st { 304 unsigned int recout_width; 305 unsigned int recout_height; 306 unsigned int full_recout_width; 307 unsigned int full_recout_height; 308 unsigned int hblank_start; 309 unsigned int hblank_end; 310 unsigned int vblank_start; 311 unsigned int vblank_end; 312 unsigned int htotal; 313 unsigned int vtotal; 314 unsigned int vactive; 315 unsigned int hactive; 316 unsigned int vstartup_start; 317 unsigned int vupdate_offset; 318 unsigned int vupdate_width; 319 unsigned int vready_offset; 320 unsigned char interlaced; 321 double pixel_rate_mhz; 322 unsigned char synchronized_vblank_all_planes; 323 unsigned char otg_inst; 324 unsigned char odm_combine; 325 unsigned char use_maximum_vstartup; 326 unsigned int vtotal_max; 327 unsigned int vtotal_min; 328}; 329 330struct _vcs_dpi_display_pipe_params_st { 331 display_pipe_source_params_st src; 332 display_pipe_dest_params_st dest; 333 scaler_ratio_depth_st scale_ratio_depth; 334 scaler_taps_st scale_taps; 335}; 336 337struct _vcs_dpi_display_clocks_and_cfg_st { 338 int voltage; 339 double dppclk_mhz; 340 double refclk_mhz; 341 double dispclk_mhz; 342 double dcfclk_mhz; 343 double socclk_mhz; 344}; 345 346struct _vcs_dpi_display_e2e_pipe_params_st { 347 display_pipe_params_st pipe; 348 display_output_params_st dout; 349 display_clocks_and_cfg_st clks_cfg; 350}; 351 352struct _vcs_dpi_display_data_rq_misc_params_st { 353 unsigned int full_swath_bytes; 354 unsigned int stored_swath_bytes; 355 unsigned int blk256_height; 356 unsigned int blk256_width; 357 unsigned int req_height; 358 unsigned int req_width; 359}; 360 361struct _vcs_dpi_display_data_rq_sizing_params_st { 362 unsigned int chunk_bytes; 363 unsigned int min_chunk_bytes; 364 unsigned int meta_chunk_bytes; 365 unsigned int min_meta_chunk_bytes; 366 unsigned int mpte_group_bytes; 367 unsigned int dpte_group_bytes; 368}; 369 370struct _vcs_dpi_display_data_rq_dlg_params_st { 371 unsigned int swath_width_ub; 372 unsigned int swath_height; 373 unsigned int req_per_swath_ub; 374 unsigned int meta_pte_bytes_per_frame_ub; 375 unsigned int dpte_req_per_row_ub; 376 unsigned int dpte_groups_per_row_ub; 377 unsigned int dpte_row_height; 378 unsigned int dpte_bytes_per_row_ub; 379 unsigned int meta_chunks_per_row_ub; 380 unsigned int meta_req_per_row_ub; 381 unsigned int meta_row_height; 382 unsigned int meta_bytes_per_row_ub; 383}; 384 385struct _vcs_dpi_display_rq_dlg_params_st { 386 display_data_rq_dlg_params_st rq_l; 387 display_data_rq_dlg_params_st rq_c; 388}; 389 390struct _vcs_dpi_display_rq_sizing_params_st { 391 display_data_rq_sizing_params_st rq_l; 392 display_data_rq_sizing_params_st rq_c; 393}; 394 395struct _vcs_dpi_display_rq_misc_params_st { 396 display_data_rq_misc_params_st rq_l; 397 display_data_rq_misc_params_st rq_c; 398}; 399 400struct _vcs_dpi_display_rq_params_st { 401 unsigned char yuv420; 402 unsigned char yuv420_10bpc; 403 display_rq_misc_params_st misc; 404 display_rq_sizing_params_st sizing; 405 display_rq_dlg_params_st dlg; 406}; 407 408struct _vcs_dpi_display_dlg_regs_st { 409 unsigned int refcyc_h_blank_end; 410 unsigned int dlg_vblank_end; 411 unsigned int min_dst_y_next_start; 412 unsigned int refcyc_per_htotal; 413 unsigned int refcyc_x_after_scaler; 414 unsigned int dst_y_after_scaler; 415 unsigned int dst_y_prefetch; 416 unsigned int dst_y_per_vm_vblank; 417 unsigned int dst_y_per_row_vblank; 418 unsigned int dst_y_per_vm_flip; 419 unsigned int dst_y_per_row_flip; 420 unsigned int ref_freq_to_pix_freq; 421 unsigned int vratio_prefetch; 422 unsigned int vratio_prefetch_c; 423 unsigned int refcyc_per_pte_group_vblank_l; 424 unsigned int refcyc_per_pte_group_vblank_c; 425 unsigned int refcyc_per_meta_chunk_vblank_l; 426 unsigned int refcyc_per_meta_chunk_vblank_c; 427 unsigned int refcyc_per_pte_group_flip_l; 428 unsigned int refcyc_per_pte_group_flip_c; 429 unsigned int refcyc_per_meta_chunk_flip_l; 430 unsigned int refcyc_per_meta_chunk_flip_c; 431 unsigned int dst_y_per_pte_row_nom_l; 432 unsigned int dst_y_per_pte_row_nom_c; 433 unsigned int refcyc_per_pte_group_nom_l; 434 unsigned int refcyc_per_pte_group_nom_c; 435 unsigned int dst_y_per_meta_row_nom_l; 436 unsigned int dst_y_per_meta_row_nom_c; 437 unsigned int refcyc_per_meta_chunk_nom_l; 438 unsigned int refcyc_per_meta_chunk_nom_c; 439 unsigned int refcyc_per_line_delivery_pre_l; 440 unsigned int refcyc_per_line_delivery_pre_c; 441 unsigned int refcyc_per_line_delivery_l; 442 unsigned int refcyc_per_line_delivery_c; 443 unsigned int chunk_hdl_adjust_cur0; 444 unsigned int chunk_hdl_adjust_cur1; 445 unsigned int vready_after_vcount0; 446 unsigned int dst_y_offset_cur0; 447 unsigned int dst_y_offset_cur1; 448 unsigned int xfc_reg_transfer_delay; 449 unsigned int xfc_reg_precharge_delay; 450 unsigned int xfc_reg_remote_surface_flip_latency; 451 unsigned int xfc_reg_prefetch_margin; 452 unsigned int dst_y_delta_drq_limit; 453 unsigned int refcyc_per_vm_group_vblank; 454 unsigned int refcyc_per_vm_group_flip; 455 unsigned int refcyc_per_vm_req_vblank; 456 unsigned int refcyc_per_vm_req_flip; 457 unsigned int refcyc_per_vm_dmdata; 458}; 459 460struct _vcs_dpi_display_ttu_regs_st { 461 unsigned int qos_level_low_wm; 462 unsigned int qos_level_high_wm; 463 unsigned int min_ttu_vblank; 464 unsigned int qos_level_flip; 465 unsigned int refcyc_per_req_delivery_l; 466 unsigned int refcyc_per_req_delivery_c; 467 unsigned int refcyc_per_req_delivery_cur0; 468 unsigned int refcyc_per_req_delivery_cur1; 469 unsigned int refcyc_per_req_delivery_pre_l; 470 unsigned int refcyc_per_req_delivery_pre_c; 471 unsigned int refcyc_per_req_delivery_pre_cur0; 472 unsigned int refcyc_per_req_delivery_pre_cur1; 473 unsigned int qos_level_fixed_l; 474 unsigned int qos_level_fixed_c; 475 unsigned int qos_level_fixed_cur0; 476 unsigned int qos_level_fixed_cur1; 477 unsigned int qos_ramp_disable_l; 478 unsigned int qos_ramp_disable_c; 479 unsigned int qos_ramp_disable_cur0; 480 unsigned int qos_ramp_disable_cur1; 481}; 482 483struct _vcs_dpi_display_data_rq_regs_st { 484 unsigned int chunk_size; 485 unsigned int min_chunk_size; 486 unsigned int meta_chunk_size; 487 unsigned int min_meta_chunk_size; 488 unsigned int dpte_group_size; 489 unsigned int mpte_group_size; 490 unsigned int swath_height; 491 unsigned int pte_row_height_linear; 492}; 493 494struct _vcs_dpi_display_rq_regs_st { 495 display_data_rq_regs_st rq_regs_l; 496 display_data_rq_regs_st rq_regs_c; 497 unsigned int drq_expansion_mode; 498 unsigned int prq_expansion_mode; 499 unsigned int mrq_expansion_mode; 500 unsigned int crq_expansion_mode; 501 unsigned int plane1_base_address; 502}; 503 504struct _vcs_dpi_display_dlg_sys_params_st { 505 double t_mclk_wm_us; 506 double t_urg_wm_us; 507 double t_sr_wm_us; 508 double t_extra_us; 509 double mem_trip_us; 510 double t_srx_delay_us; 511 double deepsleep_dcfclk_mhz; 512 double total_flip_bw; 513 unsigned int total_flip_bytes; 514}; 515 516struct _vcs_dpi_display_arb_params_st { 517 int max_req_outstanding; 518 int min_req_outstanding; 519 int sat_level_us; 520}; 521 522#endif /*__DISPLAY_MODE_STRUCTS_H__*/ 523