LXR linux/drivers/gpu/drm/ast/ast

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the
   6 * "Software"), to deal in the Software without restriction, including
   7 * without limitation the rights to use, copy, modify, merge, publish,
   8 * distribute, sub license, and/or sell copies of the Software, and to
   9 * permit persons to whom the Software is furnished to do so, subject to
  10 * the following conditions:
  11 *
  12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
  19 *
  20 * The above copyright notice and this permission notice (including the
  21 * next paragraph) shall be included in all copies or substantial portions
  22 * of the Software.
  23 *
  24 */
  25/*
  26 * Authors: Dave Airlie <airlied@redhat.com>
  27 */
  28
  29#include <linux/delay.h>
  30#include <linux/pci.h>
  31
  32#include <drm/drm_print.h>
  33
  34#include "ast_dram_tables.h"
  35#include "ast_drv.h"
  36
  37static void ast_post_chip_2300(struct drm_device *dev);
  38static void ast_post_chip_2500(struct drm_device *dev);
  39
  40void ast_enable_vga(struct drm_device *dev)
  41{
  42        struct ast_private *ast = dev->dev_private;
  43
  44        ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01);
  45        ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01);
  46}
  47
  48void ast_enable_mmio(struct drm_device *dev)
  49{
  50        struct ast_private *ast = dev->dev_private;
  51
  52        ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
  53}
  54
  55
  56bool ast_is_vga_enabled(struct drm_device *dev)
  57{
  58        struct ast_private *ast = dev->dev_private;
  59        u8 ch;
  60
  61        if (ast->chip == AST1180) {
  62                /* TODO 1180 */
  63        } else {
  64                ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
  65                return !!(ch & 0x01);
  66        }
  67        return false;
  68}
  69
  70static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
  71static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
  72static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
  73
  74static void
  75ast_set_def_ext_reg(struct drm_device *dev)
  76{
  77        struct ast_private *ast = dev->dev_private;
  78        u8 i, index, reg;
  79        const u8 *ext_reg_info;
  80
  81        /* reset scratch */
  82        for (i = 0x81; i <= 0x9f; i++)
  83                ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
  84
  85        if (ast->chip == AST2300 || ast->chip == AST2400 ||
  86            ast->chip == AST2500) {
  87                if (dev->pdev->revision >= 0x20)
  88                        ext_reg_info = extreginfo_ast2300;
  89                else
  90                        ext_reg_info = extreginfo_ast2300a0;
  91        } else
  92                ext_reg_info = extreginfo;
  93
  94        index = 0xa0;
  95        while (*ext_reg_info != 0xff) {
  96                ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
  97                index++;
  98                ext_reg_info++;
  99        }
 100
 101        /* disable standard IO/MEM decode if secondary */
 102        /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
 103
 104        /* Set Ext. Default */
 105        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
 106        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
 107
 108        /* Enable RAMDAC for A1 */
 109        reg = 0x04;
 110        if (ast->chip == AST2300 || ast->chip == AST2400 ||
 111            ast->chip == AST2500)
 112                reg |= 0x20;
 113        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
 114}
 115
 116u32 ast_mindwm(struct ast_private *ast, u32 r)
 117{
 118        uint32_t data;
 119
 120        ast_write32(ast, 0xf004, r & 0xffff0000);
 121        ast_write32(ast, 0xf000, 0x1);
 122
 123        do {
 124                data = ast_read32(ast, 0xf004) & 0xffff0000;
 125        } while (data != (r & 0xffff0000));
 126        return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
 127}
 128
 129void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
 130{
 131        uint32_t data;
 132        ast_write32(ast, 0xf004, r & 0xffff0000);
 133        ast_write32(ast, 0xf000, 0x1);
 134        do {
 135                data = ast_read32(ast, 0xf004) & 0xffff0000;
 136        } while (data != (r & 0xffff0000));
 137        ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
 138}
 139
 140/*
 141 * AST2100/2150 DLL CBR Setting
 142 */
 143#define CBR_SIZE_AST2150             ((16 << 10) - 1)
 144#define CBR_PASSNUM_AST2150          5
 145#define CBR_THRESHOLD_AST2150        10
 146#define CBR_THRESHOLD2_AST2150       10
 147#define TIMEOUT_AST2150              5000000
 148
 149#define CBR_PATNUM_AST2150           8
 150
 151static const u32 pattern_AST2150[14] = {
 152        0xFF00FF00,
 153        0xCC33CC33,
 154        0xAA55AA55,
 155        0xFFFE0001,
 156        0x683501FE,
 157        0x0F1929B0,
 158        0x2D0B4346,
 159        0x60767F02,
 160        0x6FBE36A6,
 161        0x3A253035,
 162        0x3019686D,
 163        0x41C6167E,
 164        0x620152BF,
 165        0x20F050E0
 166};
 167
 168static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
 169{
 170        u32 data, timeout;
 171
 172        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 173        ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
 174        timeout = 0;
 175        do {
 176                data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
 177                if (++timeout > TIMEOUT_AST2150) {
 178                        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 179                        return 0xffffffff;
 180                }
 181        } while (!data);
 182        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 183        ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
 184        timeout = 0;
 185        do {
 186                data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
 187                if (++timeout > TIMEOUT_AST2150) {
 188                        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 189                        return 0xffffffff;
 190                }
 191        } while (!data);
 192        data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
 193        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 194        return data;
 195}
 196
 197#if 0 /* unused in DDX driver - here for completeness */
 198static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
 199{
 200        u32 data, timeout;
 201
 202        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 203        ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
 204        timeout = 0;
 205        do {
 206                data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
 207                if (++timeout > TIMEOUT_AST2150) {
 208                        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 209                        return 0xffffffff;
 210                }
 211        } while (!data);
 212        data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
 213        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 214        return data;
 215}
 216#endif
 217
 218static int cbrtest_ast2150(struct ast_private *ast)
 219{
 220        int i;
 221
 222        for (i = 0; i < 8; i++)
 223                if (mmctestburst2_ast2150(ast, i))
 224                        return 0;
 225        return 1;
 226}
 227
 228static int cbrscan_ast2150(struct ast_private *ast, int busw)
 229{
 230        u32 patcnt, loop;
 231
 232        for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
 233                ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
 234                for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
 235                        if (cbrtest_ast2150(ast))
 236                                break;
 237                }
 238                if (loop == CBR_PASSNUM_AST2150)
 239                        return 0;
 240        }
 241        return 1;
 242}
 243
 244
 245static void cbrdlli_ast2150(struct ast_private *ast, int busw)
 246{
 247        u32 dll_min[4], dll_max[4], dlli, data, passcnt;
 248
 249cbr_start:
 250        dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
 251        dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
 252        passcnt = 0;
 253
 254        for (dlli = 0; dlli < 100; dlli++) {
 255                ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
 256                data = cbrscan_ast2150(ast, busw);
 257                if (data != 0) {
 258                        if (data & 0x1) {
 259                                if (dll_min[0] > dlli)
 260                                        dll_min[0] = dlli;
 261                                if (dll_max[0] < dlli)
 262                                        dll_max[0] = dlli;
 263                        }
 264                        passcnt++;
 265                } else if (passcnt >= CBR_THRESHOLD_AST2150)
 266                        goto cbr_start;
 267        }
 268        if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
 269                goto cbr_start;
 270
 271        dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
 272        ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
 273}
 274
 275
 276
 277static void ast_init_dram_reg(struct drm_device *dev)
 278{
 279        struct ast_private *ast = dev->dev_private;
 280        u8 j;
 281        u32 data, temp, i;
 282        const struct ast_dramstruct *dram_reg_info;
 283
 284        j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
 285
 286        if ((j & 0x80) == 0) { /* VGA only */
 287                if (ast->chip == AST2000) {
 288                        dram_reg_info = ast2000_dram_table_data;
 289                        ast_write32(ast, 0xf004, 0x1e6e0000);
 290                        ast_write32(ast, 0xf000, 0x1);
 291                        ast_write32(ast, 0x10100, 0xa8);
 292
 293                        do {
 294                                ;
 295                        } while (ast_read32(ast, 0x10100) != 0xa8);
 296                } else {/* AST2100/1100 */
 297                        if (ast->chip == AST2100 || ast->chip == 2200)
 298                                dram_reg_info = ast2100_dram_table_data;
 299                        else
 300                                dram_reg_info = ast1100_dram_table_data;
 301
 302                        ast_write32(ast, 0xf004, 0x1e6e0000);
 303                        ast_write32(ast, 0xf000, 0x1);
 304                        ast_write32(ast, 0x12000, 0x1688A8A8);
 305                        do {
 306                                ;
 307                        } while (ast_read32(ast, 0x12000) != 0x01);
 308
 309                        ast_write32(ast, 0x10000, 0xfc600309);
 310                        do {
 311                                ;
 312                        } while (ast_read32(ast, 0x10000) != 0x01);
 313                }
 314
 315                while (dram_reg_info->index != 0xffff) {
 316                        if (dram_reg_info->index == 0xff00) {/* delay fn */
 317                                for (i = 0; i < 15; i++)
 318                                        udelay(dram_reg_info->data);
 319                        } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) {
 320                                data = dram_reg_info->data;
 321                                if (ast->dram_type == AST_DRAM_1Gx16)
 322                                        data = 0x00000d89;
 323                                else if (ast->dram_type == AST_DRAM_1Gx32)
 324                                        data = 0x00000c8d;
 325
 326                                temp = ast_read32(ast, 0x12070);
 327                                temp &= 0xc;
 328                                temp <<= 2;
 329                                ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
 330                        } else
 331                                ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
 332                        dram_reg_info++;
 333                }
 334
 335                /* AST 2100/2150 DRAM calibration */
 336                data = ast_read32(ast, 0x10120);
 337                if (data == 0x5061) { /* 266Mhz */
 338                        data = ast_read32(ast, 0x10004);
 339                        if (data & 0x40)
 340                                cbrdlli_ast2150(ast, 16); /* 16 bits */
 341                        else
 342                                cbrdlli_ast2150(ast, 32); /* 32 bits */
 343                }
 344
 345                switch (ast->chip) {
 346                case AST2000:
 347                        temp = ast_read32(ast, 0x10140);
 348                        ast_write32(ast, 0x10140, temp | 0x40);
 349                        break;
 350                case AST1100:
 351                case AST2100:
 352                case AST2200:
 353                case AST2150:
 354                        temp = ast_read32(ast, 0x1200c);
 355                        ast_write32(ast, 0x1200c, temp & 0xfffffffd);
 356                        temp = ast_read32(ast, 0x12040);
 357                        ast_write32(ast, 0x12040, temp | 0x40);
 358                        break;
 359                default:
 360                        break;
 361                }
 362        }
 363
 364        /* wait ready */
 365        do {
 366                j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
 367        } while ((j & 0x40) == 0);
 368}
 369
 370void ast_post_gpu(struct drm_device *dev)
 371{
 372        u32 reg;
 373        struct ast_private *ast = dev->dev_private;
 374
 375        pci_read_config_dword(ast->dev->pdev, 0x04, &reg);
 376        reg |= 0x3;
 377        pci_write_config_dword(ast->dev->pdev, 0x04, reg);
 378
 379        ast_enable_vga(dev);
 380        ast_open_key(ast);
 381        ast_enable_mmio(dev);
 382        ast_set_def_ext_reg(dev);
 383
 384        if (ast->config_mode == ast_use_p2a) {
 385                if (ast->chip == AST2500)
 386                        ast_post_chip_2500(dev);
 387                else if (ast->chip == AST2300 || ast->chip == AST2400)
 388                        ast_post_chip_2300(dev);
 389                else
 390                        ast_init_dram_reg(dev);
 391
 392                ast_init_3rdtx(dev);
 393        } else {
 394                if (ast->tx_chip_type != AST_TX_NONE)
 395                        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);        /* Enable DVO */
 396        }
 397}
 398
 399/* AST 2300 DRAM settings */
 400#define AST_DDR3 0
 401#define AST_DDR2 1
 402
 403struct ast2300_dram_param {
 404        u32 dram_type;
 405        u32 dram_chipid;
 406        u32 dram_freq;
 407        u32 vram_size;
 408        u32 odt;
 409        u32 wodt;
 410        u32 rodt;
 411        u32 dram_config;
 412        u32 reg_PERIOD;
 413        u32 reg_MADJ;
 414        u32 reg_SADJ;
 415        u32 reg_MRS;
 416        u32 reg_EMRS;
 417        u32 reg_AC1;
 418        u32 reg_AC2;
 419        u32 reg_DQSIC;
 420        u32 reg_DRV;
 421        u32 reg_IOZ;
 422        u32 reg_DQIDLY;
 423        u32 reg_FREQ;
 424        u32 madj_max;
 425        u32 dll2_finetune_step;
 426};
 427
 428/*
 429 * DQSI DLL CBR Setting
 430 */
 431#define CBR_SIZE0            ((1  << 10) - 1)
 432#define CBR_SIZE1            ((4  << 10) - 1)
 433#define CBR_SIZE2            ((64 << 10) - 1)
 434#define CBR_PASSNUM          5
 435#define CBR_PASSNUM2         5
 436#define CBR_THRESHOLD        10
 437#define CBR_THRESHOLD2       10
 438#define TIMEOUT              5000000
 439#define CBR_PATNUM           8
 440
 441static const u32 pattern[8] = {
 442        0xFF00FF00,
 443        0xCC33CC33,
 444        0xAA55AA55,
 445        0x88778877,
 446        0x92CC4D6E,
 447        0x543D3CDE,
 448        0xF1E843C7,
 449        0x7C61D253
 450};
 451
 452static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
 453{
 454        u32 data, timeout;
 455
 456        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 457        ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
 458        timeout = 0;
 459        do {
 460                data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
 461                if (data & 0x2000)
 462                        return false;
 463                if (++timeout > TIMEOUT) {
 464                        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 465                        return false;
 466                }
 467        } while (!data);
 468        ast_moutdwm(ast, 0x1e6e0070, 0x0);
 469        return true;
 470}
 471
 472static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
 473{
 474        u32 data, timeout;
 475
 476        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 477        ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
 478        timeout = 0;
 479        do {
 480                data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
 481                if (++timeout > TIMEOUT) {
 482                        ast_moutdwm(ast, 0x1e6e0070, 0x0);
 483                        return 0xffffffff;
 484                }
 485        } while (!data);
 486        data = ast_mindwm(ast, 0x1e6e0078);
 487        data = (data | (data >> 16)) & 0xffff;
 488        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 489        return data;
 490}
 491
 492
 493static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
 494{
 495        return mmc_test(ast, datagen, 0xc1);
 496}
 497
 498static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
 499{
 500        return mmc_test2(ast, datagen, 0x41);
 501}
 502
 503static bool mmc_test_single(struct ast_private *ast, u32 datagen)
 504{
 505        return mmc_test(ast, datagen, 0xc5);
 506}
 507
 508static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
 509{
 510        return mmc_test2(ast, datagen, 0x05);
 511}
 512
 513static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
 514{
 515        return mmc_test(ast, datagen, 0x85);
 516}
 517
 518static int cbr_test(struct ast_private *ast)
 519{
 520        u32 data;
 521        int i;
 522        data = mmc_test_single2(ast, 0);
 523        if ((data & 0xff) && (data & 0xff00))
 524                return 0;
 525        for (i = 0; i < 8; i++) {
 526                data = mmc_test_burst2(ast, i);
 527                if ((data & 0xff) && (data & 0xff00))
 528                        return 0;
 529        }
 530        if (!data)
 531                return 3;
 532        else if (data & 0xff)
 533                return 2;
 534        return 1;
 535}
 536
 537static int cbr_scan(struct ast_private *ast)
 538{
 539        u32 data, data2, patcnt, loop;
 540
 541        data2 = 3;
 542        for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
 543                ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
 544                for (loop = 0; loop < CBR_PASSNUM2; loop++) {
 545                        if ((data = cbr_test(ast)) != 0) {
 546                                data2 &= data;
 547                                if (!data2)
 548                                        return 0;
 549                                break;
 550                        }
 551                }
 552                if (loop == CBR_PASSNUM2)
 553                        return 0;
 554        }
 555        return data2;
 556}
 557
 558static u32 cbr_test2(struct ast_private *ast)
 559{
 560        u32 data;
 561
 562        data = mmc_test_burst2(ast, 0);
 563        if (data == 0xffff)
 564                return 0;
 565        data |= mmc_test_single2(ast, 0);
 566        if (data == 0xffff)
 567                return 0;
 568
 569        return ~data & 0xffff;
 570}
 571
 572static u32 cbr_scan2(struct ast_private *ast)
 573{
 574        u32 data, data2, patcnt, loop;
 575
 576        data2 = 0xffff;
 577        for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
 578                ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
 579                for (loop = 0; loop < CBR_PASSNUM2; loop++) {
 580                        if ((data = cbr_test2(ast)) != 0) {
 581                                data2 &= data;
 582                                if (!data2)
 583                                        return 0;
 584                                break;
 585                        }
 586                }
 587                if (loop == CBR_PASSNUM2)
 588                        return 0;
 589        }
 590        return data2;
 591}
 592
 593static bool cbr_test3(struct ast_private *ast)
 594{
 595        if (!mmc_test_burst(ast, 0))
 596                return false;
 597        if (!mmc_test_single(ast, 0))
 598                return false;
 599        return true;
 600}
 601
 602static bool cbr_scan3(struct ast_private *ast)
 603{
 604        u32 patcnt, loop;
 605
 606        for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
 607                ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
 608                for (loop = 0; loop < 2; loop++) {
 609                        if (cbr_test3(ast))
 610                                break;
 611                }
 612                if (loop == 2)
 613                        return false;
 614        }
 615        return true;
 616}
 617
 618static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
 619{
 620        u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
 621        bool status = false;
 622FINETUNE_START:
 623        for (cnt = 0; cnt < 16; cnt++) {
 624                dllmin[cnt] = 0xff;
 625                dllmax[cnt] = 0x0;
 626        }
 627        passcnt = 0;
 628        for (dlli = 0; dlli < 76; dlli++) {
 629                ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
 630                ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
 631                data = cbr_scan2(ast);
 632                if (data != 0) {
 633                        mask = 0x00010001;
 634                        for (cnt = 0; cnt < 16; cnt++) {
 635                                if (data & mask) {
 636                                        if (dllmin[cnt] > dlli) {
 637                                                dllmin[cnt] = dlli;
 638                                        }
 639                                        if (dllmax[cnt] < dlli) {
 640                                                dllmax[cnt] = dlli;
 641                                        }
 642                                }
 643                                mask <<= 1;
 644                        }
 645                        passcnt++;
 646                } else if (passcnt >= CBR_THRESHOLD2) {
 647                        break;
 648                }
 649        }
 650        gold_sadj[0] = 0x0;
 651        passcnt = 0;
 652        for (cnt = 0; cnt < 16; cnt++) {
 653                if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
 654                        gold_sadj[0] += dllmin[cnt];
 655                        passcnt++;
 656                }
 657        }
 658        if (retry++ > 10)
 659                goto FINETUNE_DONE;
 660        if (passcnt != 16) {
 661                goto FINETUNE_START;
 662        }
 663        status = true;
 664FINETUNE_DONE:
 665        gold_sadj[0] = gold_sadj[0] >> 4;
 666        gold_sadj[1] = gold_sadj[0];
 667
 668        data = 0;
 669        for (cnt = 0; cnt < 8; cnt++) {
 670                data >>= 3;
 671                if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
 672                        dlli = dllmin[cnt];
 673                        if (gold_sadj[0] >= dlli) {
 674                                dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
 675                                if (dlli > 3) {
 676                                        dlli = 3;
 677                                }
 678                        } else {
 679                                dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
 680                                if (dlli > 4) {
 681                                        dlli = 4;
 682                                }
 683                                dlli = (8 - dlli) & 0x7;
 684                        }
 685                        data |= dlli << 21;
 686                }
 687        }
 688        ast_moutdwm(ast, 0x1E6E0080, data);
 689
 690        data = 0;
 691        for (cnt = 8; cnt < 16; cnt++) {
 692                data >>= 3;
 693                if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
 694                        dlli = dllmin[cnt];
 695                        if (gold_sadj[1] >= dlli) {
 696                                dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
 697                                if (dlli > 3) {
 698                                        dlli = 3;
 699                                } else {
 700                                        dlli = (dlli - 1) & 0x7;
 701                                }
 702                        } else {
 703                                dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
 704                                dlli += 1;
 705                                if (dlli > 4) {
 706                                        dlli = 4;
 707                                }
 708                                dlli = (8 - dlli) & 0x7;
 709                        }
 710                        data |= dlli << 21;
 711                }
 712        }
 713        ast_moutdwm(ast, 0x1E6E0084, data);
 714        return status;
 715} /* finetuneDQI_L */
 716
 717static void finetuneDQSI(struct ast_private *ast)
 718{
 719        u32 dlli, dqsip, dqidly;
 720        u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
 721        u32 g_dqidly, g_dqsip, g_margin, g_side;
 722        u16 pass[32][2][2];
 723        char tag[2][76];
 724
 725        /* Disable DQI CBR */
 726        reg_mcr0c  = ast_mindwm(ast, 0x1E6E000C);
 727        reg_mcr18  = ast_mindwm(ast, 0x1E6E0018);
 728        reg_mcr18 &= 0x0000ffff;
 729        ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
 730
 731        for (dlli = 0; dlli < 76; dlli++) {
 732                tag[0][dlli] = 0x0;
 733                tag[1][dlli] = 0x0;
 734        }
 735        for (dqidly = 0; dqidly < 32; dqidly++) {
 736                pass[dqidly][0][0] = 0xff;
 737                pass[dqidly][0][1] = 0x0;
 738                pass[dqidly][1][0] = 0xff;
 739                pass[dqidly][1][1] = 0x0;
 740        }
 741        for (dqidly = 0; dqidly < 32; dqidly++) {
 742                passcnt[0] = passcnt[1] = 0;
 743                for (dqsip = 0; dqsip < 2; dqsip++) {
 744                        ast_moutdwm(ast, 0x1E6E000C, 0);
 745                        ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
 746                        ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
 747                        for (dlli = 0; dlli < 76; dlli++) {
 748                                ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
 749                                ast_moutdwm(ast, 0x1E6E0070, 0);
 750                                ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
 751                                if (cbr_scan3(ast)) {
 752                                        if (dlli == 0)
 753                                                break;
 754                                        passcnt[dqsip]++;
 755                                        tag[dqsip][dlli] = 'P';
 756                                        if (dlli < pass[dqidly][dqsip][0])
 757                                                pass[dqidly][dqsip][0] = (u16) dlli;
 758                                        if (dlli > pass[dqidly][dqsip][1])
 759                                                pass[dqidly][dqsip][1] = (u16) dlli;
 760                                } else if (passcnt[dqsip] >= 5)
 761                                        break;
 762                                else {
 763                                        pass[dqidly][dqsip][0] = 0xff;
 764                                        pass[dqidly][dqsip][1] = 0x0;
 765                                }
 766                        }
 767                }
 768                if (passcnt[0] == 0 && passcnt[1] == 0)
 769                        dqidly++;
 770        }
 771        /* Search margin */
 772        g_dqidly = g_dqsip = g_margin = g_side = 0;
 773
 774        for (dqidly = 0; dqidly < 32; dqidly++) {
 775                for (dqsip = 0; dqsip < 2; dqsip++) {
 776                        if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
 777                                continue;
 778                        diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
 779                        if ((diff+2) < g_margin)
 780                                continue;
 781                        passcnt[0] = passcnt[1] = 0;
 782                        for (dlli = pass[dqidly][dqsip][0]; dlli > 0  && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
 783                        for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
 784                        if (passcnt[0] > passcnt[1])
 785                                passcnt[0] = passcnt[1];
 786                        passcnt[1] = 0;
 787                        if (passcnt[0] > g_side)
 788                                passcnt[1] = passcnt[0] - g_side;
 789                        if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
 790                                g_margin = diff;
 791                                g_dqidly = dqidly;
 792                                g_dqsip  = dqsip;
 793                                g_side   = passcnt[0];
 794                        } else if (passcnt[1] > 1 && g_side < 8) {
 795                                if (diff > g_margin)
 796                                        g_margin = diff;
 797                                g_dqidly = dqidly;
 798                                g_dqsip  = dqsip;
 799                                g_side   = passcnt[0];
 800                        }
 801                }
 802        }
 803        reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
 804        ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
 805
 806}
 807static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
 808{
 809        u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
 810        bool status = false;
 811
 812        finetuneDQSI(ast);
 813        if (finetuneDQI_L(ast, param) == false)
 814                return status;
 815
 816CBR_START2:
 817        dllmin[0] = dllmin[1] = 0xff;
 818        dllmax[0] = dllmax[1] = 0x0;
 819        passcnt = 0;
 820        for (dlli = 0; dlli < 76; dlli++) {
 821                ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
 822                ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
 823                data = cbr_scan(ast);
 824                if (data != 0) {
 825                        if (data & 0x1) {
 826                                if (dllmin[0] > dlli) {
 827                                        dllmin[0] = dlli;
 828                                }
 829                                if (dllmax[0] < dlli) {
 830                                        dllmax[0] = dlli;
 831                                }
 832                        }
 833                        if (data & 0x2) {
 834                                if (dllmin[1] > dlli) {
 835                                        dllmin[1] = dlli;
 836                                }
 837                                if (dllmax[1] < dlli) {
 838                                        dllmax[1] = dlli;
 839                                }
 840                        }
 841                        passcnt++;
 842                } else if (passcnt >= CBR_THRESHOLD) {
 843                        break;
 844                }
 845        }
 846        if (retry++ > 10)
 847                goto CBR_DONE2;
 848        if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
 849                goto CBR_START2;
 850        }
 851        if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
 852                goto CBR_START2;
 853        }
 854        status = true;
 855CBR_DONE2:
 856        dlli  = (dllmin[1] + dllmax[1]) >> 1;
 857        dlli <<= 8;
 858        dlli += (dllmin[0] + dllmax[0]) >> 1;
 859        ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
 860        return status;
 861} /* CBRDLL2 */
 862
 863static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
 864{
 865        u32 trap, trap_AC2, trap_MRS;
 866
 867        ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
 868
 869        /* Ger trap info */
 870        trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
 871        trap_AC2  = 0x00020000 + (trap << 16);
 872        trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
 873        trap_MRS  = 0x00000010 + (trap << 4);
 874        trap_MRS |= ((trap & 0x2) << 18);
 875
 876        param->reg_MADJ       = 0x00034C4C;
 877        param->reg_SADJ       = 0x00001800;
 878        param->reg_DRV        = 0x000000F0;
 879        param->reg_PERIOD     = param->dram_freq;
 880        param->rodt           = 0;
 881
 882        switch (param->dram_freq) {
 883        case 336:
 884                ast_moutdwm(ast, 0x1E6E2020, 0x0190);
 885                param->wodt          = 0;
 886                param->reg_AC1       = 0x22202725;
 887                param->reg_AC2       = 0xAA007613 | trap_AC2;
 888                param->reg_DQSIC     = 0x000000BA;
 889                param->reg_MRS       = 0x04001400 | trap_MRS;
 890                param->reg_EMRS      = 0x00000000;
 891                param->reg_IOZ       = 0x00000023;
 892                param->reg_DQIDLY    = 0x00000074;
 893                param->reg_FREQ      = 0x00004DC0;
 894                param->madj_max      = 96;
 895                param->dll2_finetune_step = 3;
 896                switch (param->dram_chipid) {
 897                default:
 898                case AST_DRAM_512Mx16:
 899                case AST_DRAM_1Gx16:
 900                        param->reg_AC2   = 0xAA007613 | trap_AC2;
 901                        break;
 902                case AST_DRAM_2Gx16:
 903                        param->reg_AC2   = 0xAA00761C | trap_AC2;
 904                        break;
 905                case AST_DRAM_4Gx16:
 906                        param->reg_AC2   = 0xAA007636 | trap_AC2;
 907                        break;
 908                }
 909                break;
 910        default:
 911        case 396:
 912                ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
 913                param->wodt          = 1;
 914                param->reg_AC1       = 0x33302825;
 915                param->reg_AC2       = 0xCC009617 | trap_AC2;
 916                param->reg_DQSIC     = 0x000000E2;
 917                param->reg_MRS       = 0x04001600 | trap_MRS;
 918                param->reg_EMRS      = 0x00000000;
 919                param->reg_IOZ       = 0x00000034;
 920                param->reg_DRV       = 0x000000FA;
 921                param->reg_DQIDLY    = 0x00000089;
 922                param->reg_FREQ      = 0x00005040;
 923                param->madj_max      = 96;
 924                param->dll2_finetune_step = 4;
 925
 926                switch (param->dram_chipid) {
 927                default:
 928                case AST_DRAM_512Mx16:
 929                case AST_DRAM_1Gx16:
 930                        param->reg_AC2   = 0xCC009617 | trap_AC2;
 931                        break;
 932                case AST_DRAM_2Gx16:
 933                        param->reg_AC2   = 0xCC009622 | trap_AC2;
 934                        break;
 935                case AST_DRAM_4Gx16:
 936                        param->reg_AC2   = 0xCC00963F | trap_AC2;
 937                        break;
 938                }
 939                break;
 940
 941        case 408:
 942                ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
 943                param->wodt          = 1;
 944                param->reg_AC1       = 0x33302825;
 945                param->reg_AC2       = 0xCC009617 | trap_AC2;
 946                param->reg_DQSIC     = 0x000000E2;
 947                param->reg_MRS       = 0x04001600 | trap_MRS;
 948                param->reg_EMRS      = 0x00000000;
 949                param->reg_IOZ       = 0x00000023;
 950                param->reg_DRV       = 0x000000FA;
 951                param->reg_DQIDLY    = 0x00000089;
 952                param->reg_FREQ      = 0x000050C0;
 953                param->madj_max      = 96;
 954                param->dll2_finetune_step = 4;
 955
 956                switch (param->dram_chipid) {
 957                default:
 958                case AST_DRAM_512Mx16:
 959                case AST_DRAM_1Gx16:
 960                        param->reg_AC2   = 0xCC009617 | trap_AC2;
 961                        break;
 962                case AST_DRAM_2Gx16:
 963                        param->reg_AC2   = 0xCC009622 | trap_AC2;
 964                        break;
 965                case AST_DRAM_4Gx16:
 966                        param->reg_AC2   = 0xCC00963F | trap_AC2;
 967                        break;
 968                }
 969
 970                break;
 971        case 456:
 972                ast_moutdwm(ast, 0x1E6E2020, 0x0230);
 973                param->wodt          = 0;
 974                param->reg_AC1       = 0x33302926;
 975                param->reg_AC2       = 0xCD44961A;
 976                param->reg_DQSIC     = 0x000000FC;
 977                param->reg_MRS       = 0x00081830;
 978                param->reg_EMRS      = 0x00000000;
 979                param->reg_IOZ       = 0x00000045;
 980                param->reg_DQIDLY    = 0x00000097;
 981                param->reg_FREQ      = 0x000052C0;
 982                param->madj_max      = 88;
 983                param->dll2_finetune_step = 4;
 984                break;
 985        case 504:
 986                ast_moutdwm(ast, 0x1E6E2020, 0x0270);
 987                param->wodt          = 1;
 988                param->reg_AC1       = 0x33302926;
 989                param->reg_AC2       = 0xDE44A61D;
 990                param->reg_DQSIC     = 0x00000117;
 991                param->reg_MRS       = 0x00081A30;
 992                param->reg_EMRS      = 0x00000000;
 993                param->reg_IOZ       = 0x070000BB;
 994                param->reg_DQIDLY    = 0x000000A0;
 995                param->reg_FREQ      = 0x000054C0;
 996                param->madj_max      = 79;
 997                param->dll2_finetune_step = 4;
 998                break;
 999        case 528:
1000                ast_moutdwm(ast, 0x1E6E2020, 0x0290);

1001                param->wodt          = 1;
1002                param->rodt          = 1;
1003                param->reg_AC1       = 0x33302926;
1004                param->reg_AC2       = 0xEF44B61E;
1005                param->reg_DQSIC     = 0x00000125;
1006                param->reg_MRS       = 0x00081A30;
1007                param->reg_EMRS      = 0x00000040;
1008                param->reg_DRV       = 0x000000F5;
1009                param->reg_IOZ       = 0x00000023;
1010                param->reg_DQIDLY    = 0x00000088;
1011                param->reg_FREQ      = 0x000055C0;
1012                param->madj_max      = 76;
1013                param->dll2_finetune_step = 3;
1014                break;
1015        case 576:
1016                ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1017                param->reg_MADJ      = 0x00136868;
1018                param->reg_SADJ      = 0x00004534;
1019                param->wodt          = 1;
1020                param->rodt          = 1;
1021                param->reg_AC1       = 0x33302A37;
1022                param->reg_AC2       = 0xEF56B61E;
1023                param->reg_DQSIC     = 0x0000013F;
1024                param->reg_MRS       = 0x00101A50;
1025                param->reg_EMRS      = 0x00000040;
1026                param->reg_DRV       = 0x000000FA;
1027                param->reg_IOZ       = 0x00000023;
1028                param->reg_DQIDLY    = 0x00000078;
1029                param->reg_FREQ      = 0x000057C0;
1030                param->madj_max      = 136;
1031                param->dll2_finetune_step = 3;
1032                break;
1033        case 600:
1034                ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1035                param->reg_MADJ      = 0x00136868;
1036                param->reg_SADJ      = 0x00004534;
1037                param->wodt          = 1;
1038                param->rodt          = 1;
1039                param->reg_AC1       = 0x32302A37;
1040                param->reg_AC2       = 0xDF56B61F;
1041                param->reg_DQSIC     = 0x0000014D;
1042                param->reg_MRS       = 0x00101A50;
1043                param->reg_EMRS      = 0x00000004;
1044                param->reg_DRV       = 0x000000F5;
1045                param->reg_IOZ       = 0x00000023;
1046                param->reg_DQIDLY    = 0x00000078;
1047                param->reg_FREQ      = 0x000058C0;
1048                param->madj_max      = 132;
1049                param->dll2_finetune_step = 3;
1050                break;
1051        case 624:
1052                ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1053                param->reg_MADJ      = 0x00136868;
1054                param->reg_SADJ      = 0x00004534;
1055                param->wodt          = 1;
1056                param->rodt          = 1;
1057                param->reg_AC1       = 0x32302A37;
1058                param->reg_AC2       = 0xEF56B621;
1059                param->reg_DQSIC     = 0x0000015A;
1060                param->reg_MRS       = 0x02101A50;
1061                param->reg_EMRS      = 0x00000004;
1062                param->reg_DRV       = 0x000000F5;
1063                param->reg_IOZ       = 0x00000034;
1064                param->reg_DQIDLY    = 0x00000078;
1065                param->reg_FREQ      = 0x000059C0;
1066                param->madj_max      = 128;
1067                param->dll2_finetune_step = 3;
1068                break;
1069        } /* switch freq */
1070
1071        switch (param->dram_chipid) {
1072        case AST_DRAM_512Mx16:
1073                param->dram_config = 0x130;
1074                break;
1075        default:
1076        case AST_DRAM_1Gx16:
1077                param->dram_config = 0x131;
1078                break;
1079        case AST_DRAM_2Gx16:
1080                param->dram_config = 0x132;
1081                break;
1082        case AST_DRAM_4Gx16:
1083                param->dram_config = 0x133;
1084                break;
1085        } /* switch size */
1086
1087        switch (param->vram_size) {
1088        default:
1089        case AST_VIDMEM_SIZE_8M:
1090                param->dram_config |= 0x00;
1091                break;
1092        case AST_VIDMEM_SIZE_16M:
1093                param->dram_config |= 0x04;
1094                break;
1095        case AST_VIDMEM_SIZE_32M:
1096                param->dram_config |= 0x08;
1097                break;
1098        case AST_VIDMEM_SIZE_64M:
1099                param->dram_config |= 0x0c;
1100                break;
1101        }
1102
1103}
1104
1105static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1106{
1107        u32 data, data2, retry = 0;
1108
1109ddr3_init_start:
1110        ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1111        ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1112        ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1113        ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1114        udelay(10);
1115        ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1116        ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1117        udelay(10);
1118        ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1119        udelay(10);
1120
1121        ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1122        ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1123        ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1124        ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1125        ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1126        ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1127        ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1128        ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1129        ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1130        ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1131        ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1132        ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1133        ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1134        ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1135        ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1136        ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1137        ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1138        ast_moutdwm(ast, 0x1E6E0054, 0);
1139        ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1140        ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1141        ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1142        ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1143        ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1144        ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1145        /* Wait MCLK2X lock to MCLK */
1146        do {
1147                data = ast_mindwm(ast, 0x1E6E001C);
1148        } while (!(data & 0x08000000));
1149        data = ast_mindwm(ast, 0x1E6E001C);
1150        data = (data >> 8) & 0xff;
1151        while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1152                data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1153                if ((data2 & 0xff) > param->madj_max) {
1154                        break;
1155                }
1156                ast_moutdwm(ast, 0x1E6E0064, data2);
1157                if (data2 & 0x00100000) {
1158                        data2 = ((data2 & 0xff) >> 3) + 3;
1159                } else {
1160                        data2 = ((data2 & 0xff) >> 2) + 5;
1161                }
1162                data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1163                data2 += data & 0xff;
1164                data = data | (data2 << 8);
1165                ast_moutdwm(ast, 0x1E6E0068, data);
1166                udelay(10);
1167                ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1168                udelay(10);
1169                data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1170                ast_moutdwm(ast, 0x1E6E0018, data);
1171                data = data | 0x200;
1172                ast_moutdwm(ast, 0x1E6E0018, data);
1173                do {
1174                        data = ast_mindwm(ast, 0x1E6E001C);
1175                } while (!(data & 0x08000000));
1176
1177                data = ast_mindwm(ast, 0x1E6E001C);
1178                data = (data >> 8) & 0xff;
1179        }
1180        ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1181        data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1182        ast_moutdwm(ast, 0x1E6E0018, data);
1183
1184        ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1185        ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1186        udelay(50);
1187        /* Mode Register Setting */
1188        ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1189        ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1190        ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1191        ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1192        ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1193        ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1194        ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1195        ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1196        ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1197
1198        ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1199        data = 0;
1200        if (param->wodt) {
1201                data = 0x300;
1202        }
1203        if (param->rodt) {
1204                data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1205        }
1206        ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1207
1208        /* Calibrate the DQSI delay */
1209        if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1210                goto ddr3_init_start;
1211
1212        ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1213        /* ECC Memory Initialization */
1214#ifdef ECC
1215        ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1216        ast_moutdwm(ast, 0x1E6E0070, 0x221);
1217        do {
1218                data = ast_mindwm(ast, 0x1E6E0070);
1219        } while (!(data & 0x00001000));
1220        ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1221        ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1222        ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1223#endif
1224
1225
1226}
1227
1228static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
1229{
1230        u32 trap, trap_AC2, trap_MRS;
1231
1232        ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1233
1234        /* Ger trap info */
1235        trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1236        trap_AC2  = (trap << 20) | (trap << 16);
1237        trap_AC2 += 0x00110000;
1238        trap_MRS  = 0x00000040 | (trap << 4);
1239
1240
1241        param->reg_MADJ       = 0x00034C4C;
1242        param->reg_SADJ       = 0x00001800;
1243        param->reg_DRV        = 0x000000F0;
1244        param->reg_PERIOD     = param->dram_freq;
1245        param->rodt           = 0;
1246
1247        switch (param->dram_freq) {
1248        case 264:
1249                ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1250                param->wodt          = 0;
1251                param->reg_AC1       = 0x11101513;
1252                param->reg_AC2       = 0x78117011;
1253                param->reg_DQSIC     = 0x00000092;
1254                param->reg_MRS       = 0x00000842;
1255                param->reg_EMRS      = 0x00000000;
1256                param->reg_DRV       = 0x000000F0;
1257                param->reg_IOZ       = 0x00000034;
1258                param->reg_DQIDLY    = 0x0000005A;
1259                param->reg_FREQ      = 0x00004AC0;
1260                param->madj_max      = 138;
1261                param->dll2_finetune_step = 3;
1262                break;
1263        case 336:
1264                ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1265                param->wodt          = 1;
1266                param->reg_AC1       = 0x22202613;
1267                param->reg_AC2       = 0xAA009016 | trap_AC2;
1268                param->reg_DQSIC     = 0x000000BA;
1269                param->reg_MRS       = 0x00000A02 | trap_MRS;
1270                param->reg_EMRS      = 0x00000040;
1271                param->reg_DRV       = 0x000000FA;
1272                param->reg_IOZ       = 0x00000034;
1273                param->reg_DQIDLY    = 0x00000074;
1274                param->reg_FREQ      = 0x00004DC0;
1275                param->madj_max      = 96;
1276                param->dll2_finetune_step = 3;
1277                switch (param->dram_chipid) {
1278                default:
1279                case AST_DRAM_512Mx16:
1280                        param->reg_AC2   = 0xAA009012 | trap_AC2;
1281                        break;
1282                case AST_DRAM_1Gx16:
1283                        param->reg_AC2   = 0xAA009016 | trap_AC2;
1284                        break;
1285                case AST_DRAM_2Gx16:
1286                        param->reg_AC2   = 0xAA009023 | trap_AC2;
1287                        break;
1288                case AST_DRAM_4Gx16:
1289                        param->reg_AC2   = 0xAA00903B | trap_AC2;
1290                        break;
1291                }
1292                break;
1293        default:
1294        case 396:
1295                ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1296                param->wodt          = 1;
1297                param->rodt          = 0;
1298                param->reg_AC1       = 0x33302714;
1299                param->reg_AC2       = 0xCC00B01B | trap_AC2;
1300                param->reg_DQSIC     = 0x000000E2;
1301                param->reg_MRS       = 0x00000C02 | trap_MRS;
1302                param->reg_EMRS      = 0x00000040;
1303                param->reg_DRV       = 0x000000FA;
1304                param->reg_IOZ       = 0x00000034;
1305                param->reg_DQIDLY    = 0x00000089;
1306                param->reg_FREQ      = 0x00005040;
1307                param->madj_max      = 96;
1308                param->dll2_finetune_step = 4;
1309
1310                switch (param->dram_chipid) {
1311                case AST_DRAM_512Mx16:
1312                        param->reg_AC2   = 0xCC00B016 | trap_AC2;
1313                        break;
1314                default:
1315                case AST_DRAM_1Gx16:
1316                        param->reg_AC2   = 0xCC00B01B | trap_AC2;
1317                        break;
1318                case AST_DRAM_2Gx16:
1319                        param->reg_AC2   = 0xCC00B02B | trap_AC2;
1320                        break;
1321                case AST_DRAM_4Gx16:
1322                        param->reg_AC2   = 0xCC00B03F | trap_AC2;
1323                        break;
1324                }
1325
1326                break;
1327
1328        case 408:
1329                ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1330                param->wodt          = 1;
1331                param->rodt          = 0;
1332                param->reg_AC1       = 0x33302714;
1333                param->reg_AC2       = 0xCC00B01B | trap_AC2;
1334                param->reg_DQSIC     = 0x000000E2;
1335                param->reg_MRS       = 0x00000C02 | trap_MRS;
1336                param->reg_EMRS      = 0x00000040;
1337                param->reg_DRV       = 0x000000FA;
1338                param->reg_IOZ       = 0x00000034;
1339                param->reg_DQIDLY    = 0x00000089;
1340                param->reg_FREQ      = 0x000050C0;
1341                param->madj_max      = 96;
1342                param->dll2_finetune_step = 4;
1343
1344                switch (param->dram_chipid) {
1345                case AST_DRAM_512Mx16:
1346                        param->reg_AC2   = 0xCC00B016 | trap_AC2;
1347                        break;
1348                default:
1349                case AST_DRAM_1Gx16:
1350                        param->reg_AC2   = 0xCC00B01B | trap_AC2;
1351                        break;
1352                case AST_DRAM_2Gx16:
1353                        param->reg_AC2   = 0xCC00B02B | trap_AC2;
1354                        break;
1355                case AST_DRAM_4Gx16:
1356                        param->reg_AC2   = 0xCC00B03F | trap_AC2;
1357                        break;
1358                }
1359
1360                break;
1361        case 456:
1362                ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1363                param->wodt          = 0;
1364                param->reg_AC1       = 0x33302815;
1365                param->reg_AC2       = 0xCD44B01E;
1366                param->reg_DQSIC     = 0x000000FC;
1367                param->reg_MRS       = 0x00000E72;
1368                param->reg_EMRS      = 0x00000000;
1369                param->reg_DRV       = 0x00000000;
1370                param->reg_IOZ       = 0x00000034;
1371                param->reg_DQIDLY    = 0x00000097;
1372                param->reg_FREQ      = 0x000052C0;
1373                param->madj_max      = 88;
1374                param->dll2_finetune_step = 3;
1375                break;
1376        case 504:
1377                ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1378                param->wodt          = 1;
1379                param->rodt          = 1;
1380                param->reg_AC1       = 0x33302815;
1381                param->reg_AC2       = 0xDE44C022;
1382                param->reg_DQSIC     = 0x00000117;
1383                param->reg_MRS       = 0x00000E72;
1384                param->reg_EMRS      = 0x00000040;
1385                param->reg_DRV       = 0x0000000A;
1386                param->reg_IOZ       = 0x00000045;
1387                param->reg_DQIDLY    = 0x000000A0;
1388                param->reg_FREQ      = 0x000054C0;
1389                param->madj_max      = 79;
1390                param->dll2_finetune_step = 3;
1391                break;
1392        case 528:
1393                ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1394                param->wodt          = 1;
1395                param->rodt          = 1;
1396                param->reg_AC1       = 0x33302815;
1397                param->reg_AC2       = 0xEF44D024;
1398                param->reg_DQSIC     = 0x00000125;
1399                param->reg_MRS       = 0x00000E72;
1400                param->reg_EMRS      = 0x00000004;
1401                param->reg_DRV       = 0x000000F9;
1402                param->reg_IOZ       = 0x00000045;
1403                param->reg_DQIDLY    = 0x000000A7;
1404                param->reg_FREQ      = 0x000055C0;
1405                param->madj_max      = 76;
1406                param->dll2_finetune_step = 3;
1407                break;
1408        case 552:
1409                ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1410                param->wodt          = 1;
1411                param->rodt          = 1;
1412                param->reg_AC1       = 0x43402915;
1413                param->reg_AC2       = 0xFF44E025;
1414                param->reg_DQSIC     = 0x00000132;
1415                param->reg_MRS       = 0x00000E72;
1416                param->reg_EMRS      = 0x00000040;
1417                param->reg_DRV       = 0x0000000A;
1418                param->reg_IOZ       = 0x00000045;
1419                param->reg_DQIDLY    = 0x000000AD;
1420                param->reg_FREQ      = 0x000056C0;
1421                param->madj_max      = 76;
1422                param->dll2_finetune_step = 3;
1423                break;
1424        case 576:
1425                ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1426                param->wodt          = 1;
1427                param->rodt          = 1;
1428                param->reg_AC1       = 0x43402915;
1429                param->reg_AC2       = 0xFF44E027;
1430                param->reg_DQSIC     = 0x0000013F;
1431                param->reg_MRS       = 0x00000E72;
1432                param->reg_EMRS      = 0x00000004;
1433                param->reg_DRV       = 0x000000F5;
1434                param->reg_IOZ       = 0x00000045;
1435                param->reg_DQIDLY    = 0x000000B3;
1436                param->reg_FREQ      = 0x000057C0;
1437                param->madj_max      = 76;
1438                param->dll2_finetune_step = 3;
1439                break;
1440        }
1441
1442        switch (param->dram_chipid) {
1443        case AST_DRAM_512Mx16:
1444                param->dram_config = 0x100;
1445                break;
1446        default:
1447        case AST_DRAM_1Gx16:
1448                param->dram_config = 0x121;
1449                break;
1450        case AST_DRAM_2Gx16:
1451                param->dram_config = 0x122;
1452                break;
1453        case AST_DRAM_4Gx16:
1454                param->dram_config = 0x123;
1455                break;
1456        } /* switch size */
1457
1458        switch (param->vram_size) {
1459        default:
1460        case AST_VIDMEM_SIZE_8M:
1461                param->dram_config |= 0x00;
1462                break;
1463        case AST_VIDMEM_SIZE_16M:
1464                param->dram_config |= 0x04;
1465                break;
1466        case AST_VIDMEM_SIZE_32M:
1467                param->dram_config |= 0x08;
1468                break;
1469        case AST_VIDMEM_SIZE_64M:
1470                param->dram_config |= 0x0c;
1471                break;
1472        }
1473}
1474
1475static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1476{
1477        u32 data, data2, retry = 0;
1478
1479ddr2_init_start:
1480        ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1481        ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1482        ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1483        ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1484        ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1485        udelay(10);
1486        ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1487        udelay(10);
1488
1489        ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1490        ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1491        ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1492        ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1493        ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1494        ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1495        ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1496        ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1497        ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1498        ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1499        ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1500        ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1501        ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1502        ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1503        ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1504        ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1505        ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1506        ast_moutdwm(ast, 0x1E6E0054, 0);
1507        ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1508        ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1509        ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1510        ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1511        ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1512        ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1513
1514        /* Wait MCLK2X lock to MCLK */
1515        do {
1516                data = ast_mindwm(ast, 0x1E6E001C);
1517        } while (!(data & 0x08000000));
1518        data = ast_mindwm(ast, 0x1E6E001C);
1519        data = (data >> 8) & 0xff;
1520        while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1521                data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1522                if ((data2 & 0xff) > param->madj_max) {
1523                        break;
1524                }
1525                ast_moutdwm(ast, 0x1E6E0064, data2);
1526                if (data2 & 0x00100000) {
1527                        data2 = ((data2 & 0xff) >> 3) + 3;
1528                } else {
1529                        data2 = ((data2 & 0xff) >> 2) + 5;
1530                }
1531                data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1532                data2 += data & 0xff;
1533                data = data | (data2 << 8);
1534                ast_moutdwm(ast, 0x1E6E0068, data);
1535                udelay(10);
1536                ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1537                udelay(10);
1538                data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1539                ast_moutdwm(ast, 0x1E6E0018, data);
1540                data = data | 0x200;
1541                ast_moutdwm(ast, 0x1E6E0018, data);
1542                do {
1543                        data = ast_mindwm(ast, 0x1E6E001C);
1544                } while (!(data & 0x08000000));
1545
1546                data = ast_mindwm(ast, 0x1E6E001C);
1547                data = (data >> 8) & 0xff;
1548        }
1549        ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1550        data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1551        ast_moutdwm(ast, 0x1E6E0018, data);
1552
1553        ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1554        ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1555        udelay(50);
1556        /* Mode Register Setting */
1557        ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1558        ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1559        ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1560        ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1561        ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1562        ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1563
1564        ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1565        ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1566        ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1567        ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1568        ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1569        ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1570        ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1571
1572        ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1573        data = 0;
1574        if (param->wodt) {
1575                data = 0x500;
1576        }
1577        if (param->rodt) {
1578                data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1579        }
1580        ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1581        ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1582
1583        /* Calibrate the DQSI delay */
1584        if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1585                goto ddr2_init_start;
1586
1587        /* ECC Memory Initialization */
1588#ifdef ECC
1589        ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1590        ast_moutdwm(ast, 0x1E6E0070, 0x221);
1591        do {
1592                data = ast_mindwm(ast, 0x1E6E0070);
1593        } while (!(data & 0x00001000));
1594        ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1595        ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1596        ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1597#endif
1598
1599}
1600
1601static void ast_post_chip_2300(struct drm_device *dev)
1602{
1603        struct ast_private *ast = dev->dev_private;
1604        struct ast2300_dram_param param;
1605        u32 temp;
1606        u8 reg;
1607
1608        reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1609        if ((reg & 0x80) == 0) {/* vga only */
1610                ast_write32(ast, 0xf004, 0x1e6e0000);
1611                ast_write32(ast, 0xf000, 0x1);
1612                ast_write32(ast, 0x12000, 0x1688a8a8);
1613                do {
1614                        ;
1615                } while (ast_read32(ast, 0x12000) != 0x1);
1616
1617                ast_write32(ast, 0x10000, 0xfc600309);
1618                do {
1619                        ;
1620                } while (ast_read32(ast, 0x10000) != 0x1);
1621
1622                /* Slow down CPU/AHB CLK in VGA only mode */
1623                temp = ast_read32(ast, 0x12008);
1624                temp |= 0x73;
1625                ast_write32(ast, 0x12008, temp);
1626
1627                param.dram_freq = 396;
1628                param.dram_type = AST_DDR3;
1629                temp = ast_mindwm(ast, 0x1e6e2070);
1630                if (temp & 0x01000000)
1631                        param.dram_type = AST_DDR2;
1632                switch (temp & 0x18000000) {
1633                case 0:
1634                        param.dram_chipid = AST_DRAM_512Mx16;
1635                        break;
1636                default:
1637                case 0x08000000:
1638                        param.dram_chipid = AST_DRAM_1Gx16;
1639                        break;
1640                case 0x10000000:
1641                        param.dram_chipid = AST_DRAM_2Gx16;
1642                        break;
1643                case 0x18000000:
1644                        param.dram_chipid = AST_DRAM_4Gx16;
1645                        break;
1646                }
1647                switch (temp & 0x0c) {
1648                default:
1649                case 0x00:
1650                        param.vram_size = AST_VIDMEM_SIZE_8M;
1651                        break;
1652
1653                case 0x04:
1654                        param.vram_size = AST_VIDMEM_SIZE_16M;
1655                        break;
1656
1657                case 0x08:
1658                        param.vram_size = AST_VIDMEM_SIZE_32M;
1659                        break;
1660
1661                case 0x0c:
1662                        param.vram_size = AST_VIDMEM_SIZE_64M;
1663                        break;
1664                }
1665
1666                if (param.dram_type == AST_DDR3) {
1667                        get_ddr3_info(ast, &param);
1668                        ddr3_init(ast, &param);
1669                } else {
1670                        get_ddr2_info(ast, &param);
1671                        ddr2_init(ast, &param);
1672                }
1673
1674                temp = ast_mindwm(ast, 0x1e6e2040);
1675                ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1676        }
1677
1678        /* wait ready */
1679        do {
1680                reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1681        } while ((reg & 0x40) == 0);
1682}
1683
1684static bool cbr_test_2500(struct ast_private *ast)
1685{
1686        ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1687        ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1688        if (!mmc_test_burst(ast, 0))
1689                return false;
1690        if (!mmc_test_single_2500(ast, 0))
1691                return false;
1692        return true;
1693}
1694
1695static bool ddr_test_2500(struct ast_private *ast)
1696{
1697        ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1698        ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1699        if (!mmc_test_burst(ast, 0))
1700                return false;
1701        if (!mmc_test_burst(ast, 1))
1702                return false;
1703        if (!mmc_test_burst(ast, 2))
1704                return false;
1705        if (!mmc_test_burst(ast, 3))
1706                return false;
1707        if (!mmc_test_single_2500(ast, 0))
1708                return false;
1709        return true;
1710}
1711
1712static void ddr_init_common_2500(struct ast_private *ast)
1713{
1714        ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1715        ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1716        ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1717        ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1718        ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1719        ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1720        ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1721        ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1722        ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1723        ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1724        ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1725        ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1726        ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1727        ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1728        ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1729        ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1730        ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1731        ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1732        ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1733}
1734
1735static void ddr_phy_init_2500(struct ast_private *ast)
1736{
1737        u32 data, pass, timecnt;
1738
1739        pass = 0;
1740        ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1741        while (!pass) {
1742                for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
1743                        data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1744                        if (!data)
1745                                break;
1746                }
1747                if (timecnt != TIMEOUT) {
1748                        data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1749                        if (!data)
1750                                pass = 1;
1751                }
1752                if (!pass) {
1753                        ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1754                        udelay(10); /* delay 10 us */
1755                        ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1756                }
1757        }
1758
1759        ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1760}
1761
1762/*
1763 * Check DRAM Size
1764 * 1Gb : 0x80000000 ~ 0x87FFFFFF
1765 * 2Gb : 0x80000000 ~ 0x8FFFFFFF
1766 * 4Gb : 0x80000000 ~ 0x9FFFFFFF
1767 * 8Gb : 0x80000000 ~ 0xBFFFFFFF
1768 */
1769static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
1770{
1771        u32 reg_04, reg_14;
1772
1773        reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1774        reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1775
1776        ast_moutdwm(ast, 0xA0100000, 0x41424344);
1777        ast_moutdwm(ast, 0x90100000, 0x35363738);
1778        ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1779        ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1780
1781        /* Check 8Gbit */
1782        if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1783                reg_04 |= 0x03;
1784                reg_14 |= (tRFC >> 24) & 0xFF;
1785                /* Check 4Gbit */
1786        } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1787                reg_04 |= 0x02;
1788                reg_14 |= (tRFC >> 16) & 0xFF;
1789                /* Check 2Gbit */
1790        } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1791                reg_04 |= 0x01;
1792                reg_14 |= (tRFC >> 8) & 0xFF;
1793        } else {
1794                reg_14 |= tRFC & 0xFF;
1795        }
1796        ast_moutdwm(ast, 0x1E6E0004, reg_04);
1797        ast_moutdwm(ast, 0x1E6E0014, reg_14);
1798}
1799
1800static void enable_cache_2500(struct ast_private *ast)
1801{
1802        u32 reg_04, data;
1803
1804        reg_04 = ast_mindwm(ast, 0x1E6E0004);
1805        ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1806
1807        do
1808                data = ast_mindwm(ast, 0x1E6E0004);
1809        while (!(data & 0x80000));
1810        ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1811}
1812
1813static void set_mpll_2500(struct ast_private *ast)
1814{
1815        u32 addr, data, param;
1816
1817        /* Reset MMC */
1818        ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1819        ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1820        for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
1821                ast_moutdwm(ast, addr, 0x0);
1822                addr += 4;
1823        }
1824        ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1825
1826        ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1827        data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1828        if (data) {
1829                /* CLKIN = 25MHz */
1830                param = 0x930023E0;
1831                ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1832        } else {
1833                /* CLKIN = 24MHz */
1834                param = 0x93002400;
1835        }
1836        ast_moutdwm(ast, 0x1E6E2020, param);
1837        udelay(100);
1838}
1839
1840static void reset_mmc_2500(struct ast_private *ast)
1841{
1842        ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1843        ast_moutdwm(ast, 0x1E785044, 0x00000001);
1844        ast_moutdwm(ast, 0x1E785048, 0x00004755);
1845        ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1846        mdelay(100);
1847        ast_moutdwm(ast, 0x1E785054, 0x00000077);
1848        ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1849}
1850
1851static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
1852{
1853
1854        ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1855        ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1856        ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1857        ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1858        ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);         /* MODEREG4/6 */
1859        ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);         /* MODEREG5 */
1860        ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1861        ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);         /* MODEREG1/3 */
1862
1863        /* DDR PHY Setting */
1864        ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1865        ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1866        ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1867        ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1868        ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1869        ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1870        ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1871        ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1872        ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1873        ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1874        ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1875        ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1876        ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1877        ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1878
1879        /* Controller Setting */
1880        ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1881
1882        /* Wait DDR PHY init done */
1883        ddr_phy_init_2500(ast);
1884
1885        ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1886        ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1887        ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1888
1889        check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1890        enable_cache_2500(ast);
1891        ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1892        ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1893}
1894
1895static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
1896{
1897        u32 data, data2, pass, retrycnt;
1898        u32 ddr_vref, phy_vref;
1899        u32 min_ddr_vref = 0, min_phy_vref = 0;
1900        u32 max_ddr_vref = 0, max_phy_vref = 0;
1901
1902        ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1903        ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1904        ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1905        ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1906        ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);         /* MODEREG4/6 */
1907        ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);         /* MODEREG5 */
1908        ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1909        ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);         /* MODEREG1/3 */
1910
1911        /* DDR PHY Setting */
1912        ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1913        ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1914        ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1915        ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1916        ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1917        ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1918        ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1919        ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1920        ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1921        ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1922        ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1923        ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1924        ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1925        ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1926        ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1927
1928        /* Controller Setting */
1929        ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1930
1931        /* Train PHY Vref first */
1932        pass = 0;
1933
1934        for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1935                max_phy_vref = 0x0;
1936                pass = 0;
1937                ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1938                for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
1939                        ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1940                        ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1941                        ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1942                        /* Fire DFI Init */
1943                        ddr_phy_init_2500(ast);
1944                        ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1945                        if (cbr_test_2500(ast)) {
1946                                pass++;
1947                                data = ast_mindwm(ast, 0x1E6E03D0);
1948                                data2 = data >> 8;
1949                                data  = data & 0xff;
1950                                if (data > data2)
1951                                        data = data2;
1952                                if (max_phy_vref < data) {
1953                                        max_phy_vref = data;
1954                                        min_phy_vref = phy_vref;
1955                                }
1956                        } else if (pass > 0)
1957                                break;
1958                }
1959        }
1960        ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1961
1962        /* Train DDR Vref next */
1963        pass = 0;
1964
1965        for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1966                min_ddr_vref = 0xFF;
1967                max_ddr_vref = 0x0;
1968                pass = 0;
1969                for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
1970                        ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1971                        ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1972                        ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1973                        /* Fire DFI Init */
1974                        ddr_phy_init_2500(ast);
1975                        ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1976                        if (cbr_test_2500(ast)) {
1977                                pass++;
1978                                if (min_ddr_vref > ddr_vref)
1979                                        min_ddr_vref = ddr_vref;
1980                                if (max_ddr_vref < ddr_vref)
1981                                        max_ddr_vref = ddr_vref;
1982                        } else if (pass != 0)
1983                                break;
1984                }
1985        }
1986
1987        ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1988        ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1989        ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
1990        ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1991
1992        /* Wait DDR PHY init done */
1993        ddr_phy_init_2500(ast);
1994
1995        ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1996        ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1997        ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1998
1999        check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
2000        enable_cache_2500(ast);

2001        ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
2002        ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
2003}
2004
2005static bool ast_dram_init_2500(struct ast_private *ast)
2006{
2007        u32 data;
2008        u32 max_tries = 5;
2009
2010        do {
2011                if (max_tries-- == 0)
2012                        return false;
2013                set_mpll_2500(ast);
2014                reset_mmc_2500(ast);
2015                ddr_init_common_2500(ast);
2016
2017                data = ast_mindwm(ast, 0x1E6E2070);
2018                if (data & 0x01000000)
2019                        ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
2020                else
2021                        ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
2022        } while (!ddr_test_2500(ast));
2023
2024        ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
2025
2026        /* Patch code */
2027        data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
2028        ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
2029
2030        return true;
2031}
2032
2033void ast_post_chip_2500(struct drm_device *dev)
2034{
2035        struct ast_private *ast = dev->dev_private;
2036        u32 temp;
2037        u8 reg;
2038
2039        reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2040        if ((reg & 0x80) == 0) {/* vga only */
2041                /* Clear bus lock condition */
2042                ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
2043                ast_moutdwm(ast, 0x1e600084, 0x00010000);
2044                ast_moutdwm(ast, 0x1e600088, 0x00000000);
2045                ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
2046                ast_write32(ast, 0xf004, 0x1e6e0000);
2047                ast_write32(ast, 0xf000, 0x1);
2048                ast_write32(ast, 0x12000, 0x1688a8a8);
2049                while (ast_read32(ast, 0x12000) != 0x1)
2050                        ;
2051
2052                ast_write32(ast, 0x10000, 0xfc600309);
2053                while (ast_read32(ast, 0x10000) != 0x1)
2054                        ;
2055
2056                /* Slow down CPU/AHB CLK in VGA only mode */
2057                temp = ast_read32(ast, 0x12008);
2058                temp |= 0x73;
2059                ast_write32(ast, 0x12008, temp);
2060
2061                /* Reset USB port to patch USB unknown device issue */
2062                ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
2063                temp  = ast_mindwm(ast, 0x1e6e2094);
2064                temp |= 0x00004000;
2065                ast_moutdwm(ast, 0x1e6e2094, temp);
2066                temp  = ast_mindwm(ast, 0x1e6e2070);
2067                if (temp & 0x00800000) {
2068                        ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
2069                        mdelay(100);
2070                        ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
2071                }
2072
2073                if (!ast_dram_init_2500(ast))
2074                        DRM_ERROR("DRAM init failed !\n");
2075
2076                temp = ast_mindwm(ast, 0x1e6e2040);
2077                ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2078        }
2079
2080        /* wait ready */
2081        do {
2082                reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2083        } while ((reg & 0x40) == 0);
2084}
2085