/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/debugfs.h>
#include <linux/highmem.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/bitmap.h>
#if defined(CONFIG_X86)
#include <asm/pat.h>
#endif
#include <linux/sched.h>
#include <linux/sched/mm.h>
#include <linux/sched/task.h>
#include <linux/delay.h>
#include <rdma/ib_user_verbs.h>
#include <rdma/ib_addr.h>
#include <rdma/ib_cache.h>
#include <linux/mlx5/port.h>
#include <linux/mlx5/vport.h>
#include <linux/mlx5/fs.h>
#include <linux/mlx5/eswitch.h>
#include <linux/list.h>
#include <rdma/ib_smi.h>
#include <rdma/ib_umem.h>
#include <linux/in.h>
#include <linux/etherdevice.h>
#include "mlx5_ib.h"
#include "ib_rep.h"
#include "cmd.h"
#include "srq.h"
#include <linux/mlx5/fs_helpers.h>
#include <linux/mlx5/accel.h>
#include <rdma/uverbs_std_types.h>
#include <rdma/mlx5_user_ioctl_verbs.h>
#include <rdma/mlx5_user_ioctl_cmds.h>

#define UVERBS_MODULE_NAME mlx5_ib
#include <rdma/uverbs_named_ioctl.h>

#define DRIVER_NAME "mlx5_ib"
#define DRIVER_VERSION "5.0-0"

MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
MODULE_LICENSE("Dual BSD/GPL");

static char mlx5_version[] =
        DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
        DRIVER_VERSION "\n";

struct mlx5_ib_event_work {
        struct work_struct      work;
        union {
                struct mlx5_ib_dev            *dev;
                struct mlx5_ib_multiport_info *mpi;
        };
        bool                    is_slave;
        unsigned int            event;
        void                    *param;
};

enum {
        MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
};

static struct workqueue_struct *mlx5_ib_event_wq;
static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
static LIST_HEAD(mlx5_ib_dev_list);
/*
 * This mutex should be held when accessing either of the above lists
 */
static DEFINE_MUTEX(mlx5_ib_multiport_mutex);

/* We can't use an array for xlt_emergency_page because dma_map_single
 * doesn't work on kernel modules memory
 */
static unsigned long xlt_emergency_page;
static struct mutex xlt_emergency_page_mutex;

struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
{
        struct mlx5_ib_dev *dev;

        mutex_lock(&mlx5_ib_multiport_mutex);
        dev = mpi->ibdev;
        mutex_unlock(&mlx5_ib_multiport_mutex);
        return dev;
}

static enum rdma_link_layer
mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
{
        switch (port_type_cap) {
        case MLX5_CAP_PORT_TYPE_IB:
                return IB_LINK_LAYER_INFINIBAND;
        case MLX5_CAP_PORT_TYPE_ETH:
                return IB_LINK_LAYER_ETHERNET;
        default:
                return IB_LINK_LAYER_UNSPECIFIED;
        }
}

static enum rdma_link_layer
mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
{
        struct mlx5_ib_dev *dev = to_mdev(device);
        int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);

        return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
}

static int get_port_state(struct ib_device *ibdev,
                          u8 port_num,
                          enum ib_port_state *state)
{
        struct ib_port_attr attr;
        int ret;

        memset(&attr, 0, sizeof(attr));
        ret = ibdev->ops.query_port(ibdev, port_num, &attr);
        if (!ret)
                *state = attr.state;
        return ret;
}

static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
                                           struct net_device *ndev,
                                           u8 *port_num)
{
        struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
        struct net_device *rep_ndev;
        struct mlx5_ib_port *port;
        int i;

        for (i = 0; i < dev->num_ports; i++) {
                port  = &dev->port[i];
                if (!port->rep)
                        continue;

                read_lock(&port->roce.netdev_lock);
                rep_ndev = mlx5_ib_get_rep_netdev(esw,
                                                  port->rep->vport);
                if (rep_ndev == ndev) {
                        read_unlock(&port->roce.netdev_lock);
                        *port_num = i + 1;
                        return &port->roce;
                }
                read_unlock(&port->roce.netdev_lock);
        }

        return NULL;
}

static int mlx5_netdev_event(struct notifier_block *this,
                             unsigned long event, void *ptr)
{
        struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
        struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
        u8 port_num = roce->native_port_num;
        struct mlx5_core_dev *mdev;
        struct mlx5_ib_dev *ibdev;

        ibdev = roce->dev;
        mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
        if (!mdev)
                return NOTIFY_DONE;

        switch (event) {
        case NETDEV_REGISTER:
                /* Should already be registered during the load */
                if (ibdev->is_rep)
                        break;
                write_lock(&roce->netdev_lock);
                if (ndev->dev.parent == mdev->device)
                        roce->netdev = ndev;
                write_unlock(&roce->netdev_lock);
                break;

        case NETDEV_UNREGISTER:
                /* In case of reps, ib device goes away before the netdevs */
                write_lock(&roce->netdev_lock);
                if (roce->netdev == ndev)
                        roce->netdev = NULL;
                write_unlock(&roce->netdev_lock);
                break;

        case NETDEV_CHANGE:
        case NETDEV_UP:
        case NETDEV_DOWN: {
                struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
                struct net_device *upper = NULL;

                if (lag_ndev) {
                        upper = netdev_master_upper_dev_get(lag_ndev);
                        dev_put(lag_ndev);
                }

                if (ibdev->is_rep)
                        roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
                if (!roce)
                        return NOTIFY_DONE;
                if ((upper == ndev || (!upper && ndev == roce->netdev))
                    && ibdev->ib_active) {
                        struct ib_event ibev = { };
                        enum ib_port_state port_state;

                        if (get_port_state(&ibdev->ib_dev, port_num,
                                           &port_state))
                                goto done;

                        if (roce->last_port_state == port_state)
                                goto done;

                        roce->last_port_state = port_state;
                        ibev.device = &ibdev->ib_dev;
                        if (port_state == IB_PORT_DOWN)
                                ibev.event = IB_EVENT_PORT_ERR;
                        else if (port_state == IB_PORT_ACTIVE)
                                ibev.event = IB_EVENT_PORT_ACTIVE;
                        else
                                goto done;

                        ibev.element.port_num = port_num;
                        ib_dispatch_event(&ibev);
                }
                break;
        }

        default:
                break;
        }
done:
        mlx5_ib_put_native_port_mdev(ibdev, port_num);
        return NOTIFY_DONE;
}

static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
                                             u8 port_num)
{
        struct mlx5_ib_dev *ibdev = to_mdev(device);
        struct net_device *ndev;
        struct mlx5_core_dev *mdev;

        mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
        if (!mdev)
                return NULL;

        ndev = mlx5_lag_get_roce_netdev(mdev);
        if (ndev)
                goto out;

        /* Ensure ndev does not disappear before we invoke dev_hold()
         */
        read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
        ndev = ibdev->port[port_num - 1].roce.netdev;
        if (ndev)
                dev_hold(ndev);
        read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);

out:
        mlx5_ib_put_native_port_mdev(ibdev, port_num);
        return ndev;
}

struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
                                                   u8 ib_port_num,
                                                   u8 *native_port_num)
{
        enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
                                                          ib_port_num);
        struct mlx5_core_dev *mdev = NULL;
        struct mlx5_ib_multiport_info *mpi;
        struct mlx5_ib_port *port;

        if (!mlx5_core_mp_enabled(ibdev->mdev) ||
            ll != IB_LINK_LAYER_ETHERNET) {
                if (native_port_num)
                        *native_port_num = ib_port_num;
                return ibdev->mdev;
        }

        if (native_port_num)
                *native_port_num = 1;

        port = &ibdev->port[ib_port_num - 1];
        if (!port)
                return NULL;

        spin_lock(&port->mp.mpi_lock);
        mpi = ibdev->port[ib_port_num - 1].mp.mpi;
        if (mpi && !mpi->unaffiliate) {
                mdev = mpi->mdev;
                /* If it's the master no need to refcount, it'll exist
                 * as long as the ib_dev exists.
                 */
                if (!mpi->is_master)
                        mpi->mdev_refcnt++;
        }
        spin_unlock(&port->mp.mpi_lock);

        return mdev;
}

void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
{
        enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
                                                          port_num);
        struct mlx5_ib_multiport_info *mpi;
        struct mlx5_ib_port *port;

        if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
                return;

        port = &ibdev->port[port_num - 1];

        spin_lock(&port->mp.mpi_lock);
        mpi = ibdev->port[port_num - 1].mp.mpi;
        if (mpi->is_master)
                goto out;

        mpi->mdev_refcnt--;
        if (mpi->unaffiliate)
                complete(&mpi->unref_comp);
out:
        spin_unlock(&port->mp.mpi_lock);
}

static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
                                           u8 *active_width)
{
        switch (eth_proto_oper) {
        case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
        case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
        case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
        case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
                *active_width = IB_WIDTH_1X;
                *active_speed = IB_SPEED_SDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
        case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
        case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
        case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
        case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
        case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
        case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
                *active_width = IB_WIDTH_1X;
                *active_speed = IB_SPEED_QDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
        case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
        case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
                *active_width = IB_WIDTH_1X;
                *active_speed = IB_SPEED_EDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
        case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
        case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
        case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
                *active_width = IB_WIDTH_4X;
                *active_speed = IB_SPEED_QDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
        case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
        case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
                *active_width = IB_WIDTH_1X;
                *active_speed = IB_SPEED_HDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
                *active_width = IB_WIDTH_4X;
                *active_speed = IB_SPEED_FDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
        case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
        case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
        case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
                *active_width = IB_WIDTH_4X;
                *active_speed = IB_SPEED_EDR;
                break;
        default:
                return -EINVAL;
        }

        return 0;
}

static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
                                        u8 *active_width)
{
        switch (eth_proto_oper) {
        case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
        case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
                *active_width = IB_WIDTH_1X;
                *active_speed = IB_SPEED_SDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
                *active_width = IB_WIDTH_1X;
                *active_speed = IB_SPEED_DDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
                *active_width = IB_WIDTH_1X;
                *active_speed = IB_SPEED_QDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
                *active_width = IB_WIDTH_4X;
                *active_speed = IB_SPEED_QDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
                *active_width = IB_WIDTH_1X;
                *active_speed = IB_SPEED_EDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
                *active_width = IB_WIDTH_2X;
                *active_speed = IB_SPEED_EDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
                *active_width = IB_WIDTH_1X;
                *active_speed = IB_SPEED_HDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
                *active_width = IB_WIDTH_4X;
                *active_speed = IB_SPEED_EDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
                *active_width = IB_WIDTH_2X;
                *active_speed = IB_SPEED_HDR;
                break;
        case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
                *active_width = IB_WIDTH_4X;
                *active_speed = IB_SPEED_HDR;
                break;
        default:
                return -EINVAL;
        }

        return 0;
}

static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
                                    u8 *active_width, bool ext)
{
        return ext ?
                translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
                                             active_width) :
                translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
                                                active_width);
}

static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
                                struct ib_port_attr *props)
{
        struct mlx5_ib_dev *dev = to_mdev(device);
        u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
        struct mlx5_core_dev *mdev;
        struct net_device *ndev, *upper;
        enum ib_mtu ndev_ib_mtu;
        bool put_mdev = true;
        u16 qkey_viol_cntr;
        u32 eth_prot_oper;
        u8 mdev_port_num;
        bool ext;
        int err;

        mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
        if (!mdev) {
                /* This means the port isn't affiliated yet. Get the
                 * info for the master port instead.
                 */
                put_mdev = false;
                mdev = dev->mdev;
                mdev_port_num = 1;
                port_num = 1;
        }

        /* Possible bad flows are checked before filling out props so in case
         * of an error it will still be zeroed out.
         * Use native port in case of reps
         */
        if (dev->is_rep)
                err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
                                           1);
        else
                err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
                                           mdev_port_num);
        if (err)
                goto out;
        ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
        eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);

        props->active_width     = IB_WIDTH_4X;
        props->active_speed     = IB_SPEED_QDR;

        translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
                                 &props->active_width, ext);

        props->port_cap_flags |= IB_PORT_CM_SUP;
        props->ip_gids = true;

        props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
                                                roce_address_table_size);
        props->max_mtu          = IB_MTU_4096;
        props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
        props->pkey_tbl_len     = 1;
        props->state            = IB_PORT_DOWN;
        props->phys_state       = IB_PORT_PHYS_STATE_DISABLED;

        mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
        props->qkey_viol_cntr = qkey_viol_cntr;

        /* If this is a stub query for an unaffiliated port stop here */
        if (!put_mdev)
                goto out;

        ndev = mlx5_ib_get_netdev(device, port_num);
        if (!ndev)
                goto out;

        if (dev->lag_active) {
                rcu_read_lock();
                upper = netdev_master_upper_dev_get_rcu(ndev);
                if (upper) {
                        dev_put(ndev);
                        ndev = upper;
                        dev_hold(ndev);
                }
                rcu_read_unlock();
        }

        if (netif_running(ndev) && netif_carrier_ok(ndev)) {
                props->state      = IB_PORT_ACTIVE;
                props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
        }

        ndev_ib_mtu = iboe_get_mtu(ndev->mtu);

        dev_put(ndev);

        props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
out:
        if (put_mdev)
                mlx5_ib_put_native_port_mdev(dev, port_num);
        return err;
}

static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
                         unsigned int index, const union ib_gid *gid,
                         const struct ib_gid_attr *attr)
{
        enum ib_gid_type gid_type = IB_GID_TYPE_IB;
        u16 vlan_id = 0xffff;
        u8 roce_version = 0;
        u8 roce_l3_type = 0;
        u8 mac[ETH_ALEN];
        int ret;

        if (gid) {
                gid_type = attr->gid_type;
                ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
                if (ret)
                        return ret;
        }

        switch (gid_type) {
        case IB_GID_TYPE_IB:
                roce_version = MLX5_ROCE_VERSION_1;
                break;
        case IB_GID_TYPE_ROCE_UDP_ENCAP:
                roce_version = MLX5_ROCE_VERSION_2;
                if (ipv6_addr_v4mapped((void *)gid))
                        roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
                else
                        roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
                break;

        default:
                mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
        }

        return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
                                      roce_l3_type, gid->raw, mac,
                                      vlan_id < VLAN_CFI_MASK, vlan_id,
                                      port_num);
}

static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
                           __always_unused void **context)
{
        return set_roce_addr(to_mdev(attr->device), attr->port_num,
                             attr->index, &attr->gid, attr);
}

static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
                           __always_unused void **context)
{
        return set_roce_addr(to_mdev(attr->device), attr->port_num,
                             attr->index, NULL, NULL);
}

__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
                               const struct ib_gid_attr *attr)
{
        if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
                return 0;

        return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
}

static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
{
        if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
                return !MLX5_CAP_GEN(dev->mdev, ib_virt);
        return 0;
}

enum {
        MLX5_VPORT_ACCESS_METHOD_MAD,
        MLX5_VPORT_ACCESS_METHOD_HCA,
        MLX5_VPORT_ACCESS_METHOD_NIC,
};

static int mlx5_get_vport_access_method(struct ib_device *ibdev)
{
        if (mlx5_use_mad_ifc(to_mdev(ibdev)))
                return MLX5_VPORT_ACCESS_METHOD_MAD;

        if (mlx5_ib_port_link_layer(ibdev, 1) ==
            IB_LINK_LAYER_ETHERNET)
                return MLX5_VPORT_ACCESS_METHOD_NIC;

        return MLX5_VPORT_ACCESS_METHOD_HCA;
}

static void get_atomic_caps(struct mlx5_ib_dev *dev,
                            u8 atomic_size_qp,
                            struct ib_device_attr *props)
{
        u8 tmp;
        u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
        u8 atomic_req_8B_endianness_mode =
                MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);

        /* Check if HW supports 8 bytes standard atomic operations and capable
         * of host endianness respond
         */
        tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
        if (((atomic_operations & tmp) == tmp) &&
            (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
            (atomic_req_8B_endianness_mode)) {
                props->atomic_cap = IB_ATOMIC_HCA;
        } else {
                props->atomic_cap = IB_ATOMIC_NONE;
        }
}

static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
                               struct ib_device_attr *props)
{
        u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);

        get_atomic_caps(dev, atomic_size_qp, props);
}

static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
                               struct ib_device_attr *props)
{
        u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);

        get_atomic_caps(dev, atomic_size_qp, props);
}

bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
{
        struct ib_device_attr props = {};

        get_atomic_caps_dc(dev, &props);
        return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
}
static int mlx5_query_system_image_guid(struct ib_device *ibdev,
                                        __be64 *sys_image_guid)
{
        struct mlx5_ib_dev *dev = to_mdev(ibdev);
        struct mlx5_core_dev *mdev = dev->mdev;
        u64 tmp;
        int err;

        switch (mlx5_get_vport_access_method(ibdev)) {
        case MLX5_VPORT_ACCESS_METHOD_MAD:
                return mlx5_query_mad_ifc_system_image_guid(ibdev,
                                                            sys_image_guid);

        case MLX5_VPORT_ACCESS_METHOD_HCA:
                err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
                break;

        case MLX5_VPORT_ACCESS_METHOD_NIC:
                err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
                break;

        default:
                return -EINVAL;
        }

        if (!err)
                *sys_image_guid = cpu_to_be64(tmp);

        return err;

}

static int mlx5_query_max_pkeys(struct ib_device *ibdev,
                                u16 *max_pkeys)
{
        struct mlx5_ib_dev *dev = to_mdev(ibdev);
        struct mlx5_core_dev *mdev = dev->mdev;

        switch (mlx5_get_vport_access_method(ibdev)) {
        case MLX5_VPORT_ACCESS_METHOD_MAD:
                return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);

        case MLX5_VPORT_ACCESS_METHOD_HCA:
        case MLX5_VPORT_ACCESS_METHOD_NIC:
                *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
                                                pkey_table_size));
                return 0;

        default:
                return -EINVAL;
        }
}

static int mlx5_query_vendor_id(struct ib_device *ibdev,
                                u32 *vendor_id)
{
        struct mlx5_ib_dev *dev = to_mdev(ibdev);

        switch (mlx5_get_vport_access_method(ibdev)) {
        case MLX5_VPORT_ACCESS_METHOD_MAD:
                return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);

        case MLX5_VPORT_ACCESS_METHOD_HCA:
        case MLX5_VPORT_ACCESS_METHOD_NIC:
                return mlx5_core_query_vendor_id(dev->mdev, vendor_id);

        default:
                return -EINVAL;
        }
}

static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
                                __be64 *node_guid)
{
        u64 tmp;
        int err;

        switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
        case MLX5_VPORT_ACCESS_METHOD_MAD:
                return mlx5_query_mad_ifc_node_guid(dev, node_guid);

        case MLX5_VPORT_ACCESS_METHOD_HCA:
                err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
                break;

        case MLX5_VPORT_ACCESS_METHOD_NIC:
                err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
                break;

        default:
                return -EINVAL;
        }

        if (!err)
                *node_guid = cpu_to_be64(tmp);

        return err;
}

struct mlx5_reg_node_desc {
        u8      desc[IB_DEVICE_NODE_DESC_MAX];
};

static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
{
        struct mlx5_reg_node_desc in;

        if (mlx5_use_mad_ifc(dev))
                return mlx5_query_mad_ifc_node_desc(dev, node_desc);

        memset(&in, 0, sizeof(in));

        return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
                                    sizeof(struct mlx5_reg_node_desc),
                                    MLX5_REG_NODE_DESC, 0, 0);
}

static int mlx5_ib_query_device(struct ib_device *ibdev,
                                struct ib_device_attr *props,
                                struct ib_udata *uhw)
{
        struct mlx5_ib_dev *dev = to_mdev(ibdev);
        struct mlx5_core_dev *mdev = dev->mdev;
        int err = -ENOMEM;
        int max_sq_desc;
        int max_rq_sg;
        int max_sq_sg;
        u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
        bool raw_support = !mlx5_core_mp_enabled(mdev);
        struct mlx5_ib_query_device_resp resp = {};
        size_t resp_len;
        u64 max_tso;

        resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
        if (uhw->outlen && uhw->outlen < resp_len)
                return -EINVAL;
        else
                resp.response_length = resp_len;

        if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
                return -EINVAL;

        memset(props, 0, sizeof(*props));
        err = mlx5_query_system_image_guid(ibdev,
                                           &props->sys_image_guid);
        if (err)
                return err;

        err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
        if (err)
                return err;

        err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
        if (err)
                return err;

        props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
                (fw_rev_min(dev->mdev) << 16) |
                fw_rev_sub(dev->mdev);
        props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
                IB_DEVICE_PORT_ACTIVE_EVENT             |
                IB_DEVICE_SYS_IMAGE_GUID                |
                IB_DEVICE_RC_RNR_NAK_GEN;

        if (MLX5_CAP_GEN(mdev, pkv))
                props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
        if (MLX5_CAP_GEN(mdev, qkv))
                props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
        if (MLX5_CAP_GEN(mdev, apm))
                props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
        if (MLX5_CAP_GEN(mdev, xrc))
                props->device_cap_flags |= IB_DEVICE_XRC;
        if (MLX5_CAP_GEN(mdev, imaicl)) {
                props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
                                           IB_DEVICE_MEM_WINDOW_TYPE_2B;
                props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
                /* We support 'Gappy' memory registration too */
                props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
        }
        props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
        if (MLX5_CAP_GEN(mdev, sho)) {
                props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
                /* At this stage no support for signature handover */
                props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
                                      IB_PROT_T10DIF_TYPE_2 |
                                      IB_PROT_T10DIF_TYPE_3;
                props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
                                       IB_GUARD_T10DIF_CSUM;
        }
        if (MLX5_CAP_GEN(mdev, block_lb_mc))
                props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;

        if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
                if (MLX5_CAP_ETH(mdev, csum_cap)) {
                        /* Legacy bit to support old userspace libraries */
                        props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
                        props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
                }

                if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
                        props->raw_packet_caps |=
                                IB_RAW_PACKET_CAP_CVLAN_STRIPPING;

                if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
                        max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
                        if (max_tso) {
                                resp.tso_caps.max_tso = 1 << max_tso;
                                resp.tso_caps.supported_qpts |=
                                        1 << IB_QPT_RAW_PACKET;
                                resp.response_length += sizeof(resp.tso_caps);
                        }
                }

                if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
                        resp.rss_caps.rx_hash_function =
                                                MLX5_RX_HASH_FUNC_TOEPLITZ;
                        resp.rss_caps.rx_hash_fields_mask =
                                                MLX5_RX_HASH_SRC_IPV4 |
                                                MLX5_RX_HASH_DST_IPV4 |
                                                MLX5_RX_HASH_SRC_IPV6 |
                                                MLX5_RX_HASH_DST_IPV6 |
                                                MLX5_RX_HASH_SRC_PORT_TCP |
                                                MLX5_RX_HASH_DST_PORT_TCP |
                                                MLX5_RX_HASH_SRC_PORT_UDP |
                                                MLX5_RX_HASH_DST_PORT_UDP |
                                                MLX5_RX_HASH_INNER;
                        if (mlx5_accel_ipsec_device_caps(dev->mdev) &
                            MLX5_ACCEL_IPSEC_CAP_DEVICE)
                                resp.rss_caps.rx_hash_fields_mask |=
                                        MLX5_RX_HASH_IPSEC_SPI;
                        resp.response_length += sizeof(resp.rss_caps);
                }
        } else {
                if (field_avail(typeof(resp), tso_caps, uhw->outlen))
                        resp.response_length += sizeof(resp.tso_caps);
                if (field_avail(typeof(resp), rss_caps, uhw->outlen))
                        resp.response_length += sizeof(resp.rss_caps);
        }

        if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
                props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
                props->device_cap_flags |= IB_DEVICE_UD_TSO;
        }

        if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
            MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
            raw_support)
                props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;

        if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
            MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
                props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;

        if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
            MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
            raw_support) {
                /* Legacy bit to support old userspace libraries */
                props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
                props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
        }

        if (MLX5_CAP_DEV_MEM(mdev, memic)) {
                props->max_dm_size =
                        MLX5_CAP_DEV_MEM(mdev, max_memic_size);
        }

        if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
                props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;

        if (MLX5_CAP_GEN(mdev, end_pad))
                props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;

        props->vendor_part_id      = mdev->pdev->device;
        props->hw_ver              = mdev->pdev->revision;

        props->max_mr_size         = ~0ull;
        props->page_size_cap       = ~(min_page_size - 1);
        props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
        props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
        max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
                     sizeof(struct mlx5_wqe_data_seg);
        max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
        max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
                     sizeof(struct mlx5_wqe_raddr_seg)) /
                sizeof(struct mlx5_wqe_data_seg);
        props->max_send_sge = max_sq_sg;
        props->max_recv_sge = max_rq_sg;
        props->max_sge_rd          = MLX5_MAX_SGE_RD;
        props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
        props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;

        props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
        props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
        props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
        props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
        props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
        props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
        props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
        props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
        props->max_srq_sge         = max_rq_sg - 1;
        props->max_fast_reg_page_list_len =
                1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
        props->max_pi_fast_reg_page_list_len =
                props->max_fast_reg_page_list_len / 2;
        get_atomic_caps_qp(dev, props);
        props->masked_atomic_cap   = IB_ATOMIC_NONE;
        props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
        props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
        props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
                                           props->max_mcast_grp;
        props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
        props->max_ah = INT_MAX;
        props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
        props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;

        if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
                if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
                        props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
                props->odp_caps = dev->odp_caps;
        }

        if (MLX5_CAP_GEN(mdev, cd))
                props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;

        if (!mlx5_core_is_pf(mdev))
                props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;

        if (mlx5_ib_port_link_layer(ibdev, 1) ==
            IB_LINK_LAYER_ETHERNET && raw_support) {
                props->rss_caps.max_rwq_indirection_tables =
                        1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
                props->rss_caps.max_rwq_indirection_table_size =
                        1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
                props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
                props->max_wq_type_rq =
                        1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
        }

        if (MLX5_CAP_GEN(mdev, tag_matching)) {
                props->tm_caps.max_num_tags =
                        (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
                props->tm_caps.max_ops =
                        1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
                props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
        }

        if (MLX5_CAP_GEN(mdev, tag_matching) &&
            MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
                props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
                props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
        }

        if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
                props->cq_caps.max_cq_moderation_count =
                                                MLX5_MAX_CQ_COUNT;
                props->cq_caps.max_cq_moderation_period =
                                                MLX5_MAX_CQ_PERIOD;
        }

        if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
                resp.response_length += sizeof(resp.cqe_comp_caps);

                if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
                        resp.cqe_comp_caps.max_num =
                                MLX5_CAP_GEN(dev->mdev,
                                             cqe_compression_max_num);

                        resp.cqe_comp_caps.supported_format =
                                MLX5_IB_CQE_RES_FORMAT_HASH |
                                MLX5_IB_CQE_RES_FORMAT_CSUM;

                        if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
                                resp.cqe_comp_caps.supported_format |=
                                        MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
                }
        }

        if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
            raw_support) {
                if (MLX5_CAP_QOS(mdev, packet_pacing) &&
                    MLX5_CAP_GEN(mdev, qos)) {
                        resp.packet_pacing_caps.qp_rate_limit_max =
                                MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
                        resp.packet_pacing_caps.qp_rate_limit_min =
                                MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
                        resp.packet_pacing_caps.supported_qpts |=
                                1 << IB_QPT_RAW_PACKET;
                        if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
                            MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
                                resp.packet_pacing_caps.cap_flags |=
                                        MLX5_IB_PP_SUPPORT_BURST;
                }
                resp.response_length += sizeof(resp.packet_pacing_caps);
        }

        if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
                        uhw->outlen)) {
                if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
                        resp.mlx5_ib_support_multi_pkt_send_wqes =
                                MLX5_IB_ALLOW_MPW;

                if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
                        resp.mlx5_ib_support_multi_pkt_send_wqes |=
                                MLX5_IB_SUPPORT_EMPW;

                resp.response_length +=
                        sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
        }

        if (field_avail(typeof(resp), flags, uhw->outlen)) {
                resp.response_length += sizeof(resp.flags);

                if (MLX5_CAP_GEN(mdev, cqe_compression_128))
                        resp.flags |=
                                MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;

                if (MLX5_CAP_GEN(mdev, cqe_128_always))
                        resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
                if (MLX5_CAP_GEN(mdev, qp_packet_based))
                        resp.flags |=
                                MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;

                resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
        }

        if (field_avail(typeof(resp), sw_parsing_caps,
                        uhw->outlen)) {
                resp.response_length += sizeof(resp.sw_parsing_caps);
                if (MLX5_CAP_ETH(mdev, swp)) {
                        resp.sw_parsing_caps.sw_parsing_offloads |=
                                MLX5_IB_SW_PARSING;

                        if (MLX5_CAP_ETH(mdev, swp_csum))
                                resp.sw_parsing_caps.sw_parsing_offloads |=
                                        MLX5_IB_SW_PARSING_CSUM;

                        if (MLX5_CAP_ETH(mdev, swp_lso))
                                resp.sw_parsing_caps.sw_parsing_offloads |=
                                        MLX5_IB_SW_PARSING_LSO;

                        if (resp.sw_parsing_caps.sw_parsing_offloads)
                                resp.sw_parsing_caps.supported_qpts =
                                        BIT(IB_QPT_RAW_PACKET);
                }
        }

        if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
            raw_support) {
                resp.response_length += sizeof(resp.striding_rq_caps);
                if (MLX5_CAP_GEN(mdev, striding_rq)) {
                        resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
                                MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
                        resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
                                MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
                        resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
                                MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
                        resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
                                MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
                        resp.striding_rq_caps.supported_qpts =
                                BIT(IB_QPT_RAW_PACKET);
                }
        }

        if (field_avail(typeof(resp), tunnel_offloads_caps,
                        uhw->outlen)) {
                resp.response_length += sizeof(resp.tunnel_offloads_caps);
                if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
                        resp.tunnel_offloads_caps |=
                                MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
                if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
                        resp.tunnel_offloads_caps |=
                                MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
                if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
                        resp.tunnel_offloads_caps |=
                                MLX5_IB_TUNNELED_OFFLOADS_GRE;
                if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
                    MLX5_FLEX_PROTO_CW_MPLS_GRE)
                        resp.tunnel_offloads_caps |=
                                MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
                if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
                    MLX5_FLEX_PROTO_CW_MPLS_UDP)
                        resp.tunnel_offloads_caps |=
                                MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
        }

        if (uhw->outlen) {
                err = ib_copy_to_udata(uhw, &resp, resp.response_length);

                if (err)
                        return err;
        }

        return 0;
}

enum mlx5_ib_width {
        MLX5_IB_WIDTH_1X        = 1 << 0,
        MLX5_IB_WIDTH_2X        = 1 << 1,
        MLX5_IB_WIDTH_4X        = 1 << 2,
        MLX5_IB_WIDTH_8X        = 1 << 3,
        MLX5_IB_WIDTH_12X       = 1 << 4
};

static void translate_active_width(struct ib_device *ibdev, u8 active_width,
                                  u8 *ib_width)
{
        struct mlx5_ib_dev *dev = to_mdev(ibdev);

        if (active_width & MLX5_IB_WIDTH_1X)
                *ib_width = IB_WIDTH_1X;
        else if (active_width & MLX5_IB_WIDTH_2X)
                *ib_width = IB_WIDTH_2X;
        else if (active_width & MLX5_IB_WIDTH_4X)
                *ib_width = IB_WIDTH_4X;
        else if (active_width & MLX5_IB_WIDTH_8X)
                *ib_width = IB_WIDTH_8X;
        else if (active_width & MLX5_IB_WIDTH_12X)
                *ib_width = IB_WIDTH_12X;
        else {
                mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
                            (int)active_width);
                *ib_width = IB_WIDTH_4X;
        }

        return;
}

static int mlx5_mtu_to_ib_mtu(int mtu)
{
        switch (mtu) {
        case 256: return 1;
        case 512: return 2;
        case 1024: return 3;
        case 2048: return 4;
        case 4096: return 5;
        default:
                pr_warn("invalid mtu\n");
                return -1;
        }
}

enum ib_max_vl_num {
        __IB_MAX_VL_0           = 1,
        __IB_MAX_VL_0_1         = 2,
        __IB_MAX_VL_0_3         = 3,
        __IB_MAX_VL_0_7         = 4,
        __IB_MAX_VL_0_14        = 5,
};

enum mlx5_vl_hw_cap {
        MLX5_VL_HW_0    = 1,
        MLX5_VL_HW_0_1  = 2,
        MLX5_VL_HW_0_2  = 3,
        MLX5_VL_HW_0_3  = 4,
        MLX5_VL_HW_0_4  = 5,
        MLX5_VL_HW_0_5  = 6,
        MLX5_VL_HW_0_6  = 7,
        MLX5_VL_HW_0_7  = 8,
        MLX5_VL_HW_0_14 = 15
};

static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
                                u8 *max_vl_num)
{
        switch (vl_hw_cap) {
        case MLX5_VL_HW_0:
                *max_vl_num = __IB_MAX_VL_0;
                break;
        case MLX5_VL_HW_0_1:
                *max_vl_num = __IB_MAX_VL_0_1;
                break;
        case MLX5_VL_HW_0_3:
                *max_vl_num = __IB_MAX_VL_0_3;
                break;
        case MLX5_VL_HW_0_7:
                *max_vl_num = __IB_MAX_VL_0_7;
                break;
        case MLX5_VL_HW_0_14:
                *max_vl_num = __IB_MAX_VL_0_14;
                break;

        default:
                return -EINVAL;
        }

        return 0;
}

static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
                               struct ib_port_attr *props)
{
        struct mlx5_ib_dev *dev = to_mdev(ibdev);
        struct mlx5_core_dev *mdev = dev->mdev;
        struct mlx5_hca_vport_context *rep;
        u16 max_mtu;
        u16 oper_mtu;
        int err;
        u8 ib_link_width_oper;
        u8 vl_hw_cap;

        rep = kzalloc(sizeof(*rep), GFP_KERNEL);
        if (!rep) {
                err = -ENOMEM;
                goto out;
        }

        /* props being zeroed by the caller, avoid zeroing it here */

        err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
        if (err)
                goto out;

        props->lid              = rep->lid;
        props->lmc              = rep->lmc;
        props->sm_lid           = rep->sm_lid;
        props->sm_sl            = rep->sm_sl;
        props->state            = rep->vport_state;
        props->phys_state       = rep->port_physical_state;
        props->port_cap_flags   = rep->cap_mask1;
        props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
        props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
        props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
        props->bad_pkey_cntr    = rep->pkey_violation_counter;
        props->qkey_viol_cntr   = rep->qkey_violation_counter;
        props->subnet_timeout   = rep->subnet_timeout;
        props->init_type_reply  = rep->init_type_reply;

        if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
                props->port_cap_flags2 = rep->cap_mask2;

        err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
        if (err)
                goto out;

        translate_active_width(ibdev, ib_link_width_oper, &props->active_width);

        err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
        if (err)
                goto out;

        mlx5_query_port_max_mtu(mdev, &max_mtu, port);

        props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);

        mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);

        props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);

        err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
        if (err)
                goto out;

        err = translate_max_vl_num(ibdev, vl_hw_cap,
                                   &props->max_vl_num);
out:
        kfree(rep);
        return err;
}

int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
                       struct ib_port_attr *props)
{
        unsigned int count;
        int ret;

        switch (mlx5_get_vport_access_method(ibdev)) {
        case MLX5_VPORT_ACCESS_METHOD_MAD:
                ret = mlx5_query_mad_ifc_port(ibdev, port, props);
                break;

        case MLX5_VPORT_ACCESS_METHOD_HCA:
                ret = mlx5_query_hca_port(ibdev, port, props);
                break;

        case MLX5_VPORT_ACCESS_METHOD_NIC:
                ret = mlx5_query_port_roce(ibdev, port, props);
                break;

        default:
                ret = -EINVAL;
        }

        if (!ret && props) {
                struct mlx5_ib_dev *dev = to_mdev(ibdev);
                struct mlx5_core_dev *mdev;
                bool put_mdev = true;

                mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
                if (!mdev) {
                        /* If the port isn't affiliated yet query the master.
                         * The master and slave will have the same values.
                         */
                        mdev = dev->mdev;
                        port = 1;
                        put_mdev = false;
                }
                count = mlx5_core_reserved_gids_count(mdev);
                if (put_mdev)
                        mlx5_ib_put_native_port_mdev(dev, port);
                props->gid_tbl_len -= count;
        }
        return ret;
}

static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
                                  struct ib_port_attr *props)
{
        int ret;

        /* Only link layer == ethernet is valid for representors
         * and we always use port 1
         */
        ret = mlx5_query_port_roce(ibdev, port, props);
        if (ret || !props)
                return ret;

        /* We don't support GIDS */
        props->gid_tbl_len = 0;

        return ret;
}

static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
                             union ib_gid *gid)
{
        struct mlx5_ib_dev *dev = to_mdev(ibdev);
        struct mlx5_core_dev *mdev = dev->mdev;

        switch (mlx5_get_vport_access_method(ibdev)) {
        case MLX5_VPORT_ACCESS_METHOD_MAD:
                return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);

        case MLX5_VPORT_ACCESS_METHOD_HCA:
                return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);

        default:
                return -EINVAL;
        }

}

static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
                                   u16 index, u16 *pkey)
{
        struct mlx5_ib_dev *dev = to_mdev(ibdev);
        struct mlx5_core_dev *mdev;
        bool put_mdev = true;
        u8 mdev_port_num;
        int err;

        mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
        if (!mdev) {
                /* The port isn't affiliated yet, get the PKey from the master
                 * port. For RoCE the PKey tables will be the same.
                 */
                put_mdev = false;
                mdev = dev->mdev;
                mdev_port_num = 1;
        }

        err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
                                        index, pkey);
        if (put_mdev)
                mlx5_ib_put_native_port_mdev(dev, port);

        return err;
}

static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
                              u16 *pkey)
{
        switch (mlx5_get_vport_access_method(ibdev)) {
        case MLX5_VPORT_ACCESS_METHOD_MAD:
                return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);

        case MLX5_VPORT_ACCESS_METHOD_HCA:
        case MLX5_VPORT_ACCESS_METHOD_NIC:
                return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
        default:
                return -EINVAL;
        }
}

static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
                                 struct ib_device_modify *props)
{
        struct mlx5_ib_dev *dev = to_mdev(ibdev);
        struct mlx5_reg_node_desc in;
        struct mlx5_reg_node_desc out;
        int err;

        if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
                return -EOPNOTSUPP;

        if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
                return 0;

        /*
         * If possible, pass node desc to FW, so it can generate
         * a 144 trap.  If cmd fails, just ignore.
         */
        memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
        err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
                                   sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
        if (err)
                return err;

        memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);

        return err;
}

static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
                                u32 value)
{
        struct mlx5_hca_vport_context ctx = {};
        struct mlx5_core_dev *mdev;
        u8 mdev_port_num;
        int err;

        mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
        if (!mdev)
                return -ENODEV;

        err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
        if (err)
                goto out;

        if (~ctx.cap_mask1_perm & mask) {
                mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
                             mask, ctx.cap_mask1_perm);
                err = -EINVAL;
                goto out;
        }

        ctx.cap_mask1 = value;
        ctx.cap_mask1_perm = mask;
        err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
                                                 0, &ctx);

out:
        mlx5_ib_put_native_port_mdev(dev, port_num);

        return err;
}

static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
                               struct ib_port_modify *props)
{
        struct mlx5_ib_dev *dev = to_mdev(ibdev);
        struct ib_port_attr attr;
        u32 tmp;
        int err;
        u32 change_mask;
        u32 value;
        bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
                      IB_LINK_LAYER_INFINIBAND);

        /* CM layer calls ib_modify_port() regardless of the link layer. For
         * Ethernet ports, qkey violation and Port capabilities are meaningless.
         */
        if (!is_ib)
                return 0;

        if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
                change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
                value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
                return set_port_caps_atomic(dev, port, change_mask, value);
        }

        mutex_lock(&dev->cap_mask_mutex);

        err = ib_query_port(ibdev, port, &attr);
        if (err)
                goto out;

        tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
                ~props->clr_port_cap_mask;

        err = mlx5_set_port_caps(dev->mdev, port, tmp);

out:
        mutex_unlock(&dev->cap_mask_mutex);
        return err;
}

static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
{
        mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
                    caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
}

static u16 calc_dynamic_bfregs(int uars_per_sys_page)
{
        /* Large page with non 4k uar support might limit the dynamic size */
        if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
                return MLX5_MIN_DYN_BFREGS;

        return MLX5_MAX_DYN_BFREGS;
}

static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
                             struct mlx5_ib_alloc_ucontext_req_v2 *req,
                             struct mlx5_bfreg_info *bfregi)
{
        int uars_per_sys_page;
        int bfregs_per_sys_page;
        int ref_bfregs = req->total_num_bfregs;

        if (req->total_num_bfregs == 0)
                return -EINVAL;

        BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
        BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);

        if (req->total_num_bfregs > MLX5_MAX_BFREGS)
                return -ENOMEM;

        uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
        bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
        /* This holds the required static allocation asked by the user */
        req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
        if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
                return -EINVAL;

        bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
        bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
        bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
        bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;

        mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
                    MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
                    lib_uar_4k ? "yes" : "no", ref_bfregs,
                    req->total_num_bfregs, bfregi->total_num_bfregs,
                    bfregi->num_sys_pages);

        return 0;
}

static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
{
        struct mlx5_bfreg_info *bfregi;
        int err;
        int i;

        bfregi = &context->bfregi;
        for (i = 0; i < bfregi->num_static_sys_pages; i++) {
                err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
                if (err)
                        goto error;

                mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
        }

        for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
                bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;

        return 0;

error:
        for (--i; i >= 0; i--)
                if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
                        mlx5_ib_warn(dev, "failed to free uar %d\n", i);

        return err;
}

static void deallocate_uars(struct mlx5_ib_dev *dev,
                            struct mlx5_ib_ucontext *context)
{
        struct mlx5_bfreg_info *bfregi;
        int i;

        bfregi = &context->bfregi;
        for (i = 0; i < bfregi->num_sys_pages; i++)
                if (i < bfregi->num_static_sys_pages ||
                    bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
                        mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
}

int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
{
        int err = 0;

        mutex_lock(&dev->lb.mutex);
        if (td)
                dev->lb.user_td++;
        if (qp)
                dev->lb.qps++;

        if (dev->lb.user_td == 2 ||
            dev->lb.qps == 1) {
                if (!dev->lb.enabled) {
                        err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
                        dev->lb.enabled = true;
                }
        }

        mutex_unlock(&dev->lb.mutex);

        return err;
}

void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
{
        mutex_lock(&dev->lb.mutex);
        if (td)
                dev->lb.user_td--;
        if (qp)
                dev->lb.qps--;

        if (dev->lb.user_td == 1 &&
            dev->lb.qps == 0) {
                if (dev->lb.enabled) {
                        mlx5_nic_vport_update_local_lb(dev->mdev, false);
                        dev->lb.enabled = false;
                }
        }

        mutex_unlock(&dev->lb.mutex);
}

static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
                                          u16 uid)
{
        int err;

        if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
                return 0;

        err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
        if (err)
                return err;

        if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
            (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
             !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
                return err;

        return mlx5_ib_enable_lb(dev, true, false);
}

static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
                                             u16 uid)
{
        if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
                return;

        mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);

        if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
            (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
             !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
                return;

        mlx5_ib_disable_lb(dev, true, false);
}

static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
                                  struct ib_udata *udata)
{
        struct ib_device *ibdev = uctx->device;
        struct mlx5_ib_dev *dev = to_mdev(ibdev);
        struct mlx5_ib_alloc_ucontext_req_v2 req = {};
        struct mlx5_ib_alloc_ucontext_resp resp = {};
        struct mlx5_core_dev *mdev = dev->mdev;
        struct mlx5_ib_ucontext *context = to_mucontext(uctx);
        struct mlx5_bfreg_info *bfregi;
        int ver;
        int err;
        size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
                                     max_cqe_version);
        u32 dump_fill_mkey;
        bool lib_uar_4k;

        if (!dev->ib_active)
                return -EAGAIN;

        if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
                ver = 0;
        else if (udata->inlen >= min_req_v2)
                ver = 2;
        else
                return -EINVAL;

        err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
        if (err)
                return err;

        if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
                return -EOPNOTSUPP;

        if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
                return -EOPNOTSUPP;

        req.total_num_bfregs = ALIGN(req.total_num_bfregs,
                                    MLX5_NON_FP_BFREGS_PER_UAR);
        if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
                return -EINVAL;

        resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
        if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
                resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
        resp.cache_line_size = cache_line_size();
        resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
        resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
        resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
        resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
        resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
        resp.cqe_version = min_t(__u8,
                                 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
                                 req.max_cqe_version);
        resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
                                MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
        resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
                                        MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
        resp.response_length = min(offsetof(typeof(resp), response_length) +
                                   sizeof(resp.response_length), udata->outlen);

        if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
                if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
                        resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
                if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
                        resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
                if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
                        resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
                if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
                        resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
                /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
        }

        lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
        bfregi = &context->bfregi;

        /* updates req->total_num_bfregs */
        err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
        if (err)
                goto out_ctx;

        mutex_init(&bfregi->lock);
        bfregi->lib_uar_4k = lib_uar_4k;
        bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
                                GFP_KERNEL);
        if (!bfregi->count) {
                err = -ENOMEM;
                goto out_ctx;
        }

        bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
                                    sizeof(*bfregi->sys_pages),
                                    GFP_KERNEL);
        if (!bfregi->sys_pages) {
                err = -ENOMEM;
                goto out_count;
        }

        err = allocate_uars(dev, context);
        if (err)
                goto out_sys_pages;

        if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
                err = mlx5_ib_devx_create(dev, true);
                if (err < 0)
                        goto out_uars;
                context->devx_uid = err;
        }

        err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
                                             context->devx_uid);
        if (err)
                goto out_devx;

        if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
                err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
                if (err)
                        goto out_mdev;
        }

        INIT_LIST_HEAD(&context->db_page_list);
        mutex_init(&context->db_page_mutex);

        resp.tot_bfregs = req.total_num_bfregs;
        resp.num_ports = dev->num_ports;

        if (field_avail(typeof(resp), cqe_version, udata->outlen))
                resp.response_length += sizeof(resp.cqe_version);

        if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
                resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
                                      MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
                resp.response_length += sizeof(resp.cmds_supp_uhw);
        }

        if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
                if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
                        mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
                        resp.eth_min_inline++;
                }
                resp.response_length += sizeof(resp.eth_min_inline);
        }

        if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
                if (mdev->clock_info)
                        resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
                resp.response_length += sizeof(resp.clock_info_versions);
        }

        /*
         * We don't want to expose information from the PCI bar that is located
         * after 4096 bytes, so if the arch only supports larger pages, let's
         * pretend we don't support reading the HCA's core clock. This is also
         * forced by mmap function.
         */
        if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
                if (PAGE_SIZE <= 4096) {
                        resp.comp_mask |=
                                MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
                        resp.hca_core_clock_offset =
                                offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
                }
                resp.response_length += sizeof(resp.hca_core_clock_offset);
        }

        if (field_avail(typeof(resp), log_uar_size, udata->outlen))
                resp.response_length += sizeof(resp.log_uar_size);

        if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
                resp.response_length += sizeof(resp.num_uars_per_page);

        if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
                resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
                resp.response_length += sizeof(resp.num_dyn_bfregs);
        }

        if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
                if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
                        resp.dump_fill_mkey = dump_fill_mkey;
                        resp.comp_mask |=
                                MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
                }
                resp.response_length += sizeof(resp.dump_fill_mkey);
        }

        err = ib_copy_to_udata(udata, &resp, resp.response_length);
        if (err)
                goto out_mdev;

        bfregi->ver = ver;
        bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
        context->cqe_version = resp.cqe_version;
        context->lib_caps = req.lib_caps;
        print_lib_caps(dev, context->lib_caps);

        if (dev->lag_active) {
                u8 port = mlx5_core_native_port_num(dev->mdev) - 1;

                atomic_set(&context->tx_port_affinity,
                           atomic_add_return(
                                   1, &dev->port[port].roce.tx_port_affinity));
        }

        return 0;

out_mdev:
        mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
out_devx:
        if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
                mlx5_ib_devx_destroy(dev, context->devx_uid);

out_uars:
        deallocate_uars(dev, context);

out_sys_pages:
        kfree(bfregi->sys_pages);

out_count:
        kfree(bfregi->count);

out_ctx:
        return err;
}

static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
{
        struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
        struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
        struct mlx5_bfreg_info *bfregi;

        bfregi = &context->bfregi;
        mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);

        if (context->devx_uid)
                mlx5_ib_devx_destroy(dev, context->devx_uid);

        deallocate_uars(dev, context);
        kfree(bfregi->sys_pages);
        kfree(bfregi->count);
}

static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
                                 int uar_idx)
{
        int fw_uars_per_page;

        fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;

        return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
}

static int get_command(unsigned long offset)
{
        return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
}

static int get_arg(unsigned long offset)
{
        return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
}

static int get_index(unsigned long offset)
{
        return get_arg(offset);
}

/* Index resides in an extra byte to enable larger values than 255 */
static int get_extended_index(unsigned long offset)
{
        return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
}


static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
{
}

static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
{
        switch (cmd) {
        case MLX5_IB_MMAP_WC_PAGE:
                return "WC";
        case MLX5_IB_MMAP_REGULAR_PAGE:
                return "best effort WC";
        case MLX5_IB_MMAP_NC_PAGE:
                return "NC";
        case MLX5_IB_MMAP_DEVICE_MEM:
                return "Device Memory";
        default:
                return NULL;
        }
}

static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
                                        struct vm_area_struct *vma,
                                        struct mlx5_ib_ucontext *context)
{
        if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
            !(vma->vm_flags & VM_SHARED))
                return -EINVAL;

        if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
                return -EOPNOTSUPP;

        if (vma->vm_flags & (VM_WRITE | VM_EXEC))
                return -EPERM;
        vma->vm_flags &= ~VM_MAYWRITE;

        if (!dev->mdev->clock_info)
                return -EOPNOTSUPP;

        return vm_insert_page(vma, vma->vm_start,
                              virt_to_page(dev->mdev->clock_info));
}

static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
                    struct vm_area_struct *vma,
                    struct mlx5_ib_ucontext *context)
{
        struct mlx5_bfreg_info *bfregi = &context->bfregi;
        int err;
        unsigned long idx;
        phys_addr_t pfn;
        pgprot_t prot;
        u32 bfreg_dyn_idx = 0;
        u32 uar_index;
        int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
        int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
                                bfregi->num_static_sys_pages;

        if (vma->vm_end - vma->vm_start != PAGE_SIZE)
                return -EINVAL;

        if (dyn_uar)
                idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
        else
                idx = get_index(vma->vm_pgoff);

        if (idx >= max_valid_idx) {
                mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
                             idx, max_valid_idx);
                return -EINVAL;
        }

        switch (cmd) {
        case MLX5_IB_MMAP_WC_PAGE:
        case MLX5_IB_MMAP_ALLOC_WC:
/* Some architectures don't support WC memory */
#if defined(CONFIG_X86)
                if (!pat_enabled())
                        return -EPERM;
#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
                        return -EPERM;
#endif
        /* fall through */
        case MLX5_IB_MMAP_REGULAR_PAGE:
                /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
                prot = pgprot_writecombine(vma->vm_page_prot);
                break;
        case MLX5_IB_MMAP_NC_PAGE:
                prot = pgprot_noncached(vma->vm_page_prot);
                break;
        default:
                return -EINVAL;
        }

        if (dyn_uar) {
                int uars_per_page;

                uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
                bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
                if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
                        mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
                                     bfreg_dyn_idx, bfregi->total_num_bfregs);
                        return -EINVAL;
                }

                mutex_lock(&bfregi->lock);
                /* Fail if uar already allocated, first bfreg index of each
                 * page holds its count.
                 */
                if (bfregi->count[bfreg_dyn_idx]) {
                        mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
                        mutex_unlock(&bfregi->lock);
                        return -EINVAL;
                }

                bfregi->count[bfreg_dyn_idx]++;
                mutex_unlock(&bfregi->lock);

                err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
                if (err) {
                        mlx5_ib_warn(dev, "UAR alloc failed\n");
                        goto free_bfreg;
                }
        } else {
                uar_index = bfregi->sys_pages[idx];
        }

        pfn = uar_index2pfn(dev, uar_index);
        mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);

        err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
                                prot);
        if (err) {
                mlx5_ib_err(dev,
                            "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
                            err, mmap_cmd2str(cmd));
                goto err;
        }

        if (dyn_uar)
                bfregi->sys_pages[idx] = uar_index;
        return 0;

err:
        if (!dyn_uar)
                return err;

        mlx5_cmd_free_uar(dev->mdev, idx);

free_bfreg:
        mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);

        return err;
}

static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
{
        struct mlx5_ib_ucontext *mctx = to_mucontext(context);
        struct mlx5_ib_dev *dev = to_mdev(context->device);
        u16 page_idx = get_extended_index(vma->vm_pgoff);
        size_t map_size = vma->vm_end - vma->vm_start;
        u32 npages = map_size >> PAGE_SHIFT;
        phys_addr_t pfn;

        if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
            page_idx + npages)
                return -EINVAL;

        pfn = ((dev->mdev->bar_addr +
              MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
              PAGE_SHIFT) +
              page_idx;
        return rdma_user_mmap_io(context, vma, pfn, map_size,
                                 pgprot_writecombine(vma->vm_page_prot));
}

static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
{
        struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
        struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
        unsigned long command;
        phys_addr_t pfn;

        command = get_command(vma->vm_pgoff);
        switch (command) {
        case MLX5_IB_MMAP_WC_PAGE:
        case MLX5_IB_MMAP_NC_PAGE:
        case MLX5_IB_MMAP_REGULAR_PAGE:
        case MLX5_IB_MMAP_ALLOC_WC:
                return uar_mmap(dev, command, vma, context);

        case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
                return -ENOSYS;

        case MLX5_IB_MMAP_CORE_CLOCK:
                if (vma->vm_end - vma->vm_start != PAGE_SIZE)
                        return -EINVAL;

                if (vma->vm_flags & VM_WRITE)
                        return -EPERM;
                vma->vm_flags &= ~VM_MAYWRITE;

                /* Don't expose to user-space information it shouldn't have */
                if (PAGE_SIZE > 4096)
                        return -EOPNOTSUPP;

                pfn = (dev->mdev->iseg_base +
                       offsetof(struct mlx5_init_seg, internal_timer_h)) >>
                        PAGE_SHIFT;
                return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
                                         PAGE_SIZE,
                                         pgprot_noncached(vma->vm_page_prot));
        case MLX5_IB_MMAP_CLOCK_INFO:
                return mlx5_ib_mmap_clock_info_page(dev, vma, context);

        case MLX5_IB_MMAP_DEVICE_MEM:
                return dm_mmap(ibcontext, vma);

        default:
                return -EINVAL;
        }

        return 0;
}

static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
                                        u32 type)
{
        switch (type) {
        case MLX5_IB_UAPI_DM_TYPE_MEMIC:
                if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
                        return -EOPNOTSUPP;
                break;
        case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
        case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
                if (!capable(CAP_SYS_RAWIO) ||
                    !capable(CAP_NET_RAW))
                        return -EPERM;

                if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
                      MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
                        return -EOPNOTSUPP;
                break;
        }

        return 0;
}

static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
                                 struct mlx5_ib_dm *dm,
                                 struct ib_dm_alloc_attr *attr,
                                 struct uverbs_attr_bundle *attrs)
{
        struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
        u64 start_offset;
        u32 page_idx;
        int err;

        dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);

        err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
                                   dm->size, attr->alignment);
        if (err)
                return err;

        page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
                    MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
                    PAGE_SHIFT;

        err = uverbs_copy_to(attrs,
                             MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
                             &page_idx, sizeof(page_idx));
        if (err)
                goto err_dealloc;

        start_offset = dm->dev_addr & ~PAGE_MASK;
        err = uverbs_copy_to(attrs,
                             MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
                             &start_offset, sizeof(start_offset));
        if (err)
                goto err_dealloc;

        bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
                   DIV_ROUND_UP(dm->size, PAGE_SIZE));

        return 0;

err_dealloc:
        mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);

        return err;
}

static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
                                  struct mlx5_ib_dm *dm,
                                  struct ib_dm_alloc_attr *attr,
                                  struct uverbs_attr_bundle *attrs,
                                  int type)
{
        struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
        u64 act_size;
        int err;

        /* Allocation size must a multiple of the basic block size
         * and a power of 2.
         */
        act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
        act_size = roundup_pow_of_two(act_size);

        dm->size = act_size;
        err = mlx5_dm_sw_icm_alloc(dev, type, act_size,
                                   to_mucontext(ctx)->devx_uid, &dm->dev_addr,
                                   &dm->icm_dm.obj_id);
        if (err)
                return err;

        err = uverbs_copy_to(attrs,
                             MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
                             &dm->dev_addr, sizeof(dm->dev_addr));
        if (err)
                mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
                                       to_mucontext(ctx)->devx_uid, dm->dev_addr,
                                       dm->icm_dm.obj_id);

        return err;
}

struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
                               struct ib_ucontext *context,
                               struct ib_dm_alloc_attr *attr,
                               struct uverbs_attr_bundle *attrs)
{
        struct mlx5_ib_dm *dm;
        enum mlx5_ib_uapi_dm_type type;
        int err;

        err = uverbs_get_const_default(&type, attrs,
                                       MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
                                       MLX5_IB_UAPI_DM_TYPE_MEMIC);
        if (err)
                return ERR_PTR(err);

        mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
                    type, attr->length, attr->alignment);

        err = check_dm_type_support(to_mdev(ibdev), type);
        if (err)
                return ERR_PTR(err);

        dm = kzalloc(sizeof(*dm), GFP_KERNEL);
        if (!dm)
                return ERR_PTR(-ENOMEM);

        dm->type = type;

        switch (type) {
        case MLX5_IB_UAPI_DM_TYPE_MEMIC:
                err = handle_alloc_dm_memic(context, dm,
                                            attr,
                                            attrs);
                break;
        case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
                err = handle_alloc_dm_sw_icm(context, dm,
                                             attr, attrs,
                                             MLX5_SW_ICM_TYPE_STEERING);
                break;
        case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
                err = handle_alloc_dm_sw_icm(context, dm,
                                             attr, attrs,
                                             MLX5_SW_ICM_TYPE_HEADER_MODIFY);
                break;
        default:
                err = -EOPNOTSUPP;
        }

        if (err)
                goto err_free;

        return &dm->ibdm;

err_free:
        kfree(dm);
        return ERR_PTR(err);
}

int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
{
        struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
                &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
        struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
        struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
        struct mlx5_ib_dm *dm = to_mdm(ibdm);
        u32 page_idx;
        int ret;

        switch (dm->type) {
        case MLX5_IB_UAPI_DM_TYPE_MEMIC:
                ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
                if (ret)
                        return ret;

                page_idx = (dm->dev_addr - pci_resource_start(dev->pdev, 0) -
                            MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr)) >>
                            PAGE_SHIFT;
                bitmap_clear(ctx->dm_pages, page_idx,
                             DIV_ROUND_UP(dm->size, PAGE_SIZE));
                break;
        case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
                ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
                                             dm->size, ctx->devx_uid, dm->dev_addr,
                                             dm->icm_dm.obj_id);
                if (ret)
                        return ret;
                break;
        case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
                ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
                                             dm->size, ctx->devx_uid, dm->dev_addr,
                                             dm->icm_dm.obj_id);
                if (ret)
                        return ret;
                break;
        default:
                return -EOPNOTSUPP;
        }

        kfree(dm);

        return 0;
}

static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
{
        struct mlx5_ib_pd *pd = to_mpd(ibpd);
        struct ib_device *ibdev = ibpd->device;
        struct mlx5_ib_alloc_pd_resp resp;
        int err;
        u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
        u32 in[MLX5_ST_SZ_DW(alloc_pd_in)]   = {};
        u16 uid = 0;
        struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
                udata, struct mlx5_ib_ucontext, ibucontext);

        uid = context ? context->devx_uid : 0;
        MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
        MLX5_SET(alloc_pd_in, in, uid, uid);
        err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
                            out, sizeof(out));
        if (err)
                return err;

        pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
        pd->uid = uid;
        if (udata) {
                resp.pdn = pd->pdn;
                if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
                        mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
                        return -EFAULT;
                }
        }

        return 0;
}

static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
{
        struct mlx5_ib_dev *mdev = to_mdev(pd->device);
        struct mlx5_ib_pd *mpd = to_mpd(pd);

        mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
}

enum {
        MATCH_CRITERIA_ENABLE_OUTER_BIT,
        MATCH_CRITERIA_ENABLE_MISC_BIT,
        MATCH_CRITERIA_ENABLE_INNER_BIT,
        MATCH_CRITERIA_ENABLE_MISC2_BIT
};

#define HEADER_IS_ZERO(match_criteria, headers)                            \
        !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
                    0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \

static u8 get_match_criteria_enable(u32 *match_criteria)
{
        u8 match_criteria_enable;

        match_criteria_enable =
                (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
                MATCH_CRITERIA_ENABLE_OUTER_BIT;
        match_criteria_enable |=
                (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
                MATCH_CRITERIA_ENABLE_MISC_BIT;
        match_criteria_enable |=
                (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
                MATCH_CRITERIA_ENABLE_INNER_BIT;
        match_criteria_enable |=
                (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
                MATCH_CRITERIA_ENABLE_MISC2_BIT;

        return match_criteria_enable;
}

static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
{
        u8 entry_mask;
        u8 entry_val;
        int err = 0;

        if (!mask)
                goto out;

        entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
                              ip_protocol);
        entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
                             ip_protocol);
        if (!entry_mask) {
                MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
                MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
                goto out;
        }
        /* Don't override existing ip protocol */
        if (mask != entry_mask || val != entry_val)
                err = -EINVAL;
out:
        return err;
}

static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
                           bool inner)
{
        if (inner) {
                MLX5_SET(fte_match_set_misc,
                         misc_c, inner_ipv6_flow_label, mask);
                MLX5_SET(fte_match_set_misc,
                         misc_v, inner_ipv6_flow_label, val);
        } else {
                MLX5_SET(fte_match_set_misc,
                         misc_c, outer_ipv6_flow_label, mask);
                MLX5_SET(fte_match_set_misc,
                         misc_v, outer_ipv6_flow_label, val);
        }
}

static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
{
        MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
        MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
        MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
        MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
}

static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
{
        if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
            !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
                return -EOPNOTSUPP;

        if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
            !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
                return -EOPNOTSUPP;

        if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
            !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
                return -EOPNOTSUPP;

        if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
            !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
                return -EOPNOTSUPP;

        return 0;
}

#define LAST_ETH_FIELD vlan_tag
#define LAST_IB_FIELD sl
#define LAST_IPV4_FIELD tos
#define LAST_IPV6_FIELD traffic_class
#define LAST_TCP_UDP_FIELD src_port
#define LAST_TUNNEL_FIELD tunnel_id
#define LAST_FLOW_TAG_FIELD tag_id
#define LAST_DROP_FIELD size
#define LAST_COUNTERS_FIELD counters

/* Field is the last supported field */
#define FIELDS_NOT_SUPPORTED(filter, field)\
        memchr_inv((void *)&filter.field  +\
                   sizeof(filter.field), 0,\
                   sizeof(filter) -\
                   offsetof(typeof(filter), field) -\
                   sizeof(filter.field))

int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
                           bool is_egress,
                           struct mlx5_flow_act *action)
{

        switch (maction->ib_action.type) {
        case IB_FLOW_ACTION_ESP:
                if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
                        return -EINVAL;
                /* Currently only AES_GCM keymat is supported by the driver */
                action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
                action->action |= is_egress ?
                        MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
                        MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
                return 0;
        case IB_FLOW_ACTION_UNSPECIFIED:
                if (maction->flow_action_raw.sub_type ==
                    MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
                        if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
                                return -EINVAL;
                        action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
                        action->modify_hdr =
                                maction->flow_action_raw.modify_hdr;
                        return 0;
                }
                if (maction->flow_action_raw.sub_type ==
                    MLX5_IB_FLOW_ACTION_DECAP) {
                        if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
                                return -EINVAL;
                        action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
                        return 0;
                }
                if (maction->flow_action_raw.sub_type ==
                    MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
                        if (action->action &
                            MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
                                return -EINVAL;
                        action->action |=
                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
                        action->pkt_reformat =
                                maction->flow_action_raw.pkt_reformat;
                        return 0;
                }
                /* fall through */
        default:
                return -EOPNOTSUPP;
        }
}

static int parse_flow_attr(struct mlx5_core_dev *mdev,
                           struct mlx5_flow_spec *spec,
                           const union ib_flow_spec *ib_spec,
                           const struct ib_flow_attr *flow_attr,
                           struct mlx5_flow_act *action, u32 prev_type)
{
        struct mlx5_flow_context *flow_context = &spec->flow_context;
        u32 *match_c = spec->match_criteria;
        u32 *match_v = spec->match_value;
        void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
                                           misc_parameters);
        void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
                                           misc_parameters);
        void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
                                            misc_parameters_2);
        void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
                                            misc_parameters_2);
        void *headers_c;
        void *headers_v;
        int match_ipv;
        int ret;

        if (ib_spec->type & IB_FLOW_SPEC_INNER) {
                headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
                                         inner_headers);
                headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
                                         inner_headers);
                match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
                                        ft_field_support.inner_ip_version);
        } else {
                headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
                                         outer_headers);
                headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
                                         outer_headers);
                match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
                                        ft_field_support.outer_ip_version);
        }

        switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
        case IB_FLOW_SPEC_ETH:
                if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
                        return -EOPNOTSUPP;

                ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
                                             dmac_47_16),
                                ib_spec->eth.mask.dst_mac);
                ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
                                             dmac_47_16),
                                ib_spec->eth.val.dst_mac);

                ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
                                             smac_47_16),
                                ib_spec->eth.mask.src_mac);
                ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
                                             smac_47_16),
                                ib_spec->eth.val.src_mac);

                if (ib_spec->eth.mask.vlan_tag) {
                        MLX5_SET(fte_match_set_lyr_2_4, headers_c,
                                 cvlan_tag, 1);
                        MLX5_SET(fte_match_set_lyr_2_4, headers_v,
                                 cvlan_tag, 1);

                        MLX5_SET(fte_match_set_lyr_2_4, headers_c,
                                 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
                        MLX5_SET(fte_match_set_lyr_2_4, headers_v,
                                 first_vid, ntohs(ib_spec->eth.val.vlan_tag));

                        MLX5_SET(fte_match_set_lyr_2_4, headers_c,
                                 first_cfi,
                                 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
                        MLX5_SET(fte_match_set_lyr_2_4, headers_v,
                                 first_cfi,
                                 ntohs(ib_spec->eth.val.vlan_tag) >> 12);

                        MLX5_SET(fte_match_set_lyr_2_4, headers_c,
                                 first_prio,
                                 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
                        MLX5_SET(fte_match_set_lyr_2_4, headers_v,
                                 first_prio,
                                 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
                }
                MLX5_SET(fte_match_set_lyr_2_4, headers_c,
                         ethertype, ntohs(ib_spec->eth.mask.ether_type));
                MLX5_SET(fte_match_set_lyr_2_4, headers_v,
                         ethertype, ntohs(ib_spec->eth.val.ether_type));
                break;
        case IB_FLOW_SPEC_IPV4:
                if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
                        return -EOPNOTSUPP;

                if (match_ipv) {
                        MLX5_SET(fte_match_set_lyr_2_4, headers_c,
                                 ip_version, 0xf);
                        MLX5_SET(fte_match_set_lyr_2_4, headers_v,
                                 ip_version, MLX5_FS_IPV4_VERSION);
                } else {
                        MLX5_SET(fte_match_set_lyr_2_4, headers_c,
                                 ethertype, 0xffff);
                        MLX5_SET(fte_match_set_lyr_2_4, headers_v,
                                 ethertype, ETH_P_IP);
                }

                memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
                                    src_ipv4_src_ipv6.ipv4_layout.ipv4),
                       &ib_spec->ipv4.mask.src_ip,
                       sizeof(ib_spec->ipv4.mask.src_ip));
                memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
                                    src_ipv4_src_ipv6.ipv4_layout.ipv4),
                       &ib_spec->ipv4.val.src_ip,
                       sizeof(ib_spec->ipv4.val.src_ip));
                memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
                                    dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
                       &ib_spec->ipv4.mask.dst_ip,
                       sizeof(ib_spec->ipv4.mask.dst_ip));
                memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
                                    dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
                       &ib_spec->ipv4.val.dst_ip,
                       sizeof(ib_spec->ipv4.val.dst_ip));

                set_tos(headers_c, headers_v,
                        ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);

                if (set_proto(headers_c, headers_v,
                              ib_spec->ipv4.mask.proto,
                              ib_spec->ipv4.val.proto))
                        return -EINVAL;
                break;
        case IB_FLOW_SPEC_IPV6:
                if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
                        return -EOPNOTSUPP;

                if (match_ipv) {
                        MLX5_SET(fte_match_set_lyr_2_4, headers_c,
                                 ip_version, 0xf);
                        MLX5_SET(fte_match_set_lyr_2_4, headers_v,
                                 ip_version, MLX5_FS_IPV6_VERSION);
                } else {
                        MLX5_SET(fte_match_set_lyr_2_4, headers_c,
                                 ethertype, 0xffff);
                        MLX5_SET(fte_match_set_lyr_2_4, headers_v,
                                 ethertype, ETH_P_IPV6);
                }

                memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
                                    src_ipv4_src_ipv6.ipv6_layout.ipv6),
                       &ib_spec->ipv6.mask.src_ip,
                       sizeof(ib_spec->ipv6.mask.src_ip));
                memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
                                    src_ipv4_src_ipv6.ipv6_layout.ipv6),
                       &ib_spec->ipv6.val.src_ip,
                       sizeof(ib_spec->ipv6.val.src_ip));
                memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
                                    dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
                       &ib_spec->ipv6.mask.dst_ip,
                       sizeof(ib_spec->ipv6.mask.dst_ip));
                memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
                                    dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
                       &ib_spec->ipv6.val.dst_ip,
                       sizeof(ib_spec->ipv6.val.dst_ip));

                set_tos(headers_c, headers_v,
                        ib_spec->ipv6.mask.traffic_class,
                        ib_spec->ipv6.val.traffic_class);

                if (set_proto(headers_c, headers_v,
                              ib_spec->ipv6.mask.next_hdr,
                              ib_spec->ipv6.val.next_hdr))
                        return -EINVAL;

                set_flow_label(misc_params_c, misc_params_v,
                               ntohl(ib_spec->ipv6.mask.flow_label),
                               ntohl(ib_spec->ipv6.val.flow_label),
                               ib_spec->type & IB_FLOW_SPEC_INNER);
                break;
        case IB_FLOW_SPEC_ESP:
                if (ib_spec->esp.mask.seq)
                        return -EOPNOTSUPP;

                MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
                         ntohl(ib_spec->esp.mask.spi));
                MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
                         ntohl(ib_spec->esp.val.spi));
                break;
        case IB_FLOW_SPEC_TCP:
                if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
                                         LAST_TCP_UDP_FIELD))
                        return -EOPNOTSUPP;

                if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
                        return -EINVAL;

                MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
                         ntohs(ib_spec->tcp_udp.mask.src_port));
                MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
                         ntohs(ib_spec->tcp_udp.val.src_port));

                MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
                         ntohs(ib_spec->tcp_udp.mask.dst_port));
                MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
                         ntohs(ib_spec->tcp_udp.val.dst_port));
                break;
        case IB_FLOW_SPEC_UDP:
                if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
                                         LAST_TCP_UDP_FIELD))
                        return -EOPNOTSUPP;

                if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
                        return -EINVAL;

                MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
                         ntohs(ib_spec->tcp_udp.mask.src_port));
                MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
                         ntohs(ib_spec->tcp_udp.val.src_port));

                MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
                         ntohs(ib_spec->tcp_udp.mask.dst_port));
                MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
                         ntohs(ib_spec->tcp_udp.val.dst_port));
                break;
        case IB_FLOW_SPEC_GRE:
                if (ib_spec->gre.mask.c_ks_res0_ver)
                        return -EOPNOTSUPP;

                if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
                        return -EINVAL;

                MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
                         0xff);
                MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
                         IPPROTO_GRE);

                MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
                         ntohs(ib_spec->gre.mask.protocol));
                MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
                         ntohs(ib_spec->gre.val.protocol));

                memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
                                    gre_key.nvgre.hi),
                       &ib_spec->gre.mask.key,
                       sizeof(ib_spec->gre.mask.key));
                memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
                                    gre_key.nvgre.hi),
                       &ib_spec->gre.val.key,
                       sizeof(ib_spec->gre.val.key));
                break;
        case IB_FLOW_SPEC_MPLS:
                switch (prev_type) {
                case IB_FLOW_SPEC_UDP:
                        if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
                                                   ft_field_support.outer_first_mpls_over_udp),
                                                   &ib_spec->mpls.mask.tag))
                                return -EOPNOTSUPP;

                        memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
                                            outer_first_mpls_over_udp),
                               &ib_spec->mpls.val.tag,
                               sizeof(ib_spec->mpls.val.tag));
                        memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
                                            outer_first_mpls_over_udp),
                               &ib_spec->mpls.mask.tag,
                               sizeof(ib_spec->mpls.mask.tag));
                        break;
                case IB_FLOW_SPEC_GRE:
                        if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
                                                   ft_field_support.outer_first_mpls_over_gre),
                                                   &ib_spec->mpls.mask.tag))
                                return -EOPNOTSUPP;

                        memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
                                            outer_first_mpls_over_gre),
                               &ib_spec->mpls.val.tag,
                               sizeof(ib_spec->mpls.val.tag));
                        memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
                                            outer_first_mpls_over_gre),
                               &ib_spec->mpls.mask.tag,
                               sizeof(ib_spec->mpls.mask.tag));
                        break;
                default:
                        if (ib_spec->type & IB_FLOW_SPEC_INNER) {
                                if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
                                                           ft_field_support.inner_first_mpls),
                                                           &ib_spec->mpls.mask.tag))
                                        return -EOPNOTSUPP;

                                memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
                                                    inner_first_mpls),
                                       &ib_spec->mpls.val.tag,
                                       sizeof(ib_spec->mpls.val.tag));
                                memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
                                                    inner_first_mpls),
                                       &ib_spec->mpls.mask.tag,
                                       sizeof(ib_spec->mpls.mask.tag));
                        } else {
                                if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
                                                           ft_field_support.outer_first_mpls),
                                                           &ib_spec->mpls.mask.tag))
                                        return -EOPNOTSUPP;

                                memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
                                                    outer_first_mpls),
                                       &ib_spec->mpls.val.tag,
                                       sizeof(ib_spec->mpls.val.tag));
                                memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
                                                    outer_first_mpls),
                                       &ib_spec->mpls.mask.tag,
                                       sizeof(ib_spec->mpls.mask.tag));
                        }
                }
                break;
        case IB_FLOW_SPEC_VXLAN_TUNNEL:
                if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
                                         LAST_TUNNEL_FIELD))
                        return -EOPNOTSUPP;

                MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
                         ntohl(ib_spec->tunnel.mask.tunnel_id));
                MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
                         ntohl(ib_spec->tunnel.val.tunnel_id));
                break;
        case IB_FLOW_SPEC_ACTION_TAG: