linux/drivers/iommu/omap-iommu.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * omap iommu: tlb and pagetable primitives
   4 *
   5 * Copyright (C) 2008-2010 Nokia Corporation
   6 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
   7 *
   8 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
   9 *              Paul Mundt and Toshihiro Kobayashi
  10 */
  11
  12#include <linux/dma-mapping.h>
  13#include <linux/err.h>
  14#include <linux/slab.h>
  15#include <linux/interrupt.h>
  16#include <linux/ioport.h>
  17#include <linux/platform_device.h>
  18#include <linux/iommu.h>
  19#include <linux/omap-iommu.h>
  20#include <linux/mutex.h>
  21#include <linux/spinlock.h>
  22#include <linux/io.h>
  23#include <linux/pm_runtime.h>
  24#include <linux/of.h>
  25#include <linux/of_iommu.h>
  26#include <linux/of_irq.h>
  27#include <linux/of_platform.h>
  28#include <linux/regmap.h>
  29#include <linux/mfd/syscon.h>
  30
  31#include <linux/platform_data/iommu-omap.h>
  32
  33#include "omap-iopgtable.h"
  34#include "omap-iommu.h"
  35
  36static const struct iommu_ops omap_iommu_ops;
  37
  38struct orphan_dev {
  39        struct device *dev;
  40        struct list_head node;
  41};
  42
  43static LIST_HEAD(orphan_dev_list);
  44
  45static DEFINE_SPINLOCK(orphan_lock);
  46
  47#define to_iommu(dev)   ((struct omap_iommu *)dev_get_drvdata(dev))
  48
  49/* bitmap of the page sizes currently supported */
  50#define OMAP_IOMMU_PGSIZES      (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
  51
  52#define MMU_LOCK_BASE_SHIFT     10
  53#define MMU_LOCK_BASE_MASK      (0x1f << MMU_LOCK_BASE_SHIFT)
  54#define MMU_LOCK_BASE(x)        \
  55        ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
  56
  57#define MMU_LOCK_VICT_SHIFT     4
  58#define MMU_LOCK_VICT_MASK      (0x1f << MMU_LOCK_VICT_SHIFT)
  59#define MMU_LOCK_VICT(x)        \
  60        ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
  61
  62static struct platform_driver omap_iommu_driver;
  63static struct kmem_cache *iopte_cachep;
  64
  65static int _omap_iommu_add_device(struct device *dev);
  66
  67/**
  68 * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain
  69 * @dom:        generic iommu domain handle
  70 **/
  71static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom)
  72{
  73        return container_of(dom, struct omap_iommu_domain, domain);
  74}
  75
  76/**
  77 * omap_iommu_save_ctx - Save registers for pm off-mode support
  78 * @dev:        client device
  79 *
  80 * This should be treated as an deprecated API. It is preserved only
  81 * to maintain existing functionality for OMAP3 ISP driver.
  82 **/
  83void omap_iommu_save_ctx(struct device *dev)
  84{
  85        struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
  86        struct omap_iommu *obj;
  87        u32 *p;
  88        int i;
  89
  90        if (!arch_data)
  91                return;
  92
  93        while (arch_data->iommu_dev) {
  94                obj = arch_data->iommu_dev;
  95                p = obj->ctx;
  96                for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
  97                        p[i] = iommu_read_reg(obj, i * sizeof(u32));
  98                        dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i,
  99                                p[i]);
 100                }
 101                arch_data++;
 102        }
 103}
 104EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
 105
 106/**
 107 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
 108 * @dev:        client device
 109 *
 110 * This should be treated as an deprecated API. It is preserved only
 111 * to maintain existing functionality for OMAP3 ISP driver.
 112 **/
 113void omap_iommu_restore_ctx(struct device *dev)
 114{
 115        struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
 116        struct omap_iommu *obj;
 117        u32 *p;
 118        int i;
 119
 120        if (!arch_data)
 121                return;
 122
 123        while (arch_data->iommu_dev) {
 124                obj = arch_data->iommu_dev;
 125                p = obj->ctx;
 126                for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
 127                        iommu_write_reg(obj, p[i], i * sizeof(u32));
 128                        dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i,
 129                                p[i]);
 130                }
 131                arch_data++;
 132        }
 133}
 134EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
 135
 136static void dra7_cfg_dspsys_mmu(struct omap_iommu *obj, bool enable)
 137{
 138        u32 val, mask;
 139
 140        if (!obj->syscfg)
 141                return;
 142
 143        mask = (1 << (obj->id * DSP_SYS_MMU_CONFIG_EN_SHIFT));
 144        val = enable ? mask : 0;
 145        regmap_update_bits(obj->syscfg, DSP_SYS_MMU_CONFIG, mask, val);
 146}
 147
 148static void __iommu_set_twl(struct omap_iommu *obj, bool on)
 149{
 150        u32 l = iommu_read_reg(obj, MMU_CNTL);
 151
 152        if (on)
 153                iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
 154        else
 155                iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
 156
 157        l &= ~MMU_CNTL_MASK;
 158        if (on)
 159                l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
 160        else
 161                l |= (MMU_CNTL_MMU_EN);
 162
 163        iommu_write_reg(obj, l, MMU_CNTL);
 164}
 165
 166static int omap2_iommu_enable(struct omap_iommu *obj)
 167{
 168        u32 l, pa;
 169
 170        if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
 171                return -EINVAL;
 172
 173        pa = virt_to_phys(obj->iopgd);
 174        if (!IS_ALIGNED(pa, SZ_16K))
 175                return -EINVAL;
 176
 177        l = iommu_read_reg(obj, MMU_REVISION);
 178        dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
 179                 (l >> 4) & 0xf, l & 0xf);
 180
 181        iommu_write_reg(obj, pa, MMU_TTB);
 182
 183        dra7_cfg_dspsys_mmu(obj, true);
 184
 185        if (obj->has_bus_err_back)
 186                iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG);
 187
 188        __iommu_set_twl(obj, true);
 189
 190        return 0;
 191}
 192
 193static void omap2_iommu_disable(struct omap_iommu *obj)
 194{
 195        u32 l = iommu_read_reg(obj, MMU_CNTL);
 196
 197        l &= ~MMU_CNTL_MASK;
 198        iommu_write_reg(obj, l, MMU_CNTL);
 199        dra7_cfg_dspsys_mmu(obj, false);
 200
 201        dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
 202}
 203
 204static int iommu_enable(struct omap_iommu *obj)
 205{
 206        int ret;
 207
 208        ret = pm_runtime_get_sync(obj->dev);
 209        if (ret < 0)
 210                pm_runtime_put_noidle(obj->dev);
 211
 212        return ret < 0 ? ret : 0;
 213}
 214
 215static void iommu_disable(struct omap_iommu *obj)
 216{
 217        pm_runtime_put_sync(obj->dev);
 218}
 219
 220/*
 221 *      TLB operations
 222 */
 223static u32 iotlb_cr_to_virt(struct cr_regs *cr)
 224{
 225        u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
 226        u32 mask = get_cam_va_mask(cr->cam & page_size);
 227
 228        return cr->cam & mask;
 229}
 230
 231static u32 get_iopte_attr(struct iotlb_entry *e)
 232{
 233        u32 attr;
 234
 235        attr = e->mixed << 5;
 236        attr |= e->endian;
 237        attr |= e->elsz >> 3;
 238        attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
 239                        (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
 240        return attr;
 241}
 242
 243static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
 244{
 245        u32 status, fault_addr;
 246
 247        status = iommu_read_reg(obj, MMU_IRQSTATUS);
 248        status &= MMU_IRQ_MASK;
 249        if (!status) {
 250                *da = 0;
 251                return 0;
 252        }
 253
 254        fault_addr = iommu_read_reg(obj, MMU_FAULT_AD);
 255        *da = fault_addr;
 256
 257        iommu_write_reg(obj, status, MMU_IRQSTATUS);
 258
 259        return status;
 260}
 261
 262void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
 263{
 264        u32 val;
 265
 266        val = iommu_read_reg(obj, MMU_LOCK);
 267
 268        l->base = MMU_LOCK_BASE(val);
 269        l->vict = MMU_LOCK_VICT(val);
 270}
 271
 272void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
 273{
 274        u32 val;
 275
 276        val = (l->base << MMU_LOCK_BASE_SHIFT);
 277        val |= (l->vict << MMU_LOCK_VICT_SHIFT);
 278
 279        iommu_write_reg(obj, val, MMU_LOCK);
 280}
 281
 282static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
 283{
 284        cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
 285        cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
 286}
 287
 288static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
 289{
 290        iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
 291        iommu_write_reg(obj, cr->ram, MMU_RAM);
 292
 293        iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
 294        iommu_write_reg(obj, 1, MMU_LD_TLB);
 295}
 296
 297/* only used in iotlb iteration for-loop */
 298struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
 299{
 300        struct cr_regs cr;
 301        struct iotlb_lock l;
 302
 303        iotlb_lock_get(obj, &l);
 304        l.vict = n;
 305        iotlb_lock_set(obj, &l);
 306        iotlb_read_cr(obj, &cr);
 307
 308        return cr;
 309}
 310
 311#ifdef PREFETCH_IOTLB
 312static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
 313                                      struct iotlb_entry *e)
 314{
 315        struct cr_regs *cr;
 316
 317        if (!e)
 318                return NULL;
 319
 320        if (e->da & ~(get_cam_va_mask(e->pgsz))) {
 321                dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
 322                        e->da);
 323                return ERR_PTR(-EINVAL);
 324        }
 325
 326        cr = kmalloc(sizeof(*cr), GFP_KERNEL);
 327        if (!cr)
 328                return ERR_PTR(-ENOMEM);
 329
 330        cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
 331        cr->ram = e->pa | e->endian | e->elsz | e->mixed;
 332
 333        return cr;
 334}
 335
 336/**
 337 * load_iotlb_entry - Set an iommu tlb entry
 338 * @obj:        target iommu
 339 * @e:          an iommu tlb entry info
 340 **/
 341static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
 342{
 343        int err = 0;
 344        struct iotlb_lock l;
 345        struct cr_regs *cr;
 346
 347        if (!obj || !obj->nr_tlb_entries || !e)
 348                return -EINVAL;
 349
 350        pm_runtime_get_sync(obj->dev);
 351
 352        iotlb_lock_get(obj, &l);
 353        if (l.base == obj->nr_tlb_entries) {
 354                dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
 355                err = -EBUSY;
 356                goto out;
 357        }
 358        if (!e->prsvd) {
 359                int i;
 360                struct cr_regs tmp;
 361
 362                for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
 363                        if (!iotlb_cr_valid(&tmp))
 364                                break;
 365
 366                if (i == obj->nr_tlb_entries) {
 367                        dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
 368                        err = -EBUSY;
 369                        goto out;
 370                }
 371
 372                iotlb_lock_get(obj, &l);
 373        } else {
 374                l.vict = l.base;
 375                iotlb_lock_set(obj, &l);
 376        }
 377
 378        cr = iotlb_alloc_cr(obj, e);
 379        if (IS_ERR(cr)) {
 380                pm_runtime_put_sync(obj->dev);
 381                return PTR_ERR(cr);
 382        }
 383
 384        iotlb_load_cr(obj, cr);
 385        kfree(cr);
 386
 387        if (e->prsvd)
 388                l.base++;
 389        /* increment victim for next tlb load */
 390        if (++l.vict == obj->nr_tlb_entries)
 391                l.vict = l.base;
 392        iotlb_lock_set(obj, &l);
 393out:
 394        pm_runtime_put_sync(obj->dev);
 395        return err;
 396}
 397
 398#else /* !PREFETCH_IOTLB */
 399
 400static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
 401{
 402        return 0;
 403}
 404
 405#endif /* !PREFETCH_IOTLB */
 406
 407static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
 408{
 409        return load_iotlb_entry(obj, e);
 410}
 411
 412/**
 413 * flush_iotlb_page - Clear an iommu tlb entry
 414 * @obj:        target iommu
 415 * @da:         iommu device virtual address
 416 *
 417 * Clear an iommu tlb entry which includes 'da' address.
 418 **/
 419static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
 420{
 421        int i;
 422        struct cr_regs cr;
 423
 424        pm_runtime_get_sync(obj->dev);
 425
 426        for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
 427                u32 start;
 428                size_t bytes;
 429
 430                if (!iotlb_cr_valid(&cr))
 431                        continue;
 432
 433                start = iotlb_cr_to_virt(&cr);
 434                bytes = iopgsz_to_bytes(cr.cam & 3);
 435
 436                if ((start <= da) && (da < start + bytes)) {
 437                        dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
 438                                __func__, start, da, bytes);
 439                        iotlb_load_cr(obj, &cr);
 440                        iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
 441                        break;
 442                }
 443        }
 444        pm_runtime_put_sync(obj->dev);
 445
 446        if (i == obj->nr_tlb_entries)
 447                dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
 448}
 449
 450/**
 451 * flush_iotlb_all - Clear all iommu tlb entries
 452 * @obj:        target iommu
 453 **/
 454static void flush_iotlb_all(struct omap_iommu *obj)
 455{
 456        struct iotlb_lock l;
 457
 458        pm_runtime_get_sync(obj->dev);
 459
 460        l.base = 0;
 461        l.vict = 0;
 462        iotlb_lock_set(obj, &l);
 463
 464        iommu_write_reg(obj, 1, MMU_GFLUSH);
 465
 466        pm_runtime_put_sync(obj->dev);
 467}
 468
 469/*
 470 *      H/W pagetable operations
 471 */
 472static void flush_iopte_range(struct device *dev, dma_addr_t dma,
 473                              unsigned long offset, int num_entries)
 474{
 475        size_t size = num_entries * sizeof(u32);
 476
 477        dma_sync_single_range_for_device(dev, dma, offset, size, DMA_TO_DEVICE);
 478}
 479
 480static void iopte_free(struct omap_iommu *obj, u32 *iopte, bool dma_valid)
 481{
 482        dma_addr_t pt_dma;
 483
 484        /* Note: freed iopte's must be clean ready for re-use */
 485        if (iopte) {
 486                if (dma_valid) {
 487                        pt_dma = virt_to_phys(iopte);
 488                        dma_unmap_single(obj->dev, pt_dma, IOPTE_TABLE_SIZE,
 489                                         DMA_TO_DEVICE);
 490                }
 491
 492                kmem_cache_free(iopte_cachep, iopte);
 493        }
 494}
 495
 496static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd,
 497                        dma_addr_t *pt_dma, u32 da)
 498{
 499        u32 *iopte;
 500        unsigned long offset = iopgd_index(da) * sizeof(da);
 501
 502        /* a table has already existed */
 503        if (*iopgd)
 504                goto pte_ready;
 505
 506        /*
 507         * do the allocation outside the page table lock
 508         */
 509        spin_unlock(&obj->page_table_lock);
 510        iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
 511        spin_lock(&obj->page_table_lock);
 512
 513        if (!*iopgd) {
 514                if (!iopte)
 515                        return ERR_PTR(-ENOMEM);
 516
 517                *pt_dma = dma_map_single(obj->dev, iopte, IOPTE_TABLE_SIZE,
 518                                         DMA_TO_DEVICE);
 519                if (dma_mapping_error(obj->dev, *pt_dma)) {
 520                        dev_err(obj->dev, "DMA map error for L2 table\n");
 521                        iopte_free(obj, iopte, false);
 522                        return ERR_PTR(-ENOMEM);
 523                }
 524
 525                /*
 526                 * we rely on dma address and the physical address to be
 527                 * the same for mapping the L2 table
 528                 */
 529                if (WARN_ON(*pt_dma != virt_to_phys(iopte))) {
 530                        dev_err(obj->dev, "DMA translation error for L2 table\n");
 531                        dma_unmap_single(obj->dev, *pt_dma, IOPTE_TABLE_SIZE,
 532                                         DMA_TO_DEVICE);
 533                        iopte_free(obj, iopte, false);
 534                        return ERR_PTR(-ENOMEM);
 535                }
 536
 537                *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
 538
 539                flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
 540                dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
 541        } else {
 542                /* We raced, free the reduniovant table */
 543                iopte_free(obj, iopte, false);
 544        }
 545
 546pte_ready:
 547        iopte = iopte_offset(iopgd, da);
 548        *pt_dma = iopgd_page_paddr(iopgd);
 549        dev_vdbg(obj->dev,
 550                 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
 551                 __func__, da, iopgd, *iopgd, iopte, *iopte);
 552
 553        return iopte;
 554}
 555
 556static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
 557{
 558        u32 *iopgd = iopgd_offset(obj, da);
 559        unsigned long offset = iopgd_index(da) * sizeof(da);
 560
 561        if ((da | pa) & ~IOSECTION_MASK) {
 562                dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
 563                        __func__, da, pa, IOSECTION_SIZE);
 564                return -EINVAL;
 565        }
 566
 567        *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
 568        flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
 569        return 0;
 570}
 571
 572static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
 573{
 574        u32 *iopgd = iopgd_offset(obj, da);
 575        unsigned long offset = iopgd_index(da) * sizeof(da);
 576        int i;
 577
 578        if ((da | pa) & ~IOSUPER_MASK) {
 579                dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
 580                        __func__, da, pa, IOSUPER_SIZE);
 581                return -EINVAL;
 582        }
 583
 584        for (i = 0; i < 16; i++)
 585                *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
 586        flush_iopte_range(obj->dev, obj->pd_dma, offset, 16);
 587        return 0;
 588}
 589
 590static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
 591{
 592        u32 *iopgd = iopgd_offset(obj, da);
 593        dma_addr_t pt_dma;
 594        u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da);
 595        unsigned long offset = iopte_index(da) * sizeof(da);
 596
 597        if (IS_ERR(iopte))
 598                return PTR_ERR(iopte);
 599
 600        *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
 601        flush_iopte_range(obj->dev, pt_dma, offset, 1);
 602
 603        dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
 604                 __func__, da, pa, iopte, *iopte);
 605
 606        return 0;
 607}
 608
 609static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
 610{
 611        u32 *iopgd = iopgd_offset(obj, da);
 612        dma_addr_t pt_dma;
 613        u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da);
 614        unsigned long offset = iopte_index(da) * sizeof(da);
 615        int i;
 616
 617        if ((da | pa) & ~IOLARGE_MASK) {
 618                dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
 619                        __func__, da, pa, IOLARGE_SIZE);
 620                return -EINVAL;
 621        }
 622
 623        if (IS_ERR(iopte))
 624                return PTR_ERR(iopte);
 625
 626        for (i = 0; i < 16; i++)
 627                *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
 628        flush_iopte_range(obj->dev, pt_dma, offset, 16);
 629        return 0;
 630}
 631
 632static int
 633iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
 634{
 635        int (*fn)(struct omap_iommu *, u32, u32, u32);
 636        u32 prot;
 637        int err;
 638
 639        if (!obj || !e)
 640                return -EINVAL;
 641
 642        switch (e->pgsz) {
 643        case MMU_CAM_PGSZ_16M:
 644                fn = iopgd_alloc_super;
 645                break;
 646        case MMU_CAM_PGSZ_1M:
 647                fn = iopgd_alloc_section;
 648                break;
 649        case MMU_CAM_PGSZ_64K:
 650                fn = iopte_alloc_large;
 651                break;
 652        case MMU_CAM_PGSZ_4K:
 653                fn = iopte_alloc_page;
 654                break;
 655        default:
 656                fn = NULL;
 657                break;
 658        }
 659
 660        if (WARN_ON(!fn))
 661                return -EINVAL;
 662
 663        prot = get_iopte_attr(e);
 664
 665        spin_lock(&obj->page_table_lock);
 666        err = fn(obj, e->da, e->pa, prot);
 667        spin_unlock(&obj->page_table_lock);
 668
 669        return err;
 670}
 671
 672/**
 673 * omap_iopgtable_store_entry - Make an iommu pte entry
 674 * @obj:        target iommu
 675 * @e:          an iommu tlb entry info
 676 **/
 677static int
 678omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
 679{
 680        int err;
 681
 682        flush_iotlb_page(obj, e->da);
 683        err = iopgtable_store_entry_core(obj, e);
 684        if (!err)
 685                prefetch_iotlb_entry(obj, e);
 686        return err;
 687}
 688
 689/**
 690 * iopgtable_lookup_entry - Lookup an iommu pte entry
 691 * @obj:        target iommu
 692 * @da:         iommu device virtual address
 693 * @ppgd:       iommu pgd entry pointer to be returned
 694 * @ppte:       iommu pte entry pointer to be returned
 695 **/
 696static void
 697iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
 698{
 699        u32 *iopgd, *iopte = NULL;
 700
 701        iopgd = iopgd_offset(obj, da);
 702        if (!*iopgd)
 703                goto out;
 704
 705        if (iopgd_is_table(*iopgd))
 706                iopte = iopte_offset(iopgd, da);
 707out:
 708        *ppgd = iopgd;
 709        *ppte = iopte;
 710}
 711
 712static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
 713{
 714        size_t bytes;
 715        u32 *iopgd = iopgd_offset(obj, da);
 716        int nent = 1;
 717        dma_addr_t pt_dma;
 718        unsigned long pd_offset = iopgd_index(da) * sizeof(da);
 719        unsigned long pt_offset = iopte_index(da) * sizeof(da);
 720
 721        if (!*iopgd)
 722                return 0;
 723
 724        if (iopgd_is_table(*iopgd)) {
 725                int i;
 726                u32 *iopte = iopte_offset(iopgd, da);
 727
 728                bytes = IOPTE_SIZE;
 729                if (*iopte & IOPTE_LARGE) {
 730                        nent *= 16;
 731                        /* rewind to the 1st entry */
 732                        iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
 733                }
 734                bytes *= nent;
 735                memset(iopte, 0, nent * sizeof(*iopte));
 736                pt_dma = iopgd_page_paddr(iopgd);
 737                flush_iopte_range(obj->dev, pt_dma, pt_offset, nent);
 738
 739                /*
 740                 * do table walk to check if this table is necessary or not
 741                 */
 742                iopte = iopte_offset(iopgd, 0);
 743                for (i = 0; i < PTRS_PER_IOPTE; i++)
 744                        if (iopte[i])
 745                                goto out;
 746
 747                iopte_free(obj, iopte, true);
 748                nent = 1; /* for the next L1 entry */
 749        } else {
 750                bytes = IOPGD_SIZE;
 751                if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
 752                        nent *= 16;
 753                        /* rewind to the 1st entry */
 754                        iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
 755                }
 756                bytes *= nent;
 757        }
 758        memset(iopgd, 0, nent * sizeof(*iopgd));
 759        flush_iopte_range(obj->dev, obj->pd_dma, pd_offset, nent);
 760out:
 761        return bytes;
 762}
 763
 764/**
 765 * iopgtable_clear_entry - Remove an iommu pte entry
 766 * @obj:        target iommu
 767 * @da:         iommu device virtual address
 768 **/
 769static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
 770{
 771        size_t bytes;
 772
 773        spin_lock(&obj->page_table_lock);
 774
 775        bytes = iopgtable_clear_entry_core(obj, da);
 776        flush_iotlb_page(obj, da);
 777
 778        spin_unlock(&obj->page_table_lock);
 779
 780        return bytes;
 781}
 782
 783static void iopgtable_clear_entry_all(struct omap_iommu *obj)
 784{
 785        unsigned long offset;
 786        int i;
 787
 788        spin_lock(&obj->page_table_lock);
 789
 790        for (i = 0; i < PTRS_PER_IOPGD; i++) {
 791                u32 da;
 792                u32 *iopgd;
 793
 794                da = i << IOPGD_SHIFT;
 795                iopgd = iopgd_offset(obj, da);
 796                offset = iopgd_index(da) * sizeof(da);
 797
 798                if (!*iopgd)
 799                        continue;
 800
 801                if (iopgd_is_table(*iopgd))
 802                        iopte_free(obj, iopte_offset(iopgd, 0), true);
 803
 804                *iopgd = 0;
 805                flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
 806        }
 807
 808        flush_iotlb_all(obj);
 809
 810        spin_unlock(&obj->page_table_lock);
 811}
 812
 813/*
 814 *      Device IOMMU generic operations
 815 */
 816static irqreturn_t iommu_fault_handler(int irq, void *data)
 817{
 818        u32 da, errs;
 819        u32 *iopgd, *iopte;
 820        struct omap_iommu *obj = data;
 821        struct iommu_domain *domain = obj->domain;
 822        struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
 823
 824        if (!omap_domain->dev)
 825                return IRQ_NONE;
 826
 827        errs = iommu_report_fault(obj, &da);
 828        if (errs == 0)
 829                return IRQ_HANDLED;
 830
 831        /* Fault callback or TLB/PTE Dynamic loading */
 832        if (!report_iommu_fault(domain, obj->dev, da, 0))
 833                return IRQ_HANDLED;
 834
 835        iommu_write_reg(obj, 0, MMU_IRQENABLE);
 836
 837        iopgd = iopgd_offset(obj, da);
 838
 839        if (!iopgd_is_table(*iopgd)) {
 840                dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
 841                        obj->name, errs, da, iopgd, *iopgd);
 842                return IRQ_NONE;
 843        }
 844
 845        iopte = iopte_offset(iopgd, da);
 846
 847        dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
 848                obj->name, errs, da, iopgd, *iopgd, iopte, *iopte);
 849
 850        return IRQ_NONE;
 851}
 852
 853/**
 854 * omap_iommu_attach() - attach iommu device to an iommu domain
 855 * @obj:        target omap iommu device
 856 * @iopgd:      page table
 857 **/
 858static int omap_iommu_attach(struct omap_iommu *obj, u32 *iopgd)
 859{
 860        int err;
 861
 862        spin_lock(&obj->iommu_lock);
 863
 864        obj->pd_dma = dma_map_single(obj->dev, iopgd, IOPGD_TABLE_SIZE,
 865                                     DMA_TO_DEVICE);
 866        if (dma_mapping_error(obj->dev, obj->pd_dma)) {
 867                dev_err(obj->dev, "DMA map error for L1 table\n");
 868                err = -ENOMEM;
 869                goto out_err;
 870        }
 871
 872        obj->iopgd = iopgd;
 873        err = iommu_enable(obj);
 874        if (err)
 875                goto out_err;
 876        flush_iotlb_all(obj);
 877
 878        spin_unlock(&obj->iommu_lock);
 879
 880        dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
 881
 882        return 0;
 883
 884out_err:
 885        spin_unlock(&obj->iommu_lock);
 886
 887        return err;
 888}
 889
 890/**
 891 * omap_iommu_detach - release iommu device
 892 * @obj:        target iommu
 893 **/
 894static void omap_iommu_detach(struct omap_iommu *obj)
 895{
 896        if (!obj || IS_ERR(obj))
 897                return;
 898
 899        spin_lock(&obj->iommu_lock);
 900
 901        dma_unmap_single(obj->dev, obj->pd_dma, IOPGD_TABLE_SIZE,
 902                         DMA_TO_DEVICE);
 903        obj->pd_dma = 0;
 904        obj->iopgd = NULL;
 905        iommu_disable(obj);
 906
 907        spin_unlock(&obj->iommu_lock);
 908
 909        dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
 910}
 911
 912static void omap_iommu_save_tlb_entries(struct omap_iommu *obj)
 913{
 914        struct iotlb_lock lock;
 915        struct cr_regs cr;
 916        struct cr_regs *tmp;
 917        int i;
 918
 919        /* check if there are any locked tlbs to save */
 920        iotlb_lock_get(obj, &lock);
 921        obj->num_cr_ctx = lock.base;
 922        if (!obj->num_cr_ctx)
 923                return;
 924
 925        tmp = obj->cr_ctx;
 926        for_each_iotlb_cr(obj, obj->num_cr_ctx, i, cr)
 927                * tmp++ = cr;
 928}
 929
 930static void omap_iommu_restore_tlb_entries(struct omap_iommu *obj)
 931{
 932        struct iotlb_lock l;
 933        struct cr_regs *tmp;
 934        int i;
 935
 936        /* no locked tlbs to restore */
 937        if (!obj->num_cr_ctx)
 938                return;
 939
 940        l.base = 0;
 941        tmp = obj->cr_ctx;
 942        for (i = 0; i < obj->num_cr_ctx; i++, tmp++) {
 943                l.vict = i;
 944                iotlb_lock_set(obj, &l);
 945                iotlb_load_cr(obj, tmp);
 946        }
 947        l.base = obj->num_cr_ctx;
 948        l.vict = i;
 949        iotlb_lock_set(obj, &l);
 950}
 951
 952/**
 953 * omap_iommu_domain_deactivate - deactivate attached iommu devices
 954 * @domain: iommu domain attached to the target iommu device
 955 *
 956 * This API allows the client devices of IOMMU devices to suspend
 957 * the IOMMUs they control at runtime, after they are idled and
 958 * suspended all activity. System Suspend will leverage the PM
 959 * driver late callbacks.
 960 **/
 961int omap_iommu_domain_deactivate(struct iommu_domain *domain)
 962{
 963        struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
 964        struct omap_iommu_device *iommu;
 965        struct omap_iommu *oiommu;
 966        int i;
 967
 968        if (!omap_domain->dev)
 969                return 0;
 970
 971        iommu = omap_domain->iommus;
 972        iommu += (omap_domain->num_iommus - 1);
 973        for (i = 0; i < omap_domain->num_iommus; i++, iommu--) {
 974                oiommu = iommu->iommu_dev;
 975                pm_runtime_put_sync(oiommu->dev);
 976        }
 977
 978        return 0;
 979}
 980EXPORT_SYMBOL_GPL(omap_iommu_domain_deactivate);
 981
 982/**
 983 * omap_iommu_domain_activate - activate attached iommu devices
 984 * @domain: iommu domain attached to the target iommu device
 985 *
 986 * This API allows the client devices of IOMMU devices to resume the
 987 * IOMMUs they control at runtime, before they can resume operations.
 988 * System Resume will leverage the PM driver late callbacks.
 989 **/
 990int omap_iommu_domain_activate(struct iommu_domain *domain)
 991{
 992        struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
 993        struct omap_iommu_device *iommu;
 994        struct omap_iommu *oiommu;
 995        int i;
 996
 997        if (!omap_domain->dev)
 998                return 0;
 999
1000        iommu = omap_domain->iommus;
1001        for (i = 0; i < omap_domain->num_iommus; i++, iommu++) {
1002                oiommu = iommu->iommu_dev;
1003                pm_runtime_get_sync(oiommu->dev);
1004        }
1005
1006        return 0;
1007}
1008EXPORT_SYMBOL_GPL(omap_iommu_domain_activate);
1009
1010/**
1011 * omap_iommu_runtime_suspend - disable an iommu device
1012 * @dev:        iommu device
1013 *
1014 * This function performs all that is necessary to disable an
1015 * IOMMU device, either during final detachment from a client
1016 * device, or during system/runtime suspend of the device. This
1017 * includes programming all the appropriate IOMMU registers, and
1018 * managing the associated omap_hwmod's state and the device's
1019 * reset line. This function also saves the context of any
1020 * locked TLBs if suspending.
1021 **/
1022static __maybe_unused int omap_iommu_runtime_suspend(struct device *dev)
1023{
1024        struct platform_device *pdev = to_platform_device(dev);
1025        struct iommu_platform_data *pdata = dev_get_platdata(dev);
1026        struct omap_iommu *obj = to_iommu(dev);
1027        int ret;
1028
1029        /* save the TLBs only during suspend, and not for power down */
1030        if (obj->domain && obj->iopgd)
1031                omap_iommu_save_tlb_entries(obj);
1032
1033        omap2_iommu_disable(obj);
1034
1035        if (pdata && pdata->device_idle)
1036                pdata->device_idle(pdev);
1037
1038        if (pdata && pdata->assert_reset)
1039                pdata->assert_reset(pdev, pdata->reset_name);
1040
1041        if (pdata && pdata->set_pwrdm_constraint) {
1042                ret = pdata->set_pwrdm_constraint(pdev, false, &obj->pwrst);
1043                if (ret) {
1044                        dev_warn(obj->dev, "pwrdm_constraint failed to be reset, status = %d\n",
1045                                 ret);
1046                }
1047        }
1048
1049        return 0;
1050}
1051
1052/**
1053 * omap_iommu_runtime_resume - enable an iommu device
1054 * @dev:        iommu device
1055 *
1056 * This function performs all that is necessary to enable an
1057 * IOMMU device, either during initial attachment to a client
1058 * device, or during system/runtime resume of the device. This
1059 * includes programming all the appropriate IOMMU registers, and
1060 * managing the associated omap_hwmod's state and the device's
1061 * reset line. The function also restores any locked TLBs if
1062 * resuming after a suspend.
1063 **/
1064static __maybe_unused int omap_iommu_runtime_resume(struct device *dev)
1065{
1066        struct platform_device *pdev = to_platform_device(dev);
1067        struct iommu_platform_data *pdata = dev_get_platdata(dev);
1068        struct omap_iommu *obj = to_iommu(dev);
1069        int ret = 0;
1070
1071        if (pdata && pdata->set_pwrdm_constraint) {
1072                ret = pdata->set_pwrdm_constraint(pdev, true, &obj->pwrst);
1073                if (ret) {
1074                        dev_warn(obj->dev, "pwrdm_constraint failed to be set, status = %d\n",
1075                                 ret);
1076                }
1077        }
1078
1079        if (pdata && pdata->deassert_reset) {
1080                ret = pdata->deassert_reset(pdev, pdata->reset_name);
1081                if (ret) {
1082                        dev_err(dev, "deassert_reset failed: %d\n", ret);
1083                        return ret;
1084                }
1085        }
1086
1087        if (pdata && pdata->device_enable)
1088                pdata->device_enable(pdev);
1089
1090        /* restore the TLBs only during resume, and not for power up */
1091        if (obj->domain)
1092                omap_iommu_restore_tlb_entries(obj);
1093
1094        ret = omap2_iommu_enable(obj);
1095
1096        return ret;
1097}
1098
1099/**
1100 * omap_iommu_suspend_prepare - prepare() dev_pm_ops implementation
1101 * @dev:        iommu device
1102 *
1103 * This function performs the necessary checks to determine if the IOMMU
1104 * device needs suspending or not. The function checks if the runtime_pm
1105 * status of the device is suspended, and returns 1 in that case. This
1106 * results in the PM core to skip invoking any of the Sleep PM callbacks
1107 * (suspend, suspend_late, resume, resume_early etc).
1108 */
1109static int omap_iommu_prepare(struct device *dev)
1110{
1111        if (pm_runtime_status_suspended(dev))
1112                return 1;
1113        return 0;
1114}
1115
1116static bool omap_iommu_can_register(struct platform_device *pdev)
1117{
1118        struct device_node *np = pdev->dev.of_node;
1119
1120        if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
1121                return true;
1122
1123        /*
1124         * restrict IOMMU core registration only for processor-port MDMA MMUs
1125         * on DRA7 DSPs
1126         */
1127        if ((!strcmp(dev_name(&pdev->dev), "40d01000.mmu")) ||
1128            (!strcmp(dev_name(&pdev->dev), "41501000.mmu")))
1129                return true;
1130
1131        return false;
1132}
1133
1134static int omap_iommu_dra7_get_dsp_system_cfg(struct platform_device *pdev,
1135                                              struct omap_iommu *obj)
1136{
1137        struct device_node *np = pdev->dev.of_node;
1138        int ret;
1139
1140        if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
1141                return 0;
1142
1143        if (!of_property_read_bool(np, "ti,syscon-mmuconfig")) {
1144                dev_err(&pdev->dev, "ti,syscon-mmuconfig property is missing\n");
1145                return -EINVAL;
1146        }
1147
1148        obj->syscfg =
1149                syscon_regmap_lookup_by_phandle(np, "ti,syscon-mmuconfig");
1150        if (IS_ERR(obj->syscfg)) {
1151                /* can fail with -EPROBE_DEFER */
1152                ret = PTR_ERR(obj->syscfg);
1153                return ret;
1154        }
1155
1156        if (of_property_read_u32_index(np, "ti,syscon-mmuconfig", 1,
1157                                       &obj->id)) {
1158                dev_err(&pdev->dev, "couldn't get the IOMMU instance id within subsystem\n");
1159                return -EINVAL;
1160        }
1161
1162        if (obj->id != 0 && obj->id != 1) {
1163                dev_err(&pdev->dev, "invalid IOMMU instance id\n");
1164                return -EINVAL;
1165        }
1166
1167        return 0;
1168}
1169
1170/*
1171 *      OMAP Device MMU(IOMMU) detection
1172 */
1173static int omap_iommu_probe(struct platform_device *pdev)
1174{
1175        int err = -ENODEV;
1176        int irq;
1177        struct omap_iommu *obj;
1178        struct resource *res;
1179        struct device_node *of = pdev->dev.of_node;
1180        struct orphan_dev *orphan_dev, *tmp;
1181
1182        if (!of) {
1183                pr_err("%s: only DT-based devices are supported\n", __func__);
1184                return -ENODEV;
1185        }
1186
1187        obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
1188        if (!obj)
1189                return -ENOMEM;
1190
1191        /*
1192         * self-manage the ordering dependencies between omap_device_enable/idle
1193         * and omap_device_assert/deassert_hardreset API
1194         */
1195        if (pdev->dev.pm_domain) {
1196                dev_dbg(&pdev->dev, "device pm_domain is being reset\n");
1197                pdev->dev.pm_domain = NULL;
1198        }
1199
1200        obj->name = dev_name(&pdev->dev);
1201        obj->nr_tlb_entries = 32;
1202        err = of_property_read_u32(of, "ti,#tlb-entries", &obj->nr_tlb_entries);
1203        if (err && err != -EINVAL)
1204                return err;
1205        if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8)
1206                return -EINVAL;
1207        if (of_find_property(of, "ti,iommu-bus-err-back", NULL))
1208                obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN;
1209
1210        obj->dev = &pdev->dev;
1211        obj->ctx = (void *)obj + sizeof(*obj);
1212        obj->cr_ctx = devm_kzalloc(&pdev->dev,
1213                                   sizeof(*obj->cr_ctx) * obj->nr_tlb_entries,
1214                                   GFP_KERNEL);
1215        if (!obj->cr_ctx)
1216                return -ENOMEM;
1217
1218        spin_lock_init(&obj->iommu_lock);
1219        spin_lock_init(&obj->page_table_lock);
1220
1221        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1222        obj->regbase = devm_ioremap_resource(obj->dev, res);
1223        if (IS_ERR(obj->regbase))
1224                return PTR_ERR(obj->regbase);
1225
1226        err = omap_iommu_dra7_get_dsp_system_cfg(pdev, obj);
1227        if (err)
1228                return err;
1229
1230        irq = platform_get_irq(pdev, 0);
1231        if (irq < 0)
1232                return -ENODEV;
1233
1234        err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED,
1235                               dev_name(obj->dev), obj);
1236        if (err < 0)
1237                return err;
1238        platform_set_drvdata(pdev, obj);
1239
1240        if (omap_iommu_can_register(pdev)) {
1241                obj->group = iommu_group_alloc();
1242                if (IS_ERR(obj->group))
1243                        return PTR_ERR(obj->group);
1244
1245                err = iommu_device_sysfs_add(&obj->iommu, obj->dev, NULL,
1246                                             obj->name);
1247                if (err)
1248                        goto out_group;
1249
1250                iommu_device_set_ops(&obj->iommu, &omap_iommu_ops);
1251
1252                err = iommu_device_register(&obj->iommu);
1253                if (err)
1254                        goto out_sysfs;
1255        }
1256
1257        pm_runtime_enable(obj->dev);
1258
1259        omap_iommu_debugfs_add(obj);
1260
1261        dev_info(&pdev->dev, "%s registered\n", obj->name);
1262
1263        list_for_each_entry_safe(orphan_dev, tmp, &orphan_dev_list, node) {
1264                err = _omap_iommu_add_device(orphan_dev->dev);
1265                if (!err) {
1266                        list_del(&orphan_dev->node);
1267                        kfree(orphan_dev);
1268                }
1269        }
1270
1271        return 0;
1272
1273out_sysfs:
1274        iommu_device_sysfs_remove(&obj->iommu);
1275out_group:
1276        iommu_group_put(obj->group);
1277        return err;
1278}
1279
1280static int omap_iommu_remove(struct platform_device *pdev)
1281{
1282        struct omap_iommu *obj = platform_get_drvdata(pdev);
1283
1284        if (obj->group) {
1285                iommu_group_put(obj->group);
1286                obj->group = NULL;
1287
1288                iommu_device_sysfs_remove(&obj->iommu);
1289                iommu_device_unregister(&obj->iommu);
1290        }
1291
1292        omap_iommu_debugfs_remove(obj);
1293
1294        pm_runtime_disable(obj->dev);
1295
1296        dev_info(&pdev->dev, "%s removed\n", obj->name);
1297        return 0;
1298}
1299
1300static const struct dev_pm_ops omap_iommu_pm_ops = {
1301        .prepare = omap_iommu_prepare,
1302        SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1303                                     pm_runtime_force_resume)
1304        SET_RUNTIME_PM_OPS(omap_iommu_runtime_suspend,
1305                           omap_iommu_runtime_resume, NULL)
1306};
1307
1308static const struct of_device_id omap_iommu_of_match[] = {
1309        { .compatible = "ti,omap2-iommu" },
1310        { .compatible = "ti,omap4-iommu" },
1311        { .compatible = "ti,dra7-iommu" },
1312        { .compatible = "ti,dra7-dsp-iommu" },
1313        {},
1314};
1315
1316static struct platform_driver omap_iommu_driver = {
1317        .probe  = omap_iommu_probe,
1318        .remove = omap_iommu_remove,
1319        .driver = {
1320                .name   = "omap-iommu",
1321                .pm     = &omap_iommu_pm_ops,
1322                .of_match_table = of_match_ptr(omap_iommu_of_match),
1323        },
1324};
1325
1326static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz)
1327{
1328        memset(e, 0, sizeof(*e));
1329
1330        e->da           = da;
1331        e->pa           = pa;
1332        e->valid        = MMU_CAM_V;
1333        e->pgsz         = pgsz;
1334        e->endian       = MMU_RAM_ENDIAN_LITTLE;
1335        e->elsz         = MMU_RAM_ELSZ_8;
1336        e->mixed        = 0;
1337
1338        return iopgsz_to_bytes(e->pgsz);
1339}
1340
1341static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1342                          phys_addr_t pa, size_t bytes, int prot)
1343{
1344        struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1345        struct device *dev = omap_domain->dev;
1346        struct omap_iommu_device *iommu;
1347        struct omap_iommu *oiommu;
1348        struct iotlb_entry e;
1349        int omap_pgsz;
1350        u32 ret = -EINVAL;
1351        int i;
1352
1353        omap_pgsz = bytes_to_iopgsz(bytes);
1354        if (omap_pgsz < 0) {
1355                dev_err(dev, "invalid size to map: %d\n", bytes);
1356                return -EINVAL;
1357        }
1358
1359        dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes);
1360
1361        iotlb_init_entry(&e, da, pa, omap_pgsz);
1362
1363        iommu = omap_domain->iommus;
1364        for (i = 0; i < omap_domain->num_iommus; i++, iommu++) {
1365                oiommu = iommu->iommu_dev;
1366                ret = omap_iopgtable_store_entry(oiommu, &e);
1367                if (ret) {
1368                        dev_err(dev, "omap_iopgtable_store_entry failed: %d\n",
1369                                ret);
1370                        break;
1371                }
1372        }
1373
1374        if (ret) {
1375                while (i--) {
1376                        iommu--;
1377                        oiommu = iommu->iommu_dev;
1378                        iopgtable_clear_entry(oiommu, da);
1379                }
1380        }
1381
1382        return ret;
1383}
1384
1385static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1386                               size_t size, struct iommu_iotlb_gather *gather)
1387{
1388        struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1389        struct device *dev = omap_domain->dev;
1390        struct omap_iommu_device *iommu;
1391        struct omap_iommu *oiommu;
1392        bool error = false;
1393        size_t bytes = 0;
1394        int i;
1395
1396        dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
1397
1398        iommu = omap_domain->iommus;
1399        for (i = 0; i < omap_domain->num_iommus; i++, iommu++) {
1400                oiommu = iommu->iommu_dev;
1401                bytes = iopgtable_clear_entry(oiommu, da);
1402                if (!bytes)
1403                        error = true;
1404        }
1405
1406        /*
1407         * simplify return - we are only checking if any of the iommus
1408         * reported an error, but not if all of them are unmapping the
1409         * same number of entries. This should not occur due to the
1410         * mirror programming.
1411         */
1412        return error ? 0 : bytes;
1413}
1414
1415static int omap_iommu_count(struct device *dev)
1416{
1417        struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1418        int count = 0;
1419
1420        while (arch_data->iommu_dev) {
1421                count++;
1422                arch_data++;
1423        }
1424
1425        return count;
1426}
1427
1428/* caller should call cleanup if this function fails */
1429static int omap_iommu_attach_init(struct device *dev,
1430                                  struct omap_iommu_domain *odomain)
1431{
1432        struct omap_iommu_device *iommu;
1433        int i;
1434
1435        odomain->num_iommus = omap_iommu_count(dev);
1436        if (!odomain->num_iommus)
1437                return -EINVAL;
1438
1439        odomain->iommus = kcalloc(odomain->num_iommus, sizeof(*iommu),
1440                                  GFP_ATOMIC);
1441        if (!odomain->iommus)
1442                return -ENOMEM;
1443
1444        iommu = odomain->iommus;
1445        for (i = 0; i < odomain->num_iommus; i++, iommu++) {
1446                iommu->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_ATOMIC);
1447                if (!iommu->pgtable)
1448                        return -ENOMEM;
1449
1450                /*
1451                 * should never fail, but please keep this around to ensure
1452                 * we keep the hardware happy
1453                 */
1454                if (WARN_ON(!IS_ALIGNED((long)iommu->pgtable,
1455                                        IOPGD_TABLE_SIZE)))
1456                        return -EINVAL;
1457        }
1458
1459        return 0;
1460}
1461
1462static void omap_iommu_detach_fini(struct omap_iommu_domain *odomain)
1463{
1464        int i;
1465        struct omap_iommu_device *iommu = odomain->iommus;
1466
1467        for (i = 0; iommu && i < odomain->num_iommus; i++, iommu++)
1468                kfree(iommu->pgtable);
1469
1470        kfree(odomain->iommus);
1471        odomain->num_iommus = 0;
1472        odomain->iommus = NULL;
1473}
1474
1475static int
1476omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1477{
1478        struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1479        struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1480        struct omap_iommu_device *iommu;
1481        struct omap_iommu *oiommu;
1482        int ret = 0;
1483        int i;
1484
1485        if (!arch_data || !arch_data->iommu_dev) {
1486                dev_err(dev, "device doesn't have an associated iommu\n");
1487                return -EINVAL;
1488        }
1489
1490        spin_lock(&omap_domain->lock);
1491
1492        /* only a single client device can be attached to a domain */
1493        if (omap_domain->dev) {
1494                dev_err(dev, "iommu domain is already attached\n");
1495                ret = -EBUSY;
1496                goto out;
1497        }
1498
1499        ret = omap_iommu_attach_init(dev, omap_domain);
1500        if (ret) {
1501                dev_err(dev, "failed to allocate required iommu data %d\n",
1502                        ret);
1503                goto init_fail;
1504        }
1505
1506        iommu = omap_domain->iommus;
1507        for (i = 0; i < omap_domain->num_iommus; i++, iommu++, arch_data++) {
1508                /* configure and enable the omap iommu */
1509                oiommu = arch_data->iommu_dev;
1510                ret = omap_iommu_attach(oiommu, iommu->pgtable);
1511                if (ret) {
1512                        dev_err(dev, "can't get omap iommu: %d\n", ret);
1513                        goto attach_fail;
1514                }
1515
1516                oiommu->domain = domain;
1517                iommu->iommu_dev = oiommu;
1518        }
1519
1520        omap_domain->dev = dev;
1521
1522        goto out;
1523
1524attach_fail:
1525        while (i--) {
1526                iommu--;
1527                arch_data--;
1528                oiommu = iommu->iommu_dev;
1529                omap_iommu_detach(oiommu);
1530                iommu->iommu_dev = NULL;
1531                oiommu->domain = NULL;
1532        }
1533init_fail:
1534        omap_iommu_detach_fini(omap_domain);
1535out:
1536        spin_unlock(&omap_domain->lock);
1537        return ret;
1538}
1539
1540static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
1541                                   struct device *dev)
1542{
1543        struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1544        struct omap_iommu_device *iommu = omap_domain->iommus;
1545        struct omap_iommu *oiommu;
1546        int i;
1547
1548        if (!omap_domain->dev) {
1549                dev_err(dev, "domain has no attached device\n");
1550                return;
1551        }
1552
1553        /* only a single device is supported per domain for now */
1554        if (omap_domain->dev != dev) {
1555                dev_err(dev, "invalid attached device\n");
1556                return;
1557        }
1558
1559        /*
1560         * cleanup in the reverse order of attachment - this addresses
1561         * any h/w dependencies between multiple instances, if any
1562         */
1563        iommu += (omap_domain->num_iommus - 1);
1564        arch_data += (omap_domain->num_iommus - 1);
1565        for (i = 0; i < omap_domain->num_iommus; i++, iommu--, arch_data--) {
1566                oiommu = iommu->iommu_dev;
1567                iopgtable_clear_entry_all(oiommu);
1568
1569                omap_iommu_detach(oiommu);
1570                iommu->iommu_dev = NULL;
1571                oiommu->domain = NULL;
1572        }
1573
1574        omap_iommu_detach_fini(omap_domain);
1575
1576        omap_domain->dev = NULL;
1577}
1578
1579static void omap_iommu_detach_dev(struct iommu_domain *domain,
1580                                  struct device *dev)
1581{
1582        struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1583
1584        spin_lock(&omap_domain->lock);
1585        _omap_iommu_detach_dev(omap_domain, dev);
1586        spin_unlock(&omap_domain->lock);
1587}
1588
1589static struct iommu_domain *omap_iommu_domain_alloc(unsigned type)
1590{
1591        struct omap_iommu_domain *omap_domain;
1592
1593        if (type != IOMMU_DOMAIN_UNMANAGED)
1594                return NULL;
1595
1596        omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1597        if (!omap_domain)
1598                return NULL;
1599
1600        spin_lock_init(&omap_domain->lock);
1601
1602        omap_domain->domain.geometry.aperture_start = 0;
1603        omap_domain->domain.geometry.aperture_end   = (1ULL << 32) - 1;
1604        omap_domain->domain.geometry.force_aperture = true;
1605
1606        return &omap_domain->domain;
1607}
1608
1609static void omap_iommu_domain_free(struct iommu_domain *domain)
1610{
1611        struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1612
1613        /*
1614         * An iommu device is still attached
1615         * (currently, only one device can be attached) ?
1616         */
1617        if (omap_domain->dev)
1618                _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1619
1620        kfree(omap_domain);
1621}
1622
1623static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1624                                           dma_addr_t da)
1625{
1626        struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1627        struct omap_iommu_device *iommu = omap_domain->iommus;
1628        struct omap_iommu *oiommu = iommu->iommu_dev;
1629        struct device *dev = oiommu->dev;
1630        u32 *pgd, *pte;
1631        phys_addr_t ret = 0;
1632
1633        /*
1634         * all the iommus within the domain will have identical programming,
1635         * so perform the lookup using just the first iommu
1636         */
1637        iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1638
1639        if (pte) {
1640                if (iopte_is_small(*pte))
1641                        ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1642                else if (iopte_is_large(*pte))
1643                        ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1644                else
1645                        dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte,
1646                                (unsigned long long)da);
1647        } else {
1648                if (iopgd_is_section(*pgd))
1649                        ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1650                else if (iopgd_is_super(*pgd))
1651                        ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1652                else
1653                        dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd,
1654                                (unsigned long long)da);
1655        }
1656
1657        return ret;
1658}
1659
1660static int _omap_iommu_add_device(struct device *dev)
1661{
1662        struct omap_iommu_arch_data *arch_data, *tmp;
1663        struct omap_iommu *oiommu;
1664        struct iommu_group *group;
1665        struct device_node *np;
1666        struct platform_device *pdev;
1667        int num_iommus, i;
1668        int ret;
1669        struct orphan_dev *orphan_dev;
1670        unsigned long flags;
1671
1672        /*
1673         * Allocate the archdata iommu structure for DT-based devices.
1674         *
1675         * TODO: Simplify this when removing non-DT support completely from the
1676         * IOMMU users.
1677         */
1678        if (!dev->of_node)
1679                return 0;
1680
1681        /*
1682         * retrieve the count of IOMMU nodes using phandle size as element size
1683         * since #iommu-cells = 0 for OMAP
1684         */
1685        num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus",
1686                                                     sizeof(phandle));
1687        if (num_iommus < 0)
1688                return 0;
1689
1690        arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL);
1691        if (!arch_data)
1692                return -ENOMEM;
1693
1694        for (i = 0, tmp = arch_data; i < num_iommus; i++, tmp++) {
1695                np = of_parse_phandle(dev->of_node, "iommus", i);
1696                if (!np) {
1697                        kfree(arch_data);
1698                        return -EINVAL;
1699                }
1700
1701                pdev = of_find_device_by_node(np);
1702                if (!pdev) {
1703                        of_node_put(np);
1704                        kfree(arch_data);
1705                        spin_lock_irqsave(&orphan_lock, flags);
1706                        list_for_each_entry(orphan_dev, &orphan_dev_list,
1707                                            node) {
1708                                if (orphan_dev->dev == dev)
1709                                        break;
1710                        }
1711                        spin_unlock_irqrestore(&orphan_lock, flags);
1712
1713                        if (orphan_dev && orphan_dev->dev == dev)
1714                                return -EPROBE_DEFER;
1715
1716                        orphan_dev = kzalloc(sizeof(*orphan_dev), GFP_KERNEL);
1717                        orphan_dev->dev = dev;
1718                        spin_lock_irqsave(&orphan_lock, flags);
1719                        list_add(&orphan_dev->node, &orphan_dev_list);
1720                        spin_unlock_irqrestore(&orphan_lock, flags);
1721                        return -EPROBE_DEFER;
1722                }
1723
1724                oiommu = platform_get_drvdata(pdev);
1725                if (!oiommu) {
1726                        of_node_put(np);
1727                        kfree(arch_data);
1728                        return -EINVAL;
1729                }
1730
1731                tmp->iommu_dev = oiommu;
1732                tmp->dev = &pdev->dev;
1733
1734                of_node_put(np);
1735        }
1736
1737        /*
1738         * use the first IOMMU alone for the sysfs device linking.
1739         * TODO: Evaluate if a single iommu_group needs to be
1740         * maintained for both IOMMUs
1741         */
1742        oiommu = arch_data->iommu_dev;
1743        ret = iommu_device_link(&oiommu->iommu, dev);
1744        if (ret) {
1745                kfree(arch_data);
1746                return ret;
1747        }
1748
1749        dev->archdata.iommu = arch_data;
1750
1751        /*
1752         * IOMMU group initialization calls into omap_iommu_device_group, which
1753         * needs a valid dev->archdata.iommu pointer
1754         */
1755        group = iommu_group_get_for_dev(dev);
1756        if (IS_ERR(group)) {
1757                iommu_device_unlink(&oiommu->iommu, dev);
1758                dev->archdata.iommu = NULL;
1759                kfree(arch_data);
1760                return PTR_ERR(group);
1761        }
1762        iommu_group_put(group);
1763
1764        return 0;
1765}
1766
1767static int omap_iommu_add_device(struct device *dev)
1768{
1769        int ret;
1770
1771        ret = _omap_iommu_add_device(dev);
1772        if (ret == -EPROBE_DEFER)
1773                return 0;
1774
1775        return ret;
1776}
1777
1778static void omap_iommu_remove_device(struct device *dev)
1779{
1780        struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1781
1782        if (!dev->of_node || !arch_data)
1783                return;
1784
1785        iommu_device_unlink(&arch_data->iommu_dev->iommu, dev);
1786        iommu_group_remove_device(dev);
1787
1788        dev->archdata.iommu = NULL;
1789        kfree(arch_data);
1790
1791}
1792
1793static struct iommu_group *omap_iommu_device_group(struct device *dev)
1794{
1795        struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1796        struct iommu_group *group = ERR_PTR(-EINVAL);
1797
1798        if (arch_data->iommu_dev)
1799                group = iommu_group_ref_get(arch_data->iommu_dev->group);
1800
1801        return group;
1802}
1803
1804static const struct iommu_ops omap_iommu_ops = {
1805        .domain_alloc   = omap_iommu_domain_alloc,
1806        .domain_free    = omap_iommu_domain_free,
1807        .attach_dev     = omap_iommu_attach_dev,
1808        .detach_dev     = omap_iommu_detach_dev,
1809        .map            = omap_iommu_map,
1810        .unmap          = omap_iommu_unmap,
1811        .iova_to_phys   = omap_iommu_iova_to_phys,
1812        .add_device     = omap_iommu_add_device,
1813        .remove_device  = omap_iommu_remove_device,
1814        .device_group   = omap_iommu_device_group,
1815        .pgsize_bitmap  = OMAP_IOMMU_PGSIZES,
1816};
1817
1818static int __init omap_iommu_init(void)
1819{
1820        struct kmem_cache *p;
1821        const slab_flags_t flags = SLAB_HWCACHE_ALIGN;
1822        size_t align = 1 << 10; /* L2 pagetable alignement */
1823        struct device_node *np;
1824        int ret;
1825
1826        np = of_find_matching_node(NULL, omap_iommu_of_match);
1827        if (!np)
1828                return 0;
1829
1830        of_node_put(np);
1831
1832        p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1833                              NULL);
1834        if (!p)
1835                return -ENOMEM;
1836        iopte_cachep = p;
1837
1838        omap_iommu_debugfs_init();
1839
1840        ret = platform_driver_register(&omap_iommu_driver);
1841        if (ret) {
1842                pr_err("%s: failed to register driver\n", __func__);
1843                goto fail_driver;
1844        }
1845
1846        ret = bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1847        if (ret)
1848                goto fail_bus;
1849
1850        return 0;
1851
1852fail_bus:
1853        platform_driver_unregister(&omap_iommu_driver);
1854fail_driver:
1855        kmem_cache_destroy(iopte_cachep);
1856        return ret;
1857}
1858subsys_initcall(omap_iommu_init);
1859/* must be ready before omap3isp is probed */
1860