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35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include "t4_hw.h"
39
40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
48#include <linux/vmalloc.h>
49#include <linux/rhashtable.h>
50#include <linux/etherdevice.h>
51#include <linux/net_tstamp.h>
52#include <linux/ptp_clock_kernel.h>
53#include <linux/ptp_classify.h>
54#include <linux/crash_dump.h>
55#include <linux/thermal.h>
56#include <asm/io.h>
57#include "t4_chip_type.h"
58#include "cxgb4_uld.h"
59
60#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
61extern struct list_head adapter_list;
62extern struct mutex uld_mutex;
63
64
65
66
67
68#define ETHTXQ_STOP_THRES \
69 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
70
71enum {
72 MAX_NPORTS = 4,
73 SERNUM_LEN = 24,
74 EC_LEN = 16,
75 ID_LEN = 16,
76 PN_LEN = 16,
77 MACADDR_LEN = 12,
78};
79
80enum {
81 T4_REGMAP_SIZE = (160 * 1024),
82 T5_REGMAP_SIZE = (332 * 1024),
83};
84
85enum {
86 MEM_EDC0,
87 MEM_EDC1,
88 MEM_MC,
89 MEM_MC0 = MEM_MC,
90 MEM_MC1,
91 MEM_HMA,
92};
93
94enum {
95 MEMWIN0_APERTURE = 2048,
96 MEMWIN0_BASE = 0x1b800,
97 MEMWIN1_APERTURE = 32768,
98 MEMWIN1_BASE = 0x28000,
99 MEMWIN1_BASE_T5 = 0x52000,
100 MEMWIN2_APERTURE = 65536,
101 MEMWIN2_BASE = 0x30000,
102 MEMWIN2_APERTURE_T5 = 131072,
103 MEMWIN2_BASE_T5 = 0x60000,
104};
105
106enum dev_master {
107 MASTER_CANT,
108 MASTER_MAY,
109 MASTER_MUST
110};
111
112enum dev_state {
113 DEV_STATE_UNINIT,
114 DEV_STATE_INIT,
115 DEV_STATE_ERR
116};
117
118enum cc_pause {
119 PAUSE_RX = 1 << 0,
120 PAUSE_TX = 1 << 1,
121 PAUSE_AUTONEG = 1 << 2
122};
123
124enum cc_fec {
125 FEC_AUTO = 1 << 0,
126 FEC_RS = 1 << 1,
127 FEC_BASER_RS = 1 << 2
128};
129
130struct port_stats {
131 u64 tx_octets;
132 u64 tx_frames;
133 u64 tx_bcast_frames;
134 u64 tx_mcast_frames;
135 u64 tx_ucast_frames;
136 u64 tx_error_frames;
137
138 u64 tx_frames_64;
139 u64 tx_frames_65_127;
140 u64 tx_frames_128_255;
141 u64 tx_frames_256_511;
142 u64 tx_frames_512_1023;
143 u64 tx_frames_1024_1518;
144 u64 tx_frames_1519_max;
145
146 u64 tx_drop;
147 u64 tx_pause;
148 u64 tx_ppp0;
149 u64 tx_ppp1;
150 u64 tx_ppp2;
151 u64 tx_ppp3;
152 u64 tx_ppp4;
153 u64 tx_ppp5;
154 u64 tx_ppp6;
155 u64 tx_ppp7;
156
157 u64 rx_octets;
158 u64 rx_frames;
159 u64 rx_bcast_frames;
160 u64 rx_mcast_frames;
161 u64 rx_ucast_frames;
162 u64 rx_too_long;
163 u64 rx_jabber;
164 u64 rx_fcs_err;
165 u64 rx_len_err;
166 u64 rx_symbol_err;
167 u64 rx_runt;
168
169 u64 rx_frames_64;
170 u64 rx_frames_65_127;
171 u64 rx_frames_128_255;
172 u64 rx_frames_256_511;
173 u64 rx_frames_512_1023;
174 u64 rx_frames_1024_1518;
175 u64 rx_frames_1519_max;
176
177 u64 rx_pause;
178 u64 rx_ppp0;
179 u64 rx_ppp1;
180 u64 rx_ppp2;
181 u64 rx_ppp3;
182 u64 rx_ppp4;
183 u64 rx_ppp5;
184 u64 rx_ppp6;
185 u64 rx_ppp7;
186
187 u64 rx_ovflow0;
188 u64 rx_ovflow1;
189 u64 rx_ovflow2;
190 u64 rx_ovflow3;
191 u64 rx_trunc0;
192 u64 rx_trunc1;
193 u64 rx_trunc2;
194 u64 rx_trunc3;
195};
196
197struct lb_port_stats {
198 u64 octets;
199 u64 frames;
200 u64 bcast_frames;
201 u64 mcast_frames;
202 u64 ucast_frames;
203 u64 error_frames;
204
205 u64 frames_64;
206 u64 frames_65_127;
207 u64 frames_128_255;
208 u64 frames_256_511;
209 u64 frames_512_1023;
210 u64 frames_1024_1518;
211 u64 frames_1519_max;
212
213 u64 drop;
214
215 u64 ovflow0;
216 u64 ovflow1;
217 u64 ovflow2;
218 u64 ovflow3;
219 u64 trunc0;
220 u64 trunc1;
221 u64 trunc2;
222 u64 trunc3;
223};
224
225struct tp_tcp_stats {
226 u32 tcp_out_rsts;
227 u64 tcp_in_segs;
228 u64 tcp_out_segs;
229 u64 tcp_retrans_segs;
230};
231
232struct tp_usm_stats {
233 u32 frames;
234 u32 drops;
235 u64 octets;
236};
237
238struct tp_fcoe_stats {
239 u32 frames_ddp;
240 u32 frames_drop;
241 u64 octets_ddp;
242};
243
244struct tp_err_stats {
245 u32 mac_in_errs[4];
246 u32 hdr_in_errs[4];
247 u32 tcp_in_errs[4];
248 u32 tnl_cong_drops[4];
249 u32 ofld_chan_drops[4];
250 u32 tnl_tx_drops[4];
251 u32 ofld_vlan_drops[4];
252 u32 tcp6_in_errs[4];
253 u32 ofld_no_neigh;
254 u32 ofld_cong_defer;
255};
256
257struct tp_cpl_stats {
258 u32 req[4];
259 u32 rsp[4];
260};
261
262struct tp_rdma_stats {
263 u32 rqe_dfr_pkt;
264 u32 rqe_dfr_mod;
265};
266
267struct sge_params {
268 u32 hps;
269 u32 eq_qpp;
270 u32 iq_qpp;
271};
272
273struct tp_params {
274 unsigned int tre;
275 unsigned int la_mask;
276 unsigned short tx_modq_map;
277
278
279 uint32_t dack_re;
280 unsigned short tx_modq[NCHAN];
281
282 u32 vlan_pri_map;
283 u32 filter_mask;
284 u32 ingress_config;
285
286
287
288
289 int rx_pkt_encap;
290
291
292
293
294
295
296
297
298
299
300
301
302 int fcoe_shift;
303 int port_shift;
304 int vnic_shift;
305 int vlan_shift;
306 int tos_shift;
307 int protocol_shift;
308 int ethertype_shift;
309 int macmatch_shift;
310 int matchtype_shift;
311 int frag_shift;
312
313 u64 hash_filter_mask;
314};
315
316struct vpd_params {
317 unsigned int cclk;
318 u8 ec[EC_LEN + 1];
319 u8 sn[SERNUM_LEN + 1];
320 u8 id[ID_LEN + 1];
321 u8 pn[PN_LEN + 1];
322 u8 na[MACADDR_LEN + 1];
323};
324
325
326
327struct pf_resources {
328 unsigned int nvi;
329 unsigned int neq;
330 unsigned int nethctrl;
331 unsigned int niqflint;
332 unsigned int niq;
333 unsigned int tc;
334 unsigned int pmask;
335 unsigned int nexactf;
336 unsigned int r_caps;
337 unsigned int wx_caps;
338};
339
340struct pci_params {
341 unsigned int vpd_cap_addr;
342 unsigned char speed;
343 unsigned char width;
344};
345
346struct devlog_params {
347 u32 memtype;
348 u32 start;
349 u32 size;
350};
351
352
353struct arch_specific_params {
354 u8 nchan;
355 u8 pm_stats_cnt;
356 u8 cng_ch_bits_log;
357 u16 mps_rplc_size;
358 u16 vfcount;
359 u32 sge_fl_db;
360 u16 mps_tcam_size;
361};
362
363struct adapter_params {
364 struct sge_params sge;
365 struct tp_params tp;
366 struct vpd_params vpd;
367 struct pf_resources pfres;
368 struct pci_params pci;
369 struct devlog_params devlog;
370 enum pcie_memwin drv_memwin;
371
372 unsigned int cim_la_size;
373
374 unsigned int sf_size;
375 unsigned int sf_nsec;
376
377 unsigned int fw_vers;
378 unsigned int bs_vers;
379 unsigned int tp_vers;
380 unsigned int er_vers;
381 unsigned int scfg_vers;
382 unsigned int vpd_vers;
383 u8 api_vers[7];
384
385 unsigned short mtus[NMTUS];
386 unsigned short a_wnd[NCCTRL_WIN];
387 unsigned short b_wnd[NCCTRL_WIN];
388
389 unsigned char nports;
390 unsigned char portvec;
391 enum chip_type chip;
392 struct arch_specific_params arch;
393 unsigned char offload;
394 unsigned char crypto;
395
396 unsigned char bypass;
397 unsigned char hash_filter;
398
399 unsigned int ofldq_wr_cred;
400 bool ulptx_memwrite_dsgl;
401
402 unsigned int nsched_cls;
403 unsigned int max_ordird_qp;
404 unsigned int max_ird_adapter;
405 bool fr_nsmr_tpte_wr_support;
406 u8 fw_caps_support;
407 bool filter2_wr_support;
408 unsigned int viid_smt_extn_support:1;
409
410
411
412
413 u8 mps_bg_map[MAX_NPORTS];
414 bool write_w_imm_support;
415 bool write_cmpl_support;
416};
417
418
419
420
421struct sge_idma_monitor_state {
422 unsigned int idma_1s_thresh;
423 unsigned int idma_stalled[2];
424 unsigned int idma_state[2];
425 unsigned int idma_qid[2];
426 unsigned int idma_warn[2];
427};
428
429
430
431
432
433struct mbox_cmd {
434 u64 cmd[MBOX_LEN / 8];
435 u64 timestamp;
436 u32 seqno;
437 s16 access;
438 s16 execute;
439};
440
441struct mbox_cmd_log {
442 unsigned int size;
443 unsigned int cursor;
444 u32 seqno;
445
446};
447
448
449
450
451static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
452 unsigned int entry_idx)
453{
454 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
455}
456
457#include "t4fw_api.h"
458
459#define FW_VERSION(chip) ( \
460 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
461 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
462 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
463 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
464#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
465
466struct fw_info {
467 u8 chip;
468 char *fs_name;
469 char *fw_mod_name;
470 struct fw_hdr fw_hdr;
471};
472
473struct trace_params {
474 u32 data[TRACE_LEN / 4];
475 u32 mask[TRACE_LEN / 4];
476 unsigned short snap_len;
477 unsigned short min_len;
478 unsigned char skip_ofst;
479 unsigned char skip_len;
480 unsigned char invert;
481 unsigned char port;
482};
483
484
485
486typedef u16 fw_port_cap16_t;
487typedef u32 fw_port_cap32_t;
488
489enum fw_caps {
490 FW_CAPS_UNKNOWN = 0,
491 FW_CAPS16 = 1,
492 FW_CAPS32 = 2,
493};
494
495struct link_config {
496 fw_port_cap32_t pcaps;
497 fw_port_cap32_t def_acaps;
498 fw_port_cap32_t acaps;
499 fw_port_cap32_t lpacaps;
500
501 fw_port_cap32_t speed_caps;
502 unsigned int speed;
503
504 enum cc_pause requested_fc;
505 enum cc_pause fc;
506
507 enum cc_fec requested_fec;
508 enum cc_fec fec;
509
510 unsigned char autoneg;
511
512 unsigned char link_ok;
513 unsigned char link_down_rc;
514
515 bool new_module;
516 bool redo_l1cfg;
517};
518
519#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
520
521enum {
522 MAX_ETH_QSETS = 32,
523 MAX_OFLD_QSETS = 16,
524 MAX_CTRL_QUEUES = NCHAN,
525};
526
527enum {
528 MAX_TXQ_ENTRIES = 16384,
529 MAX_CTRL_TXQ_ENTRIES = 1024,
530 MAX_RSPQ_ENTRIES = 16384,
531 MAX_RX_BUFFERS = 16384,
532 MIN_TXQ_ENTRIES = 32,
533 MIN_CTRL_TXQ_ENTRIES = 32,
534 MIN_RSPQ_ENTRIES = 128,
535 MIN_FL_ENTRIES = 16
536};
537
538enum {
539 MAX_TXQ_DESC_SIZE = 64,
540 MAX_RXQ_DESC_SIZE = 128,
541 MAX_FL_DESC_SIZE = 8,
542 MAX_CTRL_TXQ_DESC_SIZE = 64,
543};
544
545enum {
546 INGQ_EXTRAS = 2,
547
548 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
549};
550
551enum {
552 PRIV_FLAG_PORT_TX_VM_BIT,
553};
554
555#define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
556
557#define PRIV_FLAGS_ADAP 0
558#define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
559
560struct adapter;
561struct sge_rspq;
562
563#include "cxgb4_dcb.h"
564
565#ifdef CONFIG_CHELSIO_T4_FCOE
566#include "cxgb4_fcoe.h"
567#endif
568
569struct port_info {
570 struct adapter *adapter;
571 u16 viid;
572 int xact_addr_filt;
573 u16 rss_size;
574 s8 mdio_addr;
575 enum fw_port_type port_type;
576 u8 mod_type;
577 u8 port_id;
578 u8 tx_chan;
579 u8 lport;
580 u8 nqsets;
581 u8 first_qset;
582 u8 rss_mode;
583 struct link_config link_cfg;
584 u16 *rss;
585 struct port_stats stats_base;
586#ifdef CONFIG_CHELSIO_T4_DCB
587 struct port_dcb_info dcb;
588#endif
589#ifdef CONFIG_CHELSIO_T4_FCOE
590 struct cxgb_fcoe fcoe;
591#endif
592 bool rxtstamp;
593 struct hwtstamp_config tstamp_config;
594 bool ptp_enable;
595 struct sched_table *sched_tbl;
596 u32 eth_flags;
597
598
599
600
601 u8 vin;
602 u8 vivld;
603 u8 smt_idx;
604 u8 rx_cchan;
605};
606
607struct dentry;
608struct work_struct;
609
610enum {
611 CXGB4_FULL_INIT_DONE = (1 << 0),
612 CXGB4_DEV_ENABLED = (1 << 1),
613 CXGB4_USING_MSI = (1 << 2),
614 CXGB4_USING_MSIX = (1 << 3),
615 CXGB4_FW_OK = (1 << 4),
616 CXGB4_RSS_TNLALLLOOKUP = (1 << 5),
617 CXGB4_USING_SOFT_PARAMS = (1 << 6),
618 CXGB4_MASTER_PF = (1 << 7),
619 CXGB4_FW_OFLD_CONN = (1 << 9),
620 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10),
621 CXGB4_SHUTTING_DOWN = (1 << 11),
622 CXGB4_SGE_DBQ_TIMER = (1 << 12),
623};
624
625enum {
626 ULP_CRYPTO_LOOKASIDE = 1 << 0,
627 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
628};
629
630struct rx_sw_desc;
631
632struct sge_fl {
633 unsigned int avail;
634 unsigned int pend_cred;
635 unsigned int cidx;
636 unsigned int pidx;
637 unsigned long alloc_failed;
638 unsigned long large_alloc_failed;
639 unsigned long mapping_err;
640 unsigned long low;
641 unsigned long starving;
642
643 unsigned int cntxt_id;
644 unsigned int size;
645 struct rx_sw_desc *sdesc;
646 __be64 *desc;
647 dma_addr_t addr;
648 void __iomem *bar2_addr;
649 unsigned int bar2_qid;
650};
651
652
653struct pkt_gl {
654 u64 sgetstamp;
655 struct page_frag frags[MAX_SKB_FRAGS];
656 void *va;
657 unsigned int nfrags;
658 unsigned int tot_len;
659};
660
661typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
662 const struct pkt_gl *gl);
663typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
664
665struct t4_lro_mgr {
666#define MAX_LRO_SESSIONS 64
667 u8 lro_session_cnt;
668 unsigned long lro_pkts;
669 unsigned long lro_merged;
670 struct sk_buff_head lroq;
671};
672
673struct sge_rspq {
674 struct napi_struct napi;
675 const __be64 *cur_desc;
676 unsigned int cidx;
677 u8 gen;
678 u8 intr_params;
679 u8 next_intr_params;
680 u8 adaptive_rx;
681 u8 pktcnt_idx;
682 u8 uld;
683 u8 idx;
684 int offset;
685 u16 cntxt_id;
686 u16 abs_id;
687 __be64 *desc;
688 dma_addr_t phys_addr;
689 void __iomem *bar2_addr;
690 unsigned int bar2_qid;
691 unsigned int iqe_len;
692 unsigned int size;
693 struct adapter *adap;
694 struct net_device *netdev;
695 rspq_handler_t handler;
696 rspq_flush_handler_t flush_handler;
697 struct t4_lro_mgr lro_mgr;
698};
699
700struct sge_eth_stats {
701 unsigned long pkts;
702 unsigned long lro_pkts;
703 unsigned long lro_merged;
704 unsigned long rx_cso;
705 unsigned long vlan_ex;
706 unsigned long rx_drops;
707 unsigned long bad_rx_pkts;
708};
709
710struct sge_eth_rxq {
711 struct sge_rspq rspq;
712 struct sge_fl fl;
713 struct sge_eth_stats stats;
714} ____cacheline_aligned_in_smp;
715
716struct sge_ofld_stats {
717 unsigned long pkts;
718 unsigned long imm;
719 unsigned long an;
720 unsigned long nomem;
721};
722
723struct sge_ofld_rxq {
724 struct sge_rspq rspq;
725 struct sge_fl fl;
726 struct sge_ofld_stats stats;
727} ____cacheline_aligned_in_smp;
728
729struct tx_desc {
730 __be64 flit[8];
731};
732
733struct tx_sw_desc;
734
735struct sge_txq {
736 unsigned int in_use;
737 unsigned int q_type;
738 unsigned int size;
739 unsigned int cidx;
740 unsigned int pidx;
741 unsigned long stops;
742 unsigned long restarts;
743 unsigned int cntxt_id;
744 struct tx_desc *desc;
745 struct tx_sw_desc *sdesc;
746 struct sge_qstat *stat;
747 dma_addr_t phys_addr;
748 spinlock_t db_lock;
749 int db_disabled;
750 unsigned short db_pidx;
751 unsigned short db_pidx_inc;
752 void __iomem *bar2_addr;
753 unsigned int bar2_qid;
754};
755
756struct sge_eth_txq {
757 struct sge_txq q;
758 struct netdev_queue *txq;
759#ifdef CONFIG_CHELSIO_T4_DCB
760 u8 dcb_prio;
761#endif
762 u8 dbqt;
763 unsigned int dbqtimerix;
764 unsigned long tso;
765 unsigned long tx_cso;
766 unsigned long vlan_ins;
767 unsigned long mapping_err;
768} ____cacheline_aligned_in_smp;
769
770struct sge_uld_txq {
771 struct sge_txq q;
772 struct adapter *adap;
773 struct sk_buff_head sendq;
774 struct tasklet_struct qresume_tsk;
775 bool service_ofldq_running;
776 u8 full;
777 unsigned long mapping_err;
778} ____cacheline_aligned_in_smp;
779
780struct sge_ctrl_txq {
781 struct sge_txq q;
782 struct adapter *adap;
783 struct sk_buff_head sendq;
784 struct tasklet_struct qresume_tsk;
785 u8 full;
786} ____cacheline_aligned_in_smp;
787
788struct sge_uld_rxq_info {
789 char name[IFNAMSIZ];
790 struct sge_ofld_rxq *uldrxq;
791 u16 *msix_tbl;
792 u16 *rspq_id;
793 u16 nrxq;
794 u16 nciq;
795 u8 uld;
796};
797
798struct sge_uld_txq_info {
799 struct sge_uld_txq *uldtxq;
800 atomic_t users;
801 u16 ntxq;
802};
803
804struct sge {
805 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
806 struct sge_eth_txq ptptxq;
807 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
808
809 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
810 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
811 struct sge_uld_rxq_info **uld_rxq_info;
812 struct sge_uld_txq_info **uld_txq_info;
813
814 struct sge_rspq intrq ____cacheline_aligned_in_smp;
815 spinlock_t intrq_lock;
816
817 u16 max_ethqsets;
818 u16 ethqsets;
819 u16 ethtxq_rover;
820 u16 ofldqsets;
821 u16 nqs_per_uld;
822 u16 timer_val[SGE_NTIMERS];
823 u8 counter_val[SGE_NCOUNTERS];
824 u16 dbqtimer_tick;
825 u16 dbqtimer_val[SGE_NDBQTIMERS];
826 u32 fl_pg_order;
827 u32 stat_len;
828 u32 pktshift;
829 u32 fl_align;
830 u32 fl_starve_thres;
831
832 struct sge_idma_monitor_state idma_monitor;
833 unsigned int egr_start;
834 unsigned int egr_sz;
835 unsigned int ingr_start;
836 unsigned int ingr_sz;
837 void **egr_map;
838 struct sge_rspq **ingr_map;
839 unsigned long *starving_fl;
840 unsigned long *txq_maperr;
841 unsigned long *blocked_fl;
842 struct timer_list rx_timer;
843 struct timer_list tx_timer;
844};
845
846#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
847#define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
848
849struct l2t_data;
850
851#ifdef CONFIG_PCI_IOV
852
853
854
855
856
857#define NUM_OF_PF_WITH_SRIOV 4
858
859#endif
860
861struct doorbell_stats {
862 u32 db_drop;
863 u32 db_empty;
864 u32 db_full;
865};
866
867struct hash_mac_addr {
868 struct list_head list;
869 u8 addr[ETH_ALEN];
870 unsigned int iface_mac;
871};
872
873struct uld_msix_bmap {
874 unsigned long *msix_bmap;
875 unsigned int mapsize;
876 spinlock_t lock;
877};
878
879struct uld_msix_info {
880 unsigned short vec;
881 char desc[IFNAMSIZ + 10];
882 unsigned int idx;
883 cpumask_var_t aff_mask;
884};
885
886struct vf_info {
887 unsigned char vf_mac_addr[ETH_ALEN];
888 unsigned int tx_rate;
889 bool pf_set_mac;
890 u16 vlan;
891 int link_state;
892};
893
894enum {
895 HMA_DMA_MAPPED_FLAG = 1
896};
897
898struct hma_data {
899 unsigned char flags;
900 struct sg_table *sgt;
901 dma_addr_t *phy_addr;
902};
903
904struct mbox_list {
905 struct list_head list;
906};
907
908#if IS_ENABLED(CONFIG_THERMAL)
909struct ch_thermal {
910 struct thermal_zone_device *tzdev;
911 int trip_temp;
912 int trip_type;
913};
914#endif
915
916struct mps_entries_ref {
917 struct list_head list;
918 u8 addr[ETH_ALEN];
919 u8 mask[ETH_ALEN];
920 u16 idx;
921 refcount_t refcnt;
922};
923
924struct adapter {
925 void __iomem *regs;
926 void __iomem *bar2;
927 u32 t4_bar0;
928 struct pci_dev *pdev;
929 struct device *pdev_dev;
930 const char *name;
931 unsigned int mbox;
932 unsigned int pf;
933 unsigned int flags;
934 unsigned int adap_idx;
935 enum chip_type chip;
936 u32 eth_flags;
937
938 int msg_enable;
939 __be16 vxlan_port;
940 u8 vxlan_port_cnt;
941 __be16 geneve_port;
942 u8 geneve_port_cnt;
943
944 struct adapter_params params;
945 struct cxgb4_virt_res vres;
946 unsigned int swintr;
947
948 struct msix_info {
949 unsigned short vec;
950 char desc[IFNAMSIZ + 10];
951 cpumask_var_t aff_mask;
952 } msix_info[MAX_INGQ + 1];
953 struct uld_msix_info *msix_info_ulds;
954 struct uld_msix_bmap msix_bmap_ulds;
955 int msi_idx;
956
957 struct doorbell_stats db_stats;
958 struct sge sge;
959
960 struct net_device *port[MAX_NPORTS];
961 u8 chan_map[NCHAN];
962
963 struct vf_info *vfinfo;
964 u8 num_vfs;
965
966 u32 filter_mode;
967 unsigned int l2t_start;
968 unsigned int l2t_end;
969 struct l2t_data *l2t;
970 unsigned int clipt_start;
971 unsigned int clipt_end;
972 struct clip_tbl *clipt;
973 unsigned int rawf_start;
974 unsigned int rawf_cnt;
975 struct smt_data *smt;
976 struct cxgb4_uld_info *uld;
977 void *uld_handle[CXGB4_ULD_MAX];
978 unsigned int num_uld;
979 unsigned int num_ofld_uld;
980 struct list_head list_node;
981 struct list_head rcu_node;
982 struct list_head mac_hlist;
983 struct list_head mps_ref;
984 spinlock_t mps_ref_lock;
985
986 void *iscsi_ppm;
987
988 struct tid_info tids;
989 void **tid_release_head;
990 spinlock_t tid_release_lock;
991 struct workqueue_struct *workq;
992 struct work_struct tid_release_task;
993 struct work_struct db_full_task;
994 struct work_struct db_drop_task;
995 struct work_struct fatal_err_notify_task;
996 bool tid_release_task_busy;
997
998
999 spinlock_t mbox_lock;
1000 struct mbox_list mlist;
1001
1002
1003#define T4_OS_LOG_MBOX_CMDS 256
1004 struct mbox_cmd_log *mbox_log;
1005
1006 struct mutex uld_mutex;
1007
1008 struct dentry *debugfs_root;
1009 bool use_bd;
1010 bool trace_rss;
1011
1012
1013
1014
1015 struct ptp_clock *ptp_clock;
1016 struct ptp_clock_info ptp_clock_info;
1017 struct sk_buff *ptp_tx_skb;
1018
1019 spinlock_t ptp_lock;
1020 spinlock_t stats_lock;
1021 spinlock_t win0_lock ____cacheline_aligned_in_smp;
1022
1023
1024 struct cxgb4_tc_u32_table *tc_u32;
1025 struct chcr_stats_debug chcr_stats;
1026
1027
1028 bool tc_flower_initialized;
1029 struct rhashtable flower_tbl;
1030 struct rhashtable_params flower_ht_params;
1031 struct timer_list flower_stats_timer;
1032 struct work_struct flower_stats_work;
1033
1034
1035 struct ethtool_dump eth_dump;
1036
1037
1038 struct hma_data hma;
1039
1040 struct srq_data *srq;
1041
1042
1043 struct vmcoredd_data vmcoredd;
1044#if IS_ENABLED(CONFIG_THERMAL)
1045 struct ch_thermal ch_thermal;
1046#endif
1047};
1048
1049
1050
1051
1052struct ch_sched_params {
1053 s8 type;
1054 union {
1055 struct {
1056 s8 level;
1057 s8 mode;
1058 s8 rateunit;
1059 s8 ratemode;
1060 s8 channel;
1061 s8 class;
1062 s32 minrate;
1063 s32 maxrate;
1064 s16 weight;
1065 s16 pktsize;
1066 } params;
1067 } u;
1068};
1069
1070enum {
1071 SCHED_CLASS_TYPE_PACKET = 0,
1072};
1073
1074enum {
1075 SCHED_CLASS_LEVEL_CL_RL = 0,
1076};
1077
1078enum {
1079 SCHED_CLASS_MODE_CLASS = 0,
1080};
1081
1082enum {
1083 SCHED_CLASS_RATEUNIT_BITS = 0,
1084};
1085
1086enum {
1087 SCHED_CLASS_RATEMODE_ABS = 1,
1088};
1089
1090struct tx_sw_desc {
1091 struct sk_buff *skb;
1092 struct ulptx_sgl *sgl;
1093};
1094
1095
1096
1097
1098struct ch_sched_queue {
1099 s8 queue;
1100 s8 class;
1101};
1102
1103
1104
1105#define ETHTYPE_BITWIDTH 16
1106#define FRAG_BITWIDTH 1
1107#define MACIDX_BITWIDTH 9
1108#define FCOE_BITWIDTH 1
1109#define IPORT_BITWIDTH 3
1110#define MATCHTYPE_BITWIDTH 3
1111#define PROTO_BITWIDTH 8
1112#define TOS_BITWIDTH 8
1113#define PF_BITWIDTH 8
1114#define VF_BITWIDTH 8
1115#define IVLAN_BITWIDTH 16
1116#define OVLAN_BITWIDTH 16
1117#define ENCAP_VNI_BITWIDTH 24
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136struct ch_filter_tuple {
1137
1138
1139
1140
1141
1142
1143 uint32_t ethtype:ETHTYPE_BITWIDTH;
1144 uint32_t frag:FRAG_BITWIDTH;
1145 uint32_t ivlan_vld:1;
1146 uint32_t ovlan_vld:1;
1147 uint32_t pfvf_vld:1;
1148 uint32_t encap_vld:1;
1149 uint32_t macidx:MACIDX_BITWIDTH;
1150 uint32_t fcoe:FCOE_BITWIDTH;
1151 uint32_t iport:IPORT_BITWIDTH;
1152 uint32_t matchtype:MATCHTYPE_BITWIDTH;
1153 uint32_t proto:PROTO_BITWIDTH;
1154 uint32_t tos:TOS_BITWIDTH;
1155 uint32_t pf:PF_BITWIDTH;
1156 uint32_t vf:VF_BITWIDTH;
1157 uint32_t ivlan:IVLAN_BITWIDTH;
1158 uint32_t ovlan:OVLAN_BITWIDTH;
1159 uint32_t vni:ENCAP_VNI_BITWIDTH;
1160
1161
1162
1163
1164 uint8_t lip[16];
1165 uint8_t fip[16];
1166 uint16_t lport;
1167 uint16_t fport;
1168};
1169
1170
1171
1172struct ch_filter_specification {
1173
1174
1175 uint32_t hitcnts:1;
1176 uint32_t prio:1;
1177
1178
1179
1180
1181 uint32_t type:1;
1182 u32 hash:1;
1183
1184
1185
1186
1187
1188 uint32_t action:2;
1189
1190 uint32_t rpttid:1;
1191
1192 uint32_t dirsteer:1;
1193 uint32_t iq:10;
1194
1195 uint32_t maskhash:1;
1196 uint32_t dirsteerhash:1;
1197
1198
1199
1200
1201
1202
1203 uint32_t eport:2;
1204 uint32_t newdmac:1;
1205 uint32_t newsmac:1;
1206 uint32_t newvlan:2;
1207 uint32_t nat_mode:3;
1208 uint8_t dmac[ETH_ALEN];
1209 uint8_t smac[ETH_ALEN];
1210 uint16_t vlan;
1211
1212 u8 nat_lip[16];
1213 u8 nat_fip[16];
1214 u16 nat_lport;
1215 u16 nat_fport;
1216
1217
1218 u8 rsvd[24];
1219
1220
1221
1222 struct ch_filter_tuple val;
1223 struct ch_filter_tuple mask;
1224};
1225
1226enum {
1227 FILTER_PASS = 0,
1228 FILTER_DROP,
1229 FILTER_SWITCH
1230};
1231
1232enum {
1233 VLAN_NOCHANGE = 0,
1234 VLAN_REMOVE,
1235 VLAN_INSERT,
1236 VLAN_REWRITE
1237};
1238
1239enum {
1240 NAT_MODE_NONE = 0,
1241 NAT_MODE_DIP,
1242 NAT_MODE_DIP_DP,
1243 NAT_MODE_DIP_DP_SIP,
1244 NAT_MODE_DIP_DP_SP,
1245 NAT_MODE_SIP_SP,
1246 NAT_MODE_DIP_SIP_SP,
1247 NAT_MODE_ALL
1248};
1249
1250
1251
1252
1253
1254
1255
1256struct filter_entry {
1257
1258 u32 valid:1;
1259 u32 locked:1;
1260
1261 u32 pending:1;
1262 struct filter_ctx *ctx;
1263 struct l2t_entry *l2t;
1264 struct smt_entry *smt;
1265 struct net_device *dev;
1266 u32 tid;
1267
1268
1269
1270
1271
1272
1273 struct ch_filter_specification fs;
1274};
1275
1276static inline int is_offload(const struct adapter *adap)
1277{
1278 return adap->params.offload;
1279}
1280
1281static inline int is_hashfilter(const struct adapter *adap)
1282{
1283 return adap->params.hash_filter;
1284}
1285
1286static inline int is_pci_uld(const struct adapter *adap)
1287{
1288 return adap->params.crypto;
1289}
1290
1291static inline int is_uld(const struct adapter *adap)
1292{
1293 return (adap->params.offload || adap->params.crypto);
1294}
1295
1296static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1297{
1298 return readl(adap->regs + reg_addr);
1299}
1300
1301static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1302{
1303 writel(val, adap->regs + reg_addr);
1304}
1305
1306#ifndef readq
1307static inline u64 readq(const volatile void __iomem *addr)
1308{
1309 return readl(addr) + ((u64)readl(addr + 4) << 32);
1310}
1311
1312static inline void writeq(u64 val, volatile void __iomem *addr)
1313{
1314 writel(val, addr);
1315 writel(val >> 32, addr + 4);
1316}
1317#endif
1318
1319static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1320{
1321 return readq(adap->regs + reg_addr);
1322}
1323
1324static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1325{
1326 writeq(val, adap->regs + reg_addr);
1327}
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1339 u8 hw_addr[])
1340{
1341 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1342 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1343}
1344
1345
1346
1347
1348
1349
1350
1351static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1352{
1353 return netdev_priv(dev);
1354}
1355
1356
1357
1358
1359
1360
1361
1362
1363static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1364{
1365 return netdev_priv(adap->port[idx]);
1366}
1367
1368
1369
1370
1371
1372
1373
1374static inline struct adapter *netdev2adap(const struct net_device *dev)
1375{
1376 return netdev2pinfo(dev)->adapter;
1377}
1378
1379
1380
1381
1382
1383
1384static inline unsigned int mk_adap_vers(struct adapter *ap)
1385{
1386 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1387 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1388}
1389
1390
1391static inline unsigned int qtimer_val(const struct adapter *adap,
1392 const struct sge_rspq *q)
1393{
1394 unsigned int idx = q->intr_params >> 1;
1395
1396 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1397}
1398
1399
1400extern char cxgb4_driver_name[];
1401extern const char cxgb4_driver_version[];
1402
1403void t4_os_portmod_changed(struct adapter *adap, int port_id);
1404void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1405
1406void t4_free_sge_resources(struct adapter *adap);
1407void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1408irq_handler_t t4_intr_handler(struct adapter *adap);
1409netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1410int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1411 const struct pkt_gl *gl);
1412int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1413int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1414int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1415 struct net_device *dev, int intr_idx,
1416 struct sge_fl *fl, rspq_handler_t hnd,
1417 rspq_flush_handler_t flush_handler, int cong);
1418int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1419 struct net_device *dev, struct netdev_queue *netdevq,
1420 unsigned int iqid, u8 dbqt);
1421int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1422 struct net_device *dev, unsigned int iqid,
1423 unsigned int cmplqid);
1424int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1425 unsigned int cmplqid);
1426int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1427 struct net_device *dev, unsigned int iqid,
1428 unsigned int uld_type);
1429irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1430int t4_sge_init(struct adapter *adap);
1431void t4_sge_start(struct adapter *adap);
1432void t4_sge_stop(struct adapter *adap);
1433int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q,
1434 int maxreclaim);
1435void cxgb4_set_ethtool_ops(struct net_device *netdev);
1436int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1437enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1438extern int dbfifo_int_thresh;
1439
1440#define for_each_port(adapter, iter) \
1441 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1442
1443static inline int is_bypass(struct adapter *adap)
1444{
1445 return adap->params.bypass;
1446}
1447
1448static inline int is_bypass_device(int device)
1449{
1450
1451 switch (device) {
1452 case 0x440b:
1453 case 0x440c:
1454 return 1;
1455 default:
1456 return 0;
1457 }
1458}
1459
1460static inline int is_10gbt_device(int device)
1461{
1462
1463 switch (device) {
1464 case 0x4409:
1465 case 0x4486:
1466 return 1;
1467
1468 default:
1469 return 0;
1470 }
1471}
1472
1473static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1474{
1475 return adap->params.vpd.cclk / 1000;
1476}
1477
1478static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1479 unsigned int us)
1480{
1481 return (us * adap->params.vpd.cclk) / 1000;
1482}
1483
1484static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1485 unsigned int ticks)
1486{
1487
1488 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1489 adapter->params.vpd.cclk);
1490}
1491
1492static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1493 unsigned int ticks)
1494{
1495 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1496}
1497
1498void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1499 u32 val);
1500
1501int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1502 int size, void *rpl, bool sleep_ok, int timeout);
1503int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1504 void *rpl, bool sleep_ok);
1505
1506static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1507 const void *cmd, int size, void *rpl,
1508 int timeout)
1509{
1510 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1511 timeout);
1512}
1513
1514static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1515 int size, void *rpl)
1516{
1517 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1518}
1519
1520static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1521 int size, void *rpl)
1522{
1523 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1524}
1525
1526
1527
1528
1529
1530
1531
1532
1533static inline int hash_mac_addr(const u8 *addr)
1534{
1535 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1536 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1537
1538 a ^= b;
1539 a ^= (a >> 12);
1540 a ^= (a >> 6);
1541 return a & 0x3f;
1542}
1543
1544int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1545 unsigned int cnt);
1546static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1547 unsigned int us, unsigned int cnt,
1548 unsigned int size, unsigned int iqe_size)
1549{
1550 q->adap = adap;
1551 cxgb4_set_rspq_intr_params(q, us, cnt);
1552 q->iqe_len = iqe_size;
1553 q->size = size;
1554}
1555
1556
1557
1558
1559
1560
1561
1562
1563static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1564{
1565 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1566 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1567 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1568 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1569}
1570
1571void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1572 unsigned int data_reg, const u32 *vals,
1573 unsigned int nregs, unsigned int start_idx);
1574void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1575 unsigned int data_reg, u32 *vals, unsigned int nregs,
1576 unsigned int start_idx);
1577void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1578
1579struct fw_filter_wr;
1580
1581void t4_intr_enable(struct adapter *adapter);
1582void t4_intr_disable(struct adapter *adapter);
1583int t4_slow_intr_handler(struct adapter *adapter);
1584
1585int t4_wait_dev_ready(void __iomem *regs);
1586
1587fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
1588 struct link_config *lc);
1589int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1590 unsigned int port, struct link_config *lc,
1591 u8 sleep_ok, int timeout);
1592
1593static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1594 unsigned int port, struct link_config *lc)
1595{
1596 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1597 true, FW_CMD_MAX_TIMEOUT);
1598}
1599
1600static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1601 unsigned int port, struct link_config *lc)
1602{
1603 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1604 false, FW_CMD_MAX_TIMEOUT);
1605}
1606
1607int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1608
1609u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1610u32 t4_get_util_window(struct adapter *adap);
1611void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1612
1613int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1614 u32 *mem_base, u32 *mem_aperture);
1615void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1616void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1617 int dir);
1618#define T4_MEMORY_WRITE 0
1619#define T4_MEMORY_READ 1
1620int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1621 void *buf, int dir);
1622static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1623 u32 len, __be32 *buf)
1624{
1625 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1626}
1627
1628unsigned int t4_get_regs_len(struct adapter *adapter);
1629void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1630
1631int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1632int t4_seeprom_wp(struct adapter *adapter, bool enable);
1633int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1634int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1635int t4_get_pfres(struct adapter *adapter);
1636int t4_read_flash(struct adapter *adapter, unsigned int addr,
1637 unsigned int nwords, u32 *data, int byte_oriented);
1638int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1639int t4_load_phy_fw(struct adapter *adap,
1640 int win, spinlock_t *lock,
1641 int (*phy_fw_version)(const u8 *, size_t),
1642 const u8 *phy_fw_data, size_t phy_fw_size);
1643int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1644int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1645int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1646 const u8 *fw_data, unsigned int size, int force);
1647int t4_fl_pkt_align(struct adapter *adap);
1648unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1649int t4_check_fw_version(struct adapter *adap);
1650int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1651int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1652int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1653int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1654int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1655int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1656int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1657int t4_get_version_info(struct adapter *adapter);
1658void t4_dump_version_info(struct adapter *adapter);
1659int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1660 const u8 *fw_data, unsigned int fw_size,
1661 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1662int t4_prep_adapter(struct adapter *adapter);
1663int t4_shutdown_adapter(struct adapter *adapter);
1664
1665enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1666int t4_bar2_sge_qregs(struct adapter *adapter,
1667 unsigned int qid,
1668 enum t4_bar2_qtype qtype,
1669 int user,
1670 u64 *pbar2_qoffset,
1671 unsigned int *pbar2_qid);
1672
1673unsigned int qtimer_val(const struct adapter *adap,
1674 const struct sge_rspq *q);
1675
1676int t4_init_devlog_params(struct adapter *adapter);
1677int t4_init_sge_params(struct adapter *adapter);
1678int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1679int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1680int t4_init_rss_mode(struct adapter *adap, int mbox);
1681int t4_init_portinfo(struct port_info *pi, int mbox,
1682 int port, int pf, int vf, u8 mac[]);
1683int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1684void t4_fatal_err(struct adapter *adapter);
1685unsigned int t4_chip_rss_size(struct adapter *adapter);
1686int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1687 int start, int n, const u16 *rspq, unsigned int nrspq);
1688int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1689 unsigned int flags);
1690int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1691 unsigned int flags, unsigned int defq);
1692int t4_read_rss(struct adapter *adapter, u16 *entries);
1693void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1694void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1695 bool sleep_ok);
1696void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1697 u32 *valp, bool sleep_ok);
1698void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1699 u32 *vfl, u32 *vfh, bool sleep_ok);
1700u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1701u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1702
1703unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1704unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1705void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1706void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1707int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1708 size_t n);
1709int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1710 size_t n);
1711int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1712 unsigned int *valp);
1713int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1714 const unsigned int *valp);
1715int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1716void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1717 unsigned int *pif_req_wrptr,
1718 unsigned int *pif_rsp_wrptr);
1719void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1720void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1721const char *t4_get_port_type_description(enum fw_port_type port_type);
1722void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1723void t4_get_port_stats_offset(struct adapter *adap, int idx,
1724 struct port_stats *stats,
1725 struct port_stats *offset);
1726void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1727void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1728void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1729void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1730 unsigned int mask, unsigned int val);
1731void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1732void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1733 bool sleep_ok);
1734void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1735 bool sleep_ok);
1736void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1737 bool sleep_ok);
1738void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1739 bool sleep_ok);
1740void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1741 struct tp_tcp_stats *v6, bool sleep_ok);
1742void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1743 struct tp_fcoe_stats *st, bool sleep_ok);
1744void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1745 const unsigned short *alpha, const unsigned short *beta);
1746
1747void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1748
1749void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1750void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1751
1752void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1753 const u8 *addr);
1754int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1755 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1756
1757int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1758 enum dev_master master, enum dev_state *state);
1759int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1760int t4_early_init(struct adapter *adap, unsigned int mbox);
1761int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1762int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1763 unsigned int cache_line_size);
1764int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1765int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1766 unsigned int vf, unsigned int nparams, const u32 *params,
1767 u32 *val);
1768int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1769 unsigned int vf, unsigned int nparams, const u32 *params,
1770 u32 *val);
1771int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1772 unsigned int vf, unsigned int nparams, const u32 *params,
1773 u32 *val, int rw, bool sleep_ok);
1774int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1775 unsigned int pf, unsigned int vf,
1776 unsigned int nparams, const u32 *params,
1777 const u32 *val, int timeout);
1778int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1779 unsigned int vf, unsigned int nparams, const u32 *params,
1780 const u32 *val);
1781int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1782 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1783 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1784 unsigned int vi, unsigned int cmask, unsigned int pmask,
1785 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1786int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1787 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1788 unsigned int *rss_size, u8 *vivld, u8 *vin);
1789int t4_free_vi(struct adapter *adap, unsigned int mbox,
1790 unsigned int pf, unsigned int vf,
1791 unsigned int viid);
1792int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1793 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1794 bool sleep_ok);
1795int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1796 const u8 *addr, const u8 *mask, unsigned int idx,
1797 u8 lookup_type, u8 port_id, bool sleep_ok);
1798int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
1799 bool sleep_ok);
1800int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1801 const u8 *addr, const u8 *mask, unsigned int vni,
1802 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
1803 bool sleep_ok);
1804int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1805 const u8 *addr, const u8 *mask, unsigned int idx,
1806 u8 lookup_type, u8 port_id, bool sleep_ok);
1807int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1808 unsigned int viid, bool free, unsigned int naddr,
1809 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1810int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1811 unsigned int viid, unsigned int naddr,
1812 const u8 **addr, bool sleep_ok);
1813int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1814 int idx, const u8 *addr, bool persist, u8 *smt_idx);
1815int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1816 bool ucast, u64 vec, bool sleep_ok);
1817int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1818 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1819int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
1820 struct port_info *pi,
1821 bool rx_en, bool tx_en, bool dcb_en);
1822int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1823 bool rx_en, bool tx_en);
1824int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1825 unsigned int nblinks);
1826int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1827 unsigned int mmd, unsigned int reg, u16 *valp);
1828int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1829 unsigned int mmd, unsigned int reg, u16 val);
1830int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1831 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1832 unsigned int fl0id, unsigned int fl1id);
1833int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1834 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1835 unsigned int fl0id, unsigned int fl1id);
1836int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1837 unsigned int vf, unsigned int eqid);
1838int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1839 unsigned int vf, unsigned int eqid);
1840int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1841 unsigned int vf, unsigned int eqid);
1842int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
1843int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
1844 u16 *dbqtimers);
1845void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1846int t4_update_port_info(struct port_info *pi);
1847int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1848 unsigned int *speedp, unsigned int *mtup);
1849int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1850void t4_db_full(struct adapter *adapter);
1851void t4_db_dropped(struct adapter *adapter);
1852int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1853 int filter_index, int enable);
1854void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1855 int filter_index, int *enabled);
1856int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1857 u32 addr, u32 val);
1858void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
1859void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
1860 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
1861int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
1862 enum ctxt_type ctype, u32 *data);
1863int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
1864 enum ctxt_type ctype, u32 *data);
1865int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1866 int rateunit, int ratemode, int channel, int class,
1867 int minrate, int maxrate, int weight, int pktsize);
1868void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1869void t4_idma_monitor_init(struct adapter *adapter,
1870 struct sge_idma_monitor_state *idma);
1871void t4_idma_monitor(struct adapter *adapter,
1872 struct sge_idma_monitor_state *idma,
1873 int hz, int ticks);
1874int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1875 unsigned int naddr, u8 *addr);
1876void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1877 u32 start_index, bool sleep_ok);
1878void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1879 u32 start_index, bool sleep_ok);
1880void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
1881 u32 start_index, bool sleep_ok);
1882
1883void t4_uld_mem_free(struct adapter *adap);
1884int t4_uld_mem_alloc(struct adapter *adap);
1885void t4_uld_clean_up(struct adapter *adap);
1886void t4_register_netevent_notifier(void);
1887int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
1888 unsigned int devid, unsigned int offset,
1889 unsigned int len, u8 *buf);
1890void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1891void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1892 unsigned int n, bool unmap);
1893void free_txq(struct adapter *adap, struct sge_txq *q);
1894void cxgb4_reclaim_completed_tx(struct adapter *adap,
1895 struct sge_txq *q, bool unmap);
1896int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
1897 dma_addr_t *addr);
1898void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
1899 void *pos);
1900void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
1901 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
1902 const dma_addr_t *addr);
1903void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
1904int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
1905 u16 vlan);
1906int cxgb4_dcb_enabled(const struct net_device *dev);
1907
1908int cxgb4_thermal_init(struct adapter *adap);
1909int cxgb4_thermal_remove(struct adapter *adap);
1910int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
1911 cpumask_var_t *aff_mask, int idx);
1912void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask);
1913
1914int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
1915 int *tcam_idx, const u8 *addr,
1916 bool persistent, u8 *smt_idx);
1917
1918int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid,
1919 bool free, unsigned int naddr,
1920 const u8 **addr, u16 *idx,
1921 u64 *hash, bool sleep_ok);
1922int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
1923 unsigned int naddr, const u8 **addr, bool sleep_ok);
1924int cxgb4_init_mps_ref_entries(struct adapter *adap);
1925void cxgb4_free_mps_ref_entries(struct adapter *adap);
1926int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1927 const u8 *addr, const u8 *mask,
1928 unsigned int vni, unsigned int vni_mask,
1929 u8 dip_hit, u8 lookup_type, bool sleep_ok);
1930int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
1931 int idx, bool sleep_ok);
1932int cxgb4_free_raw_mac_filt(struct adapter *adap,
1933 unsigned int viid,
1934 const u8 *addr,
1935 const u8 *mask,
1936 unsigned int idx,
1937 u8 lookup_type,
1938 u8 port_id,
1939 bool sleep_ok);
1940int cxgb4_alloc_raw_mac_filt(struct adapter *adap,
1941 unsigned int viid,
1942 const u8 *addr,
1943 const u8 *mask,
1944 unsigned int idx,
1945 u8 lookup_type,
1946 u8 port_id,
1947 bool sleep_ok);
1948int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
1949 int *tcam_idx, const u8 *addr,
1950 bool persistent, u8 *smt_idx);
1951
1952#endif
1953