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35#ifndef __T4_MSG_H
36#define __T4_MSG_H
37
38#include <linux/types.h>
39
40enum {
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
45 CPL_GET_TCB = 0x6,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
48 CPL_ABORT_REQ = 0xA,
49 CPL_ABORT_RPL = 0xB,
50 CPL_RX_DATA_ACK = 0xD,
51 CPL_TX_PKT = 0xE,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_SMT_WRITE_REQ = 0x14,
54 CPL_TID_RELEASE = 0x1A,
55 CPL_SRQ_TABLE_REQ = 0x1C,
56 CPL_TX_DATA_ISO = 0x1F,
57
58 CPL_CLOSE_LISTSRV_RPL = 0x20,
59 CPL_GET_TCB_RPL = 0x22,
60 CPL_L2T_WRITE_RPL = 0x23,
61 CPL_PASS_OPEN_RPL = 0x24,
62 CPL_ACT_OPEN_RPL = 0x25,
63 CPL_PEER_CLOSE = 0x26,
64 CPL_ABORT_REQ_RSS = 0x2B,
65 CPL_ABORT_RPL_RSS = 0x2D,
66 CPL_SMT_WRITE_RPL = 0x2E,
67
68 CPL_RX_PHYS_ADDR = 0x30,
69 CPL_CLOSE_CON_RPL = 0x32,
70 CPL_ISCSI_HDR = 0x33,
71 CPL_RDMA_CQE = 0x35,
72 CPL_RDMA_CQE_READ_RSP = 0x36,
73 CPL_RDMA_CQE_ERR = 0x37,
74 CPL_RX_DATA = 0x39,
75 CPL_SET_TCB_RPL = 0x3A,
76 CPL_RX_PKT = 0x3B,
77 CPL_RX_DDP_COMPLETE = 0x3F,
78
79 CPL_ACT_ESTABLISH = 0x40,
80 CPL_PASS_ESTABLISH = 0x41,
81 CPL_RX_DATA_DDP = 0x42,
82 CPL_PASS_ACCEPT_REQ = 0x44,
83 CPL_RX_ISCSI_CMP = 0x45,
84 CPL_TRACE_PKT_T5 = 0x48,
85 CPL_RX_ISCSI_DDP = 0x49,
86 CPL_RX_TLS_CMP = 0x4E,
87
88 CPL_RDMA_READ_REQ = 0x60,
89
90 CPL_PASS_OPEN_REQ6 = 0x81,
91 CPL_ACT_OPEN_REQ6 = 0x83,
92
93 CPL_TX_TLS_PDU = 0x88,
94 CPL_TX_TLS_SFO = 0x89,
95 CPL_TX_SEC_PDU = 0x8A,
96 CPL_TX_TLS_ACK = 0x8B,
97
98 CPL_RDMA_TERMINATE = 0xA2,
99 CPL_RDMA_WRITE = 0xA4,
100 CPL_SGE_EGR_UPDATE = 0xA5,
101 CPL_RX_MPS_PKT = 0xAF,
102
103 CPL_TRACE_PKT = 0xB0,
104 CPL_TLS_DATA = 0xB1,
105 CPL_ISCSI_DATA = 0xB2,
106
107 CPL_FW4_MSG = 0xC0,
108 CPL_FW4_PLD = 0xC1,
109 CPL_FW4_ACK = 0xC3,
110 CPL_SRQ_TABLE_RPL = 0xCC,
111
112 CPL_RX_PHYS_DSGL = 0xD0,
113
114 CPL_FW6_MSG = 0xE0,
115 CPL_FW6_PLD = 0xE1,
116 CPL_TX_TNL_LSO = 0xEC,
117 CPL_TX_PKT_LSO = 0xED,
118 CPL_TX_PKT_XT = 0xEE,
119
120 NUM_CPL_CMDS
121};
122
123enum CPL_error {
124 CPL_ERR_NONE = 0,
125 CPL_ERR_TCAM_PARITY = 1,
126 CPL_ERR_TCAM_MISS = 2,
127 CPL_ERR_TCAM_FULL = 3,
128 CPL_ERR_BAD_LENGTH = 15,
129 CPL_ERR_BAD_ROUTE = 18,
130 CPL_ERR_CONN_RESET = 20,
131 CPL_ERR_CONN_EXIST_SYNRECV = 21,
132 CPL_ERR_CONN_EXIST = 22,
133 CPL_ERR_ARP_MISS = 23,
134 CPL_ERR_BAD_SYN = 24,
135 CPL_ERR_CONN_TIMEDOUT = 30,
136 CPL_ERR_XMIT_TIMEDOUT = 31,
137 CPL_ERR_PERSIST_TIMEDOUT = 32,
138 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
139 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
140 CPL_ERR_RTX_NEG_ADVICE = 35,
141 CPL_ERR_PERSIST_NEG_ADVICE = 36,
142 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
143 CPL_ERR_ABORT_FAILED = 42,
144 CPL_ERR_IWARP_FLM = 50,
145 CPL_CONTAINS_READ_RPL = 60,
146 CPL_CONTAINS_WRITE_RPL = 61,
147};
148
149enum {
150 CPL_CONN_POLICY_AUTO = 0,
151 CPL_CONN_POLICY_ASK = 1,
152 CPL_CONN_POLICY_FILTER = 2,
153 CPL_CONN_POLICY_DENY = 3
154};
155
156enum {
157 ULP_MODE_NONE = 0,
158 ULP_MODE_ISCSI = 2,
159 ULP_MODE_RDMA = 4,
160 ULP_MODE_TCPDDP = 5,
161 ULP_MODE_FCOE = 6,
162 ULP_MODE_TLS = 8,
163};
164
165enum {
166 ULP_CRC_HEADER = 1 << 0,
167 ULP_CRC_DATA = 1 << 1
168};
169
170enum {
171 CPL_ABORT_SEND_RST = 0,
172 CPL_ABORT_NO_RST,
173};
174
175enum {
176 TX_CSUM_TCP = 0,
177 TX_CSUM_UDP = 1,
178 TX_CSUM_CRC16 = 4,
179 TX_CSUM_CRC32 = 5,
180 TX_CSUM_CRC32C = 6,
181 TX_CSUM_FCOE = 7,
182 TX_CSUM_TCPIP = 8,
183 TX_CSUM_UDPIP = 9,
184 TX_CSUM_TCPIP6 = 10,
185 TX_CSUM_UDPIP6 = 11,
186 TX_CSUM_IP = 12,
187};
188
189union opcode_tid {
190 __be32 opcode_tid;
191 u8 opcode;
192};
193
194#define CPL_OPCODE_S 24
195#define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
196#define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
197#define TID_G(x) ((x) & 0xFFFFFF)
198
199
200#define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
201
202#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
203
204
205#define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
206
207
208#define TID_TID_S 0
209#define TID_TID_M 0x3fff
210#define TID_TID_V(x) ((x) << TID_TID_S)
211#define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
212
213#define TID_QID_S 14
214#define TID_QID_M 0x3ff
215#define TID_QID_V(x) ((x) << TID_QID_S)
216#define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
217
218struct rss_header {
219 u8 opcode;
220#if defined(__LITTLE_ENDIAN_BITFIELD)
221 u8 channel:2;
222 u8 filter_hit:1;
223 u8 filter_tid:1;
224 u8 hash_type:2;
225 u8 ipv6:1;
226 u8 send2fw:1;
227#else
228 u8 send2fw:1;
229 u8 ipv6:1;
230 u8 hash_type:2;
231 u8 filter_tid:1;
232 u8 filter_hit:1;
233 u8 channel:2;
234#endif
235 __be16 qid;
236 __be32 hash_val;
237};
238
239struct work_request_hdr {
240 __be32 wr_hi;
241 __be32 wr_mid;
242 __be64 wr_lo;
243};
244
245
246#define WR_OP_S 24
247#define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
248
249#define WR_HDR struct work_request_hdr wr
250
251
252#define TX_CHAN_S 2
253#define TX_CHAN_V(x) ((x) << TX_CHAN_S)
254
255#define ULP_MODE_S 8
256#define ULP_MODE_V(x) ((x) << ULP_MODE_S)
257
258#define RCV_BUFSIZ_S 12
259#define RCV_BUFSIZ_M 0x3FFU
260#define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
261
262#define SMAC_SEL_S 28
263#define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
264
265#define L2T_IDX_S 36
266#define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
267
268#define WND_SCALE_S 50
269#define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
270
271#define KEEP_ALIVE_S 54
272#define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
273#define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
274
275#define MSS_IDX_S 60
276#define MSS_IDX_M 0xF
277#define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
278#define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
279
280
281#define RSS_QUEUE_S 0
282#define RSS_QUEUE_M 0x3FF
283#define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
284#define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
285
286#define RSS_QUEUE_VALID_S 10
287#define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
288#define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
289
290#define RX_FC_DISABLE_S 20
291#define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
292#define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
293
294#define RX_FC_VALID_S 22
295#define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
296#define RX_FC_VALID_F RX_FC_VALID_V(1U)
297
298#define RX_CHANNEL_S 26
299#define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
300#define RX_CHANNEL_F RX_CHANNEL_V(1U)
301
302#define WND_SCALE_EN_S 28
303#define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
304#define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
305
306#define T5_OPT_2_VALID_S 31
307#define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
308#define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
309
310struct cpl_pass_open_req {
311 WR_HDR;
312 union opcode_tid ot;
313 __be16 local_port;
314 __be16 peer_port;
315 __be32 local_ip;
316 __be32 peer_ip;
317 __be64 opt0;
318 __be64 opt1;
319};
320
321
322#define NO_CONG_S 4
323#define NO_CONG_V(x) ((x) << NO_CONG_S)
324#define NO_CONG_F NO_CONG_V(1U)
325
326#define DELACK_S 5
327#define DELACK_V(x) ((x) << DELACK_S)
328#define DELACK_F DELACK_V(1U)
329
330#define NON_OFFLOAD_S 7
331#define NON_OFFLOAD_V(x) ((x) << NON_OFFLOAD_S)
332#define NON_OFFLOAD_F NON_OFFLOAD_V(1U)
333
334#define DSCP_S 22
335#define DSCP_M 0x3F
336#define DSCP_V(x) ((x) << DSCP_S)
337#define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
338
339#define TCAM_BYPASS_S 48
340#define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
341#define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
342
343#define NAGLE_S 49
344#define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
345#define NAGLE_F NAGLE_V(1ULL)
346
347
348#define SYN_RSS_ENABLE_S 0
349#define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
350#define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
351
352#define SYN_RSS_QUEUE_S 2
353#define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
354
355#define CONN_POLICY_S 22
356#define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
357
358struct cpl_pass_open_req6 {
359 WR_HDR;
360 union opcode_tid ot;
361 __be16 local_port;
362 __be16 peer_port;
363 __be64 local_ip_hi;
364 __be64 local_ip_lo;
365 __be64 peer_ip_hi;
366 __be64 peer_ip_lo;
367 __be64 opt0;
368 __be64 opt1;
369};
370
371struct cpl_pass_open_rpl {
372 union opcode_tid ot;
373 u8 rsvd[3];
374 u8 status;
375};
376
377struct tcp_options {
378 __be16 mss;
379 __u8 wsf;
380#if defined(__LITTLE_ENDIAN_BITFIELD)
381 __u8:4;
382 __u8 unknown:1;
383 __u8:1;
384 __u8 sack:1;
385 __u8 tstamp:1;
386#else
387 __u8 tstamp:1;
388 __u8 sack:1;
389 __u8:1;
390 __u8 unknown:1;
391 __u8:4;
392#endif
393};
394
395struct cpl_pass_accept_req {
396 union opcode_tid ot;
397 __be16 rsvd;
398 __be16 len;
399 __be32 hdr_len;
400 __be16 vlan;
401 __be16 l2info;
402 __be32 tos_stid;
403 struct tcp_options tcpopt;
404};
405
406
407#define SYN_RX_CHAN_S 0
408#define SYN_RX_CHAN_M 0xF
409#define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S)
410#define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M)
411
412#define TCP_HDR_LEN_S 10
413#define TCP_HDR_LEN_M 0x3F
414#define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S)
415#define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
416
417#define IP_HDR_LEN_S 16
418#define IP_HDR_LEN_M 0x3FF
419#define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S)
420#define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M)
421
422#define ETH_HDR_LEN_S 26
423#define ETH_HDR_LEN_M 0x1F
424#define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S)
425#define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M)
426
427
428#define SYN_MAC_IDX_S 0
429#define SYN_MAC_IDX_M 0x1FF
430#define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S)
431#define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M)
432
433#define SYN_XACT_MATCH_S 9
434#define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S)
435#define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U)
436
437#define SYN_INTF_S 12
438#define SYN_INTF_M 0xF
439#define SYN_INTF_V(x) ((x) << SYN_INTF_S)
440#define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)
441
442enum {
443 CONG_ALG_RENO,
444 CONG_ALG_TAHOE,
445 CONG_ALG_NEWRENO,
446 CONG_ALG_HIGHSPEED
447};
448
449#define CONG_CNTRL_S 14
450#define CONG_CNTRL_M 0x3
451#define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S)
452#define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M)
453
454#define T5_ISS_S 18
455#define T5_ISS_V(x) ((x) << T5_ISS_S)
456#define T5_ISS_F T5_ISS_V(1U)
457
458struct cpl_pass_accept_rpl {
459 WR_HDR;
460 union opcode_tid ot;
461 __be32 opt2;
462 __be64 opt0;
463};
464
465
466#define RX_COALESCE_VALID_S 11
467#define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
468#define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
469
470#define RX_COALESCE_S 12
471#define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
472
473#define PACE_S 16
474#define PACE_V(x) ((x) << PACE_S)
475
476#define TX_QUEUE_S 23
477#define TX_QUEUE_M 0x7
478#define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
479#define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
480
481#define CCTRL_ECN_S 27
482#define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
483#define CCTRL_ECN_F CCTRL_ECN_V(1U)
484
485#define TSTAMPS_EN_S 29
486#define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
487#define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
488
489#define SACK_EN_S 30
490#define SACK_EN_V(x) ((x) << SACK_EN_S)
491#define SACK_EN_F SACK_EN_V(1U)
492
493struct cpl_t5_pass_accept_rpl {
494 WR_HDR;
495 union opcode_tid ot;
496 __be32 opt2;
497 __be64 opt0;
498 __be32 iss;
499 __be32 rsvd;
500};
501
502struct cpl_act_open_req {
503 WR_HDR;
504 union opcode_tid ot;
505 __be16 local_port;
506 __be16 peer_port;
507 __be32 local_ip;
508 __be32 peer_ip;
509 __be64 opt0;
510 __be32 params;
511 __be32 opt2;
512};
513
514#define FILTER_TUPLE_S 24
515#define FILTER_TUPLE_M 0xFFFFFFFFFF
516#define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
517#define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
518struct cpl_t5_act_open_req {
519 WR_HDR;
520 union opcode_tid ot;
521 __be16 local_port;
522 __be16 peer_port;
523 __be32 local_ip;
524 __be32 peer_ip;
525 __be64 opt0;
526 __be32 rsvd;
527 __be32 opt2;
528 __be64 params;
529};
530
531struct cpl_t6_act_open_req {
532 WR_HDR;
533 union opcode_tid ot;
534 __be16 local_port;
535 __be16 peer_port;
536 __be32 local_ip;
537 __be32 peer_ip;
538 __be64 opt0;
539 __be32 rsvd;
540 __be32 opt2;
541 __be64 params;
542 __be32 rsvd2;
543 __be32 opt3;
544};
545
546struct cpl_act_open_req6 {
547 WR_HDR;
548 union opcode_tid ot;
549 __be16 local_port;
550 __be16 peer_port;
551 __be64 local_ip_hi;
552 __be64 local_ip_lo;
553 __be64 peer_ip_hi;
554 __be64 peer_ip_lo;
555 __be64 opt0;
556 __be32 params;
557 __be32 opt2;
558};
559
560struct cpl_t5_act_open_req6 {
561 WR_HDR;
562 union opcode_tid ot;
563 __be16 local_port;
564 __be16 peer_port;
565 __be64 local_ip_hi;
566 __be64 local_ip_lo;
567 __be64 peer_ip_hi;
568 __be64 peer_ip_lo;
569 __be64 opt0;
570 __be32 rsvd;
571 __be32 opt2;
572 __be64 params;
573};
574
575struct cpl_t6_act_open_req6 {
576 WR_HDR;
577 union opcode_tid ot;
578 __be16 local_port;
579 __be16 peer_port;
580 __be64 local_ip_hi;
581 __be64 local_ip_lo;
582 __be64 peer_ip_hi;
583 __be64 peer_ip_lo;
584 __be64 opt0;
585 __be32 rsvd;
586 __be32 opt2;
587 __be64 params;
588 __be32 rsvd2;
589 __be32 opt3;
590};
591
592struct cpl_act_open_rpl {
593 union opcode_tid ot;
594 __be32 atid_status;
595};
596
597
598#define AOPEN_STATUS_S 0
599#define AOPEN_STATUS_M 0xFF
600#define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
601
602#define AOPEN_ATID_S 8
603#define AOPEN_ATID_M 0xFFFFFF
604#define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
605
606struct cpl_pass_establish {
607 union opcode_tid ot;
608 __be32 rsvd;
609 __be32 tos_stid;
610 __be16 mac_idx;
611 __be16 tcp_opt;
612 __be32 snd_isn;
613 __be32 rcv_isn;
614};
615
616
617#define PASS_OPEN_TID_S 0
618#define PASS_OPEN_TID_M 0xFFFFFF
619#define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
620#define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
621
622#define PASS_OPEN_TOS_S 24
623#define PASS_OPEN_TOS_M 0xFF
624#define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
625#define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
626
627
628#define TCPOPT_WSCALE_OK_S 5
629#define TCPOPT_WSCALE_OK_M 0x1
630#define TCPOPT_WSCALE_OK_G(x) \
631 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
632
633#define TCPOPT_SACK_S 6
634#define TCPOPT_SACK_M 0x1
635#define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
636
637#define TCPOPT_TSTAMP_S 7
638#define TCPOPT_TSTAMP_M 0x1
639#define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
640
641#define TCPOPT_SND_WSCALE_S 8
642#define TCPOPT_SND_WSCALE_M 0xF
643#define TCPOPT_SND_WSCALE_G(x) \
644 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
645
646#define TCPOPT_MSS_S 12
647#define TCPOPT_MSS_M 0xF
648#define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
649
650#define T6_TCP_HDR_LEN_S 8
651#define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
652#define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
653
654#define T6_IP_HDR_LEN_S 14
655#define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
656#define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
657
658#define T6_ETH_HDR_LEN_S 24
659#define T6_ETH_HDR_LEN_M 0xFF
660#define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
661#define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
662
663struct cpl_act_establish {
664 union opcode_tid ot;
665 __be32 rsvd;
666 __be32 tos_atid;
667 __be16 mac_idx;
668 __be16 tcp_opt;
669 __be32 snd_isn;
670 __be32 rcv_isn;
671};
672
673struct cpl_get_tcb {
674 WR_HDR;
675 union opcode_tid ot;
676 __be16 reply_ctrl;
677 __be16 cookie;
678};
679
680
681#define QUEUENO_S 0
682#define QUEUENO_V(x) ((x) << QUEUENO_S)
683
684#define REPLY_CHAN_S 14
685#define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
686#define REPLY_CHAN_F REPLY_CHAN_V(1U)
687
688#define NO_REPLY_S 15
689#define NO_REPLY_V(x) ((x) << NO_REPLY_S)
690#define NO_REPLY_F NO_REPLY_V(1U)
691
692struct cpl_get_tcb_rpl {
693 union opcode_tid ot;
694 __u8 cookie;
695 __u8 status;
696 __be16 len;
697};
698
699struct cpl_set_tcb_field {
700 WR_HDR;
701 union opcode_tid ot;
702 __be16 reply_ctrl;
703 __be16 word_cookie;
704 __be64 mask;
705 __be64 val;
706};
707
708
709#define TCB_WORD_S 0
710#define TCB_WORD_V(x) ((x) << TCB_WORD_S)
711
712#define TCB_COOKIE_S 5
713#define TCB_COOKIE_M 0x7
714#define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
715#define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
716
717struct cpl_set_tcb_rpl {
718 union opcode_tid ot;
719 __be16 rsvd;
720 u8 cookie;
721 u8 status;
722 __be64 oldval;
723};
724
725struct cpl_close_con_req {
726 WR_HDR;
727 union opcode_tid ot;
728 __be32 rsvd;
729};
730
731struct cpl_close_con_rpl {
732 union opcode_tid ot;
733 u8 rsvd[3];
734 u8 status;
735 __be32 snd_nxt;
736 __be32 rcv_nxt;
737};
738
739struct cpl_close_listsvr_req {
740 WR_HDR;
741 union opcode_tid ot;
742 __be16 reply_ctrl;
743 __be16 rsvd;
744};
745
746
747#define LISTSVR_IPV6_S 14
748#define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
749#define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
750
751struct cpl_close_listsvr_rpl {
752 union opcode_tid ot;
753 u8 rsvd[3];
754 u8 status;
755};
756
757struct cpl_abort_req_rss {
758 union opcode_tid ot;
759 u8 rsvd[3];
760 u8 status;
761};
762
763struct cpl_abort_req_rss6 {
764 union opcode_tid ot;
765 __be32 srqidx_status;
766};
767
768#define ABORT_RSS_STATUS_S 0
769#define ABORT_RSS_STATUS_M 0xff
770#define ABORT_RSS_STATUS_V(x) ((x) << ABORT_RSS_STATUS_S)
771#define ABORT_RSS_STATUS_G(x) (((x) >> ABORT_RSS_STATUS_S) & ABORT_RSS_STATUS_M)
772
773#define ABORT_RSS_SRQIDX_S 8
774#define ABORT_RSS_SRQIDX_M 0xffffff
775#define ABORT_RSS_SRQIDX_V(x) ((x) << ABORT_RSS_SRQIDX_S)
776#define ABORT_RSS_SRQIDX_G(x) (((x) >> ABORT_RSS_SRQIDX_S) & ABORT_RSS_SRQIDX_M)
777
778struct cpl_abort_req {
779 WR_HDR;
780 union opcode_tid ot;
781 __be32 rsvd0;
782 u8 rsvd1;
783 u8 cmd;
784 u8 rsvd2[6];
785};
786
787struct cpl_abort_rpl_rss {
788 union opcode_tid ot;
789 u8 rsvd[3];
790 u8 status;
791};
792
793struct cpl_abort_rpl_rss6 {
794 union opcode_tid ot;
795 __be32 srqidx_status;
796};
797
798struct cpl_abort_rpl {
799 WR_HDR;
800 union opcode_tid ot;
801 __be32 rsvd0;
802 u8 rsvd1;
803 u8 cmd;
804 u8 rsvd2[6];
805};
806
807struct cpl_peer_close {
808 union opcode_tid ot;
809 __be32 rcv_nxt;
810};
811
812struct cpl_tid_release {
813 WR_HDR;
814 union opcode_tid ot;
815 __be32 rsvd;
816};
817
818struct cpl_tx_pkt_core {
819 __be32 ctrl0;
820 __be16 pack;
821 __be16 len;
822 __be64 ctrl1;
823};
824
825struct cpl_tx_pkt {
826 WR_HDR;
827 struct cpl_tx_pkt_core c;
828};
829
830#define cpl_tx_pkt_xt cpl_tx_pkt
831
832
833#define TXPKT_VF_S 0
834#define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
835
836#define TXPKT_PF_S 8
837#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
838
839#define TXPKT_VF_VLD_S 11
840#define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
841#define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U)
842
843#define TXPKT_OVLAN_IDX_S 12
844#define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
845
846#define TXPKT_T5_OVLAN_IDX_S 12
847#define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
848
849#define TXPKT_INTF_S 16
850#define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
851
852#define TXPKT_INS_OVLAN_S 21
853#define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
854#define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U)
855
856#define TXPKT_TSTAMP_S 23
857#define TXPKT_TSTAMP_V(x) ((x) << TXPKT_TSTAMP_S)
858#define TXPKT_TSTAMP_F TXPKT_TSTAMP_V(1ULL)
859
860#define TXPKT_OPCODE_S 24
861#define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
862
863
864#define TXPKT_CSUM_END_S 12
865#define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
866
867#define TXPKT_CSUM_START_S 20
868#define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
869
870#define TXPKT_IPHDR_LEN_S 20
871#define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
872
873#define TXPKT_CSUM_LOC_S 30
874#define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
875
876#define TXPKT_ETHHDR_LEN_S 34
877#define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
878
879#define T6_TXPKT_ETHHDR_LEN_S 32
880#define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
881
882#define TXPKT_CSUM_TYPE_S 40
883#define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
884
885#define TXPKT_VLAN_S 44
886#define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
887
888#define TXPKT_VLAN_VLD_S 60
889#define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
890#define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL)
891
892#define TXPKT_IPCSUM_DIS_S 62
893#define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
894#define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL)
895
896#define TXPKT_L4CSUM_DIS_S 63
897#define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
898#define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL)
899
900struct cpl_tx_pkt_lso_core {
901 __be32 lso_ctrl;
902 __be16 ipid_ofst;
903 __be16 mss;
904 __be32 seqno_offset;
905 __be32 len;
906
907};
908
909
910#define LSO_TCPHDR_LEN_S 0
911#define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
912
913#define LSO_IPHDR_LEN_S 4
914#define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
915
916#define LSO_ETHHDR_LEN_S 16
917#define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
918
919#define LSO_IPV6_S 20
920#define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
921#define LSO_IPV6_F LSO_IPV6_V(1U)
922
923#define LSO_LAST_SLICE_S 22
924#define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
925#define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
926
927#define LSO_FIRST_SLICE_S 23
928#define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
929#define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
930
931#define LSO_OPCODE_S 24
932#define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
933
934#define LSO_T5_XFER_SIZE_S 0
935#define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
936
937struct cpl_tx_pkt_lso {
938 WR_HDR;
939 struct cpl_tx_pkt_lso_core c;
940
941};
942
943struct cpl_iscsi_hdr {
944 union opcode_tid ot;
945 __be16 pdu_len_ddp;
946 __be16 len;
947 __be32 seq;
948 __be16 urg;
949 u8 rsvd;
950 u8 status;
951};
952
953
954#define ISCSI_PDU_LEN_S 0
955#define ISCSI_PDU_LEN_M 0x7FFF
956#define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
957#define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
958
959#define ISCSI_DDP_S 15
960#define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
961#define ISCSI_DDP_F ISCSI_DDP_V(1U)
962
963struct cpl_rx_data_ddp {
964 union opcode_tid ot;
965 __be16 urg;
966 __be16 len;
967 __be32 seq;
968 union {
969 __be32 nxt_seq;
970 __be32 ddp_report;
971 };
972 __be32 ulp_crc;
973 __be32 ddpvld;
974};
975
976#define cpl_rx_iscsi_ddp cpl_rx_data_ddp
977
978struct cpl_iscsi_data {
979 union opcode_tid ot;
980 __u8 rsvd0[2];
981 __be16 len;
982 __be32 seq;
983 __be16 urg;
984 __u8 rsvd1;
985 __u8 status;
986};
987
988struct cpl_rx_iscsi_cmp {
989 union opcode_tid ot;
990 __be16 pdu_len_ddp;
991 __be16 len;
992 __be32 seq;
993 __be16 urg;
994 __u8 rsvd;
995 __u8 status;
996 __be32 ulp_crc;
997 __be32 ddpvld;
998};
999
1000struct cpl_tx_data_iso {
1001 __be32 op_to_scsi;
1002 __u8 reserved1;
1003 __u8 ahs_len;
1004 __be16 mpdu;
1005 __be32 burst_size;
1006 __be32 len;
1007 __be32 reserved2_seglen_offset;
1008 __be32 datasn_offset;
1009 __be32 buffer_offset;
1010 __be32 reserved3;
1011
1012
1013};
1014
1015
1016#define CPL_TX_DATA_ISO_OP_S 24
1017#define CPL_TX_DATA_ISO_OP_M 0xff
1018#define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S)
1019#define CPL_TX_DATA_ISO_OP_G(x) \
1020 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M)
1021
1022#define CPL_TX_DATA_ISO_FIRST_S 23
1023#define CPL_TX_DATA_ISO_FIRST_M 0x1
1024#define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S)
1025#define CPL_TX_DATA_ISO_FIRST_G(x) \
1026 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M)
1027#define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U)
1028
1029#define CPL_TX_DATA_ISO_LAST_S 22
1030#define CPL_TX_DATA_ISO_LAST_M 0x1
1031#define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S)
1032#define CPL_TX_DATA_ISO_LAST_G(x) \
1033 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M)
1034#define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U)
1035
1036#define CPL_TX_DATA_ISO_CPLHDRLEN_S 21
1037#define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1
1038#define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S)
1039#define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \
1040 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M)
1041#define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U)
1042
1043#define CPL_TX_DATA_ISO_HDRCRC_S 20
1044#define CPL_TX_DATA_ISO_HDRCRC_M 0x1
1045#define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S)
1046#define CPL_TX_DATA_ISO_HDRCRC_G(x) \
1047 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M)
1048#define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U)
1049
1050#define CPL_TX_DATA_ISO_PLDCRC_S 19
1051#define CPL_TX_DATA_ISO_PLDCRC_M 0x1
1052#define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S)
1053#define CPL_TX_DATA_ISO_PLDCRC_G(x) \
1054 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M)
1055#define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U)
1056
1057#define CPL_TX_DATA_ISO_IMMEDIATE_S 18
1058#define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1
1059#define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S)
1060#define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \
1061 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M)
1062#define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U)
1063
1064#define CPL_TX_DATA_ISO_SCSI_S 16
1065#define CPL_TX_DATA_ISO_SCSI_M 0x3
1066#define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S)
1067#define CPL_TX_DATA_ISO_SCSI_G(x) \
1068 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M)
1069
1070
1071#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0
1072#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff
1073#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \
1074 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S)
1075#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \
1076 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \
1077 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M)
1078
1079struct cpl_rx_data {
1080 union opcode_tid ot;
1081 __be16 rsvd;
1082 __be16 len;
1083 __be32 seq;
1084 __be16 urg;
1085#if defined(__LITTLE_ENDIAN_BITFIELD)
1086 u8 dack_mode:2;
1087 u8 psh:1;
1088 u8 heartbeat:1;
1089 u8 ddp_off:1;
1090 u8 :3;
1091#else
1092 u8 :3;
1093 u8 ddp_off:1;
1094 u8 heartbeat:1;
1095 u8 psh:1;
1096 u8 dack_mode:2;
1097#endif
1098 u8 status;
1099};
1100
1101struct cpl_rx_data_ack {
1102 WR_HDR;
1103 union opcode_tid ot;
1104 __be32 credit_dack;
1105};
1106
1107
1108#define RX_CREDITS_S 0
1109#define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
1110
1111#define RX_FORCE_ACK_S 28
1112#define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
1113#define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
1114
1115#define RX_DACK_MODE_S 29
1116#define RX_DACK_MODE_M 0x3
1117#define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S)
1118#define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M)
1119
1120#define RX_DACK_CHANGE_S 31
1121#define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S)
1122#define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U)
1123
1124struct cpl_rx_pkt {
1125 struct rss_header rsshdr;
1126 u8 opcode;
1127#if defined(__LITTLE_ENDIAN_BITFIELD)
1128 u8 iff:4;
1129 u8 csum_calc:1;
1130 u8 ipmi_pkt:1;
1131 u8 vlan_ex:1;
1132 u8 ip_frag:1;
1133#else
1134 u8 ip_frag:1;
1135 u8 vlan_ex:1;
1136 u8 ipmi_pkt:1;
1137 u8 csum_calc:1;
1138 u8 iff:4;
1139#endif
1140 __be16 csum;
1141 __be16 vlan;
1142 __be16 len;
1143 __be32 l2info;
1144 __be16 hdr_len;
1145 __be16 err_vec;
1146};
1147
1148#define RX_T6_ETHHDR_LEN_M 0xFF
1149#define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
1150
1151#define RXF_PSH_S 20
1152#define RXF_PSH_V(x) ((x) << RXF_PSH_S)
1153#define RXF_PSH_F RXF_PSH_V(1U)
1154
1155#define RXF_SYN_S 21
1156#define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1157#define RXF_SYN_F RXF_SYN_V(1U)
1158
1159#define RXF_UDP_S 22
1160#define RXF_UDP_V(x) ((x) << RXF_UDP_S)
1161#define RXF_UDP_F RXF_UDP_V(1U)
1162
1163#define RXF_TCP_S 23
1164#define RXF_TCP_V(x) ((x) << RXF_TCP_S)
1165#define RXF_TCP_F RXF_TCP_V(1U)
1166
1167#define RXF_IP_S 24
1168#define RXF_IP_V(x) ((x) << RXF_IP_S)
1169#define RXF_IP_F RXF_IP_V(1U)
1170
1171#define RXF_IP6_S 25
1172#define RXF_IP6_V(x) ((x) << RXF_IP6_S)
1173#define RXF_IP6_F RXF_IP6_V(1U)
1174
1175#define RXF_SYN_COOKIE_S 26
1176#define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
1177#define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
1178
1179#define RXF_FCOE_S 26
1180#define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
1181#define RXF_FCOE_F RXF_FCOE_V(1U)
1182
1183#define RXF_LRO_S 27
1184#define RXF_LRO_V(x) ((x) << RXF_LRO_S)
1185#define RXF_LRO_F RXF_LRO_V(1U)
1186
1187
1188#define RX_ETHHDR_LEN_S 0
1189#define RX_ETHHDR_LEN_M 0x1F
1190#define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
1191#define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
1192
1193#define RX_T5_ETHHDR_LEN_S 0
1194#define RX_T5_ETHHDR_LEN_M 0x3F
1195#define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
1196#define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
1197
1198#define RX_MACIDX_S 8
1199#define RX_MACIDX_M 0x1FF
1200#define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
1201#define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
1202
1203#define RXF_SYN_S 21
1204#define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1205#define RXF_SYN_F RXF_SYN_V(1U)
1206
1207#define RX_CHAN_S 28
1208#define RX_CHAN_M 0xF
1209#define RX_CHAN_V(x) ((x) << RX_CHAN_S)
1210#define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
1211
1212
1213#define RX_TCPHDR_LEN_S 0
1214#define RX_TCPHDR_LEN_M 0x3F
1215#define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
1216#define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
1217
1218#define RX_IPHDR_LEN_S 6
1219#define RX_IPHDR_LEN_M 0x3FF
1220#define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
1221#define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
1222
1223
1224#define RXERR_CSUM_S 13
1225#define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
1226#define RXERR_CSUM_F RXERR_CSUM_V(1U)
1227
1228#define T6_COMPR_RXERR_LEN_S 1
1229#define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1230#define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U)
1231
1232#define T6_COMPR_RXERR_VEC_S 0
1233#define T6_COMPR_RXERR_VEC_M 0x3F
1234#define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1235#define T6_COMPR_RXERR_VEC_G(x) \
1236 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M)
1237
1238
1239#define T6_COMPR_RXERR_SUM_S 4
1240#define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S)
1241#define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U)
1242
1243#define T6_RX_TNLHDR_LEN_S 8
1244#define T6_RX_TNLHDR_LEN_M 0xFF
1245#define T6_RX_TNLHDR_LEN_V(x) ((x) << T6_RX_TNLHDR_LEN_S)
1246#define T6_RX_TNLHDR_LEN_G(x) (((x) >> T6_RX_TNLHDR_LEN_S) & T6_RX_TNLHDR_LEN_M)
1247
1248struct cpl_trace_pkt {
1249 u8 opcode;
1250 u8 intf;
1251#if defined(__LITTLE_ENDIAN_BITFIELD)
1252 u8 runt:4;
1253 u8 filter_hit:4;
1254 u8 :6;
1255 u8 err:1;
1256 u8 trunc:1;
1257#else
1258 u8 filter_hit:4;
1259 u8 runt:4;
1260 u8 trunc:1;
1261 u8 err:1;
1262 u8 :6;
1263#endif
1264 __be16 rsvd;
1265 __be16 len;
1266 __be64 tstamp;
1267};
1268
1269struct cpl_t5_trace_pkt {
1270 __u8 opcode;
1271 __u8 intf;
1272#if defined(__LITTLE_ENDIAN_BITFIELD)
1273 __u8 runt:4;
1274 __u8 filter_hit:4;
1275 __u8:6;
1276 __u8 err:1;
1277 __u8 trunc:1;
1278#else
1279 __u8 filter_hit:4;
1280 __u8 runt:4;
1281 __u8 trunc:1;
1282 __u8 err:1;
1283 __u8:6;
1284#endif
1285 __be16 rsvd;
1286 __be16 len;
1287 __be64 tstamp;
1288 __be64 rsvd1;
1289};
1290
1291struct cpl_l2t_write_req {
1292 WR_HDR;
1293 union opcode_tid ot;
1294 __be16 params;
1295 __be16 l2t_idx;
1296 __be16 vlan;
1297 u8 dst_mac[6];
1298};
1299
1300
1301#define L2T_W_INFO_S 2
1302#define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1303
1304#define L2T_W_PORT_S 8
1305#define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1306
1307#define L2T_W_NOREPLY_S 15
1308#define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1309#define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
1310
1311#define CPL_L2T_VLAN_NONE 0xfff
1312
1313struct cpl_l2t_write_rpl {
1314 union opcode_tid ot;
1315 u8 status;
1316 u8 rsvd[3];
1317};
1318
1319struct cpl_smt_write_req {
1320 WR_HDR;
1321 union opcode_tid ot;
1322 __be32 params;
1323 __be16 pfvf1;
1324 u8 src_mac1[6];
1325 __be16 pfvf0;
1326 u8 src_mac0[6];
1327};
1328
1329struct cpl_t6_smt_write_req {
1330 WR_HDR;
1331 union opcode_tid ot;
1332 __be32 params;
1333 __be64 tag;
1334 __be16 pfvf0;
1335 u8 src_mac0[6];
1336 __be32 local_ip;
1337 __be32 rsvd;
1338};
1339
1340struct cpl_smt_write_rpl {
1341 union opcode_tid ot;
1342 u8 status;
1343 u8 rsvd[3];
1344};
1345
1346
1347#define SMTW_OVLAN_IDX_S 16
1348#define SMTW_OVLAN_IDX_V(x) ((x) << SMTW_OVLAN_IDX_S)
1349
1350#define SMTW_IDX_S 20
1351#define SMTW_IDX_V(x) ((x) << SMTW_IDX_S)
1352
1353#define SMTW_NORPL_S 31
1354#define SMTW_NORPL_V(x) ((x) << SMTW_NORPL_S)
1355#define SMTW_NORPL_F SMTW_NORPL_V(1U)
1356
1357struct cpl_rdma_terminate {
1358 union opcode_tid ot;
1359 __be16 rsvd;
1360 __be16 len;
1361};
1362
1363struct cpl_sge_egr_update {
1364 __be32 opcode_qid;
1365 __be16 cidx;
1366 __be16 pidx;
1367};
1368
1369
1370#define EGR_QID_S 0
1371#define EGR_QID_M 0x1FFFF
1372#define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1373
1374
1375enum {
1376 FW_TYPE_CMD_RPL = 0,
1377 FW_TYPE_WR_RPL = 1,
1378 FW_TYPE_CQE = 2,
1379 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1380 FW_TYPE_RSSCPL = 4,
1381};
1382
1383struct cpl_fw4_pld {
1384 u8 opcode;
1385 u8 rsvd0[3];
1386 u8 type;
1387 u8 rsvd1;
1388 __be16 len;
1389 __be64 data;
1390 __be64 rsvd2;
1391};
1392
1393struct cpl_fw6_pld {
1394 u8 opcode;
1395 u8 rsvd[5];
1396 __be16 len;
1397 __be64 data[4];
1398};
1399
1400struct cpl_fw4_msg {
1401 u8 opcode;
1402 u8 type;
1403 __be16 rsvd0;
1404 __be32 rsvd1;
1405 __be64 data[2];
1406};
1407
1408struct cpl_fw4_ack {
1409 union opcode_tid ot;
1410 u8 credits;
1411 u8 rsvd0[2];
1412 u8 seq_vld;
1413 __be32 snd_nxt;
1414 __be32 snd_una;
1415 __be64 rsvd1;
1416};
1417
1418enum {
1419 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1,
1420 CPL_FW4_ACK_FLAGS_CH = 0x2,
1421 CPL_FW4_ACK_FLAGS_FLOWC = 0x4,
1422};
1423
1424struct cpl_fw6_msg {
1425 u8 opcode;
1426 u8 type;
1427 __be16 rsvd0;
1428 __be32 rsvd1;
1429 __be64 data[4];
1430};
1431
1432
1433enum {
1434 FW6_TYPE_CMD_RPL = 0,
1435 FW6_TYPE_WR_RPL = 1,
1436 FW6_TYPE_CQE = 2,
1437 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1438 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
1439};
1440
1441struct cpl_fw6_msg_ofld_connection_wr_rpl {
1442 __u64 cookie;
1443 __be32 tid;
1444 __u8 t_state;
1445 __u8 retval;
1446 __u8 rsvd[2];
1447};
1448
1449struct cpl_tx_data {
1450 union opcode_tid ot;
1451 __be32 len;
1452 __be32 rsvd;
1453 __be32 flags;
1454};
1455
1456
1457#define TX_FORCE_S 13
1458#define TX_FORCE_V(x) ((x) << TX_FORCE_S)
1459
1460#define T6_TX_FORCE_S 20
1461#define T6_TX_FORCE_V(x) ((x) << T6_TX_FORCE_S)
1462#define T6_TX_FORCE_F T6_TX_FORCE_V(1U)
1463
1464#define TX_URG_S 16
1465#define TX_URG_V(x) ((x) << TX_URG_S)
1466
1467#define TX_SHOVE_S 14
1468#define TX_SHOVE_V(x) ((x) << TX_SHOVE_S)
1469
1470#define TX_ULP_MODE_S 10
1471#define TX_ULP_MODE_M 0x7
1472#define TX_ULP_MODE_V(x) ((x) << TX_ULP_MODE_S)
1473#define TX_ULP_MODE_G(x) (((x) >> TX_ULP_MODE_S) & TX_ULP_MODE_M)
1474
1475enum {
1476 ULP_TX_MEM_READ = 2,
1477 ULP_TX_MEM_WRITE = 3,
1478 ULP_TX_PKT = 4
1479};
1480
1481enum {
1482 ULP_TX_SC_NOOP = 0x80,
1483 ULP_TX_SC_IMM = 0x81,
1484 ULP_TX_SC_DSGL = 0x82,
1485 ULP_TX_SC_ISGL = 0x83,
1486 ULP_TX_SC_MEMRD = 0x86
1487};
1488
1489#define ULPTX_CMD_S 24
1490#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1491
1492#define ULPTX_LEN16_S 0
1493#define ULPTX_LEN16_M 0xFF
1494#define ULPTX_LEN16_V(x) ((x) << ULPTX_LEN16_S)
1495
1496#define ULP_TX_SC_MORE_S 23
1497#define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
1498#define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
1499
1500struct ulptx_sge_pair {
1501 __be32 len[2];
1502 __be64 addr[2];
1503};
1504
1505struct ulptx_sgl {
1506 __be32 cmd_nsge;
1507 __be32 len0;
1508 __be64 addr0;
1509 struct ulptx_sge_pair sge[0];
1510};
1511
1512struct ulptx_idata {
1513 __be32 cmd_more;
1514 __be32 len;
1515};
1516
1517struct ulp_txpkt {
1518 __be32 cmd_dest;
1519 __be32 len;
1520};
1521
1522#define ULPTX_CMD_S 24
1523#define ULPTX_CMD_M 0xFF
1524#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1525
1526#define ULPTX_NSGE_S 0
1527#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1528
1529#define ULPTX_MORE_S 23
1530#define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1531#define ULPTX_MORE_F ULPTX_MORE_V(1U)
1532
1533#define ULP_TXPKT_DEST_S 16
1534#define ULP_TXPKT_DEST_M 0x3
1535#define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S)
1536
1537#define ULP_TXPKT_FID_S 4
1538#define ULP_TXPKT_FID_M 0x7ff
1539#define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S)
1540
1541#define ULP_TXPKT_RO_S 3
1542#define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S)
1543#define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U)
1544
1545enum cpl_tx_tnl_lso_type {
1546 TX_TNL_TYPE_OPAQUE,
1547 TX_TNL_TYPE_NVGRE,
1548 TX_TNL_TYPE_VXLAN,
1549 TX_TNL_TYPE_GENEVE,
1550};
1551
1552struct cpl_tx_tnl_lso {
1553 __be32 op_to_IpIdSplitOut;
1554 __be16 IpIdOffsetOut;
1555 __be16 UdpLenSetOut_to_TnlHdrLen;
1556 __be64 r1;
1557 __be32 Flow_to_TcpHdrLen;
1558 __be16 IpIdOffset;
1559 __be16 IpIdSplit_to_Mss;
1560 __be32 TCPSeqOffset;
1561 __be32 EthLenOffset_Size;
1562
1563};
1564
1565#define CPL_TX_TNL_LSO_OPCODE_S 24
1566#define CPL_TX_TNL_LSO_OPCODE_M 0xff
1567#define CPL_TX_TNL_LSO_OPCODE_V(x) ((x) << CPL_TX_TNL_LSO_OPCODE_S)
1568#define CPL_TX_TNL_LSO_OPCODE_G(x) \
1569 (((x) >> CPL_TX_TNL_LSO_OPCODE_S) & CPL_TX_TNL_LSO_OPCODE_M)
1570
1571#define CPL_TX_TNL_LSO_FIRST_S 23
1572#define CPL_TX_TNL_LSO_FIRST_M 0x1
1573#define CPL_TX_TNL_LSO_FIRST_V(x) ((x) << CPL_TX_TNL_LSO_FIRST_S)
1574#define CPL_TX_TNL_LSO_FIRST_G(x) \
1575 (((x) >> CPL_TX_TNL_LSO_FIRST_S) & CPL_TX_TNL_LSO_FIRST_M)
1576#define CPL_TX_TNL_LSO_FIRST_F CPL_TX_TNL_LSO_FIRST_V(1U)
1577
1578#define CPL_TX_TNL_LSO_LAST_S 22
1579#define CPL_TX_TNL_LSO_LAST_M 0x1
1580#define CPL_TX_TNL_LSO_LAST_V(x) ((x) << CPL_TX_TNL_LSO_LAST_S)
1581#define CPL_TX_TNL_LSO_LAST_G(x) \
1582 (((x) >> CPL_TX_TNL_LSO_LAST_S) & CPL_TX_TNL_LSO_LAST_M)
1583#define CPL_TX_TNL_LSO_LAST_F CPL_TX_TNL_LSO_LAST_V(1U)
1584
1585#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_S 21
1586#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_M 0x1
1587#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(x) \
1588 ((x) << CPL_TX_TNL_LSO_ETHHDRLENXOUT_S)
1589#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_G(x) \
1590 (((x) >> CPL_TX_TNL_LSO_ETHHDRLENXOUT_S) & \
1591 CPL_TX_TNL_LSO_ETHHDRLENXOUT_M)
1592#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_F CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(1U)
1593
1594#define CPL_TX_TNL_LSO_IPV6OUT_S 20
1595#define CPL_TX_TNL_LSO_IPV6OUT_M 0x1
1596#define CPL_TX_TNL_LSO_IPV6OUT_V(x) ((x) << CPL_TX_TNL_LSO_IPV6OUT_S)
1597#define CPL_TX_TNL_LSO_IPV6OUT_G(x) \
1598 (((x) >> CPL_TX_TNL_LSO_IPV6OUT_S) & CPL_TX_TNL_LSO_IPV6OUT_M)
1599#define CPL_TX_TNL_LSO_IPV6OUT_F CPL_TX_TNL_LSO_IPV6OUT_V(1U)
1600
1601#define CPL_TX_TNL_LSO_ETHHDRLEN_S 16
1602#define CPL_TX_TNL_LSO_ETHHDRLEN_M 0xf
1603#define CPL_TX_TNL_LSO_ETHHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_ETHHDRLEN_S)
1604#define CPL_TX_TNL_LSO_ETHHDRLEN_G(x) \
1605 (((x) >> CPL_TX_TNL_LSO_ETHHDRLEN_S) & CPL_TX_TNL_LSO_ETHHDRLEN_M)
1606
1607#define CPL_TX_TNL_LSO_IPHDRLEN_S 4
1608#define CPL_TX_TNL_LSO_IPHDRLEN_M 0xfff
1609#define CPL_TX_TNL_LSO_IPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLEN_S)
1610#define CPL_TX_TNL_LSO_IPHDRLEN_G(x) \
1611 (((x) >> CPL_TX_TNL_LSO_IPHDRLEN_S) & CPL_TX_TNL_LSO_IPHDRLEN_M)
1612
1613#define CPL_TX_TNL_LSO_TCPHDRLEN_S 0
1614#define CPL_TX_TNL_LSO_TCPHDRLEN_M 0xf
1615#define CPL_TX_TNL_LSO_TCPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TCPHDRLEN_S)
1616#define CPL_TX_TNL_LSO_TCPHDRLEN_G(x) \
1617 (((x) >> CPL_TX_TNL_LSO_TCPHDRLEN_S) & CPL_TX_TNL_LSO_TCPHDRLEN_M)
1618
1619#define CPL_TX_TNL_LSO_MSS_S 0
1620#define CPL_TX_TNL_LSO_MSS_M 0x3fff
1621#define CPL_TX_TNL_LSO_MSS_V(x) ((x) << CPL_TX_TNL_LSO_MSS_S)
1622#define CPL_TX_TNL_LSO_MSS_G(x) \
1623 (((x) >> CPL_TX_TNL_LSO_MSS_S) & CPL_TX_TNL_LSO_MSS_M)
1624
1625#define CPL_TX_TNL_LSO_SIZE_S 0
1626#define CPL_TX_TNL_LSO_SIZE_M 0xfffffff
1627#define CPL_TX_TNL_LSO_SIZE_V(x) ((x) << CPL_TX_TNL_LSO_SIZE_S)
1628#define CPL_TX_TNL_LSO_SIZE_G(x) \
1629 (((x) >> CPL_TX_TNL_LSO_SIZE_S) & CPL_TX_TNL_LSO_SIZE_M)
1630
1631#define CPL_TX_TNL_LSO_ETHHDRLENOUT_S 16
1632#define CPL_TX_TNL_LSO_ETHHDRLENOUT_M 0xf
1633#define CPL_TX_TNL_LSO_ETHHDRLENOUT_V(x) \
1634 ((x) << CPL_TX_TNL_LSO_ETHHDRLENOUT_S)
1635#define CPL_TX_TNL_LSO_ETHHDRLENOUT_G(x) \
1636 (((x) >> CPL_TX_TNL_LSO_ETHHDRLENOUT_S) & CPL_TX_TNL_LSO_ETHHDRLENOUT_M)
1637
1638#define CPL_TX_TNL_LSO_IPHDRLENOUT_S 4
1639#define CPL_TX_TNL_LSO_IPHDRLENOUT_M 0xfff
1640#define CPL_TX_TNL_LSO_IPHDRLENOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLENOUT_S)
1641#define CPL_TX_TNL_LSO_IPHDRLENOUT_G(x) \
1642 (((x) >> CPL_TX_TNL_LSO_IPHDRLENOUT_S) & CPL_TX_TNL_LSO_IPHDRLENOUT_M)
1643
1644#define CPL_TX_TNL_LSO_IPHDRCHKOUT_S 3
1645#define CPL_TX_TNL_LSO_IPHDRCHKOUT_M 0x1
1646#define CPL_TX_TNL_LSO_IPHDRCHKOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRCHKOUT_S)
1647#define CPL_TX_TNL_LSO_IPHDRCHKOUT_G(x) \
1648 (((x) >> CPL_TX_TNL_LSO_IPHDRCHKOUT_S) & CPL_TX_TNL_LSO_IPHDRCHKOUT_M)
1649#define CPL_TX_TNL_LSO_IPHDRCHKOUT_F CPL_TX_TNL_LSO_IPHDRCHKOUT_V(1U)
1650
1651#define CPL_TX_TNL_LSO_IPLENSETOUT_S 2
1652#define CPL_TX_TNL_LSO_IPLENSETOUT_M 0x1
1653#define CPL_TX_TNL_LSO_IPLENSETOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPLENSETOUT_S)
1654#define CPL_TX_TNL_LSO_IPLENSETOUT_G(x) \
1655 (((x) >> CPL_TX_TNL_LSO_IPLENSETOUT_S) & CPL_TX_TNL_LSO_IPLENSETOUT_M)
1656#define CPL_TX_TNL_LSO_IPLENSETOUT_F CPL_TX_TNL_LSO_IPLENSETOUT_V(1U)
1657
1658#define CPL_TX_TNL_LSO_IPIDINCOUT_S 1
1659#define CPL_TX_TNL_LSO_IPIDINCOUT_M 0x1
1660#define CPL_TX_TNL_LSO_IPIDINCOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPIDINCOUT_S)
1661#define CPL_TX_TNL_LSO_IPIDINCOUT_G(x) \
1662 (((x) >> CPL_TX_TNL_LSO_IPIDINCOUT_S) & CPL_TX_TNL_LSO_IPIDINCOUT_M)
1663#define CPL_TX_TNL_LSO_IPIDINCOUT_F CPL_TX_TNL_LSO_IPIDINCOUT_V(1U)
1664
1665#define CPL_TX_TNL_LSO_UDPCHKCLROUT_S 14
1666#define CPL_TX_TNL_LSO_UDPCHKCLROUT_M 0x1
1667#define CPL_TX_TNL_LSO_UDPCHKCLROUT_V(x) \
1668 ((x) << CPL_TX_TNL_LSO_UDPCHKCLROUT_S)
1669#define CPL_TX_TNL_LSO_UDPCHKCLROUT_G(x) \
1670 (((x) >> CPL_TX_TNL_LSO_UDPCHKCLROUT_S) & \
1671 CPL_TX_TNL_LSO_UDPCHKCLROUT_M)
1672#define CPL_TX_TNL_LSO_UDPCHKCLROUT_F CPL_TX_TNL_LSO_UDPCHKCLROUT_V(1U)
1673
1674#define CPL_TX_TNL_LSO_UDPLENSETOUT_S 15
1675#define CPL_TX_TNL_LSO_UDPLENSETOUT_M 0x1
1676#define CPL_TX_TNL_LSO_UDPLENSETOUT_V(x) \
1677 ((x) << CPL_TX_TNL_LSO_UDPLENSETOUT_S)
1678#define CPL_TX_TNL_LSO_UDPLENSETOUT_G(x) \
1679 (((x) >> CPL_TX_TNL_LSO_UDPLENSETOUT_S) & \
1680 CPL_TX_TNL_LSO_UDPLENSETOUT_M)
1681#define CPL_TX_TNL_LSO_UDPLENSETOUT_F CPL_TX_TNL_LSO_UDPLENSETOUT_V(1U)
1682
1683#define CPL_TX_TNL_LSO_TNLTYPE_S 12
1684#define CPL_TX_TNL_LSO_TNLTYPE_M 0x3
1685#define CPL_TX_TNL_LSO_TNLTYPE_V(x) ((x) << CPL_TX_TNL_LSO_TNLTYPE_S)
1686#define CPL_TX_TNL_LSO_TNLTYPE_G(x) \
1687 (((x) >> CPL_TX_TNL_LSO_TNLTYPE_S) & CPL_TX_TNL_LSO_TNLTYPE_M)
1688
1689#define S_CPL_TX_TNL_LSO_ETHHDRLEN 16
1690#define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf
1691#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN)
1692#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \
1693 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN)
1694
1695#define CPL_TX_TNL_LSO_TNLHDRLEN_S 0
1696#define CPL_TX_TNL_LSO_TNLHDRLEN_M 0xfff
1697#define CPL_TX_TNL_LSO_TNLHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TNLHDRLEN_S)
1698#define CPL_TX_TNL_LSO_TNLHDRLEN_G(x) \
1699 (((x) >> CPL_TX_TNL_LSO_TNLHDRLEN_S) & CPL_TX_TNL_LSO_TNLHDRLEN_M)
1700
1701#define CPL_TX_TNL_LSO_IPV6_S 20
1702#define CPL_TX_TNL_LSO_IPV6_M 0x1
1703#define CPL_TX_TNL_LSO_IPV6_V(x) ((x) << CPL_TX_TNL_LSO_IPV6_S)
1704#define CPL_TX_TNL_LSO_IPV6_G(x) \
1705 (((x) >> CPL_TX_TNL_LSO_IPV6_S) & CPL_TX_TNL_LSO_IPV6_M)
1706#define CPL_TX_TNL_LSO_IPV6_F CPL_TX_TNL_LSO_IPV6_V(1U)
1707
1708#define ULP_TX_SC_MORE_S 23
1709#define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
1710#define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
1711
1712struct ulp_mem_io {
1713 WR_HDR;
1714 __be32 cmd;
1715 __be32 len16;
1716 __be32 dlen;
1717 __be32 lock_addr;
1718};
1719
1720#define ULP_MEMIO_LOCK_S 31
1721#define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1722#define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1723
1724
1725#define ULP_MEMIO_ORDER_S 23
1726#define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1727#define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1728
1729#define T5_ULP_MEMIO_IMM_S 23
1730#define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1731#define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1732
1733#define T5_ULP_MEMIO_ORDER_S 22
1734#define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1735#define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
1736
1737#define T5_ULP_MEMIO_FID_S 4
1738#define T5_ULP_MEMIO_FID_M 0x7ff
1739#define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S)
1740
1741
1742#define ULP_MEMIO_ADDR_S 0
1743#define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1744
1745
1746#define ULP_MEMIO_DATA_LEN_S 0
1747#define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1748
1749#define ULPTX_NSGE_S 0
1750#define ULPTX_NSGE_M 0xFFFF
1751#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1752#define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M)
1753
1754struct ulptx_sc_memrd {
1755 __be32 cmd_to_len;
1756 __be32 addr;
1757};
1758
1759#define ULP_TXPKT_DATAMODIFY_S 23
1760#define ULP_TXPKT_DATAMODIFY_M 0x1
1761#define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S)
1762#define ULP_TXPKT_DATAMODIFY_G(x) \
1763 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M)
1764#define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U)
1765
1766#define ULP_TXPKT_CHANNELID_S 22
1767#define ULP_TXPKT_CHANNELID_M 0x1
1768#define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S)
1769#define ULP_TXPKT_CHANNELID_G(x) \
1770 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M)
1771#define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U)
1772
1773#define SCMD_SEQ_NO_CTRL_S 29
1774#define SCMD_SEQ_NO_CTRL_M 0x3
1775#define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S)
1776#define SCMD_SEQ_NO_CTRL_G(x) \
1777 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M)
1778
1779
1780#define SCMD_STATUS_PRESENT_S 28
1781#define SCMD_STATUS_PRESENT_M 0x1
1782#define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S)
1783#define SCMD_STATUS_PRESENT_G(x) \
1784 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M)
1785#define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U)
1786
1787
1788
1789
1790#define SCMD_PROTO_VERSION_S 24
1791#define SCMD_PROTO_VERSION_M 0xf
1792#define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S)
1793#define SCMD_PROTO_VERSION_G(x) \
1794 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M)
1795
1796
1797#define SCMD_ENC_DEC_CTRL_S 23
1798#define SCMD_ENC_DEC_CTRL_M 0x1
1799#define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S)
1800#define SCMD_ENC_DEC_CTRL_G(x) \
1801 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M)
1802#define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U)
1803
1804
1805#define SCMD_CIPH_AUTH_SEQ_CTRL_S 22
1806#define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1
1807#define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \
1808 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S)
1809#define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \
1810 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M)
1811#define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U)
1812
1813
1814
1815
1816#define SCMD_CIPH_MODE_S 18
1817#define SCMD_CIPH_MODE_M 0xf
1818#define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S)
1819#define SCMD_CIPH_MODE_G(x) \
1820 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M)
1821
1822
1823
1824
1825#define SCMD_AUTH_MODE_S 14
1826#define SCMD_AUTH_MODE_M 0xf
1827#define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S)
1828#define SCMD_AUTH_MODE_G(x) \
1829 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M)
1830
1831
1832
1833
1834#define SCMD_HMAC_CTRL_S 11
1835#define SCMD_HMAC_CTRL_M 0x7
1836#define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S)
1837#define SCMD_HMAC_CTRL_G(x) \
1838 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M)
1839
1840
1841#define SCMD_IV_SIZE_S 7
1842#define SCMD_IV_SIZE_M 0xf
1843#define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S)
1844#define SCMD_IV_SIZE_G(x) \
1845 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M)
1846
1847
1848#define SCMD_NUM_IVS_S 0
1849#define SCMD_NUM_IVS_M 0x7f
1850#define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S)
1851#define SCMD_NUM_IVS_G(x) \
1852 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M)
1853
1854
1855
1856
1857
1858
1859#define SCMD_ENB_DBGID_S 31
1860#define SCMD_ENB_DBGID_M 0x1
1861#define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S)
1862#define SCMD_ENB_DBGID_G(x) \
1863 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M)
1864
1865
1866#define SCMD_IV_GEN_CTRL_S 30
1867#define SCMD_IV_GEN_CTRL_M 0x1
1868#define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S)
1869#define SCMD_IV_GEN_CTRL_G(x) \
1870 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M)
1871#define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U)
1872
1873
1874#define SCMD_MORE_FRAGS_S 20
1875#define SCMD_MORE_FRAGS_M 0x1
1876#define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S)
1877#define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M)
1878
1879
1880#define SCMD_LAST_FRAG_S 19
1881#define SCMD_LAST_FRAG_M 0x1
1882#define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S)
1883#define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M)
1884
1885
1886#define SCMD_TLS_COMPPDU_S 18
1887#define SCMD_TLS_COMPPDU_M 0x1
1888#define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S)
1889#define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M)
1890
1891
1892#define SCMD_KEY_CTX_INLINE_S 17
1893#define SCMD_KEY_CTX_INLINE_M 0x1
1894#define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S)
1895#define SCMD_KEY_CTX_INLINE_G(x) \
1896 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M)
1897#define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U)
1898
1899
1900#define SCMD_TLS_FRAG_ENABLE_S 16
1901#define SCMD_TLS_FRAG_ENABLE_M 0x1
1902#define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S)
1903#define SCMD_TLS_FRAG_ENABLE_G(x) \
1904 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M)
1905#define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U)
1906
1907
1908
1909
1910
1911#define SCMD_MAC_ONLY_S 15
1912#define SCMD_MAC_ONLY_M 0x1
1913#define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S)
1914#define SCMD_MAC_ONLY_G(x) \
1915 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M)
1916#define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U)
1917
1918
1919
1920
1921#define SCMD_AADIVDROP_S 14
1922#define SCMD_AADIVDROP_M 0x1
1923#define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S)
1924#define SCMD_AADIVDROP_G(x) \
1925 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M)
1926#define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U)
1927
1928
1929
1930
1931#define SCMD_HDR_LEN_S 0
1932#define SCMD_HDR_LEN_M 0x3fff
1933#define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S)
1934#define SCMD_HDR_LEN_G(x) \
1935 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M)
1936
1937struct cpl_tx_sec_pdu {
1938 __be32 op_ivinsrtofst;
1939 __be32 pldlen;
1940 __be32 aadstart_cipherstop_hi;
1941 __be32 cipherstop_lo_authinsert;
1942 __be32 seqno_numivs;
1943 __be32 ivgen_hdrlen;
1944 __be64 scmd1;
1945};
1946
1947#define CPL_TX_SEC_PDU_OPCODE_S 24
1948#define CPL_TX_SEC_PDU_OPCODE_M 0xff
1949#define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S)
1950#define CPL_TX_SEC_PDU_OPCODE_G(x) \
1951 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M)
1952
1953
1954#define CPL_TX_SEC_PDU_RXCHID_S 22
1955#define CPL_TX_SEC_PDU_RXCHID_M 0x1
1956#define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S)
1957#define CPL_TX_SEC_PDU_RXCHID_G(x) \
1958 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M)
1959#define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U)
1960
1961
1962#define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21
1963#define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1
1964#define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S)
1965#define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \
1966 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M)
1967#define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U)
1968
1969
1970#define CPL_TX_SEC_PDU_ULPTXLPBK_S 20
1971#define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1
1972#define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S)
1973#define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \
1974 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M)
1975#define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U)
1976
1977
1978#define CPL_TX_SEC_PDU_CPLLEN_S 16
1979#define CPL_TX_SEC_PDU_CPLLEN_M 0xf
1980#define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S)
1981#define CPL_TX_SEC_PDU_CPLLEN_G(x) \
1982 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M)
1983
1984
1985#define CPL_TX_SEC_PDU_PLACEHOLDER_S 10
1986#define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1
1987#define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S)
1988#define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \
1989 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \
1990 CPL_TX_SEC_PDU_PLACEHOLDER_M)
1991
1992
1993#define CPL_TX_SEC_PDU_IVINSRTOFST_S 0
1994#define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff
1995#define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S)
1996#define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \
1997 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \
1998 CPL_TX_SEC_PDU_IVINSRTOFST_M)
1999
2000
2001
2002
2003#define CPL_TX_SEC_PDU_AADSTART_S 24
2004#define CPL_TX_SEC_PDU_AADSTART_M 0xff
2005#define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S)
2006#define CPL_TX_SEC_PDU_AADSTART_G(x) \
2007 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \
2008 CPL_TX_SEC_PDU_AADSTART_M)
2009
2010
2011
2012
2013#define CPL_TX_SEC_PDU_AADSTOP_S 15
2014#define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff
2015#define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S)
2016#define CPL_TX_SEC_PDU_AADSTOP_G(x) \
2017 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M)
2018
2019
2020
2021
2022#define CPL_TX_SEC_PDU_CIPHERSTART_S 5
2023#define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff
2024#define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S)
2025#define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \
2026 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \
2027 CPL_TX_SEC_PDU_CIPHERSTART_M)
2028
2029
2030
2031
2032#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0
2033#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f
2034#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \
2035 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S)
2036#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \
2037 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \
2038 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M)
2039
2040#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28
2041#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf
2042#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \
2043 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S)
2044#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \
2045 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \
2046 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M)
2047
2048
2049
2050
2051#define CPL_TX_SEC_PDU_AUTHSTART_S 18
2052#define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff
2053#define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S)
2054#define CPL_TX_SEC_PDU_AUTHSTART_G(x) \
2055 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \
2056 CPL_TX_SEC_PDU_AUTHSTART_M)
2057
2058
2059
2060
2061#define CPL_TX_SEC_PDU_AUTHSTOP_S 9
2062#define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff
2063#define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S)
2064#define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \
2065 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \
2066 CPL_TX_SEC_PDU_AUTHSTOP_M)
2067
2068
2069
2070
2071#define CPL_TX_SEC_PDU_AUTHINSERT_S 0
2072#define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff
2073#define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S)
2074#define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \
2075 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \
2076 CPL_TX_SEC_PDU_AUTHINSERT_M)
2077
2078struct cpl_rx_phys_dsgl {
2079 __be32 op_to_tid;
2080 __be32 pcirlxorder_to_noofsgentr;
2081 struct rss_header rss_hdr_int;
2082};
2083
2084#define CPL_RX_PHYS_DSGL_OPCODE_S 24
2085#define CPL_RX_PHYS_DSGL_OPCODE_M 0xff
2086#define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S)
2087#define CPL_RX_PHYS_DSGL_OPCODE_G(x) \
2088 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M)
2089
2090#define CPL_RX_PHYS_DSGL_ISRDMA_S 23
2091#define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1
2092#define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S)
2093#define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \
2094 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M)
2095#define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U)
2096
2097#define CPL_RX_PHYS_DSGL_RSVD1_S 20
2098#define CPL_RX_PHYS_DSGL_RSVD1_M 0x7
2099#define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S)
2100#define CPL_RX_PHYS_DSGL_RSVD1_G(x) \
2101 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \
2102 CPL_RX_PHYS_DSGL_RSVD1_M)
2103
2104#define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31
2105#define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1
2106#define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \
2107 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S)
2108#define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \
2109 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \
2110 CPL_RX_PHYS_DSGL_PCIRLXORDER_M)
2111#define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U)
2112
2113#define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30
2114#define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1
2115#define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \
2116 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S)
2117#define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \
2118 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \
2119 CPL_RX_PHYS_DSGL_PCINOSNOOP_M)
2120
2121#define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U)
2122
2123#define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29
2124#define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1
2125#define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \
2126 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S)
2127#define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \
2128 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \
2129 CPL_RX_PHYS_DSGL_PCITPHNTENB_M)
2130#define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U)
2131
2132#define CPL_RX_PHYS_DSGL_PCITPHNT_S 27
2133#define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3
2134#define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S)
2135#define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \
2136 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \
2137 CPL_RX_PHYS_DSGL_PCITPHNT_M)
2138
2139#define CPL_RX_PHYS_DSGL_DCAID_S 16
2140#define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff
2141#define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S)
2142#define CPL_RX_PHYS_DSGL_DCAID_G(x) \
2143 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \
2144 CPL_RX_PHYS_DSGL_DCAID_M)
2145
2146#define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0
2147#define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff
2148#define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \
2149 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S)
2150#define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \
2151 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \
2152 CPL_RX_PHYS_DSGL_NOOFSGENTR_M)
2153
2154struct cpl_rx_mps_pkt {
2155 __be32 op_to_r1_hi;
2156 __be32 r1_lo_length;
2157};
2158
2159#define CPL_RX_MPS_PKT_OP_S 24
2160#define CPL_RX_MPS_PKT_OP_M 0xff
2161#define CPL_RX_MPS_PKT_OP_V(x) ((x) << CPL_RX_MPS_PKT_OP_S)
2162#define CPL_RX_MPS_PKT_OP_G(x) \
2163 (((x) >> CPL_RX_MPS_PKT_OP_S) & CPL_RX_MPS_PKT_OP_M)
2164
2165#define CPL_RX_MPS_PKT_TYPE_S 20
2166#define CPL_RX_MPS_PKT_TYPE_M 0xf
2167#define CPL_RX_MPS_PKT_TYPE_V(x) ((x) << CPL_RX_MPS_PKT_TYPE_S)
2168#define CPL_RX_MPS_PKT_TYPE_G(x) \
2169 (((x) >> CPL_RX_MPS_PKT_TYPE_S) & CPL_RX_MPS_PKT_TYPE_M)
2170
2171enum {
2172 X_CPL_RX_MPS_PKT_TYPE_PAUSE = 1 << 0,
2173 X_CPL_RX_MPS_PKT_TYPE_PPP = 1 << 1,
2174 X_CPL_RX_MPS_PKT_TYPE_QFC = 1 << 2,
2175 X_CPL_RX_MPS_PKT_TYPE_PTP = 1 << 3
2176};
2177
2178struct cpl_srq_table_req {
2179 WR_HDR;
2180 union opcode_tid ot;
2181 __u8 status;
2182 __u8 rsvd[2];
2183 __u8 idx;
2184 __be64 rsvd_pdid;
2185 __be32 qlen_qbase;
2186 __be16 cur_msn;
2187 __be16 max_msn;
2188};
2189
2190struct cpl_srq_table_rpl {
2191 union opcode_tid ot;
2192 __u8 status;
2193 __u8 rsvd[2];
2194 __u8 idx;
2195 __be64 rsvd_pdid;
2196 __be32 qlen_qbase;
2197 __be16 cur_msn;
2198 __be16 max_msn;
2199};
2200
2201
2202#define SRQT_QLEN_S 28
2203#define SRQT_QLEN_M 0xF
2204#define SRQT_QLEN_V(x) ((x) << SRQT_QLEN_S)
2205#define SRQT_QLEN_G(x) (((x) >> SRQT_QLEN_S) & SRQT_QLEN_M)
2206
2207#define SRQT_QBASE_S 0
2208#define SRQT_QBASE_M 0x3FFFFFF
2209#define SRQT_QBASE_V(x) ((x) << SRQT_QBASE_S)
2210#define SRQT_QBASE_G(x) (((x) >> SRQT_QBASE_S) & SRQT_QBASE_M)
2211
2212#define SRQT_PDID_S 0
2213#define SRQT_PDID_M 0xFF
2214#define SRQT_PDID_V(x) ((x) << SRQT_PDID_S)
2215#define SRQT_PDID_G(x) (((x) >> SRQT_PDID_S) & SRQT_PDID_M)
2216
2217#define SRQT_IDX_S 0
2218#define SRQT_IDX_M 0xF
2219#define SRQT_IDX_V(x) ((x) << SRQT_IDX_S)
2220#define SRQT_IDX_G(x) (((x) >> SRQT_IDX_S) & SRQT_IDX_M)
2221
2222struct cpl_tx_tls_sfo {
2223 __be32 op_to_seg_len;
2224 __be32 pld_len;
2225 __be32 type_protover;
2226 __be32 r1_lo;
2227 __be32 seqno_numivs;
2228 __be32 ivgen_hdrlen;
2229 __be64 scmd1;
2230};
2231
2232
2233#define CPL_TX_TLS_SFO_OPCODE_S 24
2234#define CPL_TX_TLS_SFO_OPCODE_V(x) ((x) << CPL_TX_TLS_SFO_OPCODE_S)
2235
2236#define CPL_TX_TLS_SFO_DATA_TYPE_S 20
2237#define CPL_TX_TLS_SFO_DATA_TYPE_V(x) ((x) << CPL_TX_TLS_SFO_DATA_TYPE_S)
2238
2239#define CPL_TX_TLS_SFO_CPL_LEN_S 16
2240#define CPL_TX_TLS_SFO_CPL_LEN_V(x) ((x) << CPL_TX_TLS_SFO_CPL_LEN_S)
2241
2242#define CPL_TX_TLS_SFO_SEG_LEN_S 0
2243#define CPL_TX_TLS_SFO_SEG_LEN_M 0xffff
2244#define CPL_TX_TLS_SFO_SEG_LEN_V(x) ((x) << CPL_TX_TLS_SFO_SEG_LEN_S)
2245#define CPL_TX_TLS_SFO_SEG_LEN_G(x) \
2246 (((x) >> CPL_TX_TLS_SFO_SEG_LEN_S) & CPL_TX_TLS_SFO_SEG_LEN_M)
2247
2248#define CPL_TX_TLS_SFO_TYPE_S 24
2249#define CPL_TX_TLS_SFO_TYPE_M 0xff
2250#define CPL_TX_TLS_SFO_TYPE_V(x) ((x) << CPL_TX_TLS_SFO_TYPE_S)
2251#define CPL_TX_TLS_SFO_TYPE_G(x) \
2252 (((x) >> CPL_TX_TLS_SFO_TYPE_S) & CPL_TX_TLS_SFO_TYPE_M)
2253
2254#define CPL_TX_TLS_SFO_PROTOVER_S 8
2255#define CPL_TX_TLS_SFO_PROTOVER_M 0xffff
2256#define CPL_TX_TLS_SFO_PROTOVER_V(x) ((x) << CPL_TX_TLS_SFO_PROTOVER_S)
2257#define CPL_TX_TLS_SFO_PROTOVER_G(x) \
2258 (((x) >> CPL_TX_TLS_SFO_PROTOVER_S) & CPL_TX_TLS_SFO_PROTOVER_M)
2259
2260struct cpl_tls_data {
2261 struct rss_header rsshdr;
2262 union opcode_tid ot;
2263 __be32 length_pkd;
2264 __be32 seq;
2265 __be32 r1;
2266};
2267
2268#define CPL_TLS_DATA_OPCODE_S 24
2269#define CPL_TLS_DATA_OPCODE_M 0xff
2270#define CPL_TLS_DATA_OPCODE_V(x) ((x) << CPL_TLS_DATA_OPCODE_S)
2271#define CPL_TLS_DATA_OPCODE_G(x) \
2272 (((x) >> CPL_TLS_DATA_OPCODE_S) & CPL_TLS_DATA_OPCODE_M)
2273
2274#define CPL_TLS_DATA_TID_S 0
2275#define CPL_TLS_DATA_TID_M 0xffffff
2276#define CPL_TLS_DATA_TID_V(x) ((x) << CPL_TLS_DATA_TID_S)
2277#define CPL_TLS_DATA_TID_G(x) \
2278 (((x) >> CPL_TLS_DATA_TID_S) & CPL_TLS_DATA_TID_M)
2279
2280#define CPL_TLS_DATA_LENGTH_S 0
2281#define CPL_TLS_DATA_LENGTH_M 0xffff
2282#define CPL_TLS_DATA_LENGTH_V(x) ((x) << CPL_TLS_DATA_LENGTH_S)
2283#define CPL_TLS_DATA_LENGTH_G(x) \
2284 (((x) >> CPL_TLS_DATA_LENGTH_S) & CPL_TLS_DATA_LENGTH_M)
2285
2286struct cpl_rx_tls_cmp {
2287 struct rss_header rsshdr;
2288 union opcode_tid ot;
2289 __be32 pdulength_length;
2290 __be32 seq;
2291 __be32 ddp_report;
2292 __be32 r;
2293 __be32 ddp_valid;
2294};
2295
2296#define CPL_RX_TLS_CMP_OPCODE_S 24
2297#define CPL_RX_TLS_CMP_OPCODE_M 0xff
2298#define CPL_RX_TLS_CMP_OPCODE_V(x) ((x) << CPL_RX_TLS_CMP_OPCODE_S)
2299#define CPL_RX_TLS_CMP_OPCODE_G(x) \
2300 (((x) >> CPL_RX_TLS_CMP_OPCODE_S) & CPL_RX_TLS_CMP_OPCODE_M)
2301
2302#define CPL_RX_TLS_CMP_TID_S 0
2303#define CPL_RX_TLS_CMP_TID_M 0xffffff
2304#define CPL_RX_TLS_CMP_TID_V(x) ((x) << CPL_RX_TLS_CMP_TID_S)
2305#define CPL_RX_TLS_CMP_TID_G(x) \
2306 (((x) >> CPL_RX_TLS_CMP_TID_S) & CPL_RX_TLS_CMP_TID_M)
2307
2308#define CPL_RX_TLS_CMP_PDULENGTH_S 16
2309#define CPL_RX_TLS_CMP_PDULENGTH_M 0xffff
2310#define CPL_RX_TLS_CMP_PDULENGTH_V(x) ((x) << CPL_RX_TLS_CMP_PDULENGTH_S)
2311#define CPL_RX_TLS_CMP_PDULENGTH_G(x) \
2312 (((x) >> CPL_RX_TLS_CMP_PDULENGTH_S) & CPL_RX_TLS_CMP_PDULENGTH_M)
2313
2314#define CPL_RX_TLS_CMP_LENGTH_S 0
2315#define CPL_RX_TLS_CMP_LENGTH_M 0xffff
2316#define CPL_RX_TLS_CMP_LENGTH_V(x) ((x) << CPL_RX_TLS_CMP_LENGTH_S)
2317#define CPL_RX_TLS_CMP_LENGTH_G(x) \
2318 (((x) >> CPL_RX_TLS_CMP_LENGTH_S) & CPL_RX_TLS_CMP_LENGTH_M)
2319#endif
2320
