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6#include "i40e.h"
7#include "i40e_diag.h"
8#include "i40e_txrx_common.h"
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34struct i40e_stats {
35 char stat_string[ETH_GSTRING_LEN];
36 int sizeof_stat;
37 int stat_offset;
38};
39
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43
44#define I40E_STAT(_type, _name, _stat) { \
45 .stat_string = _name, \
46 .sizeof_stat = FIELD_SIZEOF(_type, _stat), \
47 .stat_offset = offsetof(_type, _stat) \
48}
49
50
51
52
53#define I40E_NETDEV_STAT(_net_stat) \
54 I40E_STAT(struct rtnl_link_stats64, #_net_stat, _net_stat)
55
56
57#define I40E_QUEUE_STAT(_name, _stat) \
58 I40E_STAT(struct i40e_ring, _name, _stat)
59
60
61static const struct i40e_stats i40e_gstrings_queue_stats[] = {
62 I40E_QUEUE_STAT("%s-%u.packets", stats.packets),
63 I40E_QUEUE_STAT("%s-%u.bytes", stats.bytes),
64};
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75
76static void
77i40e_add_one_ethtool_stat(u64 *data, void *pointer,
78 const struct i40e_stats *stat)
79{
80 char *p;
81
82 if (!pointer) {
83
84
85
86 *data = 0;
87 return;
88 }
89
90 p = (char *)pointer + stat->stat_offset;
91 switch (stat->sizeof_stat) {
92 case sizeof(u64):
93 *data = *((u64 *)p);
94 break;
95 case sizeof(u32):
96 *data = *((u32 *)p);
97 break;
98 case sizeof(u16):
99 *data = *((u16 *)p);
100 break;
101 case sizeof(u8):
102 *data = *((u8 *)p);
103 break;
104 default:
105 WARN_ONCE(1, "unexpected stat size for %s",
106 stat->stat_string);
107 *data = 0;
108 }
109}
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123
124static void
125__i40e_add_ethtool_stats(u64 **data, void *pointer,
126 const struct i40e_stats stats[],
127 const unsigned int size)
128{
129 unsigned int i;
130
131 for (i = 0; i < size; i++)
132 i40e_add_one_ethtool_stat((*data)++, pointer, &stats[i]);
133}
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148#define i40e_add_ethtool_stats(data, pointer, stats) \
149 __i40e_add_ethtool_stats(data, pointer, stats, ARRAY_SIZE(stats))
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165static void
166i40e_add_queue_stats(u64 **data, struct i40e_ring *ring)
167{
168 const unsigned int size = ARRAY_SIZE(i40e_gstrings_queue_stats);
169 const struct i40e_stats *stats = i40e_gstrings_queue_stats;
170 unsigned int start;
171 unsigned int i;
172
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176
177
178 do {
179 start = !ring ? 0 : u64_stats_fetch_begin_irq(&ring->syncp);
180 for (i = 0; i < size; i++) {
181 i40e_add_one_ethtool_stat(&(*data)[i], ring,
182 &stats[i]);
183 }
184 } while (ring && u64_stats_fetch_retry_irq(&ring->syncp, start));
185
186
187 *data += size;
188}
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199static void __i40e_add_stat_strings(u8 **p, const struct i40e_stats stats[],
200 const unsigned int size, ...)
201{
202 unsigned int i;
203
204 for (i = 0; i < size; i++) {
205 va_list args;
206
207 va_start(args, size);
208 vsnprintf(*p, ETH_GSTRING_LEN, stats[i].stat_string, args);
209 *p += ETH_GSTRING_LEN;
210 va_end(args);
211 }
212}
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226#define i40e_add_stat_strings(p, stats, ...) \
227 __i40e_add_stat_strings(p, stats, ARRAY_SIZE(stats), ## __VA_ARGS__)
228
229#define I40E_PF_STAT(_name, _stat) \
230 I40E_STAT(struct i40e_pf, _name, _stat)
231#define I40E_VSI_STAT(_name, _stat) \
232 I40E_STAT(struct i40e_vsi, _name, _stat)
233#define I40E_VEB_STAT(_name, _stat) \
234 I40E_STAT(struct i40e_veb, _name, _stat)
235#define I40E_PFC_STAT(_name, _stat) \
236 I40E_STAT(struct i40e_pfc_stats, _name, _stat)
237#define I40E_QUEUE_STAT(_name, _stat) \
238 I40E_STAT(struct i40e_ring, _name, _stat)
239
240static const struct i40e_stats i40e_gstrings_net_stats[] = {
241 I40E_NETDEV_STAT(rx_packets),
242 I40E_NETDEV_STAT(tx_packets),
243 I40E_NETDEV_STAT(rx_bytes),
244 I40E_NETDEV_STAT(tx_bytes),
245 I40E_NETDEV_STAT(rx_errors),
246 I40E_NETDEV_STAT(tx_errors),
247 I40E_NETDEV_STAT(rx_dropped),
248 I40E_NETDEV_STAT(tx_dropped),
249 I40E_NETDEV_STAT(collisions),
250 I40E_NETDEV_STAT(rx_length_errors),
251 I40E_NETDEV_STAT(rx_crc_errors),
252};
253
254static const struct i40e_stats i40e_gstrings_veb_stats[] = {
255 I40E_VEB_STAT("veb.rx_bytes", stats.rx_bytes),
256 I40E_VEB_STAT("veb.tx_bytes", stats.tx_bytes),
257 I40E_VEB_STAT("veb.rx_unicast", stats.rx_unicast),
258 I40E_VEB_STAT("veb.tx_unicast", stats.tx_unicast),
259 I40E_VEB_STAT("veb.rx_multicast", stats.rx_multicast),
260 I40E_VEB_STAT("veb.tx_multicast", stats.tx_multicast),
261 I40E_VEB_STAT("veb.rx_broadcast", stats.rx_broadcast),
262 I40E_VEB_STAT("veb.tx_broadcast", stats.tx_broadcast),
263 I40E_VEB_STAT("veb.rx_discards", stats.rx_discards),
264 I40E_VEB_STAT("veb.tx_discards", stats.tx_discards),
265 I40E_VEB_STAT("veb.tx_errors", stats.tx_errors),
266 I40E_VEB_STAT("veb.rx_unknown_protocol", stats.rx_unknown_protocol),
267};
268
269static const struct i40e_stats i40e_gstrings_veb_tc_stats[] = {
270 I40E_VEB_STAT("veb.tc_%u_tx_packets", tc_stats.tc_tx_packets),
271 I40E_VEB_STAT("veb.tc_%u_tx_bytes", tc_stats.tc_tx_bytes),
272 I40E_VEB_STAT("veb.tc_%u_rx_packets", tc_stats.tc_rx_packets),
273 I40E_VEB_STAT("veb.tc_%u_rx_bytes", tc_stats.tc_rx_bytes),
274};
275
276static const struct i40e_stats i40e_gstrings_misc_stats[] = {
277 I40E_VSI_STAT("rx_unicast", eth_stats.rx_unicast),
278 I40E_VSI_STAT("tx_unicast", eth_stats.tx_unicast),
279 I40E_VSI_STAT("rx_multicast", eth_stats.rx_multicast),
280 I40E_VSI_STAT("tx_multicast", eth_stats.tx_multicast),
281 I40E_VSI_STAT("rx_broadcast", eth_stats.rx_broadcast),
282 I40E_VSI_STAT("tx_broadcast", eth_stats.tx_broadcast),
283 I40E_VSI_STAT("rx_unknown_protocol", eth_stats.rx_unknown_protocol),
284 I40E_VSI_STAT("tx_linearize", tx_linearize),
285 I40E_VSI_STAT("tx_force_wb", tx_force_wb),
286 I40E_VSI_STAT("tx_busy", tx_busy),
287 I40E_VSI_STAT("rx_alloc_fail", rx_buf_failed),
288 I40E_VSI_STAT("rx_pg_alloc_fail", rx_page_failed),
289};
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301static const struct i40e_stats i40e_gstrings_stats[] = {
302 I40E_PF_STAT("port.rx_bytes", stats.eth.rx_bytes),
303 I40E_PF_STAT("port.tx_bytes", stats.eth.tx_bytes),
304 I40E_PF_STAT("port.rx_unicast", stats.eth.rx_unicast),
305 I40E_PF_STAT("port.tx_unicast", stats.eth.tx_unicast),
306 I40E_PF_STAT("port.rx_multicast", stats.eth.rx_multicast),
307 I40E_PF_STAT("port.tx_multicast", stats.eth.tx_multicast),
308 I40E_PF_STAT("port.rx_broadcast", stats.eth.rx_broadcast),
309 I40E_PF_STAT("port.tx_broadcast", stats.eth.tx_broadcast),
310 I40E_PF_STAT("port.tx_errors", stats.eth.tx_errors),
311 I40E_PF_STAT("port.rx_dropped", stats.eth.rx_discards),
312 I40E_PF_STAT("port.tx_dropped_link_down", stats.tx_dropped_link_down),
313 I40E_PF_STAT("port.rx_crc_errors", stats.crc_errors),
314 I40E_PF_STAT("port.illegal_bytes", stats.illegal_bytes),
315 I40E_PF_STAT("port.mac_local_faults", stats.mac_local_faults),
316 I40E_PF_STAT("port.mac_remote_faults", stats.mac_remote_faults),
317 I40E_PF_STAT("port.tx_timeout", tx_timeout_count),
318 I40E_PF_STAT("port.rx_csum_bad", hw_csum_rx_error),
319 I40E_PF_STAT("port.rx_length_errors", stats.rx_length_errors),
320 I40E_PF_STAT("port.link_xon_rx", stats.link_xon_rx),
321 I40E_PF_STAT("port.link_xoff_rx", stats.link_xoff_rx),
322 I40E_PF_STAT("port.link_xon_tx", stats.link_xon_tx),
323 I40E_PF_STAT("port.link_xoff_tx", stats.link_xoff_tx),
324 I40E_PF_STAT("port.rx_size_64", stats.rx_size_64),
325 I40E_PF_STAT("port.rx_size_127", stats.rx_size_127),
326 I40E_PF_STAT("port.rx_size_255", stats.rx_size_255),
327 I40E_PF_STAT("port.rx_size_511", stats.rx_size_511),
328 I40E_PF_STAT("port.rx_size_1023", stats.rx_size_1023),
329 I40E_PF_STAT("port.rx_size_1522", stats.rx_size_1522),
330 I40E_PF_STAT("port.rx_size_big", stats.rx_size_big),
331 I40E_PF_STAT("port.tx_size_64", stats.tx_size_64),
332 I40E_PF_STAT("port.tx_size_127", stats.tx_size_127),
333 I40E_PF_STAT("port.tx_size_255", stats.tx_size_255),
334 I40E_PF_STAT("port.tx_size_511", stats.tx_size_511),
335 I40E_PF_STAT("port.tx_size_1023", stats.tx_size_1023),
336 I40E_PF_STAT("port.tx_size_1522", stats.tx_size_1522),
337 I40E_PF_STAT("port.tx_size_big", stats.tx_size_big),
338 I40E_PF_STAT("port.rx_undersize", stats.rx_undersize),
339 I40E_PF_STAT("port.rx_fragments", stats.rx_fragments),
340 I40E_PF_STAT("port.rx_oversize", stats.rx_oversize),
341 I40E_PF_STAT("port.rx_jabber", stats.rx_jabber),
342 I40E_PF_STAT("port.VF_admin_queue_requests", vf_aq_requests),
343 I40E_PF_STAT("port.arq_overflows", arq_overflows),
344 I40E_PF_STAT("port.tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
345 I40E_PF_STAT("port.rx_hwtstamp_cleared", rx_hwtstamp_cleared),
346 I40E_PF_STAT("port.tx_hwtstamp_skipped", tx_hwtstamp_skipped),
347 I40E_PF_STAT("port.fdir_flush_cnt", fd_flush_cnt),
348 I40E_PF_STAT("port.fdir_atr_match", stats.fd_atr_match),
349 I40E_PF_STAT("port.fdir_atr_tunnel_match", stats.fd_atr_tunnel_match),
350 I40E_PF_STAT("port.fdir_atr_status", stats.fd_atr_status),
351 I40E_PF_STAT("port.fdir_sb_match", stats.fd_sb_match),
352 I40E_PF_STAT("port.fdir_sb_status", stats.fd_sb_status),
353
354
355 I40E_PF_STAT("port.tx_lpi_status", stats.tx_lpi_status),
356 I40E_PF_STAT("port.rx_lpi_status", stats.rx_lpi_status),
357 I40E_PF_STAT("port.tx_lpi_count", stats.tx_lpi_count),
358 I40E_PF_STAT("port.rx_lpi_count", stats.rx_lpi_count),
359};
360
361struct i40e_pfc_stats {
362 u64 priority_xon_rx;
363 u64 priority_xoff_rx;
364 u64 priority_xon_tx;
365 u64 priority_xoff_tx;
366 u64 priority_xon_2_xoff;
367};
368
369static const struct i40e_stats i40e_gstrings_pfc_stats[] = {
370 I40E_PFC_STAT("port.tx_priority_%u_xon_tx", priority_xon_tx),
371 I40E_PFC_STAT("port.tx_priority_%u_xoff_tx", priority_xoff_tx),
372 I40E_PFC_STAT("port.rx_priority_%u_xon_rx", priority_xon_rx),
373 I40E_PFC_STAT("port.rx_priority_%u_xoff_rx", priority_xoff_rx),
374 I40E_PFC_STAT("port.rx_priority_%u_xon_2_xoff", priority_xon_2_xoff),
375};
376
377#define I40E_NETDEV_STATS_LEN ARRAY_SIZE(i40e_gstrings_net_stats)
378
379#define I40E_MISC_STATS_LEN ARRAY_SIZE(i40e_gstrings_misc_stats)
380
381#define I40E_VSI_STATS_LEN (I40E_NETDEV_STATS_LEN + I40E_MISC_STATS_LEN)
382
383#define I40E_PFC_STATS_LEN (ARRAY_SIZE(i40e_gstrings_pfc_stats) * \
384 I40E_MAX_USER_PRIORITY)
385
386#define I40E_VEB_STATS_LEN (ARRAY_SIZE(i40e_gstrings_veb_stats) + \
387 (ARRAY_SIZE(i40e_gstrings_veb_tc_stats) * \
388 I40E_MAX_TRAFFIC_CLASS))
389
390#define I40E_GLOBAL_STATS_LEN ARRAY_SIZE(i40e_gstrings_stats)
391
392#define I40E_PF_STATS_LEN (I40E_GLOBAL_STATS_LEN + \
393 I40E_PFC_STATS_LEN + \
394 I40E_VEB_STATS_LEN + \
395 I40E_VSI_STATS_LEN)
396
397
398#define I40E_QUEUE_STATS_LEN ARRAY_SIZE(i40e_gstrings_queue_stats)
399
400enum i40e_ethtool_test_id {
401 I40E_ETH_TEST_REG = 0,
402 I40E_ETH_TEST_EEPROM,
403 I40E_ETH_TEST_INTR,
404 I40E_ETH_TEST_LINK,
405};
406
407static const char i40e_gstrings_test[][ETH_GSTRING_LEN] = {
408 "Register test (offline)",
409 "Eeprom test (offline)",
410 "Interrupt test (offline)",
411 "Link test (on/offline)"
412};
413
414#define I40E_TEST_LEN (sizeof(i40e_gstrings_test) / ETH_GSTRING_LEN)
415
416struct i40e_priv_flags {
417 char flag_string[ETH_GSTRING_LEN];
418 u64 flag;
419 bool read_only;
420};
421
422#define I40E_PRIV_FLAG(_name, _flag, _read_only) { \
423 .flag_string = _name, \
424 .flag = _flag, \
425 .read_only = _read_only, \
426}
427
428static const struct i40e_priv_flags i40e_gstrings_priv_flags[] = {
429
430 I40E_PRIV_FLAG("MFP", I40E_FLAG_MFP_ENABLED, 1),
431 I40E_PRIV_FLAG("LinkPolling", I40E_FLAG_LINK_POLLING_ENABLED, 0),
432 I40E_PRIV_FLAG("flow-director-atr", I40E_FLAG_FD_ATR_ENABLED, 0),
433 I40E_PRIV_FLAG("veb-stats", I40E_FLAG_VEB_STATS_ENABLED, 0),
434 I40E_PRIV_FLAG("hw-atr-eviction", I40E_FLAG_HW_ATR_EVICT_ENABLED, 0),
435 I40E_PRIV_FLAG("link-down-on-close",
436 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED, 0),
437 I40E_PRIV_FLAG("legacy-rx", I40E_FLAG_LEGACY_RX, 0),
438 I40E_PRIV_FLAG("disable-source-pruning",
439 I40E_FLAG_SOURCE_PRUNING_DISABLED, 0),
440 I40E_PRIV_FLAG("disable-fw-lldp", I40E_FLAG_DISABLE_FW_LLDP, 0),
441 I40E_PRIV_FLAG("rs-fec", I40E_FLAG_RS_FEC, 0),
442 I40E_PRIV_FLAG("base-r-fec", I40E_FLAG_BASE_R_FEC, 0),
443};
444
445#define I40E_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gstrings_priv_flags)
446
447
448static const struct i40e_priv_flags i40e_gl_gstrings_priv_flags[] = {
449 I40E_PRIV_FLAG("vf-true-promisc-support",
450 I40E_FLAG_TRUE_PROMISC_SUPPORT, 0),
451};
452
453#define I40E_GL_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gl_gstrings_priv_flags)
454
455
456
457
458
459static void i40e_partition_setting_complaint(struct i40e_pf *pf)
460{
461 dev_info(&pf->pdev->dev,
462 "The link settings are allowed to be changed only from the first partition of a given port. Please switch to the first partition in order to change the setting.\n");
463}
464
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468
469
470
471static void i40e_phy_type_to_ethtool(struct i40e_pf *pf,
472 struct ethtool_link_ksettings *ks)
473{
474 struct i40e_link_status *hw_link_info = &pf->hw.phy.link_info;
475 u64 phy_types = pf->hw.phy.phy_types;
476
477 ethtool_link_ksettings_zero_link_mode(ks, supported);
478 ethtool_link_ksettings_zero_link_mode(ks, advertising);
479
480 if (phy_types & I40E_CAP_PHY_TYPE_SGMII) {
481 ethtool_link_ksettings_add_link_mode(ks, supported,
482 1000baseT_Full);
483 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
484 ethtool_link_ksettings_add_link_mode(ks, advertising,
485 1000baseT_Full);
486 if (pf->hw_features & I40E_HW_100M_SGMII_CAPABLE) {
487 ethtool_link_ksettings_add_link_mode(ks, supported,
488 100baseT_Full);
489 ethtool_link_ksettings_add_link_mode(ks, advertising,
490 100baseT_Full);
491 }
492 }
493 if (phy_types & I40E_CAP_PHY_TYPE_XAUI ||
494 phy_types & I40E_CAP_PHY_TYPE_XFI ||
495 phy_types & I40E_CAP_PHY_TYPE_SFI ||
496 phy_types & I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU ||
497 phy_types & I40E_CAP_PHY_TYPE_10GBASE_AOC) {
498 ethtool_link_ksettings_add_link_mode(ks, supported,
499 10000baseT_Full);
500 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
501 ethtool_link_ksettings_add_link_mode(ks, advertising,
502 10000baseT_Full);
503 }
504 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_T) {
505 ethtool_link_ksettings_add_link_mode(ks, supported,
506 10000baseT_Full);
507 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
508 ethtool_link_ksettings_add_link_mode(ks, advertising,
509 10000baseT_Full);
510 }
511 if (phy_types & I40E_CAP_PHY_TYPE_2_5GBASE_T) {
512 ethtool_link_ksettings_add_link_mode(ks, supported,
513 2500baseT_Full);
514 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_2_5GB)
515 ethtool_link_ksettings_add_link_mode(ks, advertising,
516 2500baseT_Full);
517 }
518 if (phy_types & I40E_CAP_PHY_TYPE_5GBASE_T) {
519 ethtool_link_ksettings_add_link_mode(ks, supported,
520 5000baseT_Full);
521 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_5GB)
522 ethtool_link_ksettings_add_link_mode(ks, advertising,
523 5000baseT_Full);
524 }
525 if (phy_types & I40E_CAP_PHY_TYPE_XLAUI ||
526 phy_types & I40E_CAP_PHY_TYPE_XLPPI ||
527 phy_types & I40E_CAP_PHY_TYPE_40GBASE_AOC)
528 ethtool_link_ksettings_add_link_mode(ks, supported,
529 40000baseCR4_Full);
530 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU ||
531 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4) {
532 ethtool_link_ksettings_add_link_mode(ks, supported,
533 40000baseCR4_Full);
534 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_40GB)
535 ethtool_link_ksettings_add_link_mode(ks, advertising,
536 40000baseCR4_Full);
537 }
538 if (phy_types & I40E_CAP_PHY_TYPE_100BASE_TX) {
539 ethtool_link_ksettings_add_link_mode(ks, supported,
540 100baseT_Full);
541 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_100MB)
542 ethtool_link_ksettings_add_link_mode(ks, advertising,
543 100baseT_Full);
544 }
545 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_T) {
546 ethtool_link_ksettings_add_link_mode(ks, supported,
547 1000baseT_Full);
548 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
549 ethtool_link_ksettings_add_link_mode(ks, advertising,
550 1000baseT_Full);
551 }
552 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_SR4) {
553 ethtool_link_ksettings_add_link_mode(ks, supported,
554 40000baseSR4_Full);
555 ethtool_link_ksettings_add_link_mode(ks, advertising,
556 40000baseSR4_Full);
557 }
558 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_LR4) {
559 ethtool_link_ksettings_add_link_mode(ks, supported,
560 40000baseLR4_Full);
561 ethtool_link_ksettings_add_link_mode(ks, advertising,
562 40000baseLR4_Full);
563 }
564 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_KR4) {
565 ethtool_link_ksettings_add_link_mode(ks, supported,
566 40000baseKR4_Full);
567 ethtool_link_ksettings_add_link_mode(ks, advertising,
568 40000baseKR4_Full);
569 }
570 if (phy_types & I40E_CAP_PHY_TYPE_20GBASE_KR2) {
571 ethtool_link_ksettings_add_link_mode(ks, supported,
572 20000baseKR2_Full);
573 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_20GB)
574 ethtool_link_ksettings_add_link_mode(ks, advertising,
575 20000baseKR2_Full);
576 }
577 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4) {
578 ethtool_link_ksettings_add_link_mode(ks, supported,
579 10000baseKX4_Full);
580 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
581 ethtool_link_ksettings_add_link_mode(ks, advertising,
582 10000baseKX4_Full);
583 }
584 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR &&
585 !(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER)) {
586 ethtool_link_ksettings_add_link_mode(ks, supported,
587 10000baseKR_Full);
588 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
589 ethtool_link_ksettings_add_link_mode(ks, advertising,
590 10000baseKR_Full);
591 }
592 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX &&
593 !(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER)) {
594 ethtool_link_ksettings_add_link_mode(ks, supported,
595 1000baseKX_Full);
596 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
597 ethtool_link_ksettings_add_link_mode(ks, advertising,
598 1000baseKX_Full);
599 }
600
601 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR) {
602 ethtool_link_ksettings_add_link_mode(ks, supported,
603 25000baseKR_Full);
604 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
605 ethtool_link_ksettings_add_link_mode(ks, advertising,
606 25000baseKR_Full);
607 }
608 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR) {
609 ethtool_link_ksettings_add_link_mode(ks, supported,
610 25000baseCR_Full);
611 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
612 ethtool_link_ksettings_add_link_mode(ks, advertising,
613 25000baseCR_Full);
614 }
615 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
616 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR) {
617 ethtool_link_ksettings_add_link_mode(ks, supported,
618 25000baseSR_Full);
619 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
620 ethtool_link_ksettings_add_link_mode(ks, advertising,
621 25000baseSR_Full);
622 }
623 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_AOC ||
624 phy_types & I40E_CAP_PHY_TYPE_25GBASE_ACC) {
625 ethtool_link_ksettings_add_link_mode(ks, supported,
626 25000baseCR_Full);
627 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
628 ethtool_link_ksettings_add_link_mode(ks, advertising,
629 25000baseCR_Full);
630 }
631 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
632 phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||
633 phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
634 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR ||
635 phy_types & I40E_CAP_PHY_TYPE_25GBASE_AOC ||
636 phy_types & I40E_CAP_PHY_TYPE_25GBASE_ACC) {
637 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
638 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
639 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
640 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB) {
641 ethtool_link_ksettings_add_link_mode(ks, advertising,
642 FEC_NONE);
643 ethtool_link_ksettings_add_link_mode(ks, advertising,
644 FEC_RS);
645 ethtool_link_ksettings_add_link_mode(ks, advertising,
646 FEC_BASER);
647 }
648 }
649
650 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1 ||
651 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1_CU) {
652 ethtool_link_ksettings_add_link_mode(ks, supported,
653 10000baseCR_Full);
654 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
655 ethtool_link_ksettings_add_link_mode(ks, advertising,
656 10000baseCR_Full);
657 }
658 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_SR) {
659 ethtool_link_ksettings_add_link_mode(ks, supported,
660 10000baseSR_Full);
661 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
662 ethtool_link_ksettings_add_link_mode(ks, advertising,
663 10000baseSR_Full);
664 }
665 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_LR) {
666 ethtool_link_ksettings_add_link_mode(ks, supported,
667 10000baseLR_Full);
668 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
669 ethtool_link_ksettings_add_link_mode(ks, advertising,
670 10000baseLR_Full);
671 }
672 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_SX ||
673 phy_types & I40E_CAP_PHY_TYPE_1000BASE_LX ||
674 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL) {
675 ethtool_link_ksettings_add_link_mode(ks, supported,
676 1000baseX_Full);
677 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
678 ethtool_link_ksettings_add_link_mode(ks, advertising,
679 1000baseX_Full);
680 }
681
682 if (phy_types & I40E_CAP_PHY_TYPE_SGMII ||
683 phy_types & I40E_CAP_PHY_TYPE_40GBASE_KR4 ||
684 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU ||
685 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4 ||
686 phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
687 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR ||
688 phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
689 phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||
690 phy_types & I40E_CAP_PHY_TYPE_20GBASE_KR2 ||
691 phy_types & I40E_CAP_PHY_TYPE_10GBASE_SR ||
692 phy_types & I40E_CAP_PHY_TYPE_10GBASE_LR ||
693 phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4 ||
694 phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR ||
695 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1_CU ||
696 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1 ||
697 phy_types & I40E_CAP_PHY_TYPE_10GBASE_T ||
698 phy_types & I40E_CAP_PHY_TYPE_5GBASE_T ||
699 phy_types & I40E_CAP_PHY_TYPE_2_5GBASE_T ||
700 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL ||
701 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T ||
702 phy_types & I40E_CAP_PHY_TYPE_1000BASE_SX ||
703 phy_types & I40E_CAP_PHY_TYPE_1000BASE_LX ||
704 phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX ||
705 phy_types & I40E_CAP_PHY_TYPE_100BASE_TX) {
706 ethtool_link_ksettings_add_link_mode(ks, supported,
707 Autoneg);
708 ethtool_link_ksettings_add_link_mode(ks, advertising,
709 Autoneg);
710 }
711}
712
713
714
715
716
717
718static void i40e_get_settings_link_up_fec(u8 req_fec_info,
719 struct ethtool_link_ksettings *ks)
720{
721 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
722 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
723 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
724
725 if (I40E_AQ_SET_FEC_REQUEST_RS & req_fec_info) {
726 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
727 } else if (I40E_AQ_SET_FEC_REQUEST_KR & req_fec_info) {
728 ethtool_link_ksettings_add_link_mode(ks, advertising,
729 FEC_BASER);
730 } else {
731 ethtool_link_ksettings_add_link_mode(ks, advertising,
732 FEC_NONE);
733 if (I40E_AQ_SET_FEC_AUTO & req_fec_info) {
734 ethtool_link_ksettings_add_link_mode(ks, advertising,
735 FEC_RS);
736 ethtool_link_ksettings_add_link_mode(ks, advertising,
737 FEC_BASER);
738 }
739 }
740}
741
742
743
744
745
746
747
748
749static void i40e_get_settings_link_up(struct i40e_hw *hw,
750 struct ethtool_link_ksettings *ks,
751 struct net_device *netdev,
752 struct i40e_pf *pf)
753{
754 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
755 struct ethtool_link_ksettings cap_ksettings;
756 u32 link_speed = hw_link_info->link_speed;
757
758
759 switch (hw_link_info->phy_type) {
760 case I40E_PHY_TYPE_40GBASE_CR4:
761 case I40E_PHY_TYPE_40GBASE_CR4_CU:
762 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
763 ethtool_link_ksettings_add_link_mode(ks, supported,
764 40000baseCR4_Full);
765 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
766 ethtool_link_ksettings_add_link_mode(ks, advertising,
767 40000baseCR4_Full);
768 break;
769 case I40E_PHY_TYPE_XLAUI:
770 case I40E_PHY_TYPE_XLPPI:
771 case I40E_PHY_TYPE_40GBASE_AOC:
772 ethtool_link_ksettings_add_link_mode(ks, supported,
773 40000baseCR4_Full);
774 ethtool_link_ksettings_add_link_mode(ks, advertising,
775 40000baseCR4_Full);
776 break;
777 case I40E_PHY_TYPE_40GBASE_SR4:
778 ethtool_link_ksettings_add_link_mode(ks, supported,
779 40000baseSR4_Full);
780 ethtool_link_ksettings_add_link_mode(ks, advertising,
781 40000baseSR4_Full);
782 break;
783 case I40E_PHY_TYPE_40GBASE_LR4:
784 ethtool_link_ksettings_add_link_mode(ks, supported,
785 40000baseLR4_Full);
786 ethtool_link_ksettings_add_link_mode(ks, advertising,
787 40000baseLR4_Full);
788 break;
789 case I40E_PHY_TYPE_25GBASE_SR:
790 case I40E_PHY_TYPE_25GBASE_LR:
791 case I40E_PHY_TYPE_10GBASE_SR:
792 case I40E_PHY_TYPE_10GBASE_LR:
793 case I40E_PHY_TYPE_1000BASE_SX:
794 case I40E_PHY_TYPE_1000BASE_LX:
795 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
796 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
797 ethtool_link_ksettings_add_link_mode(ks, supported,
798 25000baseSR_Full);
799 ethtool_link_ksettings_add_link_mode(ks, advertising,
800 25000baseSR_Full);
801 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
802 ethtool_link_ksettings_add_link_mode(ks, supported,
803 10000baseSR_Full);
804 ethtool_link_ksettings_add_link_mode(ks, advertising,
805 10000baseSR_Full);
806 ethtool_link_ksettings_add_link_mode(ks, supported,
807 10000baseLR_Full);
808 ethtool_link_ksettings_add_link_mode(ks, advertising,
809 10000baseLR_Full);
810 ethtool_link_ksettings_add_link_mode(ks, supported,
811 1000baseX_Full);
812 ethtool_link_ksettings_add_link_mode(ks, advertising,
813 1000baseX_Full);
814 ethtool_link_ksettings_add_link_mode(ks, supported,
815 10000baseT_Full);
816 if (hw_link_info->module_type[2] &
817 I40E_MODULE_TYPE_1000BASE_SX ||
818 hw_link_info->module_type[2] &
819 I40E_MODULE_TYPE_1000BASE_LX) {
820 ethtool_link_ksettings_add_link_mode(ks, supported,
821 1000baseT_Full);
822 if (hw_link_info->requested_speeds &
823 I40E_LINK_SPEED_1GB)
824 ethtool_link_ksettings_add_link_mode(
825 ks, advertising, 1000baseT_Full);
826 }
827 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
828 ethtool_link_ksettings_add_link_mode(ks, advertising,
829 10000baseT_Full);
830 break;
831 case I40E_PHY_TYPE_10GBASE_T:
832 case I40E_PHY_TYPE_5GBASE_T:
833 case I40E_PHY_TYPE_2_5GBASE_T:
834 case I40E_PHY_TYPE_1000BASE_T:
835 case I40E_PHY_TYPE_100BASE_TX:
836 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
837 ethtool_link_ksettings_add_link_mode(ks, supported,
838 10000baseT_Full);
839 ethtool_link_ksettings_add_link_mode(ks, supported,
840 5000baseT_Full);
841 ethtool_link_ksettings_add_link_mode(ks, supported,
842 2500baseT_Full);
843 ethtool_link_ksettings_add_link_mode(ks, supported,
844 1000baseT_Full);
845 ethtool_link_ksettings_add_link_mode(ks, supported,
846 100baseT_Full);
847 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
848 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
849 ethtool_link_ksettings_add_link_mode(ks, advertising,
850 10000baseT_Full);
851 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_5GB)
852 ethtool_link_ksettings_add_link_mode(ks, advertising,
853 5000baseT_Full);
854 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_2_5GB)
855 ethtool_link_ksettings_add_link_mode(ks, advertising,
856 2500baseT_Full);
857 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
858 ethtool_link_ksettings_add_link_mode(ks, advertising,
859 1000baseT_Full);
860 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_100MB)
861 ethtool_link_ksettings_add_link_mode(ks, advertising,
862 100baseT_Full);
863 break;
864 case I40E_PHY_TYPE_1000BASE_T_OPTICAL:
865 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
866 ethtool_link_ksettings_add_link_mode(ks, supported,
867 1000baseT_Full);
868 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
869 ethtool_link_ksettings_add_link_mode(ks, advertising,
870 1000baseT_Full);
871 break;
872 case I40E_PHY_TYPE_10GBASE_CR1_CU:
873 case I40E_PHY_TYPE_10GBASE_CR1:
874 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
875 ethtool_link_ksettings_add_link_mode(ks, supported,
876 10000baseT_Full);
877 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
878 ethtool_link_ksettings_add_link_mode(ks, advertising,
879 10000baseT_Full);
880 break;
881 case I40E_PHY_TYPE_XAUI:
882 case I40E_PHY_TYPE_XFI:
883 case I40E_PHY_TYPE_SFI:
884 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
885 case I40E_PHY_TYPE_10GBASE_AOC:
886 ethtool_link_ksettings_add_link_mode(ks, supported,
887 10000baseT_Full);
888 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
889 ethtool_link_ksettings_add_link_mode(ks, advertising,
890 10000baseT_Full);
891 break;
892 case I40E_PHY_TYPE_SGMII:
893 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
894 ethtool_link_ksettings_add_link_mode(ks, supported,
895 1000baseT_Full);
896 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
897 ethtool_link_ksettings_add_link_mode(ks, advertising,
898 1000baseT_Full);
899 if (pf->hw_features & I40E_HW_100M_SGMII_CAPABLE) {
900 ethtool_link_ksettings_add_link_mode(ks, supported,
901 100baseT_Full);
902 if (hw_link_info->requested_speeds &
903 I40E_LINK_SPEED_100MB)
904 ethtool_link_ksettings_add_link_mode(
905 ks, advertising, 100baseT_Full);
906 }
907 break;
908 case I40E_PHY_TYPE_40GBASE_KR4:
909 case I40E_PHY_TYPE_25GBASE_KR:
910 case I40E_PHY_TYPE_20GBASE_KR2:
911 case I40E_PHY_TYPE_10GBASE_KR:
912 case I40E_PHY_TYPE_10GBASE_KX4:
913 case I40E_PHY_TYPE_1000BASE_KX:
914 ethtool_link_ksettings_add_link_mode(ks, supported,
915 40000baseKR4_Full);
916 ethtool_link_ksettings_add_link_mode(ks, supported,
917 25000baseKR_Full);
918 ethtool_link_ksettings_add_link_mode(ks, supported,
919 20000baseKR2_Full);
920 ethtool_link_ksettings_add_link_mode(ks, supported,
921 10000baseKR_Full);
922 ethtool_link_ksettings_add_link_mode(ks, supported,
923 10000baseKX4_Full);
924 ethtool_link_ksettings_add_link_mode(ks, supported,
925 1000baseKX_Full);
926 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
927 ethtool_link_ksettings_add_link_mode(ks, advertising,
928 40000baseKR4_Full);
929 ethtool_link_ksettings_add_link_mode(ks, advertising,
930 25000baseKR_Full);
931 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
932 ethtool_link_ksettings_add_link_mode(ks, advertising,
933 20000baseKR2_Full);
934 ethtool_link_ksettings_add_link_mode(ks, advertising,
935 10000baseKR_Full);
936 ethtool_link_ksettings_add_link_mode(ks, advertising,
937 10000baseKX4_Full);
938 ethtool_link_ksettings_add_link_mode(ks, advertising,
939 1000baseKX_Full);
940 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
941 break;
942 case I40E_PHY_TYPE_25GBASE_CR:
943 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
944 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
945 ethtool_link_ksettings_add_link_mode(ks, supported,
946 25000baseCR_Full);
947 ethtool_link_ksettings_add_link_mode(ks, advertising,
948 25000baseCR_Full);
949 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
950
951 break;
952 case I40E_PHY_TYPE_25GBASE_AOC:
953 case I40E_PHY_TYPE_25GBASE_ACC:
954 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
955 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
956 ethtool_link_ksettings_add_link_mode(ks, supported,
957 25000baseCR_Full);
958 ethtool_link_ksettings_add_link_mode(ks, advertising,
959 25000baseCR_Full);
960 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
961
962 ethtool_link_ksettings_add_link_mode(ks, supported,
963 10000baseCR_Full);
964 ethtool_link_ksettings_add_link_mode(ks, advertising,
965 10000baseCR_Full);
966 break;
967 default:
968
969 netdev_info(netdev,
970 "WARNING: Link is up but PHY type 0x%x is not recognized.\n",
971 hw_link_info->phy_type);
972 }
973
974
975
976
977
978 memset(&cap_ksettings, 0, sizeof(struct ethtool_link_ksettings));
979 i40e_phy_type_to_ethtool(pf, &cap_ksettings);
980 ethtool_intersect_link_masks(ks, &cap_ksettings);
981
982
983 switch (link_speed) {
984 case I40E_LINK_SPEED_40GB:
985 ks->base.speed = SPEED_40000;
986 break;
987 case I40E_LINK_SPEED_25GB:
988 ks->base.speed = SPEED_25000;
989 break;
990 case I40E_LINK_SPEED_20GB:
991 ks->base.speed = SPEED_20000;
992 break;
993 case I40E_LINK_SPEED_10GB:
994 ks->base.speed = SPEED_10000;
995 break;
996 case I40E_LINK_SPEED_5GB:
997 ks->base.speed = SPEED_5000;
998 break;
999 case I40E_LINK_SPEED_2_5GB:
1000 ks->base.speed = SPEED_2500;
1001 break;
1002 case I40E_LINK_SPEED_1GB:
1003 ks->base.speed = SPEED_1000;
1004 break;
1005 case I40E_LINK_SPEED_100MB:
1006 ks->base.speed = SPEED_100;
1007 break;
1008 default:
1009 ks->base.speed = SPEED_UNKNOWN;
1010 break;
1011 }
1012 ks->base.duplex = DUPLEX_FULL;
1013}
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023static void i40e_get_settings_link_down(struct i40e_hw *hw,
1024 struct ethtool_link_ksettings *ks,
1025 struct i40e_pf *pf)
1026{
1027
1028
1029
1030 i40e_phy_type_to_ethtool(pf, ks);
1031
1032
1033 ks->base.speed = SPEED_UNKNOWN;
1034 ks->base.duplex = DUPLEX_UNKNOWN;
1035}
1036
1037
1038
1039
1040
1041
1042
1043
1044static int i40e_get_link_ksettings(struct net_device *netdev,
1045 struct ethtool_link_ksettings *ks)
1046{
1047 struct i40e_netdev_priv *np = netdev_priv(netdev);
1048 struct i40e_pf *pf = np->vsi->back;
1049 struct i40e_hw *hw = &pf->hw;
1050 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1051 bool link_up = hw_link_info->link_info & I40E_AQ_LINK_UP;
1052
1053 ethtool_link_ksettings_zero_link_mode(ks, supported);
1054 ethtool_link_ksettings_zero_link_mode(ks, advertising);
1055
1056 if (link_up)
1057 i40e_get_settings_link_up(hw, ks, netdev, pf);
1058 else
1059 i40e_get_settings_link_down(hw, ks, pf);
1060
1061
1062
1063 ks->base.autoneg = ((hw_link_info->an_info & I40E_AQ_AN_COMPLETED) ?
1064 AUTONEG_ENABLE : AUTONEG_DISABLE);
1065
1066
1067 switch (hw->phy.media_type) {
1068 case I40E_MEDIA_TYPE_BACKPLANE:
1069 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
1070 ethtool_link_ksettings_add_link_mode(ks, supported, Backplane);
1071 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
1072 ethtool_link_ksettings_add_link_mode(ks, advertising,
1073 Backplane);
1074 ks->base.port = PORT_NONE;
1075 break;
1076 case I40E_MEDIA_TYPE_BASET:
1077 ethtool_link_ksettings_add_link_mode(ks, supported, TP);
1078 ethtool_link_ksettings_add_link_mode(ks, advertising, TP);
1079 ks->base.port = PORT_TP;
1080 break;
1081 case I40E_MEDIA_TYPE_DA:
1082 case I40E_MEDIA_TYPE_CX4:
1083 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
1084 ethtool_link_ksettings_add_link_mode(ks, advertising, FIBRE);
1085 ks->base.port = PORT_DA;
1086 break;
1087 case I40E_MEDIA_TYPE_FIBER:
1088 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
1089 ethtool_link_ksettings_add_link_mode(ks, advertising, FIBRE);
1090 ks->base.port = PORT_FIBRE;
1091 break;
1092 case I40E_MEDIA_TYPE_UNKNOWN:
1093 default:
1094 ks->base.port = PORT_OTHER;
1095 break;
1096 }
1097
1098
1099 ethtool_link_ksettings_add_link_mode(ks, supported, Pause);
1100
1101 switch (hw->fc.requested_mode) {
1102 case I40E_FC_FULL:
1103 ethtool_link_ksettings_add_link_mode(ks, advertising, Pause);
1104 break;
1105 case I40E_FC_TX_PAUSE:
1106 ethtool_link_ksettings_add_link_mode(ks, advertising,
1107 Asym_Pause);
1108 break;
1109 case I40E_FC_RX_PAUSE:
1110 ethtool_link_ksettings_add_link_mode(ks, advertising, Pause);
1111 ethtool_link_ksettings_add_link_mode(ks, advertising,
1112 Asym_Pause);
1113 break;
1114 default:
1115 ethtool_link_ksettings_del_link_mode(ks, advertising, Pause);
1116 ethtool_link_ksettings_del_link_mode(ks, advertising,
1117 Asym_Pause);
1118 break;
1119 }
1120
1121 return 0;
1122}
1123
1124
1125
1126
1127
1128
1129
1130
1131static int i40e_set_link_ksettings(struct net_device *netdev,
1132 const struct ethtool_link_ksettings *ks)
1133{
1134 struct i40e_netdev_priv *np = netdev_priv(netdev);
1135 struct i40e_aq_get_phy_abilities_resp abilities;
1136 struct ethtool_link_ksettings safe_ks;
1137 struct ethtool_link_ksettings copy_ks;
1138 struct i40e_aq_set_phy_config config;
1139 struct i40e_pf *pf = np->vsi->back;
1140 struct i40e_vsi *vsi = np->vsi;
1141 struct i40e_hw *hw = &pf->hw;
1142 bool autoneg_changed = false;
1143 i40e_status status = 0;
1144 int timeout = 50;
1145 int err = 0;
1146 u8 autoneg;
1147
1148
1149
1150
1151 if (hw->partition_id != 1) {
1152 i40e_partition_setting_complaint(pf);
1153 return -EOPNOTSUPP;
1154 }
1155 if (vsi != pf->vsi[pf->lan_vsi])
1156 return -EOPNOTSUPP;
1157 if (hw->phy.media_type != I40E_MEDIA_TYPE_BASET &&
1158 hw->phy.media_type != I40E_MEDIA_TYPE_FIBER &&
1159 hw->phy.media_type != I40E_MEDIA_TYPE_BACKPLANE &&
1160 hw->phy.media_type != I40E_MEDIA_TYPE_DA &&
1161 hw->phy.link_info.link_info & I40E_AQ_LINK_UP)
1162 return -EOPNOTSUPP;
1163 if (hw->device_id == I40E_DEV_ID_KX_B ||
1164 hw->device_id == I40E_DEV_ID_KX_C ||
1165 hw->device_id == I40E_DEV_ID_20G_KR2 ||
1166 hw->device_id == I40E_DEV_ID_20G_KR2_A ||
1167 hw->device_id == I40E_DEV_ID_25G_B ||
1168 hw->device_id == I40E_DEV_ID_KX_X722) {
1169 netdev_info(netdev, "Changing settings is not supported on backplane.\n");
1170 return -EOPNOTSUPP;
1171 }
1172
1173
1174 memcpy(©_ks, ks, sizeof(struct ethtool_link_ksettings));
1175
1176
1177 autoneg = copy_ks.base.autoneg;
1178
1179
1180 memset(&safe_ks, 0, sizeof(struct ethtool_link_ksettings));
1181 safe_ks.base.cmd = copy_ks.base.cmd;
1182 safe_ks.base.link_mode_masks_nwords =
1183 copy_ks.base.link_mode_masks_nwords;
1184 i40e_get_link_ksettings(netdev, &safe_ks);
1185
1186
1187
1188
1189 if (!bitmap_subset(copy_ks.link_modes.advertising,
1190 safe_ks.link_modes.supported,
1191 __ETHTOOL_LINK_MODE_MASK_NBITS))
1192 return -EINVAL;
1193
1194
1195 copy_ks.base.autoneg = safe_ks.base.autoneg;
1196
1197
1198
1199
1200 if (memcmp(©_ks.base, &safe_ks.base,
1201 sizeof(struct ethtool_link_settings)))
1202 return -EOPNOTSUPP;
1203
1204 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) {
1205 timeout--;
1206 if (!timeout)
1207 return -EBUSY;
1208 usleep_range(1000, 2000);
1209 }
1210
1211
1212 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1213 NULL);
1214 if (status) {
1215 err = -EAGAIN;
1216 goto done;
1217 }
1218
1219
1220
1221
1222 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1223 config.abilities = abilities.abilities;
1224
1225
1226 if (autoneg == AUTONEG_ENABLE) {
1227
1228 if (!(hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED)) {
1229
1230 if (!ethtool_link_ksettings_test_link_mode(&safe_ks,
1231 supported,
1232 Autoneg)) {
1233 netdev_info(netdev, "Autoneg not supported on this phy\n");
1234 err = -EINVAL;
1235 goto done;
1236 }
1237
1238 config.abilities = abilities.abilities |
1239 I40E_AQ_PHY_ENABLE_AN;
1240 autoneg_changed = true;
1241 }
1242 } else {
1243
1244 if (hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED) {
1245
1246
1247
1248 if (ethtool_link_ksettings_test_link_mode(&safe_ks,
1249 supported,
1250 Autoneg) &&
1251 hw->phy.link_info.phy_type !=
1252 I40E_PHY_TYPE_10GBASE_T) {
1253 netdev_info(netdev, "Autoneg cannot be disabled on this phy\n");
1254 err = -EINVAL;
1255 goto done;
1256 }
1257
1258 config.abilities = abilities.abilities &
1259 ~I40E_AQ_PHY_ENABLE_AN;
1260 autoneg_changed = true;
1261 }
1262 }
1263
1264 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1265 100baseT_Full))
1266 config.link_speed |= I40E_LINK_SPEED_100MB;
1267 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1268 1000baseT_Full) ||
1269 ethtool_link_ksettings_test_link_mode(ks, advertising,
1270 1000baseX_Full) ||
1271 ethtool_link_ksettings_test_link_mode(ks, advertising,
1272 1000baseKX_Full))
1273 config.link_speed |= I40E_LINK_SPEED_1GB;
1274 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1275 10000baseT_Full) ||
1276 ethtool_link_ksettings_test_link_mode(ks, advertising,
1277 10000baseKX4_Full) ||
1278 ethtool_link_ksettings_test_link_mode(ks, advertising,
1279 10000baseKR_Full) ||
1280 ethtool_link_ksettings_test_link_mode(ks, advertising,
1281 10000baseCR_Full) ||
1282 ethtool_link_ksettings_test_link_mode(ks, advertising,
1283 10000baseSR_Full) ||
1284 ethtool_link_ksettings_test_link_mode(ks, advertising,
1285 10000baseLR_Full))
1286 config.link_speed |= I40E_LINK_SPEED_10GB;
1287 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1288 2500baseT_Full))
1289 config.link_speed |= I40E_LINK_SPEED_2_5GB;
1290 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1291 5000baseT_Full))
1292 config.link_speed |= I40E_LINK_SPEED_5GB;
1293 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1294 20000baseKR2_Full))
1295 config.link_speed |= I40E_LINK_SPEED_20GB;
1296 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1297 25000baseCR_Full) ||
1298 ethtool_link_ksettings_test_link_mode(ks, advertising,
1299 25000baseKR_Full) ||
1300 ethtool_link_ksettings_test_link_mode(ks, advertising,
1301 25000baseSR_Full))
1302 config.link_speed |= I40E_LINK_SPEED_25GB;
1303 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1304 40000baseKR4_Full) ||
1305 ethtool_link_ksettings_test_link_mode(ks, advertising,
1306 40000baseCR4_Full) ||
1307 ethtool_link_ksettings_test_link_mode(ks, advertising,
1308 40000baseSR4_Full) ||
1309 ethtool_link_ksettings_test_link_mode(ks, advertising,
1310 40000baseLR4_Full))
1311 config.link_speed |= I40E_LINK_SPEED_40GB;
1312
1313
1314
1315
1316
1317 if (!config.link_speed)
1318 config.link_speed = abilities.link_speed;
1319 if (autoneg_changed || abilities.link_speed != config.link_speed) {
1320
1321 config.phy_type = abilities.phy_type;
1322 config.phy_type_ext = abilities.phy_type_ext;
1323 config.eee_capability = abilities.eee_capability;
1324 config.eeer = abilities.eeer_val;
1325 config.low_power_ctrl = abilities.d3_lpan;
1326 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1327 I40E_AQ_PHY_FEC_CONFIG_MASK;
1328
1329
1330 hw->phy.link_info.requested_speeds = config.link_speed;
1331
1332 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1333
1334 if (hw->phy.link_info.link_info & I40E_AQ_LINK_UP) {
1335
1336
1337
1338 i40e_print_link_message(vsi, false);
1339 netif_carrier_off(netdev);
1340 netif_tx_stop_all_queues(netdev);
1341 }
1342
1343
1344 status = i40e_aq_set_phy_config(hw, &config, NULL);
1345 if (status) {
1346 netdev_info(netdev,
1347 "Set phy config failed, err %s aq_err %s\n",
1348 i40e_stat_str(hw, status),
1349 i40e_aq_str(hw, hw->aq.asq_last_status));
1350 err = -EAGAIN;
1351 goto done;
1352 }
1353
1354 status = i40e_update_link_info(hw);
1355 if (status)
1356 netdev_dbg(netdev,
1357 "Updating link info failed with err %s aq_err %s\n",
1358 i40e_stat_str(hw, status),
1359 i40e_aq_str(hw, hw->aq.asq_last_status));
1360
1361 } else {
1362 netdev_info(netdev, "Nothing changed, exiting without setting anything.\n");
1363 }
1364
1365done:
1366 clear_bit(__I40E_CONFIG_BUSY, pf->state);
1367
1368 return err;
1369}
1370
1371static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)
1372{
1373 struct i40e_netdev_priv *np = netdev_priv(netdev);
1374 struct i40e_aq_get_phy_abilities_resp abilities;
1375 struct i40e_pf *pf = np->vsi->back;
1376 struct i40e_hw *hw = &pf->hw;
1377 i40e_status status = 0;
1378 u32 flags = 0;
1379 int err = 0;
1380
1381 flags = READ_ONCE(pf->flags);
1382 i40e_set_fec_in_flags(fec_cfg, &flags);
1383
1384
1385 memset(&abilities, 0, sizeof(abilities));
1386 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1387 NULL);
1388 if (status) {
1389 err = -EAGAIN;
1390 goto done;
1391 }
1392
1393 if (abilities.fec_cfg_curr_mod_ext_info != fec_cfg) {
1394 struct i40e_aq_set_phy_config config;
1395
1396 memset(&config, 0, sizeof(config));
1397 config.phy_type = abilities.phy_type;
1398 config.abilities = abilities.abilities;
1399 config.phy_type_ext = abilities.phy_type_ext;
1400 config.link_speed = abilities.link_speed;
1401 config.eee_capability = abilities.eee_capability;
1402 config.eeer = abilities.eeer_val;
1403 config.low_power_ctrl = abilities.d3_lpan;
1404 config.fec_config = fec_cfg & I40E_AQ_PHY_FEC_CONFIG_MASK;
1405 status = i40e_aq_set_phy_config(hw, &config, NULL);
1406 if (status) {
1407 netdev_info(netdev,
1408 "Set phy config failed, err %s aq_err %s\n",
1409 i40e_stat_str(hw, status),
1410 i40e_aq_str(hw, hw->aq.asq_last_status));
1411 err = -EAGAIN;
1412 goto done;
1413 }
1414 pf->flags = flags;
1415 status = i40e_update_link_info(hw);
1416 if (status)
1417
1418
1419
1420
1421 netdev_dbg(netdev,
1422 "Updating link info failed with err %s aq_err %s\n",
1423 i40e_stat_str(hw, status),
1424 i40e_aq_str(hw, hw->aq.asq_last_status));
1425 }
1426
1427done:
1428 return err;
1429}
1430
1431static int i40e_get_fec_param(struct net_device *netdev,
1432 struct ethtool_fecparam *fecparam)
1433{
1434 struct i40e_netdev_priv *np = netdev_priv(netdev);
1435 struct i40e_aq_get_phy_abilities_resp abilities;
1436 struct i40e_pf *pf = np->vsi->back;
1437 struct i40e_hw *hw = &pf->hw;
1438 i40e_status status = 0;
1439 int err = 0;
1440
1441
1442 memset(&abilities, 0, sizeof(abilities));
1443 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1444 NULL);
1445 if (status) {
1446 err = -EAGAIN;
1447 goto done;
1448 }
1449
1450 fecparam->fec = 0;
1451 if (abilities.fec_cfg_curr_mod_ext_info & I40E_AQ_SET_FEC_AUTO)
1452 fecparam->fec |= ETHTOOL_FEC_AUTO;
1453 if ((abilities.fec_cfg_curr_mod_ext_info &
1454 I40E_AQ_SET_FEC_REQUEST_RS) ||
1455 (abilities.fec_cfg_curr_mod_ext_info &
1456 I40E_AQ_SET_FEC_ABILITY_RS))
1457 fecparam->fec |= ETHTOOL_FEC_RS;
1458 if ((abilities.fec_cfg_curr_mod_ext_info &
1459 I40E_AQ_SET_FEC_REQUEST_KR) ||
1460 (abilities.fec_cfg_curr_mod_ext_info & I40E_AQ_SET_FEC_ABILITY_KR))
1461 fecparam->fec |= ETHTOOL_FEC_BASER;
1462 if (abilities.fec_cfg_curr_mod_ext_info == 0)
1463 fecparam->fec |= ETHTOOL_FEC_OFF;
1464
1465 if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_KR_ENA)
1466 fecparam->active_fec = ETHTOOL_FEC_BASER;
1467 else if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_RS_ENA)
1468 fecparam->active_fec = ETHTOOL_FEC_RS;
1469 else
1470 fecparam->active_fec = ETHTOOL_FEC_OFF;
1471done:
1472 return err;
1473}
1474
1475static int i40e_set_fec_param(struct net_device *netdev,
1476 struct ethtool_fecparam *fecparam)
1477{
1478 struct i40e_netdev_priv *np = netdev_priv(netdev);
1479 struct i40e_pf *pf = np->vsi->back;
1480 struct i40e_hw *hw = &pf->hw;
1481 u8 fec_cfg = 0;
1482 int err = 0;
1483
1484 if (hw->device_id != I40E_DEV_ID_25G_SFP28 &&
1485 hw->device_id != I40E_DEV_ID_25G_B) {
1486 err = -EPERM;
1487 goto done;
1488 }
1489
1490 switch (fecparam->fec) {
1491 case ETHTOOL_FEC_AUTO:
1492 fec_cfg = I40E_AQ_SET_FEC_AUTO;
1493 break;
1494 case ETHTOOL_FEC_RS:
1495 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_RS |
1496 I40E_AQ_SET_FEC_ABILITY_RS);
1497 break;
1498 case ETHTOOL_FEC_BASER:
1499 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_KR |
1500 I40E_AQ_SET_FEC_ABILITY_KR);
1501 break;
1502 case ETHTOOL_FEC_OFF:
1503 case ETHTOOL_FEC_NONE:
1504 fec_cfg = 0;
1505 break;
1506 default:
1507 dev_warn(&pf->pdev->dev, "Unsupported FEC mode: %d",
1508 fecparam->fec);
1509 err = -EINVAL;
1510 goto done;
1511 }
1512
1513 err = i40e_set_fec_cfg(netdev, fec_cfg);
1514
1515done:
1516 return err;
1517}
1518
1519static int i40e_nway_reset(struct net_device *netdev)
1520{
1521
1522 struct i40e_netdev_priv *np = netdev_priv(netdev);
1523 struct i40e_pf *pf = np->vsi->back;
1524 struct i40e_hw *hw = &pf->hw;
1525 bool link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1526 i40e_status ret = 0;
1527
1528 ret = i40e_aq_set_link_restart_an(hw, link_up, NULL);
1529 if (ret) {
1530 netdev_info(netdev, "link restart failed, err %s aq_err %s\n",
1531 i40e_stat_str(hw, ret),
1532 i40e_aq_str(hw, hw->aq.asq_last_status));
1533 return -EIO;
1534 }
1535
1536 return 0;
1537}
1538
1539
1540
1541
1542
1543
1544
1545
1546static void i40e_get_pauseparam(struct net_device *netdev,
1547 struct ethtool_pauseparam *pause)
1548{
1549 struct i40e_netdev_priv *np = netdev_priv(netdev);
1550 struct i40e_pf *pf = np->vsi->back;
1551 struct i40e_hw *hw = &pf->hw;
1552 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1553 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
1554
1555 pause->autoneg =
1556 ((hw_link_info->an_info & I40E_AQ_AN_COMPLETED) ?
1557 AUTONEG_ENABLE : AUTONEG_DISABLE);
1558
1559
1560 if (dcbx_cfg->pfc.pfcenable) {
1561 pause->rx_pause = 0;
1562 pause->tx_pause = 0;
1563 return;
1564 }
1565
1566 if (hw->fc.current_mode == I40E_FC_RX_PAUSE) {
1567 pause->rx_pause = 1;
1568 } else if (hw->fc.current_mode == I40E_FC_TX_PAUSE) {
1569 pause->tx_pause = 1;
1570 } else if (hw->fc.current_mode == I40E_FC_FULL) {
1571 pause->rx_pause = 1;
1572 pause->tx_pause = 1;
1573 }
1574}
1575
1576
1577
1578
1579
1580
1581static int i40e_set_pauseparam(struct net_device *netdev,
1582 struct ethtool_pauseparam *pause)
1583{
1584 struct i40e_netdev_priv *np = netdev_priv(netdev);
1585 struct i40e_pf *pf = np->vsi->back;
1586 struct i40e_vsi *vsi = np->vsi;
1587 struct i40e_hw *hw = &pf->hw;
1588 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1589 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
1590 bool link_up = hw_link_info->link_info & I40E_AQ_LINK_UP;
1591 i40e_status status;
1592 u8 aq_failures;
1593 int err = 0;
1594 u32 is_an;
1595
1596
1597
1598
1599 if (hw->partition_id != 1) {
1600 i40e_partition_setting_complaint(pf);
1601 return -EOPNOTSUPP;
1602 }
1603
1604 if (vsi != pf->vsi[pf->lan_vsi])
1605 return -EOPNOTSUPP;
1606
1607 is_an = hw_link_info->an_info & I40E_AQ_AN_COMPLETED;
1608 if (pause->autoneg != is_an) {
1609 netdev_info(netdev, "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
1610 return -EOPNOTSUPP;
1611 }
1612
1613
1614 if (!test_bit(__I40E_DOWN, pf->state) && !is_an) {
1615
1616 netdev_info(netdev, "Autoneg did not complete so changing settings may not result in an actual change.\n");
1617 }
1618
1619 if (dcbx_cfg->pfc.pfcenable) {
1620 netdev_info(netdev,
1621 "Priority flow control enabled. Cannot set link flow control.\n");
1622 return -EOPNOTSUPP;
1623 }
1624
1625 if (pause->rx_pause && pause->tx_pause)
1626 hw->fc.requested_mode = I40E_FC_FULL;
1627 else if (pause->rx_pause && !pause->tx_pause)
1628 hw->fc.requested_mode = I40E_FC_RX_PAUSE;
1629 else if (!pause->rx_pause && pause->tx_pause)
1630 hw->fc.requested_mode = I40E_FC_TX_PAUSE;
1631 else if (!pause->rx_pause && !pause->tx_pause)
1632 hw->fc.requested_mode = I40E_FC_NONE;
1633 else
1634 return -EINVAL;
1635
1636
1637
1638
1639 i40e_print_link_message(vsi, false);
1640 netif_carrier_off(netdev);
1641 netif_tx_stop_all_queues(netdev);
1642
1643
1644 status = i40e_set_fc(hw, &aq_failures, link_up);
1645
1646 if (aq_failures & I40E_SET_FC_AQ_FAIL_GET) {
1647 netdev_info(netdev, "Set fc failed on the get_phy_capabilities call with err %s aq_err %s\n",
1648 i40e_stat_str(hw, status),
1649 i40e_aq_str(hw, hw->aq.asq_last_status));
1650 err = -EAGAIN;
1651 }
1652 if (aq_failures & I40E_SET_FC_AQ_FAIL_SET) {
1653 netdev_info(netdev, "Set fc failed on the set_phy_config call with err %s aq_err %s\n",
1654 i40e_stat_str(hw, status),
1655 i40e_aq_str(hw, hw->aq.asq_last_status));
1656 err = -EAGAIN;
1657 }
1658 if (aq_failures & I40E_SET_FC_AQ_FAIL_UPDATE) {
1659 netdev_info(netdev, "Set fc failed on the get_link_info call with err %s aq_err %s\n",
1660 i40e_stat_str(hw, status),
1661 i40e_aq_str(hw, hw->aq.asq_last_status));
1662 err = -EAGAIN;
1663 }
1664
1665 if (!test_bit(__I40E_DOWN, pf->state) && is_an) {
1666
1667 msleep(75);
1668 if (!test_bit(__I40E_DOWN, pf->state))
1669 return i40e_nway_reset(netdev);
1670 }
1671
1672 return err;
1673}
1674
1675static u32 i40e_get_msglevel(struct net_device *netdev)
1676{
1677 struct i40e_netdev_priv *np = netdev_priv(netdev);
1678 struct i40e_pf *pf = np->vsi->back;
1679 u32 debug_mask = pf->hw.debug_mask;
1680
1681 if (debug_mask)
1682 netdev_info(netdev, "i40e debug_mask: 0x%08X\n", debug_mask);
1683
1684 return pf->msg_enable;
1685}
1686
1687static void i40e_set_msglevel(struct net_device *netdev, u32 data)
1688{
1689 struct i40e_netdev_priv *np = netdev_priv(netdev);
1690 struct i40e_pf *pf = np->vsi->back;
1691
1692 if (I40E_DEBUG_USER & data)
1693 pf->hw.debug_mask = data;
1694 else
1695 pf->msg_enable = data;
1696}
1697
1698static int i40e_get_regs_len(struct net_device *netdev)
1699{
1700 int reg_count = 0;
1701 int i;
1702
1703 for (i = 0; i40e_reg_list[i].offset != 0; i++)
1704 reg_count += i40e_reg_list[i].elements;
1705
1706 return reg_count * sizeof(u32);
1707}
1708
1709static void i40e_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
1710 void *p)
1711{
1712 struct i40e_netdev_priv *np = netdev_priv(netdev);
1713 struct i40e_pf *pf = np->vsi->back;
1714 struct i40e_hw *hw = &pf->hw;
1715 u32 *reg_buf = p;
1716 unsigned int i, j, ri;
1717 u32 reg;
1718
1719
1720
1721
1722
1723
1724
1725
1726 regs->version = 1;
1727
1728
1729 ri = 0;
1730 for (i = 0; i40e_reg_list[i].offset != 0; i++) {
1731 for (j = 0; j < i40e_reg_list[i].elements; j++) {
1732 reg = i40e_reg_list[i].offset
1733 + (j * i40e_reg_list[i].stride);
1734 reg_buf[ri++] = rd32(hw, reg);
1735 }
1736 }
1737
1738}
1739
1740static int i40e_get_eeprom(struct net_device *netdev,
1741 struct ethtool_eeprom *eeprom, u8 *bytes)
1742{
1743 struct i40e_netdev_priv *np = netdev_priv(netdev);
1744 struct i40e_hw *hw = &np->vsi->back->hw;
1745 struct i40e_pf *pf = np->vsi->back;
1746 int ret_val = 0, len, offset;
1747 u8 *eeprom_buff;
1748 u16 i, sectors;
1749 bool last;
1750 u32 magic;
1751
1752#define I40E_NVM_SECTOR_SIZE 4096
1753 if (eeprom->len == 0)
1754 return -EINVAL;
1755
1756
1757 magic = hw->vendor_id | (hw->device_id << 16);
1758 if (eeprom->magic && eeprom->magic != magic) {
1759 struct i40e_nvm_access *cmd = (struct i40e_nvm_access *)eeprom;
1760 int errno = 0;
1761
1762
1763 if ((eeprom->magic >> 16) != hw->device_id)
1764 errno = -EINVAL;
1765 else if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
1766 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
1767 errno = -EBUSY;
1768 else
1769 ret_val = i40e_nvmupd_command(hw, cmd, bytes, &errno);
1770
1771 if ((errno || ret_val) && (hw->debug_mask & I40E_DEBUG_NVM))
1772 dev_info(&pf->pdev->dev,
1773 "NVMUpdate read failed err=%d status=0x%x errno=%d module=%d offset=0x%x size=%d\n",
1774 ret_val, hw->aq.asq_last_status, errno,
1775 (u8)(cmd->config & I40E_NVM_MOD_PNT_MASK),
1776 cmd->offset, cmd->data_size);
1777
1778 return errno;
1779 }
1780
1781
1782 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1783
1784 eeprom_buff = kzalloc(eeprom->len, GFP_KERNEL);
1785 if (!eeprom_buff)
1786 return -ENOMEM;
1787
1788 ret_val = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
1789 if (ret_val) {
1790 dev_info(&pf->pdev->dev,
1791 "Failed Acquiring NVM resource for read err=%d status=0x%x\n",
1792 ret_val, hw->aq.asq_last_status);
1793 goto free_buff;
1794 }
1795
1796 sectors = eeprom->len / I40E_NVM_SECTOR_SIZE;
1797 sectors += (eeprom->len % I40E_NVM_SECTOR_SIZE) ? 1 : 0;
1798 len = I40E_NVM_SECTOR_SIZE;
1799 last = false;
1800 for (i = 0; i < sectors; i++) {
1801 if (i == (sectors - 1)) {
1802 len = eeprom->len - (I40E_NVM_SECTOR_SIZE * i);
1803 last = true;
1804 }
1805 offset = eeprom->offset + (I40E_NVM_SECTOR_SIZE * i),
1806 ret_val = i40e_aq_read_nvm(hw, 0x0, offset, len,
1807 (u8 *)eeprom_buff + (I40E_NVM_SECTOR_SIZE * i),
1808 last, NULL);
1809 if (ret_val && hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
1810 dev_info(&pf->pdev->dev,
1811 "read NVM failed, invalid offset 0x%x\n",
1812 offset);
1813 break;
1814 } else if (ret_val &&
1815 hw->aq.asq_last_status == I40E_AQ_RC_EACCES) {
1816 dev_info(&pf->pdev->dev,
1817 "read NVM failed, access, offset 0x%x\n",
1818 offset);
1819 break;
1820 } else if (ret_val) {
1821 dev_info(&pf->pdev->dev,
1822 "read NVM failed offset %d err=%d status=0x%x\n",
1823 offset, ret_val, hw->aq.asq_last_status);
1824 break;
1825 }
1826 }
1827
1828 i40e_release_nvm(hw);
1829 memcpy(bytes, (u8 *)eeprom_buff, eeprom->len);
1830free_buff:
1831 kfree(eeprom_buff);
1832 return ret_val;
1833}
1834
1835static int i40e_get_eeprom_len(struct net_device *netdev)
1836{
1837 struct i40e_netdev_priv *np = netdev_priv(netdev);
1838 struct i40e_hw *hw = &np->vsi->back->hw;
1839 u32 val;
1840
1841#define X722_EEPROM_SCOPE_LIMIT 0x5B9FFF
1842 if (hw->mac.type == I40E_MAC_X722) {
1843 val = X722_EEPROM_SCOPE_LIMIT + 1;
1844 return val;
1845 }
1846 val = (rd32(hw, I40E_GLPCI_LBARCTRL)
1847 & I40E_GLPCI_LBARCTRL_FL_SIZE_MASK)
1848 >> I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT;
1849
1850 val = (64 * 1024) * BIT(val);
1851 return val;
1852}
1853
1854static int i40e_set_eeprom(struct net_device *netdev,
1855 struct ethtool_eeprom *eeprom, u8 *bytes)
1856{
1857 struct i40e_netdev_priv *np = netdev_priv(netdev);
1858 struct i40e_hw *hw = &np->vsi->back->hw;
1859 struct i40e_pf *pf = np->vsi->back;
1860 struct i40e_nvm_access *cmd = (struct i40e_nvm_access *)eeprom;
1861 int ret_val = 0;
1862 int errno = 0;
1863 u32 magic;
1864
1865
1866 magic = hw->vendor_id | (hw->device_id << 16);
1867 if (eeprom->magic == magic)
1868 errno = -EOPNOTSUPP;
1869
1870 else if (!eeprom->magic || (eeprom->magic >> 16) != hw->device_id)
1871 errno = -EINVAL;
1872 else if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
1873 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
1874 errno = -EBUSY;
1875 else
1876 ret_val = i40e_nvmupd_command(hw, cmd, bytes, &errno);
1877
1878 if ((errno || ret_val) && (hw->debug_mask & I40E_DEBUG_NVM))
1879 dev_info(&pf->pdev->dev,
1880 "NVMUpdate write failed err=%d status=0x%x errno=%d module=%d offset=0x%x size=%d\n",
1881 ret_val, hw->aq.asq_last_status, errno,
1882 (u8)(cmd->config & I40E_NVM_MOD_PNT_MASK),
1883 cmd->offset, cmd->data_size);
1884
1885 return errno;
1886}
1887
1888static void i40e_get_drvinfo(struct net_device *netdev,
1889 struct ethtool_drvinfo *drvinfo)
1890{
1891 struct i40e_netdev_priv *np = netdev_priv(netdev);
1892 struct i40e_vsi *vsi = np->vsi;
1893 struct i40e_pf *pf = vsi->back;
1894
1895 strlcpy(drvinfo->driver, i40e_driver_name, sizeof(drvinfo->driver));
1896 strlcpy(drvinfo->version, i40e_driver_version_str,
1897 sizeof(drvinfo->version));
1898 strlcpy(drvinfo->fw_version, i40e_nvm_version_str(&pf->hw),
1899 sizeof(drvinfo->fw_version));
1900 strlcpy(drvinfo->bus_info, pci_name(pf->pdev),
1901 sizeof(drvinfo->bus_info));
1902 drvinfo->n_priv_flags = I40E_PRIV_FLAGS_STR_LEN;
1903 if (pf->hw.pf_id == 0)
1904 drvinfo->n_priv_flags += I40E_GL_PRIV_FLAGS_STR_LEN;
1905}
1906
1907static void i40e_get_ringparam(struct net_device *netdev,
1908 struct ethtool_ringparam *ring)
1909{
1910 struct i40e_netdev_priv *np = netdev_priv(netdev);
1911 struct i40e_pf *pf = np->vsi->back;
1912 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
1913
1914 ring->rx_max_pending = I40E_MAX_NUM_DESCRIPTORS;
1915 ring->tx_max_pending = I40E_MAX_NUM_DESCRIPTORS;
1916 ring->rx_mini_max_pending = 0;
1917 ring->rx_jumbo_max_pending = 0;
1918 ring->rx_pending = vsi->rx_rings[0]->count;
1919 ring->tx_pending = vsi->tx_rings[0]->count;
1920 ring->rx_mini_pending = 0;
1921 ring->rx_jumbo_pending = 0;
1922}
1923
1924static bool i40e_active_tx_ring_index(struct i40e_vsi *vsi, u16 index)
1925{
1926 if (i40e_enabled_xdp_vsi(vsi)) {
1927 return index < vsi->num_queue_pairs ||
1928 (index >= vsi->alloc_queue_pairs &&
1929 index < vsi->alloc_queue_pairs + vsi->num_queue_pairs);
1930 }
1931
1932 return index < vsi->num_queue_pairs;
1933}
1934
1935static int i40e_set_ringparam(struct net_device *netdev,
1936 struct ethtool_ringparam *ring)
1937{
1938 struct i40e_ring *tx_rings = NULL, *rx_rings = NULL;
1939 struct i40e_netdev_priv *np = netdev_priv(netdev);
1940 struct i40e_hw *hw = &np->vsi->back->hw;
1941 struct i40e_vsi *vsi = np->vsi;
1942 struct i40e_pf *pf = vsi->back;
1943 u32 new_rx_count, new_tx_count;
1944 u16 tx_alloc_queue_pairs;
1945 int timeout = 50;
1946 int i, err = 0;
1947
1948 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1949 return -EINVAL;
1950
1951 if (ring->tx_pending > I40E_MAX_NUM_DESCRIPTORS ||
1952 ring->tx_pending < I40E_MIN_NUM_DESCRIPTORS ||
1953 ring->rx_pending > I40E_MAX_NUM_DESCRIPTORS ||
1954 ring->rx_pending < I40E_MIN_NUM_DESCRIPTORS) {
1955 netdev_info(netdev,
1956 "Descriptors requested (Tx: %d / Rx: %d) out of range [%d-%d]\n",
1957 ring->tx_pending, ring->rx_pending,
1958 I40E_MIN_NUM_DESCRIPTORS, I40E_MAX_NUM_DESCRIPTORS);
1959 return -EINVAL;
1960 }
1961
1962 new_tx_count = ALIGN(ring->tx_pending, I40E_REQ_DESCRIPTOR_MULTIPLE);
1963 new_rx_count = ALIGN(ring->rx_pending, I40E_REQ_DESCRIPTOR_MULTIPLE);
1964
1965
1966 if ((new_tx_count == vsi->tx_rings[0]->count) &&
1967 (new_rx_count == vsi->rx_rings[0]->count))
1968 return 0;
1969
1970
1971
1972
1973
1974 if (i40e_xsk_any_rx_ring_enabled(vsi))
1975 return -EBUSY;
1976
1977 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) {
1978 timeout--;
1979 if (!timeout)
1980 return -EBUSY;
1981 usleep_range(1000, 2000);
1982 }
1983
1984 if (!netif_running(vsi->netdev)) {
1985
1986 for (i = 0; i < vsi->num_queue_pairs; i++) {
1987 vsi->tx_rings[i]->count = new_tx_count;
1988 vsi->rx_rings[i]->count = new_rx_count;
1989 if (i40e_enabled_xdp_vsi(vsi))
1990 vsi->xdp_rings[i]->count = new_tx_count;
1991 }
1992 vsi->num_tx_desc = new_tx_count;
1993 vsi->num_rx_desc = new_rx_count;
1994 goto done;
1995 }
1996
1997
1998
1999
2000
2001
2002
2003 tx_alloc_queue_pairs = vsi->alloc_queue_pairs *
2004 (i40e_enabled_xdp_vsi(vsi) ? 2 : 1);
2005 if (new_tx_count != vsi->tx_rings[0]->count) {
2006 netdev_info(netdev,
2007 "Changing Tx descriptor count from %d to %d.\n",
2008 vsi->tx_rings[0]->count, new_tx_count);
2009 tx_rings = kcalloc(tx_alloc_queue_pairs,
2010 sizeof(struct i40e_ring), GFP_KERNEL);
2011 if (!tx_rings) {
2012 err = -ENOMEM;
2013 goto done;
2014 }
2015
2016 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2017 if (!i40e_active_tx_ring_index(vsi, i))
2018 continue;
2019
2020 tx_rings[i] = *vsi->tx_rings[i];
2021 tx_rings[i].count = new_tx_count;
2022
2023
2024
2025 tx_rings[i].desc = NULL;
2026 tx_rings[i].rx_bi = NULL;
2027 err = i40e_setup_tx_descriptors(&tx_rings[i]);
2028 if (err) {
2029 while (i) {
2030 i--;
2031 if (!i40e_active_tx_ring_index(vsi, i))
2032 continue;
2033 i40e_free_tx_resources(&tx_rings[i]);
2034 }
2035 kfree(tx_rings);
2036 tx_rings = NULL;
2037
2038 goto done;
2039 }
2040 }
2041 }
2042
2043
2044 if (new_rx_count != vsi->rx_rings[0]->count) {
2045 netdev_info(netdev,
2046 "Changing Rx descriptor count from %d to %d\n",
2047 vsi->rx_rings[0]->count, new_rx_count);
2048 rx_rings = kcalloc(vsi->alloc_queue_pairs,
2049 sizeof(struct i40e_ring), GFP_KERNEL);
2050 if (!rx_rings) {
2051 err = -ENOMEM;
2052 goto free_tx;
2053 }
2054
2055 for (i = 0; i < vsi->num_queue_pairs; i++) {
2056 u16 unused;
2057
2058
2059 rx_rings[i] = *vsi->rx_rings[i];
2060 rx_rings[i].count = new_rx_count;
2061
2062
2063
2064 rx_rings[i].desc = NULL;
2065 rx_rings[i].rx_bi = NULL;
2066
2067 memset(&rx_rings[i].xdp_rxq, 0, sizeof(rx_rings[i].xdp_rxq));
2068
2069
2070
2071 rx_rings[i].tail = hw->hw_addr + I40E_PRTGEN_STATUS;
2072 err = i40e_setup_rx_descriptors(&rx_rings[i]);
2073 if (err)
2074 goto rx_unwind;
2075
2076
2077
2078
2079 unused = I40E_DESC_UNUSED(&rx_rings[i]);
2080 err = i40e_alloc_rx_buffers(&rx_rings[i], unused);
2081rx_unwind:
2082 if (err) {
2083 do {
2084 i40e_free_rx_resources(&rx_rings[i]);
2085 } while (i--);
2086 kfree(rx_rings);
2087 rx_rings = NULL;
2088
2089 goto free_tx;
2090 }
2091 }
2092 }
2093
2094
2095
2096
2097 i40e_down(vsi);
2098
2099 if (tx_rings) {
2100 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2101 if (i40e_active_tx_ring_index(vsi, i)) {
2102 i40e_free_tx_resources(vsi->tx_rings[i]);
2103 *vsi->tx_rings[i] = tx_rings[i];
2104 }
2105 }
2106 kfree(tx_rings);
2107 tx_rings = NULL;
2108 }
2109
2110 if (rx_rings) {
2111 for (i = 0; i < vsi->num_queue_pairs; i++) {
2112 i40e_free_rx_resources(vsi->rx_rings[i]);
2113
2114 rx_rings[i].tail = vsi->rx_rings[i]->tail;
2115
2116
2117
2118
2119
2120 rx_rings[i].next_to_use = 0;
2121 rx_rings[i].next_to_clean = 0;
2122 rx_rings[i].next_to_alloc = 0;
2123
2124 *vsi->rx_rings[i] = rx_rings[i];
2125 }
2126 kfree(rx_rings);
2127 rx_rings = NULL;
2128 }
2129
2130 vsi->num_tx_desc = new_tx_count;
2131 vsi->num_rx_desc = new_rx_count;
2132 i40e_up(vsi);
2133
2134free_tx:
2135
2136 if (tx_rings) {
2137 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2138 if (i40e_active_tx_ring_index(vsi, i))
2139 i40e_free_tx_resources(vsi->tx_rings[i]);
2140 }
2141 kfree(tx_rings);
2142 tx_rings = NULL;
2143 }
2144
2145done:
2146 clear_bit(__I40E_CONFIG_BUSY, pf->state);
2147
2148 return err;
2149}
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165static int i40e_get_stats_count(struct net_device *netdev)
2166{
2167 struct i40e_netdev_priv *np = netdev_priv(netdev);
2168 struct i40e_vsi *vsi = np->vsi;
2169 struct i40e_pf *pf = vsi->back;
2170 int stats_len;
2171
2172 if (vsi == pf->vsi[pf->lan_vsi] && pf->hw.partition_id == 1)
2173 stats_len = I40E_PF_STATS_LEN;
2174 else
2175 stats_len = I40E_VSI_STATS_LEN;
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191 stats_len += I40E_QUEUE_STATS_LEN * 2 * netdev->num_tx_queues;
2192
2193 return stats_len;
2194}
2195
2196static int i40e_get_sset_count(struct net_device *netdev, int sset)
2197{
2198 struct i40e_netdev_priv *np = netdev_priv(netdev);
2199 struct i40e_vsi *vsi = np->vsi;
2200 struct i40e_pf *pf = vsi->back;
2201
2202 switch (sset) {
2203 case ETH_SS_TEST:
2204 return I40E_TEST_LEN;
2205 case ETH_SS_STATS:
2206 return i40e_get_stats_count(netdev);
2207 case ETH_SS_PRIV_FLAGS:
2208 return I40E_PRIV_FLAGS_STR_LEN +
2209 (pf->hw.pf_id == 0 ? I40E_GL_PRIV_FLAGS_STR_LEN : 0);
2210 default:
2211 return -EOPNOTSUPP;
2212 }
2213}
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224static inline struct i40e_pfc_stats
2225i40e_get_pfc_stats(struct i40e_pf *pf, unsigned int i)
2226{
2227#define I40E_GET_PFC_STAT(stat, priority) \
2228 .stat = pf->stats.stat[priority]
2229
2230 struct i40e_pfc_stats pfc = {
2231 I40E_GET_PFC_STAT(priority_xon_rx, i),
2232 I40E_GET_PFC_STAT(priority_xoff_rx, i),
2233 I40E_GET_PFC_STAT(priority_xon_tx, i),
2234 I40E_GET_PFC_STAT(priority_xoff_tx, i),
2235 I40E_GET_PFC_STAT(priority_xon_2_xoff, i),
2236 };
2237 return pfc;
2238}
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254static void i40e_get_ethtool_stats(struct net_device *netdev,
2255 struct ethtool_stats *stats, u64 *data)
2256{
2257 struct i40e_netdev_priv *np = netdev_priv(netdev);
2258 struct i40e_vsi *vsi = np->vsi;
2259 struct i40e_pf *pf = vsi->back;
2260 struct i40e_veb *veb = NULL;
2261 unsigned int i;
2262 bool veb_stats;
2263 u64 *p = data;
2264
2265 i40e_update_stats(vsi);
2266
2267 i40e_add_ethtool_stats(&data, i40e_get_vsi_stats_struct(vsi),
2268 i40e_gstrings_net_stats);
2269
2270 i40e_add_ethtool_stats(&data, vsi, i40e_gstrings_misc_stats);
2271
2272 rcu_read_lock();
2273 for (i = 0; i < netdev->num_tx_queues; i++) {
2274 i40e_add_queue_stats(&data, READ_ONCE(vsi->tx_rings[i]));
2275 i40e_add_queue_stats(&data, READ_ONCE(vsi->rx_rings[i]));
2276 }
2277 rcu_read_unlock();
2278
2279 if (vsi != pf->vsi[pf->lan_vsi] || pf->hw.partition_id != 1)
2280 goto check_data_pointer;
2281
2282 veb_stats = ((pf->lan_veb != I40E_NO_VEB) &&
2283 (pf->lan_veb < I40E_MAX_VEB) &&
2284 (pf->flags & I40E_FLAG_VEB_STATS_ENABLED));
2285
2286 if (veb_stats) {
2287 veb = pf->veb[pf->lan_veb];
2288 i40e_update_veb_stats(veb);
2289 }
2290
2291
2292
2293
2294
2295 i40e_add_ethtool_stats(&data, veb_stats ? veb : NULL,
2296 i40e_gstrings_veb_stats);
2297
2298 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2299 i40e_add_ethtool_stats(&data, veb_stats ? veb : NULL,
2300 i40e_gstrings_veb_tc_stats);
2301
2302 i40e_add_ethtool_stats(&data, pf, i40e_gstrings_stats);
2303
2304 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
2305 struct i40e_pfc_stats pfc = i40e_get_pfc_stats(pf, i);
2306
2307 i40e_add_ethtool_stats(&data, &pfc, i40e_gstrings_pfc_stats);
2308 }
2309
2310check_data_pointer:
2311 WARN_ONCE(data - p != i40e_get_stats_count(netdev),
2312 "ethtool stats count mismatch!");
2313}
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325static void i40e_get_stat_strings(struct net_device *netdev, u8 *data)
2326{
2327 struct i40e_netdev_priv *np = netdev_priv(netdev);
2328 struct i40e_vsi *vsi = np->vsi;
2329 struct i40e_pf *pf = vsi->back;
2330 unsigned int i;
2331 u8 *p = data;
2332
2333 i40e_add_stat_strings(&data, i40e_gstrings_net_stats);
2334
2335 i40e_add_stat_strings(&data, i40e_gstrings_misc_stats);
2336
2337 for (i = 0; i < netdev->num_tx_queues; i++) {
2338 i40e_add_stat_strings(&data, i40e_gstrings_queue_stats,
2339 "tx", i);
2340 i40e_add_stat_strings(&data, i40e_gstrings_queue_stats,
2341 "rx", i);
2342 }
2343
2344 if (vsi != pf->vsi[pf->lan_vsi] || pf->hw.partition_id != 1)
2345 goto check_data_pointer;
2346
2347 i40e_add_stat_strings(&data, i40e_gstrings_veb_stats);
2348
2349 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2350 i40e_add_stat_strings(&data, i40e_gstrings_veb_tc_stats, i);
2351
2352 i40e_add_stat_strings(&data, i40e_gstrings_stats);
2353
2354 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
2355 i40e_add_stat_strings(&data, i40e_gstrings_pfc_stats, i);
2356
2357check_data_pointer:
2358 WARN_ONCE(data - p != i40e_get_stats_count(netdev) * ETH_GSTRING_LEN,
2359 "stat strings count mismatch!");
2360}
2361
2362static void i40e_get_priv_flag_strings(struct net_device *netdev, u8 *data)
2363{
2364 struct i40e_netdev_priv *np = netdev_priv(netdev);
2365 struct i40e_vsi *vsi = np->vsi;
2366 struct i40e_pf *pf = vsi->back;
2367 char *p = (char *)data;
2368 unsigned int i;
2369
2370 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++) {
2371 snprintf(p, ETH_GSTRING_LEN, "%s",
2372 i40e_gstrings_priv_flags[i].flag_string);
2373 p += ETH_GSTRING_LEN;
2374 }
2375 if (pf->hw.pf_id != 0)
2376 return;
2377 for (i = 0; i < I40E_GL_PRIV_FLAGS_STR_LEN; i++) {
2378 snprintf(p, ETH_GSTRING_LEN, "%s",
2379 i40e_gl_gstrings_priv_flags[i].flag_string);
2380 p += ETH_GSTRING_LEN;
2381 }
2382}
2383
2384static void i40e_get_strings(struct net_device *netdev, u32 stringset,
2385 u8 *data)
2386{
2387 switch (stringset) {
2388 case ETH_SS_TEST:
2389 memcpy(data, i40e_gstrings_test,
2390 I40E_TEST_LEN * ETH_GSTRING_LEN);
2391 break;
2392 case ETH_SS_STATS:
2393 i40e_get_stat_strings(netdev, data);
2394 break;
2395 case ETH_SS_PRIV_FLAGS:
2396 i40e_get_priv_flag_strings(netdev, data);
2397 break;
2398 default:
2399 break;
2400 }
2401}
2402
2403static int i40e_get_ts_info(struct net_device *dev,
2404 struct ethtool_ts_info *info)
2405{
2406 struct i40e_pf *pf = i40e_netdev_to_pf(dev);
2407
2408
2409 if (!(pf->flags & I40E_FLAG_PTP))
2410 return ethtool_op_get_ts_info(dev, info);
2411
2412 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2413 SOF_TIMESTAMPING_RX_SOFTWARE |
2414 SOF_TIMESTAMPING_SOFTWARE |
2415 SOF_TIMESTAMPING_TX_HARDWARE |
2416 SOF_TIMESTAMPING_RX_HARDWARE |
2417 SOF_TIMESTAMPING_RAW_HARDWARE;
2418
2419 if (pf->ptp_clock)
2420 info->phc_index = ptp_clock_index(pf->ptp_clock);
2421 else
2422 info->phc_index = -1;
2423
2424 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
2425
2426 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
2427 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2428 BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2429 BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ);
2430
2431 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE)
2432 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2433 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2434 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
2435 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2436 BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
2437 BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2438 BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2439 BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ);
2440
2441 return 0;
2442}
2443
2444static u64 i40e_link_test(struct net_device *netdev, u64 *data)
2445{
2446 struct i40e_netdev_priv *np = netdev_priv(netdev);
2447 struct i40e_pf *pf = np->vsi->back;
2448 i40e_status status;
2449 bool link_up = false;
2450
2451 netif_info(pf, hw, netdev, "link test\n");
2452 status = i40e_get_link_status(&pf->hw, &link_up);
2453 if (status) {
2454 netif_err(pf, drv, netdev, "link query timed out, please retry test\n");
2455 *data = 1;
2456 return *data;
2457 }
2458
2459 if (link_up)
2460 *data = 0;
2461 else
2462 *data = 1;
2463
2464 return *data;
2465}
2466
2467static u64 i40e_reg_test(struct net_device *netdev, u64 *data)
2468{
2469 struct i40e_netdev_priv *np = netdev_priv(netdev);
2470 struct i40e_pf *pf = np->vsi->back;
2471
2472 netif_info(pf, hw, netdev, "register test\n");
2473 *data = i40e_diag_reg_test(&pf->hw);
2474
2475 return *data;
2476}
2477
2478static u64 i40e_eeprom_test(struct net_device *netdev, u64 *data)
2479{
2480 struct i40e_netdev_priv *np = netdev_priv(netdev);
2481 struct i40e_pf *pf = np->vsi->back;
2482
2483 netif_info(pf, hw, netdev, "eeprom test\n");
2484 *data = i40e_diag_eeprom_test(&pf->hw);
2485
2486
2487 pf->hw.nvmupd_state = I40E_NVMUPD_STATE_INIT;
2488
2489 return *data;
2490}
2491
2492static u64 i40e_intr_test(struct net_device *netdev, u64 *data)
2493{
2494 struct i40e_netdev_priv *np = netdev_priv(netdev);
2495 struct i40e_pf *pf = np->vsi->back;
2496 u16 swc_old = pf->sw_int_count;
2497
2498 netif_info(pf, hw, netdev, "interrupt test\n");
2499 wr32(&pf->hw, I40E_PFINT_DYN_CTL0,
2500 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
2501 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
2502 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
2503 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
2504 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
2505 usleep_range(1000, 2000);
2506 *data = (swc_old == pf->sw_int_count);
2507
2508 return *data;
2509}
2510
2511static inline bool i40e_active_vfs(struct i40e_pf *pf)
2512{
2513 struct i40e_vf *vfs = pf->vf;
2514 int i;
2515
2516 for (i = 0; i < pf->num_alloc_vfs; i++)
2517 if (test_bit(I40E_VF_STATE_ACTIVE, &vfs[i].vf_states))
2518 return true;
2519 return false;
2520}
2521
2522static inline bool i40e_active_vmdqs(struct i40e_pf *pf)
2523{
2524 return !!i40e_find_vsi_by_type(pf, I40E_VSI_VMDQ2);
2525}
2526
2527static void i40e_diag_test(struct net_device *netdev,
2528 struct ethtool_test *eth_test, u64 *data)
2529{
2530 struct i40e_netdev_priv *np = netdev_priv(netdev);
2531 bool if_running = netif_running(netdev);
2532 struct i40e_pf *pf = np->vsi->back;
2533
2534 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2535
2536 netif_info(pf, drv, netdev, "offline testing starting\n");
2537
2538 set_bit(__I40E_TESTING, pf->state);
2539
2540 if (i40e_active_vfs(pf) || i40e_active_vmdqs(pf)) {
2541 dev_warn(&pf->pdev->dev,
2542 "Please take active VFs and Netqueues offline and restart the adapter before running NIC diagnostics\n");
2543 data[I40E_ETH_TEST_REG] = 1;
2544 data[I40E_ETH_TEST_EEPROM] = 1;
2545 data[I40E_ETH_TEST_INTR] = 1;
2546 data[I40E_ETH_TEST_LINK] = 1;
2547 eth_test->flags |= ETH_TEST_FL_FAILED;
2548 clear_bit(__I40E_TESTING, pf->state);
2549 goto skip_ol_tests;
2550 }
2551
2552
2553 if (if_running)
2554
2555 i40e_close(netdev);
2556 else
2557
2558
2559
2560
2561
2562 i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true);
2563
2564 if (i40e_link_test(netdev, &data[I40E_ETH_TEST_LINK]))
2565 eth_test->flags |= ETH_TEST_FL_FAILED;
2566
2567 if (i40e_eeprom_test(netdev, &data[I40E_ETH_TEST_EEPROM]))
2568 eth_test->flags |= ETH_TEST_FL_FAILED;
2569
2570 if (i40e_intr_test(netdev, &data[I40E_ETH_TEST_INTR]))
2571 eth_test->flags |= ETH_TEST_FL_FAILED;
2572
2573
2574 if (i40e_reg_test(netdev, &data[I40E_ETH_TEST_REG]))
2575 eth_test->flags |= ETH_TEST_FL_FAILED;
2576
2577 clear_bit(__I40E_TESTING, pf->state);
2578 i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true);
2579
2580 if (if_running)
2581 i40e_open(netdev);
2582 } else {
2583
2584 netif_info(pf, drv, netdev, "online testing starting\n");
2585
2586 if (i40e_link_test(netdev, &data[I40E_ETH_TEST_LINK]))
2587 eth_test->flags |= ETH_TEST_FL_FAILED;
2588
2589
2590 data[I40E_ETH_TEST_REG] = 0;
2591 data[I40E_ETH_TEST_EEPROM] = 0;
2592 data[I40E_ETH_TEST_INTR] = 0;
2593 }
2594
2595skip_ol_tests:
2596
2597 netif_info(pf, drv, netdev, "testing finished\n");
2598}
2599
2600static void i40e_get_wol(struct net_device *netdev,
2601 struct ethtool_wolinfo *wol)
2602{
2603 struct i40e_netdev_priv *np = netdev_priv(netdev);
2604 struct i40e_pf *pf = np->vsi->back;
2605 struct i40e_hw *hw = &pf->hw;
2606 u16 wol_nvm_bits;
2607
2608
2609 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
2610 if ((BIT(hw->port) & wol_nvm_bits) || (hw->partition_id != 1)) {
2611 wol->supported = 0;
2612 wol->wolopts = 0;
2613 } else {
2614 wol->supported = WAKE_MAGIC;
2615 wol->wolopts = (pf->wol_en ? WAKE_MAGIC : 0);
2616 }
2617}
2618
2619
2620
2621
2622
2623
2624static int i40e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2625{
2626 struct i40e_netdev_priv *np = netdev_priv(netdev);
2627 struct i40e_pf *pf = np->vsi->back;
2628 struct i40e_vsi *vsi = np->vsi;
2629 struct i40e_hw *hw = &pf->hw;
2630 u16 wol_nvm_bits;
2631
2632
2633 if (hw->partition_id != 1) {
2634 i40e_partition_setting_complaint(pf);
2635 return -EOPNOTSUPP;
2636 }
2637
2638 if (vsi != pf->vsi[pf->lan_vsi])
2639 return -EOPNOTSUPP;
2640
2641
2642 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
2643 if (BIT(hw->port) & wol_nvm_bits)
2644 return -EOPNOTSUPP;
2645
2646
2647 if (wol->wolopts & ~WAKE_MAGIC)
2648 return -EOPNOTSUPP;
2649
2650
2651 if (pf->wol_en != !!wol->wolopts) {
2652 pf->wol_en = !!wol->wolopts;
2653 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
2654 }
2655
2656 return 0;
2657}
2658
2659static int i40e_set_phys_id(struct net_device *netdev,
2660 enum ethtool_phys_id_state state)
2661{
2662 struct i40e_netdev_priv *np = netdev_priv(netdev);
2663 i40e_status ret = 0;
2664 struct i40e_pf *pf = np->vsi->back;
2665 struct i40e_hw *hw = &pf->hw;
2666 int blink_freq = 2;
2667 u16 temp_status;
2668
2669 switch (state) {
2670 case ETHTOOL_ID_ACTIVE:
2671 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS)) {
2672 pf->led_status = i40e_led_get(hw);
2673 } else {
2674 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE))
2675 i40e_aq_set_phy_debug(hw, I40E_PHY_DEBUG_ALL,
2676 NULL);
2677 ret = i40e_led_get_phy(hw, &temp_status,
2678 &pf->phy_led_val);
2679 pf->led_status = temp_status;
2680 }
2681 return blink_freq;
2682 case ETHTOOL_ID_ON:
2683 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS))
2684 i40e_led_set(hw, 0xf, false);
2685 else
2686 ret = i40e_led_set_phy(hw, true, pf->led_status, 0);
2687 break;
2688 case ETHTOOL_ID_OFF:
2689 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS))
2690 i40e_led_set(hw, 0x0, false);
2691 else
2692 ret = i40e_led_set_phy(hw, false, pf->led_status, 0);
2693 break;
2694 case ETHTOOL_ID_INACTIVE:
2695 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS)) {
2696 i40e_led_set(hw, pf->led_status, false);
2697 } else {
2698 ret = i40e_led_set_phy(hw, false, pf->led_status,
2699 (pf->phy_led_val |
2700 I40E_PHY_LED_MODE_ORIG));
2701 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE))
2702 i40e_aq_set_phy_debug(hw, 0, NULL);
2703 }
2704 break;
2705 default:
2706 break;
2707 }
2708 if (ret)
2709 return -ENOENT;
2710 else
2711 return 0;
2712}
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729static int __i40e_get_coalesce(struct net_device *netdev,
2730 struct ethtool_coalesce *ec,
2731 int queue)
2732{
2733 struct i40e_netdev_priv *np = netdev_priv(netdev);
2734 struct i40e_ring *rx_ring, *tx_ring;
2735 struct i40e_vsi *vsi = np->vsi;
2736
2737 ec->tx_max_coalesced_frames_irq = vsi->work_limit;
2738 ec->rx_max_coalesced_frames_irq = vsi->work_limit;
2739
2740
2741
2742
2743 if (queue < 0)
2744 queue = 0;
2745 else if (queue >= vsi->num_queue_pairs)
2746 return -EINVAL;
2747
2748 rx_ring = vsi->rx_rings[queue];
2749 tx_ring = vsi->tx_rings[queue];
2750
2751 if (ITR_IS_DYNAMIC(rx_ring->itr_setting))
2752 ec->use_adaptive_rx_coalesce = 1;
2753
2754 if (ITR_IS_DYNAMIC(tx_ring->itr_setting))
2755 ec->use_adaptive_tx_coalesce = 1;
2756
2757 ec->rx_coalesce_usecs = rx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
2758 ec->tx_coalesce_usecs = tx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
2759
2760
2761
2762
2763
2764
2765
2766 ec->rx_coalesce_usecs_high = vsi->int_rate_limit;
2767 ec->tx_coalesce_usecs_high = vsi->int_rate_limit;
2768
2769 return 0;
2770}
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781static int i40e_get_coalesce(struct net_device *netdev,
2782 struct ethtool_coalesce *ec)
2783{
2784 return __i40e_get_coalesce(netdev, ec, -1);
2785}
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795static int i40e_get_per_queue_coalesce(struct net_device *netdev, u32 queue,
2796 struct ethtool_coalesce *ec)
2797{
2798 return __i40e_get_coalesce(netdev, ec, queue);
2799}
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809static void i40e_set_itr_per_queue(struct i40e_vsi *vsi,
2810 struct ethtool_coalesce *ec,
2811 int queue)
2812{
2813 struct i40e_ring *rx_ring = vsi->rx_rings[queue];
2814 struct i40e_ring *tx_ring = vsi->tx_rings[queue];
2815 struct i40e_pf *pf = vsi->back;
2816 struct i40e_hw *hw = &pf->hw;
2817 struct i40e_q_vector *q_vector;
2818 u16 intrl;
2819
2820 intrl = i40e_intrl_usec_to_reg(vsi->int_rate_limit);
2821
2822 rx_ring->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs);
2823 tx_ring->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs);
2824
2825 if (ec->use_adaptive_rx_coalesce)
2826 rx_ring->itr_setting |= I40E_ITR_DYNAMIC;
2827 else
2828 rx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;
2829
2830 if (ec->use_adaptive_tx_coalesce)
2831 tx_ring->itr_setting |= I40E_ITR_DYNAMIC;
2832 else
2833 tx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;
2834
2835 q_vector = rx_ring->q_vector;
2836 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting);
2837
2838 q_vector = tx_ring->q_vector;
2839 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting);
2840
2841
2842
2843
2844
2845
2846 wr32(hw, I40E_PFINT_RATEN(q_vector->reg_idx), intrl);
2847 i40e_flush(hw);
2848}
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858static int __i40e_set_coalesce(struct net_device *netdev,
2859 struct ethtool_coalesce *ec,
2860 int queue)
2861{
2862 struct i40e_netdev_priv *np = netdev_priv(netdev);
2863 u16 intrl_reg, cur_rx_itr, cur_tx_itr;
2864 struct i40e_vsi *vsi = np->vsi;
2865 struct i40e_pf *pf = vsi->back;
2866 int i;
2867
2868 if (ec->tx_max_coalesced_frames_irq || ec->rx_max_coalesced_frames_irq)
2869 vsi->work_limit = ec->tx_max_coalesced_frames_irq;
2870
2871 if (queue < 0) {
2872 cur_rx_itr = vsi->rx_rings[0]->itr_setting;
2873 cur_tx_itr = vsi->tx_rings[0]->itr_setting;
2874 } else if (queue < vsi->num_queue_pairs) {
2875 cur_rx_itr = vsi->rx_rings[queue]->itr_setting;
2876 cur_tx_itr = vsi->tx_rings[queue]->itr_setting;
2877 } else {
2878 netif_info(pf, drv, netdev, "Invalid queue value, queue range is 0 - %d\n",
2879 vsi->num_queue_pairs - 1);
2880 return -EINVAL;
2881 }
2882
2883 cur_tx_itr &= ~I40E_ITR_DYNAMIC;
2884 cur_rx_itr &= ~I40E_ITR_DYNAMIC;
2885
2886
2887 if (ec->tx_coalesce_usecs_high != vsi->int_rate_limit) {
2888 netif_info(pf, drv, netdev, "tx-usecs-high is not used, please program rx-usecs-high\n");
2889 return -EINVAL;
2890 }
2891
2892 if (ec->rx_coalesce_usecs_high > INTRL_REG_TO_USEC(I40E_MAX_INTRL)) {
2893 netif_info(pf, drv, netdev, "Invalid value, rx-usecs-high range is 0-%lu\n",
2894 INTRL_REG_TO_USEC(I40E_MAX_INTRL));
2895 return -EINVAL;
2896 }
2897
2898 if (ec->rx_coalesce_usecs != cur_rx_itr &&
2899 ec->use_adaptive_rx_coalesce) {
2900 netif_info(pf, drv, netdev, "RX interrupt moderation cannot be changed if adaptive-rx is enabled.\n");
2901 return -EINVAL;
2902 }
2903
2904 if (ec->rx_coalesce_usecs > I40E_MAX_ITR) {
2905 netif_info(pf, drv, netdev, "Invalid value, rx-usecs range is 0-8160\n");
2906 return -EINVAL;
2907 }
2908
2909 if (ec->tx_coalesce_usecs != cur_tx_itr &&
2910 ec->use_adaptive_tx_coalesce) {
2911 netif_info(pf, drv, netdev, "TX interrupt moderation cannot be changed if adaptive-tx is enabled.\n");
2912 return -EINVAL;
2913 }
2914
2915 if (ec->tx_coalesce_usecs > I40E_MAX_ITR) {
2916 netif_info(pf, drv, netdev, "Invalid value, tx-usecs range is 0-8160\n");
2917 return -EINVAL;
2918 }
2919
2920 if (ec->use_adaptive_rx_coalesce && !cur_rx_itr)
2921 ec->rx_coalesce_usecs = I40E_MIN_ITR;
2922
2923 if (ec->use_adaptive_tx_coalesce && !cur_tx_itr)
2924 ec->tx_coalesce_usecs = I40E_MIN_ITR;
2925
2926 intrl_reg = i40e_intrl_usec_to_reg(ec->rx_coalesce_usecs_high);
2927 vsi->int_rate_limit = INTRL_REG_TO_USEC(intrl_reg);
2928 if (vsi->int_rate_limit != ec->rx_coalesce_usecs_high) {
2929 netif_info(pf, drv, netdev, "Interrupt rate limit rounded down to %d\n",
2930 vsi->int_rate_limit);
2931 }
2932
2933
2934
2935
2936 if (queue < 0) {
2937 for (i = 0; i < vsi->num_queue_pairs; i++)
2938 i40e_set_itr_per_queue(vsi, ec, i);
2939 } else {
2940 i40e_set_itr_per_queue(vsi, ec, queue);
2941 }
2942
2943 return 0;
2944}
2945
2946
2947
2948
2949
2950
2951
2952
2953static int i40e_set_coalesce(struct net_device *netdev,
2954 struct ethtool_coalesce *ec)
2955{
2956 return __i40e_set_coalesce(netdev, ec, -1);
2957}
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967static int i40e_set_per_queue_coalesce(struct net_device *netdev, u32 queue,
2968 struct ethtool_coalesce *ec)
2969{
2970 return __i40e_set_coalesce(netdev, ec, queue);
2971}
2972
2973
2974
2975
2976
2977
2978
2979
2980static int i40e_get_rss_hash_opts(struct i40e_pf *pf, struct ethtool_rxnfc *cmd)
2981{
2982 struct i40e_hw *hw = &pf->hw;
2983 u8 flow_pctype = 0;
2984 u64 i_set = 0;
2985
2986 cmd->data = 0;
2987
2988 switch (cmd->flow_type) {
2989 case TCP_V4_FLOW:
2990 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2991 break;
2992 case UDP_V4_FLOW:
2993 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2994 break;
2995 case TCP_V6_FLOW:
2996 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2997 break;
2998 case UDP_V6_FLOW:
2999 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3000 break;
3001 case SCTP_V4_FLOW:
3002 case AH_ESP_V4_FLOW:
3003 case AH_V4_FLOW:
3004 case ESP_V4_FLOW:
3005 case IPV4_FLOW:
3006 case SCTP_V6_FLOW:
3007 case AH_ESP_V6_FLOW:
3008 case AH_V6_FLOW:
3009 case ESP_V6_FLOW:
3010 case IPV6_FLOW:
3011
3012 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
3013 break;
3014 default:
3015 return -EINVAL;
3016 }
3017
3018
3019 if (flow_pctype) {
3020 i_set = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
3021 flow_pctype)) |
3022 ((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
3023 flow_pctype)) << 32);
3024 }
3025
3026
3027 if (i_set) {
3028 if (i_set & I40E_L4_SRC_MASK)
3029 cmd->data |= RXH_L4_B_0_1;
3030 if (i_set & I40E_L4_DST_MASK)
3031 cmd->data |= RXH_L4_B_2_3;
3032
3033 if (cmd->flow_type == TCP_V4_FLOW ||
3034 cmd->flow_type == UDP_V4_FLOW) {
3035 if (i_set & I40E_L3_SRC_MASK)
3036 cmd->data |= RXH_IP_SRC;
3037 if (i_set & I40E_L3_DST_MASK)
3038 cmd->data |= RXH_IP_DST;
3039 } else if (cmd->flow_type == TCP_V6_FLOW ||
3040 cmd->flow_type == UDP_V6_FLOW) {
3041 if (i_set & I40E_L3_V6_SRC_MASK)
3042 cmd->data |= RXH_IP_SRC;
3043 if (i_set & I40E_L3_V6_DST_MASK)
3044 cmd->data |= RXH_IP_DST;
3045 }
3046 }
3047
3048 return 0;
3049}
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059static int i40e_check_mask(u64 mask, u64 field)
3060{
3061 u64 value = mask & field;
3062
3063 if (value == field)
3064 return 1;
3065 else if (!value)
3066 return 0;
3067 else
3068 return -1;
3069}
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090static int i40e_parse_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,
3091 struct i40e_rx_flow_userdef *data)
3092{
3093 u64 value, mask;
3094 int valid;
3095
3096
3097 memset(data, 0, sizeof(*data));
3098
3099 if (!(fsp->flow_type & FLOW_EXT))
3100 return 0;
3101
3102 value = be64_to_cpu(*((__be64 *)fsp->h_ext.data));
3103 mask = be64_to_cpu(*((__be64 *)fsp->m_ext.data));
3104
3105#define I40E_USERDEF_FLEX_WORD GENMASK_ULL(15, 0)
3106#define I40E_USERDEF_FLEX_OFFSET GENMASK_ULL(31, 16)
3107#define I40E_USERDEF_FLEX_FILTER GENMASK_ULL(31, 0)
3108
3109 valid = i40e_check_mask(mask, I40E_USERDEF_FLEX_FILTER);
3110 if (valid < 0) {
3111 return -EINVAL;
3112 } else if (valid) {
3113 data->flex_word = value & I40E_USERDEF_FLEX_WORD;
3114 data->flex_offset =
3115 (value & I40E_USERDEF_FLEX_OFFSET) >> 16;
3116 data->flex_filter = true;
3117 }
3118
3119 return 0;
3120}
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130static void i40e_fill_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,
3131 struct i40e_rx_flow_userdef *data)
3132{
3133 u64 value = 0, mask = 0;
3134
3135 if (data->flex_filter) {
3136 value |= data->flex_word;
3137 value |= (u64)data->flex_offset << 16;
3138 mask |= I40E_USERDEF_FLEX_FILTER;
3139 }
3140
3141 if (value || mask)
3142 fsp->flow_type |= FLOW_EXT;
3143
3144 *((__be64 *)fsp->h_ext.data) = cpu_to_be64(value);
3145 *((__be64 *)fsp->m_ext.data) = cpu_to_be64(mask);
3146}
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159static int i40e_get_ethtool_fdir_all(struct i40e_pf *pf,
3160 struct ethtool_rxnfc *cmd,
3161 u32 *rule_locs)
3162{
3163 struct i40e_fdir_filter *rule;
3164 struct hlist_node *node2;
3165 int cnt = 0;
3166
3167
3168 cmd->data = i40e_get_fd_cnt_all(pf);
3169
3170 hlist_for_each_entry_safe(rule, node2,
3171 &pf->fdir_filter_list, fdir_node) {
3172 if (cnt == cmd->rule_cnt)
3173 return -EMSGSIZE;
3174
3175 rule_locs[cnt] = rule->fd_id;
3176 cnt++;
3177 }
3178
3179 cmd->rule_cnt = cnt;
3180
3181 return 0;
3182}
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194static int i40e_get_ethtool_fdir_entry(struct i40e_pf *pf,
3195 struct ethtool_rxnfc *cmd)
3196{
3197 struct ethtool_rx_flow_spec *fsp =
3198 (struct ethtool_rx_flow_spec *)&cmd->fs;
3199 struct i40e_rx_flow_userdef userdef = {0};
3200 struct i40e_fdir_filter *rule = NULL;
3201 struct hlist_node *node2;
3202 u64 input_set;
3203 u16 index;
3204
3205 hlist_for_each_entry_safe(rule, node2,
3206 &pf->fdir_filter_list, fdir_node) {
3207 if (fsp->location <= rule->fd_id)
3208 break;
3209 }
3210
3211 if (!rule || fsp->location != rule->fd_id)
3212 return -EINVAL;
3213
3214 fsp->flow_type = rule->flow_type;
3215 if (fsp->flow_type == IP_USER_FLOW) {
3216 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
3217 fsp->h_u.usr_ip4_spec.proto = 0;
3218 fsp->m_u.usr_ip4_spec.proto = 0;
3219 }
3220
3221
3222
3223
3224 fsp->h_u.tcp_ip4_spec.psrc = rule->dst_port;
3225 fsp->h_u.tcp_ip4_spec.pdst = rule->src_port;
3226 fsp->h_u.tcp_ip4_spec.ip4src = rule->dst_ip;
3227 fsp->h_u.tcp_ip4_spec.ip4dst = rule->src_ip;
3228
3229 switch (rule->flow_type) {
3230 case SCTP_V4_FLOW:
3231 index = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3232 break;
3233 case TCP_V4_FLOW:
3234 index = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3235 break;
3236 case UDP_V4_FLOW:
3237 index = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3238 break;
3239 case IP_USER_FLOW:
3240 index = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3241 break;
3242 default:
3243
3244
3245
3246
3247
3248 WARN(1, "Missing input set index for flow_type %d\n",
3249 rule->flow_type);
3250 input_set = 0xFFFFFFFFFFFFFFFFULL;
3251 goto no_input_set;
3252 }
3253
3254 input_set = i40e_read_fd_input_set(pf, index);
3255
3256no_input_set:
3257 if (input_set & I40E_L3_SRC_MASK)
3258 fsp->m_u.tcp_ip4_spec.ip4src = htonl(0xFFFFFFFF);
3259
3260 if (input_set & I40E_L3_DST_MASK)
3261 fsp->m_u.tcp_ip4_spec.ip4dst = htonl(0xFFFFFFFF);
3262
3263 if (input_set & I40E_L4_SRC_MASK)
3264 fsp->m_u.tcp_ip4_spec.psrc = htons(0xFFFF);
3265
3266 if (input_set & I40E_L4_DST_MASK)
3267 fsp->m_u.tcp_ip4_spec.pdst = htons(0xFFFF);
3268
3269 if (rule->dest_ctl == I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET)
3270 fsp->ring_cookie = RX_CLS_FLOW_DISC;
3271 else
3272 fsp->ring_cookie = rule->q_index;
3273
3274 if (rule->dest_vsi != pf->vsi[pf->lan_vsi]->id) {
3275 struct i40e_vsi *vsi;
3276
3277 vsi = i40e_find_vsi_from_id(pf, rule->dest_vsi);
3278 if (vsi && vsi->type == I40E_VSI_SRIOV) {
3279
3280
3281
3282 u64 ring_vf = vsi->vf_id + 1;
3283
3284 ring_vf <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
3285 fsp->ring_cookie |= ring_vf;
3286 }
3287 }
3288
3289 if (rule->flex_filter) {
3290 userdef.flex_filter = true;
3291 userdef.flex_word = be16_to_cpu(rule->flex_word);
3292 userdef.flex_offset = rule->flex_offset;
3293 }
3294
3295 i40e_fill_rx_flow_user_data(fsp, &userdef);
3296
3297 return 0;
3298}
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308static int i40e_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3309 u32 *rule_locs)
3310{
3311 struct i40e_netdev_priv *np = netdev_priv(netdev);
3312 struct i40e_vsi *vsi = np->vsi;
3313 struct i40e_pf *pf = vsi->back;
3314 int ret = -EOPNOTSUPP;
3315
3316 switch (cmd->cmd) {
3317 case ETHTOOL_GRXRINGS:
3318 cmd->data = vsi->rss_size;
3319 ret = 0;
3320 break;
3321 case ETHTOOL_GRXFH:
3322 ret = i40e_get_rss_hash_opts(pf, cmd);
3323 break;
3324 case ETHTOOL_GRXCLSRLCNT:
3325 cmd->rule_cnt = pf->fdir_pf_active_filters;
3326
3327 cmd->data = i40e_get_fd_cnt_all(pf);
3328 ret = 0;
3329 break;
3330 case ETHTOOL_GRXCLSRULE:
3331 ret = i40e_get_ethtool_fdir_entry(pf, cmd);
3332 break;
3333 case ETHTOOL_GRXCLSRLALL:
3334 ret = i40e_get_ethtool_fdir_all(pf, cmd, rule_locs);
3335 break;
3336 default:
3337 break;
3338 }
3339
3340 return ret;
3341}
3342
3343
3344
3345
3346
3347
3348
3349
3350static u64 i40e_get_rss_hash_bits(struct ethtool_rxnfc *nfc, u64 i_setc)
3351{
3352 u64 i_set = i_setc;
3353 u64 src_l3 = 0, dst_l3 = 0;
3354
3355 if (nfc->data & RXH_L4_B_0_1)
3356 i_set |= I40E_L4_SRC_MASK;
3357 else
3358 i_set &= ~I40E_L4_SRC_MASK;
3359 if (nfc->data & RXH_L4_B_2_3)
3360 i_set |= I40E_L4_DST_MASK;
3361 else
3362 i_set &= ~I40E_L4_DST_MASK;
3363
3364 if (nfc->flow_type == TCP_V6_FLOW || nfc->flow_type == UDP_V6_FLOW) {
3365 src_l3 = I40E_L3_V6_SRC_MASK;
3366 dst_l3 = I40E_L3_V6_DST_MASK;
3367 } else if (nfc->flow_type == TCP_V4_FLOW ||
3368 nfc->flow_type == UDP_V4_FLOW) {
3369 src_l3 = I40E_L3_SRC_MASK;
3370 dst_l3 = I40E_L3_DST_MASK;
3371 } else {
3372
3373 return i_set;
3374 }
3375
3376 if (nfc->data & RXH_IP_SRC)
3377 i_set |= src_l3;
3378 else
3379 i_set &= ~src_l3;
3380 if (nfc->data & RXH_IP_DST)
3381 i_set |= dst_l3;
3382 else
3383 i_set &= ~dst_l3;
3384
3385 return i_set;
3386}
3387
3388
3389
3390
3391
3392
3393
3394
3395static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
3396{
3397 struct i40e_hw *hw = &pf->hw;
3398 u64 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
3399 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
3400 u8 flow_pctype = 0;
3401 u64 i_set, i_setc;
3402
3403 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3404 dev_err(&pf->pdev->dev,
3405 "Change of RSS hash input set is not supported when MFP mode is enabled\n");
3406 return -EOPNOTSUPP;
3407 }
3408
3409
3410
3411
3412 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3413 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3414 return -EINVAL;
3415
3416 switch (nfc->flow_type) {
3417 case TCP_V4_FLOW:
3418 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3419 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3420 hena |=
3421 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3422 break;
3423 case TCP_V6_FLOW:
3424 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3425 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3426 hena |=
3427 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3428 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3429 hena |=
3430 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3431 break;
3432 case UDP_V4_FLOW:
3433 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3434 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3435 hena |=
3436 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
3437 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3438
3439 hena |= BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4);
3440 break;
3441 case UDP_V6_FLOW:
3442 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3443 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3444 hena |=
3445 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
3446 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3447
3448 hena |= BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6);
3449 break;
3450 case AH_ESP_V4_FLOW:
3451 case AH_V4_FLOW:
3452 case ESP_V4_FLOW:
3453 case SCTP_V4_FLOW:
3454 if ((nfc->data & RXH_L4_B_0_1) ||
3455 (nfc->data & RXH_L4_B_2_3))
3456 return -EINVAL;
3457 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3458 break;
3459 case AH_ESP_V6_FLOW:
3460 case AH_V6_FLOW:
3461 case ESP_V6_FLOW:
3462 case SCTP_V6_FLOW:
3463 if ((nfc->data & RXH_L4_B_0_1) ||
3464 (nfc->data & RXH_L4_B_2_3))
3465 return -EINVAL;
3466 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3467 break;
3468 case IPV4_FLOW:
3469 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |
3470 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4);
3471 break;
3472 case IPV6_FLOW:
3473 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |
3474 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6);
3475 break;
3476 default:
3477 return -EINVAL;
3478 }
3479
3480 if (flow_pctype) {
3481 i_setc = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
3482 flow_pctype)) |
3483 ((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
3484 flow_pctype)) << 32);
3485 i_set = i40e_get_rss_hash_bits(nfc, i_setc);
3486 i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, flow_pctype),
3487 (u32)i_set);
3488 i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, flow_pctype),
3489 (u32)(i_set >> 32));
3490 hena |= BIT_ULL(flow_pctype);
3491 }
3492
3493 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
3494 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
3495 i40e_flush(hw);
3496
3497 return 0;
3498}
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512static int i40e_update_ethtool_fdir_entry(struct i40e_vsi *vsi,
3513 struct i40e_fdir_filter *input,
3514 u16 sw_idx,
3515 struct ethtool_rxnfc *cmd)
3516{
3517 struct i40e_fdir_filter *rule, *parent;
3518 struct i40e_pf *pf = vsi->back;
3519 struct hlist_node *node2;
3520 int err = -EINVAL;
3521
3522 parent = NULL;
3523 rule = NULL;
3524
3525 hlist_for_each_entry_safe(rule, node2,
3526 &pf->fdir_filter_list, fdir_node) {
3527
3528 if (rule->fd_id >= sw_idx)
3529 break;
3530 parent = rule;
3531 }
3532
3533
3534 if (rule && (rule->fd_id == sw_idx)) {
3535
3536
3537
3538 err = i40e_add_del_fdir(vsi, rule, false);
3539 hlist_del(&rule->fdir_node);
3540 kfree(rule);
3541 pf->fdir_pf_active_filters--;
3542 }
3543
3544
3545
3546
3547 if (!input)
3548 return err;
3549
3550
3551 INIT_HLIST_NODE(&input->fdir_node);
3552
3553
3554 if (parent)
3555 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
3556 else
3557 hlist_add_head(&input->fdir_node,
3558 &pf->fdir_filter_list);
3559
3560
3561 pf->fdir_pf_active_filters++;
3562
3563 return 0;
3564}
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574static void i40e_prune_flex_pit_list(struct i40e_pf *pf)
3575{
3576 struct i40e_flex_pit *entry, *tmp;
3577 struct i40e_fdir_filter *rule;
3578
3579
3580 list_for_each_entry_safe(entry, tmp, &pf->l3_flex_pit_list, list) {
3581 bool found = false;
3582
3583 hlist_for_each_entry(rule, &pf->fdir_filter_list, fdir_node) {
3584 if (rule->flow_type != IP_USER_FLOW)
3585 continue;
3586 if (rule->flex_filter &&
3587 rule->flex_offset == entry->src_offset) {
3588 found = true;
3589 break;
3590 }
3591 }
3592
3593
3594
3595
3596 if (!found) {
3597 list_del(&entry->list);
3598 kfree(entry);
3599 }
3600 }
3601
3602
3603 list_for_each_entry_safe(entry, tmp, &pf->l4_flex_pit_list, list) {
3604 bool found = false;
3605
3606 hlist_for_each_entry(rule, &pf->fdir_filter_list, fdir_node) {
3607
3608
3609
3610 if (rule->flow_type == IP_USER_FLOW)
3611 continue;
3612 if (rule->flex_filter &&
3613 rule->flex_offset == entry->src_offset) {
3614 found = true;
3615 break;
3616 }
3617 }
3618
3619
3620
3621
3622 if (!found) {
3623 list_del(&entry->list);
3624 kfree(entry);
3625 }
3626 }
3627}
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639static int i40e_del_fdir_entry(struct i40e_vsi *vsi,
3640 struct ethtool_rxnfc *cmd)
3641{
3642 struct ethtool_rx_flow_spec *fsp =
3643 (struct ethtool_rx_flow_spec *)&cmd->fs;
3644 struct i40e_pf *pf = vsi->back;
3645 int ret = 0;
3646
3647 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
3648 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
3649 return -EBUSY;
3650
3651 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
3652 return -EBUSY;
3653
3654 ret = i40e_update_ethtool_fdir_entry(vsi, NULL, fsp->location, cmd);
3655
3656 i40e_prune_flex_pit_list(pf);
3657
3658 i40e_fdir_check_and_reenable(pf);
3659 return ret;
3660}
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671static u8 i40e_unused_pit_index(struct i40e_pf *pf)
3672{
3673 unsigned long available_index = 0xFF;
3674 struct i40e_flex_pit *entry;
3675
3676
3677
3678
3679
3680
3681 list_for_each_entry(entry, &pf->l4_flex_pit_list, list)
3682 clear_bit(entry->pit_index, &available_index);
3683
3684 list_for_each_entry(entry, &pf->l3_flex_pit_list, list)
3685 clear_bit(entry->pit_index, &available_index);
3686
3687 return find_first_bit(&available_index, 8);
3688}
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699static
3700struct i40e_flex_pit *i40e_find_flex_offset(struct list_head *flex_pit_list,
3701 u16 src_offset)
3702{
3703 struct i40e_flex_pit *entry;
3704 int size = 0;
3705
3706
3707
3708
3709 list_for_each_entry(entry, flex_pit_list, list) {
3710 size++;
3711 if (entry->src_offset == src_offset)
3712 return entry;
3713 }
3714
3715
3716
3717
3718
3719
3720 if (size >= I40E_FLEX_PIT_TABLE_SIZE)
3721 return ERR_PTR(-ENOSPC);
3722
3723 return NULL;
3724}
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739static int i40e_add_flex_offset(struct list_head *flex_pit_list,
3740 u16 src_offset,
3741 u8 pit_index)
3742{
3743 struct i40e_flex_pit *new_pit, *entry;
3744
3745 new_pit = kzalloc(sizeof(*entry), GFP_KERNEL);
3746 if (!new_pit)
3747 return -ENOMEM;
3748
3749 new_pit->src_offset = src_offset;
3750 new_pit->pit_index = pit_index;
3751
3752
3753
3754
3755 list_for_each_entry(entry, flex_pit_list, list) {
3756 if (new_pit->src_offset < entry->src_offset) {
3757 list_add_tail(&new_pit->list, &entry->list);
3758 return 0;
3759 }
3760
3761
3762
3763
3764
3765 if (new_pit->src_offset == entry->src_offset) {
3766 int err = 0;
3767
3768
3769
3770
3771 if (new_pit->pit_index != entry->pit_index)
3772 err = -EINVAL;
3773
3774 kfree(new_pit);
3775 return err;
3776 }
3777 }
3778
3779
3780
3781
3782 list_add_tail(&new_pit->list, flex_pit_list);
3783 return 0;
3784}
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807static void __i40e_reprogram_flex_pit(struct i40e_pf *pf,
3808 struct list_head *flex_pit_list,
3809 int flex_pit_start)
3810{
3811 struct i40e_flex_pit *entry = NULL;
3812 u16 last_offset = 0;
3813 int i = 0, j = 0;
3814
3815
3816
3817
3818 list_for_each_entry(entry, flex_pit_list, list) {
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833 for (j = i + 1; j < 3; j++) {
3834 u16 offset = entry->src_offset + j;
3835 int index = flex_pit_start + i;
3836 u32 value = I40E_FLEX_PREP_VAL(I40E_FLEX_DEST_UNUSED,
3837 1,
3838 offset - 3);
3839
3840 if (offset > I40E_MAX_FLEX_SRC_OFFSET) {
3841 i40e_write_rx_ctl(&pf->hw,
3842 I40E_PRTQF_FLX_PIT(index),
3843 value);
3844 i++;
3845 }
3846 }
3847
3848
3849 i40e_write_rx_ctl(&pf->hw,
3850 I40E_PRTQF_FLX_PIT(flex_pit_start + i),
3851 I40E_FLEX_PREP_VAL(entry->pit_index + 50,
3852 1,
3853 entry->src_offset));
3854 i++;
3855 }
3856
3857
3858
3859
3860
3861
3862
3863 if (!list_empty(flex_pit_list))
3864 last_offset = list_prev_entry(entry, list)->src_offset + 1;
3865
3866 for (; i < 3; i++, last_offset++) {
3867 i40e_write_rx_ctl(&pf->hw,
3868 I40E_PRTQF_FLX_PIT(flex_pit_start + i),
3869 I40E_FLEX_PREP_VAL(I40E_FLEX_DEST_UNUSED,
3870 1,
3871 last_offset));
3872 }
3873}
3874
3875
3876
3877
3878
3879
3880
3881
3882static void i40e_reprogram_flex_pit(struct i40e_pf *pf)
3883{
3884 __i40e_reprogram_flex_pit(pf, &pf->l3_flex_pit_list,
3885 I40E_FLEX_PIT_IDX_START_L3);
3886
3887 __i40e_reprogram_flex_pit(pf, &pf->l4_flex_pit_list,
3888 I40E_FLEX_PIT_IDX_START_L4);
3889
3890
3891 i40e_write_rx_ctl(&pf->hw,
3892 I40E_GLQF_ORT(I40E_L3_GLQF_ORT_IDX),
3893 I40E_ORT_PREP_VAL(I40E_FLEX_PIT_IDX_START_L3,
3894 3, 1));
3895
3896 i40e_write_rx_ctl(&pf->hw,
3897 I40E_GLQF_ORT(I40E_L4_GLQF_ORT_IDX),
3898 I40E_ORT_PREP_VAL(I40E_FLEX_PIT_IDX_START_L4,
3899 3, 1));
3900}
3901
3902
3903
3904
3905
3906
3907
3908
3909static const char *i40e_flow_str(struct ethtool_rx_flow_spec *fsp)
3910{
3911 switch (fsp->flow_type & ~FLOW_EXT) {
3912 case TCP_V4_FLOW:
3913 return "tcp4";
3914 case UDP_V4_FLOW:
3915 return "udp4";
3916 case SCTP_V4_FLOW:
3917 return "sctp4";
3918 case IP_USER_FLOW:
3919 return "ip4";
3920 default:
3921 return "unknown";
3922 }
3923}
3924
3925
3926
3927
3928
3929
3930
3931
3932static u64 i40e_pit_index_to_mask(int pit_index)
3933{
3934 switch (pit_index) {
3935 case 0:
3936 return I40E_FLEX_50_MASK;
3937 case 1:
3938 return I40E_FLEX_51_MASK;
3939 case 2:
3940 return I40E_FLEX_52_MASK;
3941 case 3:
3942 return I40E_FLEX_53_MASK;
3943 case 4:
3944 return I40E_FLEX_54_MASK;
3945 case 5:
3946 return I40E_FLEX_55_MASK;
3947 case 6:
3948 return I40E_FLEX_56_MASK;
3949 case 7:
3950 return I40E_FLEX_57_MASK;
3951 default:
3952 return 0;
3953 }
3954}
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966static void i40e_print_input_set(struct i40e_vsi *vsi, u64 old, u64 new)
3967{
3968 struct i40e_pf *pf = vsi->back;
3969 bool old_value, new_value;
3970 int i;
3971
3972 old_value = !!(old & I40E_L3_SRC_MASK);
3973 new_value = !!(new & I40E_L3_SRC_MASK);
3974 if (old_value != new_value)
3975 netif_info(pf, drv, vsi->netdev, "L3 source address: %s -> %s\n",
3976 old_value ? "ON" : "OFF",
3977 new_value ? "ON" : "OFF");
3978
3979 old_value = !!(old & I40E_L3_DST_MASK);
3980 new_value = !!(new & I40E_L3_DST_MASK);
3981 if (old_value != new_value)
3982 netif_info(pf, drv, vsi->netdev, "L3 destination address: %s -> %s\n",
3983 old_value ? "ON" : "OFF",
3984 new_value ? "ON" : "OFF");
3985
3986 old_value = !!(old & I40E_L4_SRC_MASK);
3987 new_value = !!(new & I40E_L4_SRC_MASK);
3988 if (old_value != new_value)
3989 netif_info(pf, drv, vsi->netdev, "L4 source port: %s -> %s\n",
3990 old_value ? "ON" : "OFF",
3991 new_value ? "ON" : "OFF");
3992
3993 old_value = !!(old & I40E_L4_DST_MASK);
3994 new_value = !!(new & I40E_L4_DST_MASK);
3995 if (old_value != new_value)
3996 netif_info(pf, drv, vsi->netdev, "L4 destination port: %s -> %s\n",
3997 old_value ? "ON" : "OFF",
3998 new_value ? "ON" : "OFF");
3999
4000 old_value = !!(old & I40E_VERIFY_TAG_MASK);
4001 new_value = !!(new & I40E_VERIFY_TAG_MASK);
4002 if (old_value != new_value)
4003 netif_info(pf, drv, vsi->netdev, "SCTP verification tag: %s -> %s\n",
4004 old_value ? "ON" : "OFF",
4005 new_value ? "ON" : "OFF");
4006
4007
4008 for (i = 0; i < I40E_FLEX_INDEX_ENTRIES; i++) {
4009 u64 flex_mask = i40e_pit_index_to_mask(i);
4010
4011 old_value = !!(old & flex_mask);
4012 new_value = !!(new & flex_mask);
4013 if (old_value != new_value)
4014 netif_info(pf, drv, vsi->netdev, "FLEX index %d: %s -> %s\n",
4015 i,
4016 old_value ? "ON" : "OFF",
4017 new_value ? "ON" : "OFF");
4018 }
4019
4020 netif_info(pf, drv, vsi->netdev, " Current input set: %0llx\n",
4021 old);
4022 netif_info(pf, drv, vsi->netdev, "Requested input set: %0llx\n",
4023 new);
4024}
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051static int i40e_check_fdir_input_set(struct i40e_vsi *vsi,
4052 struct ethtool_rx_flow_spec *fsp,
4053 struct i40e_rx_flow_userdef *userdef)
4054{
4055 struct i40e_pf *pf = vsi->back;
4056 struct ethtool_tcpip4_spec *tcp_ip4_spec;
4057 struct ethtool_usrip4_spec *usr_ip4_spec;
4058 u64 current_mask, new_mask;
4059 bool new_flex_offset = false;
4060 bool flex_l3 = false;
4061 u16 *fdir_filter_count;
4062 u16 index, src_offset = 0;
4063 u8 pit_index = 0;
4064 int err;
4065
4066 switch (fsp->flow_type & ~FLOW_EXT) {
4067 case SCTP_V4_FLOW:
4068 index = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4069 fdir_filter_count = &pf->fd_sctp4_filter_cnt;
4070 break;
4071 case TCP_V4_FLOW:
4072 index = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4073 fdir_filter_count = &pf->fd_tcp4_filter_cnt;
4074 break;
4075 case UDP_V4_FLOW:
4076 index = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4077 fdir_filter_count = &pf->fd_udp4_filter_cnt;
4078 break;
4079 case IP_USER_FLOW:
4080 index = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4081 fdir_filter_count = &pf->fd_ip4_filter_cnt;
4082 flex_l3 = true;
4083 break;
4084 default:
4085 return -EOPNOTSUPP;
4086 }
4087
4088
4089 current_mask = i40e_read_fd_input_set(pf, index);
4090 new_mask = current_mask;
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101 switch (fsp->flow_type & ~FLOW_EXT) {
4102 case SCTP_V4_FLOW:
4103 new_mask &= ~I40E_VERIFY_TAG_MASK;
4104
4105 case TCP_V4_FLOW:
4106 case UDP_V4_FLOW:
4107 tcp_ip4_spec = &fsp->m_u.tcp_ip4_spec;
4108
4109
4110 if (tcp_ip4_spec->ip4src == htonl(0xFFFFFFFF))
4111 new_mask |= I40E_L3_SRC_MASK;
4112 else if (!tcp_ip4_spec->ip4src)
4113 new_mask &= ~I40E_L3_SRC_MASK;
4114 else
4115 return -EOPNOTSUPP;
4116
4117
4118 if (tcp_ip4_spec->ip4dst == htonl(0xFFFFFFFF))
4119 new_mask |= I40E_L3_DST_MASK;
4120 else if (!tcp_ip4_spec->ip4dst)
4121 new_mask &= ~I40E_L3_DST_MASK;
4122 else
4123 return -EOPNOTSUPP;
4124
4125
4126 if (tcp_ip4_spec->psrc == htons(0xFFFF))
4127 new_mask |= I40E_L4_SRC_MASK;
4128 else if (!tcp_ip4_spec->psrc)
4129 new_mask &= ~I40E_L4_SRC_MASK;
4130 else
4131 return -EOPNOTSUPP;
4132
4133
4134 if (tcp_ip4_spec->pdst == htons(0xFFFF))
4135 new_mask |= I40E_L4_DST_MASK;
4136 else if (!tcp_ip4_spec->pdst)
4137 new_mask &= ~I40E_L4_DST_MASK;
4138 else
4139 return -EOPNOTSUPP;
4140
4141
4142 if (tcp_ip4_spec->tos)
4143 return -EOPNOTSUPP;
4144
4145 break;
4146 case IP_USER_FLOW:
4147 usr_ip4_spec = &fsp->m_u.usr_ip4_spec;
4148
4149
4150 if (usr_ip4_spec->ip4src == htonl(0xFFFFFFFF))
4151 new_mask |= I40E_L3_SRC_MASK;
4152 else if (!usr_ip4_spec->ip4src)
4153 new_mask &= ~I40E_L3_SRC_MASK;
4154 else
4155 return -EOPNOTSUPP;
4156
4157
4158 if (usr_ip4_spec->ip4dst == htonl(0xFFFFFFFF))
4159 new_mask |= I40E_L3_DST_MASK;
4160 else if (!usr_ip4_spec->ip4dst)
4161 new_mask &= ~I40E_L3_DST_MASK;
4162 else
4163 return -EOPNOTSUPP;
4164
4165
4166 if (usr_ip4_spec->l4_4_bytes == htonl(0xFFFFFFFF))
4167 new_mask |= I40E_L4_SRC_MASK | I40E_L4_DST_MASK;
4168 else if (!usr_ip4_spec->l4_4_bytes)
4169 new_mask &= ~(I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
4170 else
4171 return -EOPNOTSUPP;
4172
4173
4174 if (usr_ip4_spec->tos)
4175 return -EOPNOTSUPP;
4176
4177
4178 if (usr_ip4_spec->ip_ver)
4179 return -EINVAL;
4180
4181
4182 if (usr_ip4_spec->proto)
4183 return -EINVAL;
4184
4185 break;
4186 default:
4187 return -EOPNOTSUPP;
4188 }
4189
4190
4191 new_mask &= ~I40E_FLEX_INPUT_MASK;
4192
4193
4194
4195
4196
4197
4198 if (userdef->flex_filter) {
4199 struct i40e_flex_pit *l3_flex_pit = NULL, *flex_pit = NULL;
4200
4201
4202
4203
4204 if (userdef->flex_offset & 0x1) {
4205 dev_warn(&pf->pdev->dev,
4206 "Flexible data offset must be 2-byte aligned\n");
4207 return -EINVAL;
4208 }
4209
4210 src_offset = userdef->flex_offset >> 1;
4211
4212
4213 if (src_offset > I40E_MAX_FLEX_SRC_OFFSET) {
4214 dev_warn(&pf->pdev->dev,
4215 "Flexible data must reside within first 64 bytes of the packet payload\n");
4216 return -EINVAL;
4217 }
4218
4219
4220
4221
4222
4223
4224 flex_pit = i40e_find_flex_offset(&pf->l4_flex_pit_list,
4225 src_offset);
4226 if (IS_ERR(flex_pit))
4227 return PTR_ERR(flex_pit);
4228
4229
4230
4231
4232
4233
4234
4235
4236 if (flex_l3) {
4237 l3_flex_pit =
4238 i40e_find_flex_offset(&pf->l3_flex_pit_list,
4239 src_offset);
4240 if (IS_ERR(l3_flex_pit))
4241 return PTR_ERR(l3_flex_pit);
4242
4243 if (flex_pit) {
4244
4245
4246
4247
4248 if (l3_flex_pit) {
4249 if (l3_flex_pit->pit_index !=
4250 flex_pit->pit_index) {
4251 return -EINVAL;
4252 }
4253 } else {
4254 new_flex_offset = true;
4255 }
4256 } else {
4257 flex_pit = l3_flex_pit;
4258 }
4259 }
4260
4261
4262
4263
4264
4265
4266 if (!flex_pit) {
4267 new_flex_offset = true;
4268 pit_index = i40e_unused_pit_index(pf);
4269 } else {
4270 pit_index = flex_pit->pit_index;
4271 }
4272
4273
4274 new_mask |= i40e_pit_index_to_mask(pit_index);
4275 }
4276
4277
4278
4279
4280
4281 if (new_mask == current_mask && !new_flex_offset)
4282 return 0;
4283
4284 netif_info(pf, drv, vsi->netdev, "Input set change requested for %s flows:\n",
4285 i40e_flow_str(fsp));
4286 i40e_print_input_set(vsi, current_mask, new_mask);
4287 if (new_flex_offset) {
4288 netif_info(pf, drv, vsi->netdev, "FLEX index %d: Offset -> %d",
4289 pit_index, src_offset);
4290 }
4291
4292
4293
4294
4295
4296 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4297 netif_err(pf, drv, vsi->netdev, "Cannot change Flow Director input sets while MFP is enabled\n");
4298 return -EOPNOTSUPP;
4299 }
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310 if (*fdir_filter_count) {
4311 netif_err(pf, drv, vsi->netdev, "Cannot change input set for %s flows until %d preexisting filters are removed\n",
4312 i40e_flow_str(fsp),
4313 *fdir_filter_count);
4314 return -EOPNOTSUPP;
4315 }
4316
4317 i40e_write_fd_input_set(pf, index, new_mask);
4318
4319
4320
4321
4322
4323
4324
4325 if (index == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER)
4326 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_FRAG_IPV4,
4327 new_mask);
4328
4329
4330 if (new_flex_offset) {
4331 err = i40e_add_flex_offset(&pf->l4_flex_pit_list, src_offset,
4332 pit_index);
4333 if (err)
4334 return err;
4335
4336 if (flex_l3) {
4337 err = i40e_add_flex_offset(&pf->l3_flex_pit_list,
4338 src_offset,
4339 pit_index);
4340 if (err)
4341 return err;
4342 }
4343
4344 i40e_reprogram_flex_pit(pf);
4345 }
4346
4347 return 0;
4348}
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360static bool i40e_match_fdir_filter(struct i40e_fdir_filter *a,
4361 struct i40e_fdir_filter *b)
4362{
4363
4364 if (a->dst_ip != b->dst_ip ||
4365 a->src_ip != b->src_ip ||
4366 a->dst_port != b->dst_port ||
4367 a->src_port != b->src_port ||
4368 a->flow_type != b->flow_type ||
4369 a->ip4_proto != b->ip4_proto)
4370 return false;
4371
4372 return true;
4373}
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400static int i40e_disallow_matching_filters(struct i40e_vsi *vsi,
4401 struct i40e_fdir_filter *input)
4402{
4403 struct i40e_pf *pf = vsi->back;
4404 struct i40e_fdir_filter *rule;
4405 struct hlist_node *node2;
4406
4407
4408 hlist_for_each_entry_safe(rule, node2,
4409 &pf->fdir_filter_list, fdir_node) {
4410
4411
4412
4413
4414 if (rule->fd_id == input->fd_id)
4415 continue;
4416
4417
4418
4419
4420 if (i40e_match_fdir_filter(rule, input)) {
4421 dev_warn(&pf->pdev->dev,
4422 "Existing user defined filter %d already matches this flow.\n",
4423 rule->fd_id);
4424 return -EINVAL;
4425 }
4426 }
4427
4428 return 0;
4429}
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439static int i40e_add_fdir_ethtool(struct i40e_vsi *vsi,
4440 struct ethtool_rxnfc *cmd)
4441{
4442 struct i40e_rx_flow_userdef userdef;
4443 struct ethtool_rx_flow_spec *fsp;
4444 struct i40e_fdir_filter *input;
4445 u16 dest_vsi = 0, q_index = 0;
4446 struct i40e_pf *pf;
4447 int ret = -EINVAL;
4448 u8 dest_ctl;
4449
4450 if (!vsi)
4451 return -EINVAL;
4452 pf = vsi->back;
4453
4454 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
4455 return -EOPNOTSUPP;
4456
4457 if (test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state))
4458 return -ENOSPC;
4459
4460 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
4461 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
4462 return -EBUSY;
4463
4464 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
4465 return -EBUSY;
4466
4467 fsp = (struct ethtool_rx_flow_spec *)&cmd->fs;
4468
4469
4470 if (i40e_parse_rx_flow_user_data(fsp, &userdef))
4471 return -EINVAL;
4472
4473
4474 if (fsp->flow_type & FLOW_MAC_EXT)
4475 return -EINVAL;
4476
4477 ret = i40e_check_fdir_input_set(vsi, fsp, &userdef);
4478 if (ret)
4479 return ret;
4480
4481 if (fsp->location >= (pf->hw.func_caps.fd_filters_best_effort +
4482 pf->hw.func_caps.fd_filters_guaranteed)) {
4483 return -EINVAL;
4484 }
4485
4486
4487
4488
4489 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
4490 dest_ctl = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
4491 } else {
4492 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
4493 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
4494
4495 if (!vf) {
4496 if (ring >= vsi->num_queue_pairs)
4497 return -EINVAL;
4498 dest_vsi = vsi->id;
4499 } else {
4500
4501 vf--;
4502
4503 if (vf >= pf->num_alloc_vfs)
4504 return -EINVAL;
4505 if (ring >= pf->vf[vf].num_queue_pairs)
4506 return -EINVAL;
4507 dest_vsi = pf->vf[vf].lan_vsi_id;
4508 }
4509 dest_ctl = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
4510 q_index = ring;
4511 }
4512
4513 input = kzalloc(sizeof(*input), GFP_KERNEL);
4514
4515 if (!input)
4516 return -ENOMEM;
4517
4518 input->fd_id = fsp->location;
4519 input->q_index = q_index;
4520 input->dest_vsi = dest_vsi;
4521 input->dest_ctl = dest_ctl;
4522 input->fd_status = I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID;
4523 input->cnt_index = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
4524 input->dst_ip = fsp->h_u.tcp_ip4_spec.ip4src;
4525 input->src_ip = fsp->h_u.tcp_ip4_spec.ip4dst;
4526 input->flow_type = fsp->flow_type & ~FLOW_EXT;
4527 input->ip4_proto = fsp->h_u.usr_ip4_spec.proto;
4528
4529
4530
4531
4532 input->dst_port = fsp->h_u.tcp_ip4_spec.psrc;
4533 input->src_port = fsp->h_u.tcp_ip4_spec.pdst;
4534 input->dst_ip = fsp->h_u.tcp_ip4_spec.ip4src;
4535 input->src_ip = fsp->h_u.tcp_ip4_spec.ip4dst;
4536
4537 if (userdef.flex_filter) {
4538 input->flex_filter = true;
4539 input->flex_word = cpu_to_be16(userdef.flex_word);
4540 input->flex_offset = userdef.flex_offset;
4541 }
4542
4543
4544 ret = i40e_disallow_matching_filters(vsi, input);
4545 if (ret)
4546 goto free_filter_memory;
4547
4548
4549
4550
4551
4552 i40e_update_ethtool_fdir_entry(vsi, input, fsp->location, NULL);
4553 ret = i40e_add_del_fdir(vsi, input, true);
4554 if (ret)
4555 goto remove_sw_rule;
4556 return 0;
4557
4558remove_sw_rule:
4559 hlist_del(&input->fdir_node);
4560 pf->fdir_pf_active_filters--;
4561free_filter_memory:
4562 kfree(input);
4563 return ret;
4564}
4565
4566
4567
4568
4569
4570
4571
4572
4573static int i40e_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
4574{
4575 struct i40e_netdev_priv *np = netdev_priv(netdev);
4576 struct i40e_vsi *vsi = np->vsi;
4577 struct i40e_pf *pf = vsi->back;
4578 int ret = -EOPNOTSUPP;
4579
4580 switch (cmd->cmd) {
4581 case ETHTOOL_SRXFH:
4582 ret = i40e_set_rss_hash_opt(pf, cmd);
4583 break;
4584 case ETHTOOL_SRXCLSRLINS:
4585 ret = i40e_add_fdir_ethtool(vsi, cmd);
4586 break;
4587 case ETHTOOL_SRXCLSRLDEL:
4588 ret = i40e_del_fdir_entry(vsi, cmd);
4589 break;
4590 default:
4591 break;
4592 }
4593
4594 return ret;
4595}
4596
4597
4598
4599
4600
4601static unsigned int i40e_max_channels(struct i40e_vsi *vsi)
4602{
4603
4604 return vsi->alloc_queue_pairs;
4605}
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617static void i40e_get_channels(struct net_device *dev,
4618 struct ethtool_channels *ch)
4619{
4620 struct i40e_netdev_priv *np = netdev_priv(dev);
4621 struct i40e_vsi *vsi = np->vsi;
4622 struct i40e_pf *pf = vsi->back;
4623
4624
4625 ch->max_combined = i40e_max_channels(vsi);
4626
4627
4628 ch->other_count = (pf->flags & I40E_FLAG_FD_SB_ENABLED) ? 1 : 0;
4629 ch->max_other = ch->other_count;
4630
4631
4632 ch->combined_count = vsi->num_queue_pairs;
4633}
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643static int i40e_set_channels(struct net_device *dev,
4644 struct ethtool_channels *ch)
4645{
4646 const u8 drop = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
4647 struct i40e_netdev_priv *np = netdev_priv(dev);
4648 unsigned int count = ch->combined_count;
4649 struct i40e_vsi *vsi = np->vsi;
4650 struct i40e_pf *pf = vsi->back;
4651 struct i40e_fdir_filter *rule;
4652 struct hlist_node *node2;
4653 int new_count;
4654 int err = 0;
4655
4656
4657 if (vsi->type != I40E_VSI_MAIN)
4658 return -EINVAL;
4659
4660
4661
4662
4663 if (pf->flags & I40E_FLAG_TC_MQPRIO)
4664 return -EINVAL;
4665
4666
4667 if (!count || ch->rx_count || ch->tx_count)
4668 return -EINVAL;
4669
4670
4671 if (ch->other_count != ((pf->flags & I40E_FLAG_FD_SB_ENABLED) ? 1 : 0))
4672 return -EINVAL;
4673
4674
4675 if (count > i40e_max_channels(vsi))
4676 return -EINVAL;
4677
4678
4679
4680
4681 hlist_for_each_entry_safe(rule, node2,
4682 &pf->fdir_filter_list, fdir_node) {
4683 if (rule->dest_ctl != drop && count <= rule->q_index) {
4684 dev_warn(&pf->pdev->dev,
4685 "Existing user defined filter %d assigns flow to queue %d\n",
4686 rule->fd_id, rule->q_index);
4687 err = -EINVAL;
4688 }
4689 }
4690
4691 if (err) {
4692 dev_err(&pf->pdev->dev,
4693 "Existing filter rules must be deleted to reduce combined channel count to %d\n",
4694 count);
4695 return err;
4696 }
4697
4698
4699
4700
4701
4702
4703
4704 new_count = i40e_reconfig_rss_queues(pf, count);
4705 if (new_count > 0)
4706 return 0;
4707 else
4708 return -EINVAL;
4709}
4710
4711
4712
4713
4714
4715
4716
4717static u32 i40e_get_rxfh_key_size(struct net_device *netdev)
4718{
4719 return I40E_HKEY_ARRAY_SIZE;
4720}
4721
4722
4723
4724
4725
4726
4727
4728static u32 i40e_get_rxfh_indir_size(struct net_device *netdev)
4729{
4730 return I40E_HLUT_ARRAY_SIZE;
4731}
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743static int i40e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
4744 u8 *hfunc)
4745{
4746 struct i40e_netdev_priv *np = netdev_priv(netdev);
4747 struct i40e_vsi *vsi = np->vsi;
4748 u8 *lut, *seed = NULL;
4749 int ret;
4750 u16 i;
4751
4752 if (hfunc)
4753 *hfunc = ETH_RSS_HASH_TOP;
4754
4755 if (!indir)
4756 return 0;
4757
4758 seed = key;
4759 lut = kzalloc(I40E_HLUT_ARRAY_SIZE, GFP_KERNEL);
4760 if (!lut)
4761 return -ENOMEM;
4762 ret = i40e_get_rss(vsi, seed, lut, I40E_HLUT_ARRAY_SIZE);
4763 if (ret)
4764 goto out;
4765 for (i = 0; i < I40E_HLUT_ARRAY_SIZE; i++)
4766 indir[i] = (u32)(lut[i]);
4767
4768out:
4769 kfree(lut);
4770
4771 return ret;
4772}
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784static int i40e_set_rxfh(struct net_device *netdev, const u32 *indir,
4785 const u8 *key, const u8 hfunc)
4786{
4787 struct i40e_netdev_priv *np = netdev_priv(netdev);
4788 struct i40e_vsi *vsi = np->vsi;
4789 struct i40e_pf *pf = vsi->back;
4790 u8 *seed = NULL;
4791 u16 i;
4792
4793 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)
4794 return -EOPNOTSUPP;
4795
4796 if (key) {
4797 if (!vsi->rss_hkey_user) {
4798 vsi->rss_hkey_user = kzalloc(I40E_HKEY_ARRAY_SIZE,
4799 GFP_KERNEL);
4800 if (!vsi->rss_hkey_user)
4801 return -ENOMEM;
4802 }
4803 memcpy(vsi->rss_hkey_user, key, I40E_HKEY_ARRAY_SIZE);
4804 seed = vsi->rss_hkey_user;
4805 }
4806 if (!vsi->rss_lut_user) {
4807 vsi->rss_lut_user = kzalloc(I40E_HLUT_ARRAY_SIZE, GFP_KERNEL);
4808 if (!vsi->rss_lut_user)
4809 return -ENOMEM;
4810 }
4811
4812
4813 if (indir)
4814 for (i = 0; i < I40E_HLUT_ARRAY_SIZE; i++)
4815 vsi->rss_lut_user[i] = (u8)(indir[i]);
4816 else
4817 i40e_fill_rss_lut(pf, vsi->rss_lut_user, I40E_HLUT_ARRAY_SIZE,
4818 vsi->rss_size);
4819
4820 return i40e_config_rss(vsi, seed, vsi->rss_lut_user,
4821 I40E_HLUT_ARRAY_SIZE);
4822}
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834static u32 i40e_get_priv_flags(struct net_device *dev)
4835{
4836 struct i40e_netdev_priv *np = netdev_priv(dev);
4837 struct i40e_vsi *vsi = np->vsi;
4838 struct i40e_pf *pf = vsi->back;
4839 u32 i, j, ret_flags = 0;
4840
4841 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++) {
4842 const struct i40e_priv_flags *priv_flags;
4843
4844 priv_flags = &i40e_gstrings_priv_flags[i];
4845
4846 if (priv_flags->flag & pf->flags)
4847 ret_flags |= BIT(i);
4848 }
4849
4850 if (pf->hw.pf_id != 0)
4851 return ret_flags;
4852
4853 for (j = 0; j < I40E_GL_PRIV_FLAGS_STR_LEN; j++) {
4854 const struct i40e_priv_flags *priv_flags;
4855
4856 priv_flags = &i40e_gl_gstrings_priv_flags[j];
4857
4858 if (priv_flags->flag & pf->flags)
4859 ret_flags |= BIT(i + j);
4860 }
4861
4862 return ret_flags;
4863}
4864
4865
4866
4867
4868
4869
4870static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
4871{
4872 struct i40e_netdev_priv *np = netdev_priv(dev);
4873 u64 orig_flags, new_flags, changed_flags;
4874 enum i40e_admin_queue_err adq_err;
4875 struct i40e_vsi *vsi = np->vsi;
4876 struct i40e_pf *pf = vsi->back;
4877 bool is_reset_needed;
4878 i40e_status status;
4879 u32 i, j;
4880
4881 orig_flags = READ_ONCE(pf->flags);
4882 new_flags = orig_flags;
4883
4884 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++) {
4885 const struct i40e_priv_flags *priv_flags;
4886
4887 priv_flags = &i40e_gstrings_priv_flags[i];
4888
4889 if (flags & BIT(i))
4890 new_flags |= priv_flags->flag;
4891 else
4892 new_flags &= ~(priv_flags->flag);
4893
4894
4895 if (priv_flags->read_only &&
4896 ((orig_flags ^ new_flags) & ~BIT(i)))
4897 return -EOPNOTSUPP;
4898 }
4899
4900 if (pf->hw.pf_id != 0)
4901 goto flags_complete;
4902
4903 for (j = 0; j < I40E_GL_PRIV_FLAGS_STR_LEN; j++) {
4904 const struct i40e_priv_flags *priv_flags;
4905
4906 priv_flags = &i40e_gl_gstrings_priv_flags[j];
4907
4908 if (flags & BIT(i + j))
4909 new_flags |= priv_flags->flag;
4910 else
4911 new_flags &= ~(priv_flags->flag);
4912
4913
4914 if (priv_flags->read_only &&
4915 ((orig_flags ^ new_flags) & ~BIT(i)))
4916 return -EOPNOTSUPP;
4917 }
4918
4919flags_complete:
4920 changed_flags = orig_flags ^ new_flags;
4921
4922 is_reset_needed = !!(changed_flags & (I40E_FLAG_VEB_STATS_ENABLED |
4923 I40E_FLAG_LEGACY_RX | I40E_FLAG_SOURCE_PRUNING_DISABLED |
4924 I40E_FLAG_DISABLE_FW_LLDP));
4925
4926
4927
4928
4929
4930
4931 if ((new_flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) &&
4932 !(pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE))
4933 return -EOPNOTSUPP;
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943 if (changed_flags & I40E_FLAG_DISABLE_FW_LLDP) {
4944 if (!(pf->hw.flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) {
4945 dev_warn(&pf->pdev->dev,
4946 "Device does not support changing FW LLDP\n");
4947 return -EOPNOTSUPP;
4948 }
4949 }
4950
4951 if (((changed_flags & I40E_FLAG_RS_FEC) ||
4952 (changed_flags & I40E_FLAG_BASE_R_FEC)) &&
4953 pf->hw.device_id != I40E_DEV_ID_25G_SFP28 &&
4954 pf->hw.device_id != I40E_DEV_ID_25G_B) {
4955 dev_warn(&pf->pdev->dev,
4956 "Device does not support changing FEC configuration\n");
4957 return -EOPNOTSUPP;
4958 }
4959
4960
4961
4962
4963
4964
4965
4966 if ((changed_flags & I40E_FLAG_FD_ATR_ENABLED) &&
4967 !(new_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4968 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
4969 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
4970 }
4971
4972 if (changed_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT) {
4973 u16 sw_flags = 0, valid_flags = 0;
4974 int ret;
4975
4976 if (!(new_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT))
4977 sw_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
4978 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
4979 ret = i40e_aq_set_switch_config(&pf->hw, sw_flags, valid_flags,
4980 0, NULL);
4981 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
4982 dev_info(&pf->pdev->dev,
4983 "couldn't set switch config bits, err %s aq_err %s\n",
4984 i40e_stat_str(&pf->hw, ret),
4985 i40e_aq_str(&pf->hw,
4986 pf->hw.aq.asq_last_status));
4987
4988 }
4989 }
4990
4991 if ((changed_flags & I40E_FLAG_RS_FEC) ||
4992 (changed_flags & I40E_FLAG_BASE_R_FEC)) {
4993 u8 fec_cfg = 0;
4994
4995 if (new_flags & I40E_FLAG_RS_FEC &&
4996 new_flags & I40E_FLAG_BASE_R_FEC) {
4997 fec_cfg = I40E_AQ_SET_FEC_AUTO;
4998 } else if (new_flags & I40E_FLAG_RS_FEC) {
4999 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_RS |
5000 I40E_AQ_SET_FEC_ABILITY_RS);
5001 } else if (new_flags & I40E_FLAG_BASE_R_FEC) {
5002 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_KR |
5003 I40E_AQ_SET_FEC_ABILITY_KR);
5004 }
5005 if (i40e_set_fec_cfg(dev, fec_cfg))
5006 dev_warn(&pf->pdev->dev, "Cannot change FEC config\n");
5007 }
5008
5009 if ((changed_flags & new_flags &
5010 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED) &&
5011 (new_flags & I40E_FLAG_MFP_ENABLED))
5012 dev_warn(&pf->pdev->dev,
5013 "Turning on link-down-on-close flag may affect other partitions\n");
5014
5015 if (changed_flags & I40E_FLAG_DISABLE_FW_LLDP) {
5016 if (new_flags & I40E_FLAG_DISABLE_FW_LLDP) {
5017 struct i40e_dcbx_config *dcbcfg;
5018
5019 i40e_aq_stop_lldp(&pf->hw, true, false, NULL);
5020 i40e_aq_set_dcb_parameters(&pf->hw, true, NULL);
5021
5022 dcbcfg = &pf->hw.local_dcbx_config;
5023 dcbcfg->etscfg.willing = 1;
5024 dcbcfg->etscfg.maxtcs = 0;
5025 dcbcfg->etscfg.tcbwtable[0] = 100;
5026 for (i = 1; i < I40E_MAX_TRAFFIC_CLASS; i++)
5027 dcbcfg->etscfg.tcbwtable[i] = 0;
5028 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
5029 dcbcfg->etscfg.prioritytable[i] = 0;
5030 dcbcfg->etscfg.tsatable[0] = I40E_IEEE_TSA_ETS;
5031 dcbcfg->pfc.willing = 1;
5032 dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
5033 } else {
5034 status = i40e_aq_start_lldp(&pf->hw, false, NULL);
5035 if (status) {
5036 adq_err = pf->hw.aq.asq_last_status;
5037 switch (adq_err) {
5038 case I40E_AQ_RC_EEXIST:
5039 dev_warn(&pf->pdev->dev,
5040 "FW LLDP agent is already running\n");
5041 is_reset_needed = false;
5042 break;
5043 case I40E_AQ_RC_EPERM:
5044 dev_warn(&pf->pdev->dev,
5045 "Device configuration forbids SW from starting the LLDP agent.\n");
5046 return -EINVAL;
5047 default:
5048 dev_warn(&pf->pdev->dev,
5049 "Starting FW LLDP agent failed: error: %s, %s\n",
5050 i40e_stat_str(&pf->hw,
5051 status),
5052 i40e_aq_str(&pf->hw,
5053 adq_err));
5054 return -EINVAL;
5055 }
5056 }
5057 }
5058 }
5059
5060
5061
5062
5063
5064
5065 pf->flags = new_flags;
5066
5067
5068
5069
5070 if (is_reset_needed)
5071 i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true);
5072
5073 return 0;
5074}
5075
5076
5077
5078
5079
5080
5081static int i40e_get_module_info(struct net_device *netdev,
5082 struct ethtool_modinfo *modinfo)
5083{
5084 struct i40e_netdev_priv *np = netdev_priv(netdev);
5085 struct i40e_vsi *vsi = np->vsi;
5086 struct i40e_pf *pf = vsi->back;
5087 struct i40e_hw *hw = &pf->hw;
5088 u32 sff8472_comp = 0;
5089 u32 sff8472_swap = 0;
5090 u32 sff8636_rev = 0;
5091 i40e_status status;
5092 u32 type = 0;
5093
5094
5095 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
5096 netdev_err(vsi->netdev, "Module EEPROM memory read not supported. Please update the NVM image.\n");
5097 return -EINVAL;
5098 }
5099
5100 status = i40e_update_link_info(hw);
5101 if (status)
5102 return -EIO;
5103
5104 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
5105 netdev_err(vsi->netdev, "Cannot read module EEPROM memory. No module connected.\n");
5106 return -EINVAL;
5107 }
5108
5109 type = hw->phy.link_info.module_type[0];
5110
5111 switch (type) {
5112 case I40E_MODULE_TYPE_SFP:
5113 status = i40e_aq_get_phy_register(hw,
5114 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5115 I40E_I2C_EEPROM_DEV_ADDR,
5116 I40E_MODULE_SFF_8472_COMP,
5117 &sff8472_comp, NULL);
5118 if (status)
5119 return -EIO;
5120
5121 status = i40e_aq_get_phy_register(hw,
5122 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5123 I40E_I2C_EEPROM_DEV_ADDR,
5124 I40E_MODULE_SFF_8472_SWAP,
5125 &sff8472_swap, NULL);
5126 if (status)
5127 return -EIO;
5128
5129
5130
5131
5132 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
5133 netdev_warn(vsi->netdev, "Module address swap to access page 0xA2 is not supported.\n");
5134 modinfo->type = ETH_MODULE_SFF_8079;
5135 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5136 } else if (sff8472_comp == 0x00) {
5137
5138 modinfo->type = ETH_MODULE_SFF_8079;
5139 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5140 } else if (!(sff8472_swap & I40E_MODULE_SFF_DDM_IMPLEMENTED)) {
5141
5142
5143
5144 modinfo->type = ETH_MODULE_SFF_8079;
5145 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5146 } else {
5147 modinfo->type = ETH_MODULE_SFF_8472;
5148 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
5149 }
5150 break;
5151 case I40E_MODULE_TYPE_QSFP_PLUS:
5152
5153 status = i40e_aq_get_phy_register(hw,
5154 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5155 0,
5156 I40E_MODULE_REVISION_ADDR,
5157 &sff8636_rev, NULL);
5158 if (status)
5159 return -EIO;
5160
5161 if (sff8636_rev > 0x02) {
5162
5163 modinfo->type = ETH_MODULE_SFF_8636;
5164 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5165 } else {
5166 modinfo->type = ETH_MODULE_SFF_8436;
5167 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5168 }
5169 break;
5170 case I40E_MODULE_TYPE_QSFP28:
5171 modinfo->type = ETH_MODULE_SFF_8636;
5172 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5173 break;
5174 default:
5175 netdev_err(vsi->netdev, "Module type unrecognized\n");
5176 return -EINVAL;
5177 }
5178 return 0;
5179}
5180
5181
5182
5183
5184
5185
5186
5187static int i40e_get_module_eeprom(struct net_device *netdev,
5188 struct ethtool_eeprom *ee,
5189 u8 *data)
5190{
5191 struct i40e_netdev_priv *np = netdev_priv(netdev);
5192 struct i40e_vsi *vsi = np->vsi;
5193 struct i40e_pf *pf = vsi->back;
5194 struct i40e_hw *hw = &pf->hw;
5195 bool is_sfp = false;
5196 i40e_status status;
5197 u32 value = 0;
5198 int i;
5199
5200 if (!ee || !ee->len || !data)
5201 return -EINVAL;
5202
5203 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
5204 is_sfp = true;
5205
5206 for (i = 0; i < ee->len; i++) {
5207 u32 offset = i + ee->offset;
5208 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
5209
5210
5211 if (is_sfp) {
5212 if (offset >= ETH_MODULE_SFF_8079_LEN) {
5213 offset -= ETH_MODULE_SFF_8079_LEN;
5214 addr = I40E_I2C_EEPROM_DEV_ADDR2;
5215 }
5216 } else {
5217 while (offset >= ETH_MODULE_SFF_8436_LEN) {
5218
5219 offset -= ETH_MODULE_SFF_8436_LEN / 2;
5220 addr++;
5221 }
5222 }
5223
5224 status = i40e_aq_get_phy_register(hw,
5225 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5226 addr, offset, &value, NULL);
5227 if (status)
5228 return -EIO;
5229 data[i] = value;
5230 }
5231 return 0;
5232}
5233
5234static int i40e_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
5235{
5236 return -EOPNOTSUPP;
5237}
5238
5239static int i40e_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
5240{
5241 return -EOPNOTSUPP;
5242}
5243
5244static const struct ethtool_ops i40e_ethtool_recovery_mode_ops = {
5245 .set_eeprom = i40e_set_eeprom,
5246 .get_eeprom_len = i40e_get_eeprom_len,
5247 .get_eeprom = i40e_get_eeprom,
5248};
5249
5250static const struct ethtool_ops i40e_ethtool_ops = {
5251 .get_drvinfo = i40e_get_drvinfo,
5252 .get_regs_len = i40e_get_regs_len,
5253 .get_regs = i40e_get_regs,
5254 .nway_reset = i40e_nway_reset,
5255 .get_link = ethtool_op_get_link,
5256 .get_wol = i40e_get_wol,
5257 .set_wol = i40e_set_wol,
5258 .set_eeprom = i40e_set_eeprom,
5259 .get_eeprom_len = i40e_get_eeprom_len,
5260 .get_eeprom = i40e_get_eeprom,
5261 .get_ringparam = i40e_get_ringparam,
5262 .set_ringparam = i40e_set_ringparam,
5263 .get_pauseparam = i40e_get_pauseparam,
5264 .set_pauseparam = i40e_set_pauseparam,
5265 .get_msglevel = i40e_get_msglevel,
5266 .set_msglevel = i40e_set_msglevel,
5267 .get_rxnfc = i40e_get_rxnfc,
5268 .set_rxnfc = i40e_set_rxnfc,
5269 .self_test = i40e_diag_test,
5270 .get_strings = i40e_get_strings,
5271 .get_eee = i40e_get_eee,
5272 .set_eee = i40e_set_eee,
5273 .set_phys_id = i40e_set_phys_id,
5274 .get_sset_count = i40e_get_sset_count,
5275 .get_ethtool_stats = i40e_get_ethtool_stats,
5276 .get_coalesce = i40e_get_coalesce,
5277 .set_coalesce = i40e_set_coalesce,
5278 .get_rxfh_key_size = i40e_get_rxfh_key_size,
5279 .get_rxfh_indir_size = i40e_get_rxfh_indir_size,
5280 .get_rxfh = i40e_get_rxfh,
5281 .set_rxfh = i40e_set_rxfh,
5282 .get_channels = i40e_get_channels,
5283 .set_channels = i40e_set_channels,
5284 .get_module_info = i40e_get_module_info,
5285 .get_module_eeprom = i40e_get_module_eeprom,
5286 .get_ts_info = i40e_get_ts_info,
5287 .get_priv_flags = i40e_get_priv_flags,
5288 .set_priv_flags = i40e_set_priv_flags,
5289 .get_per_queue_coalesce = i40e_get_per_queue_coalesce,
5290 .set_per_queue_coalesce = i40e_set_per_queue_coalesce,
5291 .get_link_ksettings = i40e_get_link_ksettings,
5292 .set_link_ksettings = i40e_set_link_ksettings,
5293 .get_fecparam = i40e_get_fec_param,
5294 .set_fecparam = i40e_set_fec_param,
5295 .flash_device = i40e_ddp_flash,
5296};
5297
5298void i40e_set_ethtool_ops(struct net_device *netdev)
5299{
5300 struct i40e_netdev_priv *np = netdev_priv(netdev);
5301 struct i40e_pf *pf = np->vsi->back;
5302
5303 if (!test_bit(__I40E_RECOVERY_MODE, pf->state))
5304 netdev->ethtool_ops = &i40e_ethtool_ops;
5305 else
5306 netdev->ethtool_ops = &i40e_ethtool_recovery_mode_ops;
5307}
5308