// SPDX-License-Identifier: GPL-2.0-only
/* QLogic qed NIC Driver
 * Copyright (c) 2015 QLogic Corporation
 */

#include <linux/module.h>
#include <linux/vmalloc.h>
#include <linux/crc32.h>
#include "qed.h"
#include "qed_hsi.h"
#include "qed_hw.h"
#include "qed_mcp.h"
#include "qed_reg_addr.h"

/* Memory groups enum */
enum mem_groups {
        MEM_GROUP_PXP_MEM,
        MEM_GROUP_DMAE_MEM,
        MEM_GROUP_CM_MEM,
        MEM_GROUP_QM_MEM,
        MEM_GROUP_DORQ_MEM,
        MEM_GROUP_BRB_RAM,
        MEM_GROUP_BRB_MEM,
        MEM_GROUP_PRS_MEM,
        MEM_GROUP_IOR,
        MEM_GROUP_BTB_RAM,
        MEM_GROUP_CONN_CFC_MEM,
        MEM_GROUP_TASK_CFC_MEM,
        MEM_GROUP_CAU_PI,
        MEM_GROUP_CAU_MEM,
        MEM_GROUP_PXP_ILT,
        MEM_GROUP_TM_MEM,
        MEM_GROUP_SDM_MEM,
        MEM_GROUP_PBUF,
        MEM_GROUP_RAM,
        MEM_GROUP_MULD_MEM,
        MEM_GROUP_BTB_MEM,
        MEM_GROUP_RDIF_CTX,
        MEM_GROUP_TDIF_CTX,
        MEM_GROUP_CFC_MEM,
        MEM_GROUP_IGU_MEM,
        MEM_GROUP_IGU_MSIX,
        MEM_GROUP_CAU_SB,
        MEM_GROUP_BMB_RAM,
        MEM_GROUP_BMB_MEM,
        MEM_GROUPS_NUM
};

/* Memory groups names */
static const char * const s_mem_group_names[] = {
        "PXP_MEM",
        "DMAE_MEM",
        "CM_MEM",
        "QM_MEM",
        "DORQ_MEM",
        "BRB_RAM",
        "BRB_MEM",
        "PRS_MEM",
        "IOR",
        "BTB_RAM",
        "CONN_CFC_MEM",
        "TASK_CFC_MEM",
        "CAU_PI",
        "CAU_MEM",
        "PXP_ILT",
        "TM_MEM",
        "SDM_MEM",
        "PBUF",
        "RAM",
        "MULD_MEM",
        "BTB_MEM",
        "RDIF_CTX",
        "TDIF_CTX",
        "CFC_MEM",
        "IGU_MEM",
        "IGU_MSIX",
        "CAU_SB",
        "BMB_RAM",
        "BMB_MEM",
};

/* Idle check conditions */

static u32 cond5(const u32 *r, const u32 *imm)
{
        return ((r[0] & imm[0]) != imm[1]) && ((r[1] & imm[2]) != imm[3]);
}

static u32 cond7(const u32 *r, const u32 *imm)
{
        return ((r[0] >> imm[0]) & imm[1]) != imm[2];
}

static u32 cond6(const u32 *r, const u32 *imm)
{
        return (r[0] & imm[0]) != imm[1];
}

static u32 cond9(const u32 *r, const u32 *imm)
{
        return ((r[0] & imm[0]) >> imm[1]) !=
            (((r[0] & imm[2]) >> imm[3]) | ((r[1] & imm[4]) << imm[5]));
}

static u32 cond10(const u32 *r, const u32 *imm)
{
        return ((r[0] & imm[0]) >> imm[1]) != (r[0] & imm[2]);
}

static u32 cond4(const u32 *r, const u32 *imm)
{
        return (r[0] & ~imm[0]) != imm[1];
}

static u32 cond0(const u32 *r, const u32 *imm)
{
        return (r[0] & ~r[1]) != imm[0];
}

static u32 cond1(const u32 *r, const u32 *imm)
{
        return r[0] != imm[0];
}

static u32 cond11(const u32 *r, const u32 *imm)
{
        return r[0] != r[1] && r[2] == imm[0];
}

static u32 cond12(const u32 *r, const u32 *imm)
{
        return r[0] != r[1] && r[2] > imm[0];
}

static u32 cond3(const u32 *r, const u32 *imm)
{
        return r[0] != r[1];
}

static u32 cond13(const u32 *r, const u32 *imm)
{
        return r[0] & imm[0];
}

static u32 cond8(const u32 *r, const u32 *imm)
{
        return r[0] < (r[1] - imm[0]);
}

static u32 cond2(const u32 *r, const u32 *imm)
{
        return r[0] > imm[0];
}

/* Array of Idle Check conditions */
static u32(*cond_arr[]) (const u32 *r, const u32 *imm) = {
        cond0,
        cond1,
        cond2,
        cond3,
        cond4,
        cond5,
        cond6,
        cond7,
        cond8,
        cond9,
        cond10,
        cond11,
        cond12,
        cond13,
};

/******************************* Data Types **********************************/

enum platform_ids {
        PLATFORM_ASIC,
        PLATFORM_RESERVED,
        PLATFORM_RESERVED2,
        PLATFORM_RESERVED3,
        MAX_PLATFORM_IDS
};

/* Chip constant definitions */
struct chip_defs {
        const char *name;
};

/* Platform constant definitions */
struct platform_defs {
        const char *name;
        u32 delay_factor;
        u32 dmae_thresh;
        u32 log_thresh;
};

/* Storm constant definitions.
 * Addresses are in bytes, sizes are in quad-regs.
 */
struct storm_defs {
        char letter;
        enum block_id block_id;
        enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
        bool has_vfc;
        u32 sem_fast_mem_addr;
        u32 sem_frame_mode_addr;
        u32 sem_slow_enable_addr;
        u32 sem_slow_mode_addr;
        u32 sem_slow_mode1_conf_addr;
        u32 sem_sync_dbg_empty_addr;
        u32 sem_slow_dbg_empty_addr;
        u32 cm_ctx_wr_addr;
        u32 cm_conn_ag_ctx_lid_size;
        u32 cm_conn_ag_ctx_rd_addr;
        u32 cm_conn_st_ctx_lid_size;
        u32 cm_conn_st_ctx_rd_addr;
        u32 cm_task_ag_ctx_lid_size;
        u32 cm_task_ag_ctx_rd_addr;
        u32 cm_task_st_ctx_lid_size;
        u32 cm_task_st_ctx_rd_addr;
};

/* Block constant definitions */
struct block_defs {
        const char *name;
        bool exists[MAX_CHIP_IDS];
        bool associated_to_storm;

        /* Valid only if associated_to_storm is true */
        u32 storm_id;
        enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
        u32 dbg_select_addr;
        u32 dbg_enable_addr;
        u32 dbg_shift_addr;
        u32 dbg_force_valid_addr;
        u32 dbg_force_frame_addr;
        bool has_reset_bit;

        /* If true, block is taken out of reset before dump */
        bool unreset;
        enum dbg_reset_regs reset_reg;

        /* Bit offset in reset register */
        u8 reset_bit_offset;
};

/* Reset register definitions */
struct reset_reg_defs {
        u32 addr;
        bool exists[MAX_CHIP_IDS];
        u32 unreset_val[MAX_CHIP_IDS];
};

struct grc_param_defs {
        u32 default_val[MAX_CHIP_IDS];
        u32 min;
        u32 max;
        bool is_preset;
        bool is_persistent;
        u32 exclude_all_preset_val;
        u32 crash_preset_val;
};

/* Address is in 128b units. Width is in bits. */
struct rss_mem_defs {
        const char *mem_name;
        const char *type_name;
        u32 addr;
        u32 entry_width;
        u32 num_entries[MAX_CHIP_IDS];
};

struct vfc_ram_defs {
        const char *mem_name;
        const char *type_name;
        u32 base_row;
        u32 num_rows;
};

struct big_ram_defs {
        const char *instance_name;
        enum mem_groups mem_group_id;
        enum mem_groups ram_mem_group_id;
        enum dbg_grc_params grc_param;
        u32 addr_reg_addr;
        u32 data_reg_addr;
        u32 is_256b_reg_addr;
        u32 is_256b_bit_offset[MAX_CHIP_IDS];
        u32 ram_size[MAX_CHIP_IDS]; /* In dwords */
};

struct phy_defs {
        const char *phy_name;

        /* PHY base GRC address */
        u32 base_addr;

        /* Relative address of indirect TBUS address register (bits 0..7) */
        u32 tbus_addr_lo_addr;

        /* Relative address of indirect TBUS address register (bits 8..10) */
        u32 tbus_addr_hi_addr;

        /* Relative address of indirect TBUS data register (bits 0..7) */
        u32 tbus_data_lo_addr;

        /* Relative address of indirect TBUS data register (bits 8..11) */
        u32 tbus_data_hi_addr;
};

/* Split type definitions */
struct split_type_defs {
        const char *name;
};

/******************************** Constants **********************************/

#define MAX_LCIDS                       320
#define MAX_LTIDS                       320

#define NUM_IOR_SETS                    2
#define IORS_PER_SET                    176
#define IOR_SET_OFFSET(set_id)          ((set_id) * 256)

#define BYTES_IN_DWORD                  sizeof(u32)

/* In the macros below, size and offset are specified in bits */
#define CEIL_DWORDS(size)               DIV_ROUND_UP(size, 32)
#define FIELD_BIT_OFFSET(type, field)   type ## _ ## field ## _ ## OFFSET
#define FIELD_BIT_SIZE(type, field)     type ## _ ## field ## _ ## SIZE
#define FIELD_DWORD_OFFSET(type, field) \
         (int)(FIELD_BIT_OFFSET(type, field) / 32)
#define FIELD_DWORD_SHIFT(type, field)  (FIELD_BIT_OFFSET(type, field) % 32)
#define FIELD_BIT_MASK(type, field) \
        (((1 << FIELD_BIT_SIZE(type, field)) - 1) << \
         FIELD_DWORD_SHIFT(type, field))

#define SET_VAR_FIELD(var, type, field, val) \
        do { \
                var[FIELD_DWORD_OFFSET(type, field)] &= \
                (~FIELD_BIT_MASK(type, field)); \
                var[FIELD_DWORD_OFFSET(type, field)] |= \
                (val) << FIELD_DWORD_SHIFT(type, field); \
        } while (0)

#define ARR_REG_WR(dev, ptt, addr, arr, arr_size) \
        do { \
                for (i = 0; i < (arr_size); i++) \
                        qed_wr(dev, ptt, addr,  (arr)[i]); \
        } while (0)

#define ARR_REG_RD(dev, ptt, addr, arr, arr_size) \
        do { \
                for (i = 0; i < (arr_size); i++) \
                        (arr)[i] = qed_rd(dev, ptt, addr); \
        } while (0)

#define DWORDS_TO_BYTES(dwords)         ((dwords) * BYTES_IN_DWORD)
#define BYTES_TO_DWORDS(bytes)          ((bytes) / BYTES_IN_DWORD)

/* Extra lines include a signature line + optional latency events line */
#define NUM_EXTRA_DBG_LINES(block_desc) \
        (1 + ((block_desc)->has_latency_events ? 1 : 0))
#define NUM_DBG_LINES(block_desc) \
        ((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))

#define RAM_LINES_TO_DWORDS(lines)      ((lines) * 2)
#define RAM_LINES_TO_BYTES(lines) \
        DWORDS_TO_BYTES(RAM_LINES_TO_DWORDS(lines))

#define REG_DUMP_LEN_SHIFT              24
#define MEM_DUMP_ENTRY_SIZE_DWORDS \
        BYTES_TO_DWORDS(sizeof(struct dbg_dump_mem))

#define IDLE_CHK_RULE_SIZE_DWORDS \
        BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_rule))

#define IDLE_CHK_RESULT_HDR_DWORDS \
        BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_hdr))

#define IDLE_CHK_RESULT_REG_HDR_DWORDS \
        BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_reg_hdr))

#define IDLE_CHK_MAX_ENTRIES_SIZE       32

/* The sizes and offsets below are specified in bits */
#define VFC_CAM_CMD_STRUCT_SIZE         64
#define VFC_CAM_CMD_ROW_OFFSET          48
#define VFC_CAM_CMD_ROW_SIZE            9
#define VFC_CAM_ADDR_STRUCT_SIZE        16
#define VFC_CAM_ADDR_OP_OFFSET          0
#define VFC_CAM_ADDR_OP_SIZE            4
#define VFC_CAM_RESP_STRUCT_SIZE        256
#define VFC_RAM_ADDR_STRUCT_SIZE        16
#define VFC_RAM_ADDR_OP_OFFSET          0
#define VFC_RAM_ADDR_OP_SIZE            2
#define VFC_RAM_ADDR_ROW_OFFSET         2
#define VFC_RAM_ADDR_ROW_SIZE           10
#define VFC_RAM_RESP_STRUCT_SIZE        256

#define VFC_CAM_CMD_DWORDS              CEIL_DWORDS(VFC_CAM_CMD_STRUCT_SIZE)
#define VFC_CAM_ADDR_DWORDS             CEIL_DWORDS(VFC_CAM_ADDR_STRUCT_SIZE)
#define VFC_CAM_RESP_DWORDS             CEIL_DWORDS(VFC_CAM_RESP_STRUCT_SIZE)
#define VFC_RAM_CMD_DWORDS              VFC_CAM_CMD_DWORDS
#define VFC_RAM_ADDR_DWORDS             CEIL_DWORDS(VFC_RAM_ADDR_STRUCT_SIZE)
#define VFC_RAM_RESP_DWORDS             CEIL_DWORDS(VFC_RAM_RESP_STRUCT_SIZE)

#define NUM_VFC_RAM_TYPES               4

#define VFC_CAM_NUM_ROWS                512

#define VFC_OPCODE_CAM_RD               14
#define VFC_OPCODE_RAM_RD               0

#define NUM_RSS_MEM_TYPES               5

#define NUM_BIG_RAM_TYPES               3
#define BIG_RAM_NAME_LEN                3

#define NUM_PHY_TBUS_ADDRESSES          2048
#define PHY_DUMP_SIZE_DWORDS            (NUM_PHY_TBUS_ADDRESSES / 2)

#define RESET_REG_UNRESET_OFFSET        4

#define STALL_DELAY_MS                  500

#define STATIC_DEBUG_LINE_DWORDS        9

#define NUM_COMMON_GLOBAL_PARAMS        8

#define FW_IMG_MAIN                     1

#define REG_FIFO_ELEMENT_DWORDS         2
#define REG_FIFO_DEPTH_ELEMENTS         32
#define REG_FIFO_DEPTH_DWORDS \
        (REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS)

#define IGU_FIFO_ELEMENT_DWORDS         4
#define IGU_FIFO_DEPTH_ELEMENTS         64
#define IGU_FIFO_DEPTH_DWORDS \
        (IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS)

#define PROTECTION_OVERRIDE_ELEMENT_DWORDS      2
#define PROTECTION_OVERRIDE_DEPTH_ELEMENTS      20
#define PROTECTION_OVERRIDE_DEPTH_DWORDS \
        (PROTECTION_OVERRIDE_DEPTH_ELEMENTS * \
         PROTECTION_OVERRIDE_ELEMENT_DWORDS)

#define MCP_SPAD_TRACE_OFFSIZE_ADDR \
        (MCP_REG_SCRATCH + \
         offsetof(struct static_init, sections[SPAD_SECTION_TRACE]))

#define EMPTY_FW_VERSION_STR            "???_???_???_???"
#define EMPTY_FW_IMAGE_STR              "???????????????"

/***************************** Constant Arrays *******************************/

struct dbg_array {
        const u32 *ptr;
        u32 size_in_dwords;
};

/* Debug arrays */
static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} };

/* Chip constant definitions array */
static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = {
        {"bb"},
        {"ah"},
        {"reserved"},
};

/* Storm constant definitions array */
static struct storm_defs s_storm_defs[] = {
        /* Tstorm */
        {'T', BLOCK_TSEM,
         {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT,
          DBG_BUS_CLIENT_RBCT}, true,
         TSEM_REG_FAST_MEMORY,
         TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
         TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2,
         TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
         TCM_REG_CTX_RBC_ACCS,
         4, TCM_REG_AGG_CON_CTX,
         16, TCM_REG_SM_CON_CTX,
         2, TCM_REG_AGG_TASK_CTX,
         4, TCM_REG_SM_TASK_CTX},

        /* Mstorm */
        {'M', BLOCK_MSEM,
         {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM,
          DBG_BUS_CLIENT_RBCM}, false,
         MSEM_REG_FAST_MEMORY,
         MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
         MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2,
         MSEM_REG_SYNC_DBG_EMPTY, MSEM_REG_SLOW_DBG_EMPTY_BB_K2,
         MCM_REG_CTX_RBC_ACCS,
         1, MCM_REG_AGG_CON_CTX,
         10, MCM_REG_SM_CON_CTX,
         2, MCM_REG_AGG_TASK_CTX,
         7, MCM_REG_SM_TASK_CTX},

        /* Ustorm */
        {'U', BLOCK_USEM,
         {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU,
          DBG_BUS_CLIENT_RBCU}, false,
         USEM_REG_FAST_MEMORY,
         USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2,
         USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2,
         USEM_REG_SYNC_DBG_EMPTY, USEM_REG_SLOW_DBG_EMPTY_BB_K2,
         UCM_REG_CTX_RBC_ACCS,
         2, UCM_REG_AGG_CON_CTX,
         13, UCM_REG_SM_CON_CTX,
         3, UCM_REG_AGG_TASK_CTX,
         3, UCM_REG_SM_TASK_CTX},

        /* Xstorm */
        {'X', BLOCK_XSEM,
         {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX,
          DBG_BUS_CLIENT_RBCX}, false,
         XSEM_REG_FAST_MEMORY,
         XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
         XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2,
         XSEM_REG_SYNC_DBG_EMPTY, XSEM_REG_SLOW_DBG_EMPTY_BB_K2,
         XCM_REG_CTX_RBC_ACCS,
         9, XCM_REG_AGG_CON_CTX,
         15, XCM_REG_SM_CON_CTX,
         0, 0,
         0, 0},

        /* Ystorm */
        {'Y', BLOCK_YSEM,
         {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY,
          DBG_BUS_CLIENT_RBCY}, false,
         YSEM_REG_FAST_MEMORY,
         YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
         YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2,
         YSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
         YCM_REG_CTX_RBC_ACCS,
         2, YCM_REG_AGG_CON_CTX,
         3, YCM_REG_SM_CON_CTX,
         2, YCM_REG_AGG_TASK_CTX,
         12, YCM_REG_SM_TASK_CTX},

        /* Pstorm */
        {'P', BLOCK_PSEM,
         {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS,
          DBG_BUS_CLIENT_RBCS}, true,
         PSEM_REG_FAST_MEMORY,
         PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
         PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2,
         PSEM_REG_SYNC_DBG_EMPTY, PSEM_REG_SLOW_DBG_EMPTY_BB_K2,
         PCM_REG_CTX_RBC_ACCS,
         0, 0,
         10, PCM_REG_SM_CON_CTX,
         0, 0,
         0, 0}
};

/* Block definitions array */

static struct block_defs block_grc_defs = {
        "grc",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN},
        GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE,
        GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID,
        GRC_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISC_PL_UA, 1
};

static struct block_defs block_miscs_defs = {
        "miscs", {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_misc_defs = {
        "misc", {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_dbu_defs = {
        "dbu", {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_pglue_b_defs = {
        "pglue_b",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH},
        PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE,
        PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID,
        PGLUE_B_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISCS_PL_HV, 1
};

static struct block_defs block_cnig_defs = {
        "cnig",
        {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW,
         DBG_BUS_CLIENT_RBCW},
        CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5,
        CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5,
        CNIG_REG_DBG_FORCE_FRAME_K2_E5,
        true, false, DBG_RESET_REG_MISCS_PL_HV, 0
};

static struct block_defs block_cpmu_defs = {
        "cpmu", {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        true, false, DBG_RESET_REG_MISCS_PL_HV, 8
};

static struct block_defs block_ncsi_defs = {
        "ncsi",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
        NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE,
        NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID,
        NCSI_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISCS_PL_HV, 5
};

static struct block_defs block_opte_defs = {
        "opte", {true, true, false}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        true, false, DBG_RESET_REG_MISCS_PL_HV, 4
};

static struct block_defs block_bmb_defs = {
        "bmb",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB, DBG_BUS_CLIENT_RBCB},
        BMB_REG_DBG_SELECT, BMB_REG_DBG_DWORD_ENABLE,
        BMB_REG_DBG_SHIFT, BMB_REG_DBG_FORCE_VALID,
        BMB_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISCS_PL_UA, 7
};

static struct block_defs block_pcie_defs = {
        "pcie",
        {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
         DBG_BUS_CLIENT_RBCH},
        PCIE_REG_DBG_COMMON_SELECT_K2_E5,
        PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
        PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
        PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
        PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_mcp_defs = {
        "mcp", {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_mcp2_defs = {
        "mcp2",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
        MCP2_REG_DBG_SELECT, MCP2_REG_DBG_DWORD_ENABLE,
        MCP2_REG_DBG_SHIFT, MCP2_REG_DBG_FORCE_VALID,
        MCP2_REG_DBG_FORCE_FRAME,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_pswhst_defs = {
        "pswhst",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        PSWHST_REG_DBG_SELECT, PSWHST_REG_DBG_DWORD_ENABLE,
        PSWHST_REG_DBG_SHIFT, PSWHST_REG_DBG_FORCE_VALID,
        PSWHST_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISC_PL_HV, 0
};

static struct block_defs block_pswhst2_defs = {
        "pswhst2",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        PSWHST2_REG_DBG_SELECT, PSWHST2_REG_DBG_DWORD_ENABLE,
        PSWHST2_REG_DBG_SHIFT, PSWHST2_REG_DBG_FORCE_VALID,
        PSWHST2_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISC_PL_HV, 0
};

static struct block_defs block_pswrd_defs = {
        "pswrd",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        PSWRD_REG_DBG_SELECT, PSWRD_REG_DBG_DWORD_ENABLE,
        PSWRD_REG_DBG_SHIFT, PSWRD_REG_DBG_FORCE_VALID,
        PSWRD_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISC_PL_HV, 2
};

static struct block_defs block_pswrd2_defs = {
        "pswrd2",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        PSWRD2_REG_DBG_SELECT, PSWRD2_REG_DBG_DWORD_ENABLE,
        PSWRD2_REG_DBG_SHIFT, PSWRD2_REG_DBG_FORCE_VALID,
        PSWRD2_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISC_PL_HV, 2
};

static struct block_defs block_pswwr_defs = {
        "pswwr",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        PSWWR_REG_DBG_SELECT, PSWWR_REG_DBG_DWORD_ENABLE,
        PSWWR_REG_DBG_SHIFT, PSWWR_REG_DBG_FORCE_VALID,
        PSWWR_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISC_PL_HV, 3
};

static struct block_defs block_pswwr2_defs = {
        "pswwr2", {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        true, false, DBG_RESET_REG_MISC_PL_HV, 3
};

static struct block_defs block_pswrq_defs = {
        "pswrq",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        PSWRQ_REG_DBG_SELECT, PSWRQ_REG_DBG_DWORD_ENABLE,
        PSWRQ_REG_DBG_SHIFT, PSWRQ_REG_DBG_FORCE_VALID,
        PSWRQ_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISC_PL_HV, 1
};

static struct block_defs block_pswrq2_defs = {
        "pswrq2",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        PSWRQ2_REG_DBG_SELECT, PSWRQ2_REG_DBG_DWORD_ENABLE,
        PSWRQ2_REG_DBG_SHIFT, PSWRQ2_REG_DBG_FORCE_VALID,
        PSWRQ2_REG_DBG_FORCE_FRAME,
        true, false, DBG_RESET_REG_MISC_PL_HV, 1
};

static struct block_defs block_pglcs_defs = {
        "pglcs",
        {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
         DBG_BUS_CLIENT_RBCH},
        PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5,
        PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5,
        PGLCS_REG_DBG_FORCE_FRAME_K2_E5,
        true, false, DBG_RESET_REG_MISCS_PL_HV, 2
};

static struct block_defs block_ptu_defs = {
        "ptu",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        PTU_REG_DBG_SELECT, PTU_REG_DBG_DWORD_ENABLE,
        PTU_REG_DBG_SHIFT, PTU_REG_DBG_FORCE_VALID,
        PTU_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 20
};

static struct block_defs block_dmae_defs = {
        "dmae",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        DMAE_REG_DBG_SELECT, DMAE_REG_DBG_DWORD_ENABLE,
        DMAE_REG_DBG_SHIFT, DMAE_REG_DBG_FORCE_VALID,
        DMAE_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 28
};

static struct block_defs block_tcm_defs = {
        "tcm",
        {true, true, true}, true, DBG_TSTORM_ID,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
        TCM_REG_DBG_SELECT, TCM_REG_DBG_DWORD_ENABLE,
        TCM_REG_DBG_SHIFT, TCM_REG_DBG_FORCE_VALID,
        TCM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 5
};

static struct block_defs block_mcm_defs = {
        "mcm",
        {true, true, true}, true, DBG_MSTORM_ID,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
        MCM_REG_DBG_SELECT, MCM_REG_DBG_DWORD_ENABLE,
        MCM_REG_DBG_SHIFT, MCM_REG_DBG_FORCE_VALID,
        MCM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 3
};

static struct block_defs block_ucm_defs = {
        "ucm",
        {true, true, true}, true, DBG_USTORM_ID,
        {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
        UCM_REG_DBG_SELECT, UCM_REG_DBG_DWORD_ENABLE,
        UCM_REG_DBG_SHIFT, UCM_REG_DBG_FORCE_VALID,
        UCM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 8
};

static struct block_defs block_xcm_defs = {
        "xcm",
        {true, true, true}, true, DBG_XSTORM_ID,
        {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
        XCM_REG_DBG_SELECT, XCM_REG_DBG_DWORD_ENABLE,
        XCM_REG_DBG_SHIFT, XCM_REG_DBG_FORCE_VALID,
        XCM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 19
};

static struct block_defs block_ycm_defs = {
        "ycm",
        {true, true, true}, true, DBG_YSTORM_ID,
        {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
        YCM_REG_DBG_SELECT, YCM_REG_DBG_DWORD_ENABLE,
        YCM_REG_DBG_SHIFT, YCM_REG_DBG_FORCE_VALID,
        YCM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 5
};

static struct block_defs block_pcm_defs = {
        "pcm",
        {true, true, true}, true, DBG_PSTORM_ID,
        {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
        PCM_REG_DBG_SELECT, PCM_REG_DBG_DWORD_ENABLE,
        PCM_REG_DBG_SHIFT, PCM_REG_DBG_FORCE_VALID,
        PCM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 4
};

static struct block_defs block_qm_defs = {
        "qm",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ, DBG_BUS_CLIENT_RBCQ},
        QM_REG_DBG_SELECT, QM_REG_DBG_DWORD_ENABLE,
        QM_REG_DBG_SHIFT, QM_REG_DBG_FORCE_VALID,
        QM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 16
};

static struct block_defs block_tm_defs = {
        "tm",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
        TM_REG_DBG_SELECT, TM_REG_DBG_DWORD_ENABLE,
        TM_REG_DBG_SHIFT, TM_REG_DBG_FORCE_VALID,
        TM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 17
};

static struct block_defs block_dorq_defs = {
        "dorq",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
        DORQ_REG_DBG_SELECT, DORQ_REG_DBG_DWORD_ENABLE,
        DORQ_REG_DBG_SHIFT, DORQ_REG_DBG_FORCE_VALID,
        DORQ_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 18
};

static struct block_defs block_brb_defs = {
        "brb",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR},
        BRB_REG_DBG_SELECT, BRB_REG_DBG_DWORD_ENABLE,
        BRB_REG_DBG_SHIFT, BRB_REG_DBG_FORCE_VALID,
        BRB_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 0
};

static struct block_defs block_src_defs = {
        "src",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
        SRC_REG_DBG_SELECT, SRC_REG_DBG_DWORD_ENABLE,
        SRC_REG_DBG_SHIFT, SRC_REG_DBG_FORCE_VALID,
        SRC_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 2
};

static struct block_defs block_prs_defs = {
        "prs",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR},
        PRS_REG_DBG_SELECT, PRS_REG_DBG_DWORD_ENABLE,
        PRS_REG_DBG_SHIFT, PRS_REG_DBG_FORCE_VALID,
        PRS_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1
};

static struct block_defs block_tsdm_defs = {
        "tsdm",
        {true, true, true}, true, DBG_TSTORM_ID,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
        TSDM_REG_DBG_SELECT, TSDM_REG_DBG_DWORD_ENABLE,
        TSDM_REG_DBG_SHIFT, TSDM_REG_DBG_FORCE_VALID,
        TSDM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 3
};

static struct block_defs block_msdm_defs = {
        "msdm",
        {true, true, true}, true, DBG_MSTORM_ID,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
        MSDM_REG_DBG_SELECT, MSDM_REG_DBG_DWORD_ENABLE,
        MSDM_REG_DBG_SHIFT, MSDM_REG_DBG_FORCE_VALID,
        MSDM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 6
};

static struct block_defs block_usdm_defs = {
        "usdm",
        {true, true, true}, true, DBG_USTORM_ID,
        {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
        USDM_REG_DBG_SELECT, USDM_REG_DBG_DWORD_ENABLE,
        USDM_REG_DBG_SHIFT, USDM_REG_DBG_FORCE_VALID,
        USDM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 7
};

static struct block_defs block_xsdm_defs = {
        "xsdm",
        {true, true, true}, true, DBG_XSTORM_ID,
        {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
        XSDM_REG_DBG_SELECT, XSDM_REG_DBG_DWORD_ENABLE,
        XSDM_REG_DBG_SHIFT, XSDM_REG_DBG_FORCE_VALID,
        XSDM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 20
};

static struct block_defs block_ysdm_defs = {
        "ysdm",
        {true, true, true}, true, DBG_YSTORM_ID,
        {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
        YSDM_REG_DBG_SELECT, YSDM_REG_DBG_DWORD_ENABLE,
        YSDM_REG_DBG_SHIFT, YSDM_REG_DBG_FORCE_VALID,
        YSDM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 8
};

static struct block_defs block_psdm_defs = {
        "psdm",
        {true, true, true}, true, DBG_PSTORM_ID,
        {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
        PSDM_REG_DBG_SELECT, PSDM_REG_DBG_DWORD_ENABLE,
        PSDM_REG_DBG_SHIFT, PSDM_REG_DBG_FORCE_VALID,
        PSDM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 7
};

static struct block_defs block_tsem_defs = {
        "tsem",
        {true, true, true}, true, DBG_TSTORM_ID,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
        TSEM_REG_DBG_SELECT, TSEM_REG_DBG_DWORD_ENABLE,
        TSEM_REG_DBG_SHIFT, TSEM_REG_DBG_FORCE_VALID,
        TSEM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 4
};

static struct block_defs block_msem_defs = {
        "msem",
        {true, true, true}, true, DBG_MSTORM_ID,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
        MSEM_REG_DBG_SELECT, MSEM_REG_DBG_DWORD_ENABLE,
        MSEM_REG_DBG_SHIFT, MSEM_REG_DBG_FORCE_VALID,
        MSEM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 9
};

static struct block_defs block_usem_defs = {
        "usem",
        {true, true, true}, true, DBG_USTORM_ID,
        {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
        USEM_REG_DBG_SELECT, USEM_REG_DBG_DWORD_ENABLE,
        USEM_REG_DBG_SHIFT, USEM_REG_DBG_FORCE_VALID,
        USEM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 9
};

static struct block_defs block_xsem_defs = {
        "xsem",
        {true, true, true}, true, DBG_XSTORM_ID,
        {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
        XSEM_REG_DBG_SELECT, XSEM_REG_DBG_DWORD_ENABLE,
        XSEM_REG_DBG_SHIFT, XSEM_REG_DBG_FORCE_VALID,

        XSEM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 21
};

static struct block_defs block_ysem_defs = {
        "ysem",
        {true, true, true}, true, DBG_YSTORM_ID,
        {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
        YSEM_REG_DBG_SELECT, YSEM_REG_DBG_DWORD_ENABLE,
        YSEM_REG_DBG_SHIFT, YSEM_REG_DBG_FORCE_VALID,
        YSEM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 11
};

static struct block_defs block_psem_defs = {
        "psem",
        {true, true, true}, true, DBG_PSTORM_ID,
        {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
        PSEM_REG_DBG_SELECT, PSEM_REG_DBG_DWORD_ENABLE,
        PSEM_REG_DBG_SHIFT, PSEM_REG_DBG_FORCE_VALID,
        PSEM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10
};

static struct block_defs block_rss_defs = {
        "rss",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
        RSS_REG_DBG_SELECT, RSS_REG_DBG_DWORD_ENABLE,
        RSS_REG_DBG_SHIFT, RSS_REG_DBG_FORCE_VALID,
        RSS_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 18
};

static struct block_defs block_tmld_defs = {
        "tmld",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
        TMLD_REG_DBG_SELECT, TMLD_REG_DBG_DWORD_ENABLE,
        TMLD_REG_DBG_SHIFT, TMLD_REG_DBG_FORCE_VALID,
        TMLD_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 13
};

static struct block_defs block_muld_defs = {
        "muld",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
        MULD_REG_DBG_SELECT, MULD_REG_DBG_DWORD_ENABLE,
        MULD_REG_DBG_SHIFT, MULD_REG_DBG_FORCE_VALID,
        MULD_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 14
};

static struct block_defs block_yuld_defs = {
        "yuld",
        {true, true, false}, false, 0,
        {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU,
         MAX_DBG_BUS_CLIENTS},
        YULD_REG_DBG_SELECT_BB_K2, YULD_REG_DBG_DWORD_ENABLE_BB_K2,
        YULD_REG_DBG_SHIFT_BB_K2, YULD_REG_DBG_FORCE_VALID_BB_K2,
        YULD_REG_DBG_FORCE_FRAME_BB_K2,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
        15
};

static struct block_defs block_xyld_defs = {
        "xyld",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
        XYLD_REG_DBG_SELECT, XYLD_REG_DBG_DWORD_ENABLE,
        XYLD_REG_DBG_SHIFT, XYLD_REG_DBG_FORCE_VALID,
        XYLD_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12
};

static struct block_defs block_ptld_defs = {
        "ptld",
        {false, false, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCT},
        PTLD_REG_DBG_SELECT_E5, PTLD_REG_DBG_DWORD_ENABLE_E5,
        PTLD_REG_DBG_SHIFT_E5, PTLD_REG_DBG_FORCE_VALID_E5,
        PTLD_REG_DBG_FORCE_FRAME_E5,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
        28
};

static struct block_defs block_ypld_defs = {
        "ypld",
        {false, false, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCS},
        YPLD_REG_DBG_SELECT_E5, YPLD_REG_DBG_DWORD_ENABLE_E5,
        YPLD_REG_DBG_SHIFT_E5, YPLD_REG_DBG_FORCE_VALID_E5,
        YPLD_REG_DBG_FORCE_FRAME_E5,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
        27
};

static struct block_defs block_prm_defs = {
        "prm",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
        PRM_REG_DBG_SELECT, PRM_REG_DBG_DWORD_ENABLE,
        PRM_REG_DBG_SHIFT, PRM_REG_DBG_FORCE_VALID,
        PRM_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 21
};

static struct block_defs block_pbf_pb1_defs = {
        "pbf_pb1",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
        PBF_PB1_REG_DBG_SELECT, PBF_PB1_REG_DBG_DWORD_ENABLE,
        PBF_PB1_REG_DBG_SHIFT, PBF_PB1_REG_DBG_FORCE_VALID,
        PBF_PB1_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
        11
};

static struct block_defs block_pbf_pb2_defs = {
        "pbf_pb2",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
        PBF_PB2_REG_DBG_SELECT, PBF_PB2_REG_DBG_DWORD_ENABLE,
        PBF_PB2_REG_DBG_SHIFT, PBF_PB2_REG_DBG_FORCE_VALID,
        PBF_PB2_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
        12
};

static struct block_defs block_rpb_defs = {
        "rpb",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
        RPB_REG_DBG_SELECT, RPB_REG_DBG_DWORD_ENABLE,
        RPB_REG_DBG_SHIFT, RPB_REG_DBG_FORCE_VALID,
        RPB_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 13
};

static struct block_defs block_btb_defs = {
        "btb",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
        BTB_REG_DBG_SELECT, BTB_REG_DBG_DWORD_ENABLE,
        BTB_REG_DBG_SHIFT, BTB_REG_DBG_FORCE_VALID,
        BTB_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 10
};

static struct block_defs block_pbf_defs = {
        "pbf",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
        PBF_REG_DBG_SELECT, PBF_REG_DBG_DWORD_ENABLE,
        PBF_REG_DBG_SHIFT, PBF_REG_DBG_FORCE_VALID,
        PBF_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 15
};

static struct block_defs block_rdif_defs = {
        "rdif",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
        RDIF_REG_DBG_SELECT, RDIF_REG_DBG_DWORD_ENABLE,
        RDIF_REG_DBG_SHIFT, RDIF_REG_DBG_FORCE_VALID,
        RDIF_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 16
};

static struct block_defs block_tdif_defs = {
        "tdif",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
        TDIF_REG_DBG_SELECT, TDIF_REG_DBG_DWORD_ENABLE,
        TDIF_REG_DBG_SHIFT, TDIF_REG_DBG_FORCE_VALID,
        TDIF_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 17
};

static struct block_defs block_cdu_defs = {
        "cdu",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
        CDU_REG_DBG_SELECT, CDU_REG_DBG_DWORD_ENABLE,
        CDU_REG_DBG_SHIFT, CDU_REG_DBG_FORCE_VALID,
        CDU_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 23
};

static struct block_defs block_ccfc_defs = {
        "ccfc",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
        CCFC_REG_DBG_SELECT, CCFC_REG_DBG_DWORD_ENABLE,
        CCFC_REG_DBG_SHIFT, CCFC_REG_DBG_FORCE_VALID,
        CCFC_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 24
};

static struct block_defs block_tcfc_defs = {
        "tcfc",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
        TCFC_REG_DBG_SELECT, TCFC_REG_DBG_DWORD_ENABLE,
        TCFC_REG_DBG_SHIFT, TCFC_REG_DBG_FORCE_VALID,
        TCFC_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 25
};

static struct block_defs block_igu_defs = {
        "igu",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        IGU_REG_DBG_SELECT, IGU_REG_DBG_DWORD_ENABLE,
        IGU_REG_DBG_SHIFT, IGU_REG_DBG_FORCE_VALID,
        IGU_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 27
};

static struct block_defs block_cau_defs = {
        "cau",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
        CAU_REG_DBG_SELECT, CAU_REG_DBG_DWORD_ENABLE,
        CAU_REG_DBG_SHIFT, CAU_REG_DBG_FORCE_VALID,
        CAU_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19
};

static struct block_defs block_rgfs_defs = {
        "rgfs", {false, false, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 29
};

static struct block_defs block_rgsrc_defs = {
        "rgsrc",
        {false, false, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
        RGSRC_REG_DBG_SELECT_E5, RGSRC_REG_DBG_DWORD_ENABLE_E5,
        RGSRC_REG_DBG_SHIFT_E5, RGSRC_REG_DBG_FORCE_VALID_E5,
        RGSRC_REG_DBG_FORCE_FRAME_E5,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
        30
};

static struct block_defs block_tgfs_defs = {
        "tgfs", {false, false, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 30
};

static struct block_defs block_tgsrc_defs = {
        "tgsrc",
        {false, false, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCV},
        TGSRC_REG_DBG_SELECT_E5, TGSRC_REG_DBG_DWORD_ENABLE_E5,
        TGSRC_REG_DBG_SHIFT_E5, TGSRC_REG_DBG_FORCE_VALID_E5,
        TGSRC_REG_DBG_FORCE_FRAME_E5,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
        31
};

static struct block_defs block_umac_defs = {
        "umac",
        {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ,
         DBG_BUS_CLIENT_RBCZ},
        UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5,
        UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5,
        UMAC_REG_DBG_FORCE_FRAME_K2_E5,
        true, false, DBG_RESET_REG_MISCS_PL_HV, 6
};

static struct block_defs block_xmac_defs = {
        "xmac", {true, false, false}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_dbg_defs = {
        "dbg", {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 3
};

static struct block_defs block_nig_defs = {
        "nig",
        {true, true, true}, false, 0,
        {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN},
        NIG_REG_DBG_SELECT, NIG_REG_DBG_DWORD_ENABLE,
        NIG_REG_DBG_SHIFT, NIG_REG_DBG_FORCE_VALID,
        NIG_REG_DBG_FORCE_FRAME,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 0
};

static struct block_defs block_wol_defs = {
        "wol",
        {false, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
        WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5,
        WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5,
        WOL_REG_DBG_FORCE_FRAME_K2_E5,
        true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7
};

static struct block_defs block_bmbn_defs = {
        "bmbn",
        {false, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB,
         DBG_BUS_CLIENT_RBCB},
        BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5,
        BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5,
        BMBN_REG_DBG_FORCE_FRAME_K2_E5,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_ipc_defs = {
        "ipc", {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        true, false, DBG_RESET_REG_MISCS_PL_UA, 8
};

static struct block_defs block_nwm_defs = {
        "nwm",
        {false, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW},
        NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5,
        NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5,
        NWM_REG_DBG_FORCE_FRAME_K2_E5,
        true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0
};

static struct block_defs block_nws_defs = {
        "nws",
        {false, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW},
        NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5,
        NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5,
        NWS_REG_DBG_FORCE_FRAME_K2_E5,
        true, false, DBG_RESET_REG_MISCS_PL_HV, 12
};

static struct block_defs block_ms_defs = {
        "ms",
        {false, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
        MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5,
        MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5,
        MS_REG_DBG_FORCE_FRAME_K2_E5,
        true, false, DBG_RESET_REG_MISCS_PL_HV, 13
};

static struct block_defs block_phy_pcie_defs = {
        "phy_pcie",
        {false, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
         DBG_BUS_CLIENT_RBCH},
        PCIE_REG_DBG_COMMON_SELECT_K2_E5,
        PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
        PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
        PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
        PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_led_defs = {
        "led", {false, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        true, false, DBG_RESET_REG_MISCS_PL_HV, 14
};

static struct block_defs block_avs_wrap_defs = {
        "avs_wrap", {false, true, false}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        true, false, DBG_RESET_REG_MISCS_PL_UA, 11
};

static struct block_defs block_pxpreqbus_defs = {
        "pxpreqbus", {false, false, false}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_misc_aeu_defs = {
        "misc_aeu", {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs block_bar0_map_defs = {
        "bar0_map", {true, true, true}, false, 0,
        {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
        0, 0, 0, 0, 0,
        false, false, MAX_DBG_RESET_REGS, 0
};

static struct block_defs *s_block_defs[MAX_BLOCK_ID] = {
        &block_grc_defs,
        &block_miscs_defs,
        &block_misc_defs,
        &block_dbu_defs,
        &block_pglue_b_defs,
        &block_cnig_defs,
        &block_cpmu_defs,
        &block_ncsi_defs,
        &block_opte_defs,
        &block_bmb_defs,
        &block_pcie_defs,
        &block_mcp_defs,
        &block_mcp2_defs,
        &block_pswhst_defs,
        &block_pswhst2_defs,
        &block_pswrd_defs,
        &block_pswrd2_defs,
        &block_pswwr_defs,
        &block_pswwr2_defs,
        &block_pswrq_defs,
        &block_pswrq2_defs,
        &block_pglcs_defs,
        &block_dmae_defs,
        &block_ptu_defs,
        &block_tcm_defs,
        &block_mcm_defs,
        &block_ucm_defs,
        &block_xcm_defs,
        &block_ycm_defs,
        &block_pcm_defs,
        &block_qm_defs,
        &block_tm_defs,
        &block_dorq_defs,
        &block_brb_defs,
        &block_src_defs,
        &block_prs_defs,
        &block_tsdm_defs,
        &block_msdm_defs,
        &block_usdm_defs,
        &block_xsdm_defs,
        &block_ysdm_defs,
        &block_psdm_defs,
        &block_tsem_defs,
        &block_msem_defs,
        &block_usem_defs,
        &block_xsem_defs,
        &block_ysem_defs,
        &block_psem_defs,
        &block_rss_defs,
        &block_tmld_defs,
        &block_muld_defs,
        &block_yuld_defs,
        &block_xyld_defs,
        &block_ptld_defs,
        &block_ypld_defs,
        &block_prm_defs,
        &block_pbf_pb1_defs,
        &block_pbf_pb2_defs,
        &block_rpb_defs,
        &block_btb_defs,
        &block_pbf_defs,
        &block_rdif_defs,
        &block_tdif_defs,
        &block_cdu_defs,
        &block_ccfc_defs,
        &block_tcfc_defs,
        &block_igu_defs,
        &block_cau_defs,
        &block_rgfs_defs,
        &block_rgsrc_defs,
        &block_tgfs_defs,
        &block_tgsrc_defs,
        &block_umac_defs,
        &block_xmac_defs,
        &block_dbg_defs,
        &block_nig_defs,
        &block_wol_defs,
        &block_bmbn_defs,
        &block_ipc_defs,
        &block_nwm_defs,
        &block_nws_defs,
        &block_ms_defs,
        &block_phy_pcie_defs,
        &block_led_defs,
        &block_avs_wrap_defs,
        &block_pxpreqbus_defs,
        &block_misc_aeu_defs,
        &block_bar0_map_defs,
};

static struct platform_defs s_platform_defs[] = {
        {"asic", 1, 256, 32768},
        {"reserved", 0, 0, 0},
        {"reserved2", 0, 0, 0},
        {"reserved3", 0, 0, 0}
};

static struct grc_param_defs s_grc_param_defs[] = {
        /* DBG_GRC_PARAM_DUMP_TSTORM */
        {{1, 1, 1}, 0, 1, false, false, 1, 1},

        /* DBG_GRC_PARAM_DUMP_MSTORM */
        {{1, 1, 1}, 0, 1, false, false, 1, 1},

        /* DBG_GRC_PARAM_DUMP_USTORM */
        {{1, 1, 1}, 0, 1, false, false, 1, 1},

        /* DBG_GRC_PARAM_DUMP_XSTORM */
        {{1, 1, 1}, 0, 1, false, false, 1, 1},

        /* DBG_GRC_PARAM_DUMP_YSTORM */
        {{1, 1, 1}, 0, 1, false, false, 1, 1},

        /* DBG_GRC_PARAM_DUMP_PSTORM */
        {{1, 1, 1}, 0, 1, false, false, 1, 1},

        /* DBG_GRC_PARAM_DUMP_REGS */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_RAM */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_PBUF */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_IOR */
        {{0, 0, 0}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_VFC */
        {{0, 0, 0}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_CM_CTX */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_ILT */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_RSS */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_CAU */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_QM */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_MCP */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_MCP_TRACE_META_SIZE */
        {{1, 1, 1}, 1, 0xffffffff, false, true, 0, 1},

        /* DBG_GRC_PARAM_DUMP_CFC */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_IGU */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_BRB */
        {{0, 0, 0}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_BTB */
        {{0, 0, 0}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_BMB */
        {{0, 0, 0}, 0, 1, false, false, 0, 0},

        /* DBG_GRC_PARAM_DUMP_NIG */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_MULD */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_PRS */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_DMAE */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_TM */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_SDM */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_DIF */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_STATIC */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_UNSTALL */
        {{0, 0, 0}, 0, 1, false, false, 0, 0},

        /* DBG_GRC_PARAM_NUM_LCIDS */
        {{MAX_LCIDS, MAX_LCIDS, MAX_LCIDS}, 1, MAX_LCIDS, false, false,
         MAX_LCIDS, MAX_LCIDS},

        /* DBG_GRC_PARAM_NUM_LTIDS */
        {{MAX_LTIDS, MAX_LTIDS, MAX_LTIDS}, 1, MAX_LTIDS, false, false,
         MAX_LTIDS, MAX_LTIDS},

        /* DBG_GRC_PARAM_EXCLUDE_ALL */
        {{0, 0, 0}, 0, 1, true, false, 0, 0},

        /* DBG_GRC_PARAM_CRASH */
        {{0, 0, 0}, 0, 1, true, false, 0, 0},

        /* DBG_GRC_PARAM_PARITY_SAFE */
        {{0, 0, 0}, 0, 1, false, false, 1, 0},

        /* DBG_GRC_PARAM_DUMP_CM */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_DUMP_PHY */
        {{1, 1, 1}, 0, 1, false, false, 0, 1},

        /* DBG_GRC_PARAM_NO_MCP */
        {{0, 0, 0}, 0, 1, false, false, 0, 0},

        /* DBG_GRC_PARAM_NO_FW_VER */
        {{0, 0, 0}, 0, 1, false, false, 0, 0}
};

static struct rss_mem_defs s_rss_mem_defs[] = {
        { "rss_mem_cid", "rss_cid", 0, 32,
          {256, 320, 512} },

        { "rss_mem_key_msb", "rss_key", 1024, 256,
          {128, 208, 257} },

        { "rss_mem_key_lsb", "rss_key", 2048, 64,
          {128, 208, 257} },

        { "rss_mem_info", "rss_info", 3072, 16,
          {128, 208, 256} },

        { "rss_mem_ind", "rss_ind", 4096, 16,
          {16384, 26624, 32768} }
};

static struct vfc_ram_defs s_vfc_ram_defs[] = {
        {"vfc_ram_tt1", "vfc_ram", 0, 512},
        {"vfc_ram_mtt2", "vfc_ram", 512, 128},
        {"vfc_ram_stt2", "vfc_ram", 640, 32},
        {"vfc_ram_ro_vect", "vfc_ram", 672, 32}
};

static struct big_ram_defs s_big_ram_defs[] = {
        { "BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB,
          BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA,
          MISC_REG_BLOCK_256B_EN, {0, 0, 0},
          {153600, 180224, 282624} },

        { "BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB,
          BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA,
          MISC_REG_BLOCK_256B_EN, {0, 1, 1},
          {92160, 117760, 168960} },

        { "BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB,
          BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA,
          MISCS_REG_BLOCK_256B_EN, {0, 0, 0},
          {36864, 36864, 36864} }
};

static struct reset_reg_defs s_reset_regs_defs[] = {
        /* DBG_RESET_REG_MISCS_PL_UA */
        { MISCS_REG_RESET_PL_UA,
          {true, true, true}, {0x0, 0x0, 0x0} },

        /* DBG_RESET_REG_MISCS_PL_HV */
        { MISCS_REG_RESET_PL_HV,
          {true, true, true}, {0x0, 0x400, 0x600} },

        /* DBG_RESET_REG_MISCS_PL_HV_2 */
        { MISCS_REG_RESET_PL_HV_2_K2_E5,
          {false, true, true}, {0x0, 0x0, 0x0} },

        /* DBG_RESET_REG_MISC_PL_UA */
        { MISC_REG_RESET_PL_UA,
          {true, true, true}, {0x0, 0x0, 0x0} },

        /* DBG_RESET_REG_MISC_PL_HV */
        { MISC_REG_RESET_PL_HV,
          {true, true, true}, {0x0, 0x0, 0x0} },

        /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_1 */
        { MISC_REG_RESET_PL_PDA_VMAIN_1,
          {true, true, true}, {0x4404040, 0x4404040, 0x404040} },

        /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_2 */
        { MISC_REG_RESET_PL_PDA_VMAIN_2,
          {true, true, true}, {0x7, 0x7c00007, 0x5c08007} },

        /* DBG_RESET_REG_MISC_PL_PDA_VAUX */
        { MISC_REG_RESET_PL_PDA_VAUX,
          {true, true, true}, {0x2, 0x2, 0x2} },
};

static struct phy_defs s_phy_defs[] = {
        {"nw_phy", NWS_REG_NWS_CMU_K2,
         PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5,
         PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5,
         PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5,
         PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5},
        {"sgmii_phy", MS_REG_MS_CMU_K2_E5,
         PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
         PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
         PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
         PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
        {"pcie_phy0", PHY_PCIE_REG_PHY0_K2_E5,
         PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
         PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
         PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
         PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
        {"pcie_phy1", PHY_PCIE_REG_PHY1_K2_E5,
         PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
         PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
         PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
         PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
};

static struct split_type_defs s_split_type_defs[] = {
        /* SPLIT_TYPE_NONE */
        {"eng"},

        /* SPLIT_TYPE_PORT */
        {"port"},

        /* SPLIT_TYPE_PF */
        {"pf"},

        /* SPLIT_TYPE_PORT_PF */
        {"port"},

        /* SPLIT_TYPE_VF */
        {"vf"}
};

/**************************** Private Functions ******************************/

/* Reads and returns a single dword from the specified unaligned buffer */
static u32 qed_read_unaligned_dword(u8 *buf)
{
        u32 dword;

        memcpy((u8 *)&dword, buf, sizeof(dword));
        return dword;
}

/* Sets the value of the specified GRC param */
static void qed_grc_set_param(struct qed_hwfn *p_hwfn,
                              enum dbg_grc_params grc_param, u32 val)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;

        dev_data->grc.param_val[grc_param] = val;
}

/* Returns the value of the specified GRC param */
static u32 qed_grc_get_param(struct qed_hwfn *p_hwfn,
                             enum dbg_grc_params grc_param)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;

        return dev_data->grc.param_val[grc_param];
}

/* Initializes the GRC parameters */
static void qed_dbg_grc_init_params(struct qed_hwfn *p_hwfn)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;

        if (!dev_data->grc.params_initialized) {
                qed_dbg_grc_set_params_default(p_hwfn);
                dev_data->grc.params_initialized = 1;
        }
}

/* Initializes debug data for the specified device */
static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn,
                                        struct qed_ptt *p_ptt)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u8 num_pfs = 0, max_pfs_per_port = 0;

        if (dev_data->initialized)
                return DBG_STATUS_OK;

        /* Set chip */
        if (QED_IS_K2(p_hwfn->cdev)) {
                dev_data->chip_id = CHIP_K2;
                dev_data->mode_enable[MODE_K2] = 1;
                dev_data->num_vfs = MAX_NUM_VFS_K2;
                num_pfs = MAX_NUM_PFS_K2;
                max_pfs_per_port = MAX_NUM_PFS_K2 / 2;
        } else if (QED_IS_BB_B0(p_hwfn->cdev)) {
                dev_data->chip_id = CHIP_BB;
                dev_data->mode_enable[MODE_BB] = 1;
                dev_data->num_vfs = MAX_NUM_VFS_BB;
                num_pfs = MAX_NUM_PFS_BB;
                max_pfs_per_port = MAX_NUM_PFS_BB;
        } else {
                return DBG_STATUS_UNKNOWN_CHIP;
        }

        /* Set platofrm */
        dev_data->platform_id = PLATFORM_ASIC;
        dev_data->mode_enable[MODE_ASIC] = 1;

        /* Set port mode */
        switch (qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE)) {
        case 0:
                dev_data->mode_enable[MODE_PORTS_PER_ENG_1] = 1;
                break;
        case 1:
                dev_data->mode_enable[MODE_PORTS_PER_ENG_2] = 1;
                break;
        case 2:
                dev_data->mode_enable[MODE_PORTS_PER_ENG_4] = 1;
                break;
        }

        /* Set 100G mode */
        if (dev_data->chip_id == CHIP_BB &&
            qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB) == 2)
                dev_data->mode_enable[MODE_100G] = 1;

        /* Set number of ports */
        if (dev_data->mode_enable[MODE_PORTS_PER_ENG_1] ||
            dev_data->mode_enable[MODE_100G])
                dev_data->num_ports = 1;
        else if (dev_data->mode_enable[MODE_PORTS_PER_ENG_2])
                dev_data->num_ports = 2;
        else if (dev_data->mode_enable[MODE_PORTS_PER_ENG_4])
                dev_data->num_ports = 4;

        /* Set number of PFs per port */
        dev_data->num_pfs_per_port = min_t(u32,
                                           num_pfs / dev_data->num_ports,
                                           max_pfs_per_port);

        /* Initializes the GRC parameters */
        qed_dbg_grc_init_params(p_hwfn);

        dev_data->use_dmae = true;
        dev_data->initialized = 1;

        return DBG_STATUS_OK;
}

static struct dbg_bus_block *get_dbg_bus_block_desc(struct qed_hwfn *p_hwfn,
                                                    enum block_id block_id)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;

        return (struct dbg_bus_block *)&dbg_bus_blocks[block_id *
                                                       MAX_CHIP_IDS +
                                                       dev_data->chip_id];
}

/* Reads the FW info structure for the specified Storm from the chip,
 * and writes it to the specified fw_info pointer.
 */
static void qed_read_storm_fw_info(struct qed_hwfn *p_hwfn,
                                   struct qed_ptt *p_ptt,
                                   u8 storm_id, struct fw_info *fw_info)
{
        struct storm_defs *storm = &s_storm_defs[storm_id];
        struct fw_info_location fw_info_location;
        u32 addr, i, *dest;

        memset(&fw_info_location, 0, sizeof(fw_info_location));
        memset(fw_info, 0, sizeof(*fw_info));

        /* Read first the address that points to fw_info location.
         * The address is located in the last line of the Storm RAM.
         */
        addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM +
               DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_BB_K2) -
               sizeof(fw_info_location);
        dest = (u32 *)&fw_info_location;

        for (i = 0; i < BYTES_TO_DWORDS(sizeof(fw_info_location));
             i++, addr += BYTES_IN_DWORD)
                dest[i] = qed_rd(p_hwfn, p_ptt, addr);

        /* Read FW version info from Storm RAM */
        if (fw_info_location.size > 0 && fw_info_location.size <=
            sizeof(*fw_info)) {
                addr = fw_info_location.grc_addr;
                dest = (u32 *)fw_info;
                for (i = 0; i < BYTES_TO_DWORDS(fw_info_location.size);
                     i++, addr += BYTES_IN_DWORD)
                        dest[i] = qed_rd(p_hwfn, p_ptt, addr);
        }
}

/* Dumps the specified string to the specified buffer.
 * Returns the dumped size in bytes.
 */
static u32 qed_dump_str(char *dump_buf, bool dump, const char *str)
{
        if (dump)
                strcpy(dump_buf, str);

        return (u32)strlen(str) + 1;
}

/* Dumps zeros to align the specified buffer to dwords.
 * Returns the dumped size in bytes.
 */
static u32 qed_dump_align(char *dump_buf, bool dump, u32 byte_offset)
{
        u8 offset_in_dword, align_size;

        offset_in_dword = (u8)(byte_offset & 0x3);
        align_size = offset_in_dword ? BYTES_IN_DWORD - offset_in_dword : 0;

        if (dump && align_size)
                memset(dump_buf, 0, align_size);

        return align_size;
}

/* Writes the specified string param to the specified buffer.
 * Returns the dumped size in dwords.
 */
static u32 qed_dump_str_param(u32 *dump_buf,
                              bool dump,
                              const char *param_name, const char *param_val)
{
        char *char_buf = (char *)dump_buf;
        u32 offset = 0;

        /* Dump param name */
        offset += qed_dump_str(char_buf + offset, dump, param_name);

        /* Indicate a string param value */
        if (dump)
                *(char_buf + offset) = 1;
        offset++;

        /* Dump param value */
        offset += qed_dump_str(char_buf + offset, dump, param_val);

        /* Align buffer to next dword */
        offset += qed_dump_align(char_buf + offset, dump, offset);

        return BYTES_TO_DWORDS(offset);
}

/* Writes the specified numeric param to the specified buffer.
 * Returns the dumped size in dwords.
 */
static u32 qed_dump_num_param(u32 *dump_buf,
                              bool dump, const char *param_name, u32 param_val)
{
        char *char_buf = (char *)dump_buf;
        u32 offset = 0;

        /* Dump param name */
        offset += qed_dump_str(char_buf + offset, dump, param_name);

        /* Indicate a numeric param value */
        if (dump)
                *(char_buf + offset) = 0;
        offset++;

        /* Align buffer to next dword */
        offset += qed_dump_align(char_buf + offset, dump, offset);

        /* Dump param value (and change offset from bytes to dwords) */
        offset = BYTES_TO_DWORDS(offset);
        if (dump)
                *(dump_buf + offset) = param_val;
        offset++;

        return offset;
}

/* Reads the FW version and writes it as a param to the specified buffer.
 * Returns the dumped size in dwords.
 */
static u32 qed_dump_fw_ver_param(struct qed_hwfn *p_hwfn,
                                 struct qed_ptt *p_ptt,
                                 u32 *dump_buf, bool dump)
{
        char fw_ver_str[16] = EMPTY_FW_VERSION_STR;
        char fw_img_str[16] = EMPTY_FW_IMAGE_STR;
        struct fw_info fw_info = { {0}, {0} };
        u32 offset = 0;

        if (dump && !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) {
                /* Read FW info from chip */
                qed_read_fw_info(p_hwfn, p_ptt, &fw_info);

                /* Create FW version/image strings */
                if (snprintf(fw_ver_str, sizeof(fw_ver_str),
                             "%d_%d_%d_%d", fw_info.ver.num.major,
                             fw_info.ver.num.minor, fw_info.ver.num.rev,
                             fw_info.ver.num.eng) < 0)
                        DP_NOTICE(p_hwfn,
                                  "Unexpected debug error: invalid FW version string\n");
                switch (fw_info.ver.image_id) {
                case FW_IMG_MAIN:
                        strcpy(fw_img_str, "main");
                        break;
                default:
                        strcpy(fw_img_str, "unknown");
                        break;
                }
        }

        /* Dump FW version, image and timestamp */
        offset += qed_dump_str_param(dump_buf + offset,
                                     dump, "fw-version", fw_ver_str);
        offset += qed_dump_str_param(dump_buf + offset,
                                     dump, "fw-image", fw_img_str);
        offset += qed_dump_num_param(dump_buf + offset,
                                     dump,
                                     "fw-timestamp", fw_info.ver.timestamp);

        return offset;
}

/* Reads the MFW version and writes it as a param to the specified buffer.
 * Returns the dumped size in dwords.
 */
static u32 qed_dump_mfw_ver_param(struct qed_hwfn *p_hwfn,
                                  struct qed_ptt *p_ptt,
                                  u32 *dump_buf, bool dump)
{
        char mfw_ver_str[16] = EMPTY_FW_VERSION_STR;

        if (dump &&
            !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) {
                u32 global_section_offsize, global_section_addr, mfw_ver;
                u32 public_data_addr, global_section_offsize_addr;

                /* Find MCP public data GRC address. Needs to be ORed with
                 * MCP_REG_SCRATCH due to a HW bug.
                 */
                public_data_addr = qed_rd(p_hwfn,
                                          p_ptt,
                                          MISC_REG_SHARED_MEM_ADDR) |
                                   MCP_REG_SCRATCH;

                /* Find MCP public global section offset */
                global_section_offsize_addr = public_data_addr +
                                              offsetof(struct mcp_public_data,
                                                       sections) +
                                              sizeof(offsize_t) * PUBLIC_GLOBAL;
                global_section_offsize = qed_rd(p_hwfn, p_ptt,
                                                global_section_offsize_addr);
                global_section_addr =
                        MCP_REG_SCRATCH +
                        (global_section_offsize & OFFSIZE_OFFSET_MASK) * 4;

                /* Read MFW version from MCP public global section */
                mfw_ver = qed_rd(p_hwfn, p_ptt,
                                 global_section_addr +
                                 offsetof(struct public_global, mfw_ver));

                /* Dump MFW version param */
                if (snprintf(mfw_ver_str, sizeof(mfw_ver_str), "%d_%d_%d_%d",
                             (u8)(mfw_ver >> 24), (u8)(mfw_ver >> 16),
                             (u8)(mfw_ver >> 8), (u8)mfw_ver) < 0)
                        DP_NOTICE(p_hwfn,
                                  "Unexpected debug error: invalid MFW version string\n");
        }

        return qed_dump_str_param(dump_buf, dump, "mfw-version", mfw_ver_str);
}

/* Writes a section header to the specified buffer.
 * Returns the dumped size in dwords.
 */
static u32 qed_dump_section_hdr(u32 *dump_buf,
                                bool dump, const char *name, u32 num_params)
{
        return qed_dump_num_param(dump_buf, dump, name, num_params);
}

/* Writes the common global params to the specified buffer.
 * Returns the dumped size in dwords.
 */
static u32 qed_dump_common_global_params(struct qed_hwfn *p_hwfn,
                                         struct qed_ptt *p_ptt,
                                         u32 *dump_buf,
                                         bool dump,
                                         u8 num_specific_global_params)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u32 offset = 0;
        u8 num_params;

        /* Dump global params section header */
        num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params;
        offset += qed_dump_section_hdr(dump_buf + offset,
                                       dump, "global_params", num_params);

        /* Store params */
        offset += qed_dump_fw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump);
        offset += qed_dump_mfw_ver_param(p_hwfn,
                                         p_ptt, dump_buf + offset, dump);
        offset += qed_dump_num_param(dump_buf + offset,
                                     dump, "tools-version", TOOLS_VERSION);
        offset += qed_dump_str_param(dump_buf + offset,
                                     dump,
                                     "chip",
                                     s_chip_defs[dev_data->chip_id].name);
        offset += qed_dump_str_param(dump_buf + offset,
                                     dump,
                                     "platform",
                                     s_platform_defs[dev_data->platform_id].
                                     name);
        offset +=
            qed_dump_num_param(dump_buf + offset, dump, "pci-func",
                               p_hwfn->abs_pf_id);

        return offset;
}

/* Writes the "last" section (including CRC) to the specified buffer at the
 * given offset. Returns the dumped size in dwords.
 */
static u32 qed_dump_last_section(u32 *dump_buf, u32 offset, bool dump)
{
        u32 start_offset = offset;

        /* Dump CRC section header */
        offset += qed_dump_section_hdr(dump_buf + offset, dump, "last", 0);

        /* Calculate CRC32 and add it to the dword after the "last" section */
        if (dump)
                *(dump_buf + offset) = ~crc32(0xffffffff,
                                              (u8 *)dump_buf,
                                              DWORDS_TO_BYTES(offset));

        offset++;

        return offset - start_offset;
}

/* Update blocks reset state  */
static void qed_update_blocks_reset_state(struct qed_hwfn *p_hwfn,
                                          struct qed_ptt *p_ptt)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
        u32 i;

        /* Read reset registers */
        for (i = 0; i < MAX_DBG_RESET_REGS; i++)
                if (s_reset_regs_defs[i].exists[dev_data->chip_id])
                        reg_val[i] = qed_rd(p_hwfn,
                                            p_ptt, s_reset_regs_defs[i].addr);

        /* Check if blocks are in reset */
        for (i = 0; i < MAX_BLOCK_ID; i++) {
                struct block_defs *block = s_block_defs[i];

                dev_data->block_in_reset[i] = block->has_reset_bit &&
                    !(reg_val[block->reset_reg] & BIT(block->reset_bit_offset));
        }
}

/* Enable / disable the Debug block */
static void qed_bus_enable_dbg_block(struct qed_hwfn *p_hwfn,
                                     struct qed_ptt *p_ptt, bool enable)
{
        qed_wr(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON, enable ? 1 : 0);
}

/* Resets the Debug block */
static void qed_bus_reset_dbg_block(struct qed_hwfn *p_hwfn,
                                    struct qed_ptt *p_ptt)
{
        u32 dbg_reset_reg_addr, old_reset_reg_val, new_reset_reg_val;
        struct block_defs *dbg_block = s_block_defs[BLOCK_DBG];

        dbg_reset_reg_addr = s_reset_regs_defs[dbg_block->reset_reg].addr;
        old_reset_reg_val = qed_rd(p_hwfn, p_ptt, dbg_reset_reg_addr);
        new_reset_reg_val =
            old_reset_reg_val & ~BIT(dbg_block->reset_bit_offset);

        qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, new_reset_reg_val);
        qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, old_reset_reg_val);
}

static void qed_bus_set_framing_mode(struct qed_hwfn *p_hwfn,
                                     struct qed_ptt *p_ptt,
                                     enum dbg_bus_frame_modes mode)
{
        qed_wr(p_hwfn, p_ptt, DBG_REG_FRAMING_MODE, (u8)mode);
}

/* Enable / disable Debug Bus clients according to the specified mask
 * (1 = enable, 0 = disable).
 */
static void qed_bus_enable_clients(struct qed_hwfn *p_hwfn,
                                   struct qed_ptt *p_ptt, u32 client_mask)
{
        qed_wr(p_hwfn, p_ptt, DBG_REG_CLIENT_ENABLE, client_mask);
}

static bool qed_is_mode_match(struct qed_hwfn *p_hwfn, u16 *modes_buf_offset)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        bool arg1, arg2;
        const u32 *ptr;
        u8 tree_val;

        /* Get next element from modes tree buffer */
        ptr = s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr;
        tree_val = ((u8 *)ptr)[(*modes_buf_offset)++];

        switch (tree_val) {
        case INIT_MODE_OP_NOT:
                return !qed_is_mode_match(p_hwfn, modes_buf_offset);
        case INIT_MODE_OP_OR:
        case INIT_MODE_OP_AND:
                arg1 = qed_is_mode_match(p_hwfn, modes_buf_offset);
                arg2 = qed_is_mode_match(p_hwfn, modes_buf_offset);
                return (tree_val == INIT_MODE_OP_OR) ? (arg1 ||
                                                        arg2) : (arg1 && arg2);
        default:
                return dev_data->mode_enable[tree_val - MAX_INIT_MODE_OPS] > 0;
        }
}

/* Returns true if the specified entity (indicated by GRC param) should be
 * included in the dump, false otherwise.
 */
static bool qed_grc_is_included(struct qed_hwfn *p_hwfn,
                                enum dbg_grc_params grc_param)
{
        return qed_grc_get_param(p_hwfn, grc_param) > 0;
}

/* Returns true of the specified Storm should be included in the dump, false
 * otherwise.
 */
static bool qed_grc_is_storm_included(struct qed_hwfn *p_hwfn,
                                      enum dbg_storms storm)
{
        return qed_grc_get_param(p_hwfn, (enum dbg_grc_params)storm) > 0;
}

/* Returns true if the specified memory should be included in the dump, false
 * otherwise.
 */
static bool qed_grc_is_mem_included(struct qed_hwfn *p_hwfn,
                                    enum block_id block_id, u8 mem_group_id)
{
        struct block_defs *block = s_block_defs[block_id];
        u8 i;

        /* Check Storm match */
        if (block->associated_to_storm &&
            !qed_grc_is_storm_included(p_hwfn,
                                       (enum dbg_storms)block->storm_id))
                return false;

        for (i = 0; i < NUM_BIG_RAM_TYPES; i++) {
                struct big_ram_defs *big_ram = &s_big_ram_defs[i];

                if (mem_group_id == big_ram->mem_group_id ||
                    mem_group_id == big_ram->ram_mem_group_id)
                        return qed_grc_is_included(p_hwfn, big_ram->grc_param);
        }

        switch (mem_group_id) {
        case MEM_GROUP_PXP_ILT:
        case MEM_GROUP_PXP_MEM:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PXP);
        case MEM_GROUP_RAM:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RAM);
        case MEM_GROUP_PBUF:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PBUF);
        case MEM_GROUP_CAU_MEM:
        case MEM_GROUP_CAU_SB:
        case MEM_GROUP_CAU_PI:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CAU);
        case MEM_GROUP_QM_MEM:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_QM);
        case MEM_GROUP_CFC_MEM:
        case MEM_GROUP_CONN_CFC_MEM:
        case MEM_GROUP_TASK_CFC_MEM:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CFC) ||
                       qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX);
        case MEM_GROUP_IGU_MEM:
        case MEM_GROUP_IGU_MSIX:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IGU);
        case MEM_GROUP_MULD_MEM:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MULD);
        case MEM_GROUP_PRS_MEM:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PRS);
        case MEM_GROUP_DMAE_MEM:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DMAE);
        case MEM_GROUP_TM_MEM:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_TM);
        case MEM_GROUP_SDM_MEM:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_SDM);
        case MEM_GROUP_TDIF_CTX:
        case MEM_GROUP_RDIF_CTX:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DIF);
        case MEM_GROUP_CM_MEM:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM);
        case MEM_GROUP_IOR:
                return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR);
        default:
                return true;
        }
}

/* Stalls all Storms */
static void qed_grc_stall_storms(struct qed_hwfn *p_hwfn,
                                 struct qed_ptt *p_ptt, bool stall)
{
        u32 reg_addr;
        u8 storm_id;

        for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
                if (!qed_grc_is_storm_included(p_hwfn,
                                               (enum dbg_storms)storm_id))
                        continue;

                reg_addr = s_storm_defs[storm_id].sem_fast_mem_addr +
                    SEM_FAST_REG_STALL_0_BB_K2;
                qed_wr(p_hwfn, p_ptt, reg_addr, stall ? 1 : 0);
        }

        msleep(STALL_DELAY_MS);
}

/* Takes all blocks out of reset */
static void qed_grc_unreset_blocks(struct qed_hwfn *p_hwfn,
                                   struct qed_ptt *p_ptt)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
        u32 block_id, i;

        /* Fill reset regs values */
        for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
                struct block_defs *block = s_block_defs[block_id];

                if (block->exists[dev_data->chip_id] && block->has_reset_bit &&
                    block->unreset)
                        reg_val[block->reset_reg] |=
                            BIT(block->reset_bit_offset);
        }

        /* Write reset registers */
        for (i = 0; i < MAX_DBG_RESET_REGS; i++) {
                if (!s_reset_regs_defs[i].exists[dev_data->chip_id])
                        continue;

                reg_val[i] |=
                        s_reset_regs_defs[i].unreset_val[dev_data->chip_id];

                if (reg_val[i])
                        qed_wr(p_hwfn,
                               p_ptt,
                               s_reset_regs_defs[i].addr +
                               RESET_REG_UNRESET_OFFSET, reg_val[i]);
        }
}

/* Returns the attention block data of the specified block */
static const struct dbg_attn_block_type_data *
qed_get_block_attn_data(enum block_id block_id, enum dbg_attn_type attn_type)
{
        const struct dbg_attn_block *base_attn_block_arr =
                (const struct dbg_attn_block *)
                s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr;

        return &base_attn_block_arr[block_id].per_type_data[attn_type];
}

/* Returns the attention registers of the specified block */
static const struct dbg_attn_reg *
qed_get_block_attn_regs(enum block_id block_id, enum dbg_attn_type attn_type,
                        u8 *num_attn_regs)
{
        const struct dbg_attn_block_type_data *block_type_data =
                qed_get_block_attn_data(block_id, attn_type);

        *num_attn_regs = block_type_data->num_regs;

        return &((const struct dbg_attn_reg *)
                 s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)[block_type_data->
                                                          regs_offset];
}

/* For each block, clear the status of all parities */
static void qed_grc_clear_all_prty(struct qed_hwfn *p_hwfn,
                                   struct qed_ptt *p_ptt)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        const struct dbg_attn_reg *attn_reg_arr;
        u8 reg_idx, num_attn_regs;
        u32 block_id;

        for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
                if (dev_data->block_in_reset[block_id])
                        continue;

                attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id,
                                                       ATTN_TYPE_PARITY,
                                                       &num_attn_regs);

                for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) {
                        const struct dbg_attn_reg *reg_data =
                                &attn_reg_arr[reg_idx];
                        u16 modes_buf_offset;
                        bool eval_mode;

                        /* Check mode */
                        eval_mode = GET_FIELD(reg_data->mode.data,
                                              DBG_MODE_HDR_EVAL_MODE) > 0;
                        modes_buf_offset =
                                GET_FIELD(reg_data->mode.data,
                                          DBG_MODE_HDR_MODES_BUF_OFFSET);

                        /* If Mode match: clear parity status */
                        if (!eval_mode ||
                            qed_is_mode_match(p_hwfn, &modes_buf_offset))
                                qed_rd(p_hwfn, p_ptt,
                                       DWORDS_TO_BYTES(reg_data->
                                                       sts_clr_address));
                }
        }
}

/* Dumps GRC registers section header. Returns the dumped size in dwords.
 * The following parameters are dumped:
 * - count: no. of dumped entries
 * - split_type: split type
 * - split_id: split ID (dumped only if split_id != SPLIT_TYPE_NONE)
 * - param_name: user parameter value (dumped only if param_name != NULL
 *               and param_val != NULL).
 */
static u32 qed_grc_dump_regs_hdr(u32 *dump_buf,
                                 bool dump,
                                 u32 num_reg_entries,
                                 enum init_split_types split_type,
                                 u8 split_id,
                                 const char *param_name, const char *param_val)
{
        u8 num_params = 2 +
            (split_type != SPLIT_TYPE_NONE ? 1 : 0) + (param_name ? 1 : 0);
        u32 offset = 0;

        offset += qed_dump_section_hdr(dump_buf + offset,
                                       dump, "grc_regs", num_params);
        offset += qed_dump_num_param(dump_buf + offset,
                                     dump, "count", num_reg_entries);
        offset += qed_dump_str_param(dump_buf + offset,
                                     dump, "split",
                                     s_split_type_defs[split_type].name);
        if (split_type != SPLIT_TYPE_NONE)
                offset += qed_dump_num_param(dump_buf + offset,
                                             dump, "id", split_id);
        if (param_name && param_val)
                offset += qed_dump_str_param(dump_buf + offset,
                                             dump, param_name, param_val);

        return offset;
}

/* Reads the specified registers into the specified buffer.
 * The addr and len arguments are specified in dwords.
 */
void qed_read_regs(struct qed_hwfn *p_hwfn,
                   struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len)
{
        u32 i;

        for (i = 0; i < len; i++)
                buf[i] = qed_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr + i));
}

/* Dumps the GRC registers in the specified address range.
 * Returns the dumped size in dwords.
 * The addr and len arguments are specified in dwords.
 */
static u32 qed_grc_dump_addr_range(struct qed_hwfn *p_hwfn,
                                   struct qed_ptt *p_ptt,
                                   u32 *dump_buf,
                                   bool dump, u32 addr, u32 len, bool wide_bus,
                                   enum init_split_types split_type,
                                   u8 split_id)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u8 port_id = 0, pf_id = 0, vf_id = 0, fid = 0;

        if (!dump)
                return len;

        /* Print log if needed */
        dev_data->num_regs_read += len;
        if (dev_data->num_regs_read >=
            s_platform_defs[dev_data->platform_id].log_thresh) {
                DP_VERBOSE(p_hwfn,
                           QED_MSG_DEBUG,
                           "Dumping %d registers...\n",
                           dev_data->num_regs_read);
                dev_data->num_regs_read = 0;
        }

        switch (split_type) {
        case SPLIT_TYPE_PORT:
                port_id = split_id;
                break;
        case SPLIT_TYPE_PF:
                pf_id = split_id;
                break;
        case SPLIT_TYPE_PORT_PF:
                port_id = split_id / dev_data->num_pfs_per_port;
                pf_id = port_id + dev_data->num_ports *
                    (split_id % dev_data->num_pfs_per_port);
                break;
        case SPLIT_TYPE_VF:
                vf_id = split_id;
                break;
        default:
                break;
        }

        /* Try reading using DMAE */
        if (dev_data->use_dmae && split_type == SPLIT_TYPE_NONE &&
            (len >= s_platform_defs[dev_data->platform_id].dmae_thresh ||
             wide_bus)) {
                if (!qed_dmae_grc2host(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr),
                                       (u64)(uintptr_t)(dump_buf), len, NULL))
                        return len;
                dev_data->use_dmae = 0;
                DP_VERBOSE(p_hwfn,
                           QED_MSG_DEBUG,
                           "Failed reading from chip using DMAE, using GRC instead\n");
        }

        /* If not read using DMAE, read using GRC */

        /* Set pretend */
        if (split_type != dev_data->pretend.split_type || split_id !=
            dev_data->pretend.split_id) {
                switch (split_type) {
                case SPLIT_TYPE_PORT:
                        qed_port_pretend(p_hwfn, p_ptt, port_id);
                        break;
                case SPLIT_TYPE_PF:
                        fid = pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT;
                        qed_fid_pretend(p_hwfn, p_ptt, fid);
                        break;
                case SPLIT_TYPE_PORT_PF:
                        fid = pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT;
                        qed_port_fid_pretend(p_hwfn, p_ptt, port_id, fid);
                        break;
                case SPLIT_TYPE_VF:
                        fid = BIT(PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT) |
                              (vf_id << PXP_PRETEND_CONCRETE_FID_VFID_SHIFT);
                        qed_fid_pretend(p_hwfn, p_ptt, fid);
                        break;
                default:
                        break;
                }

                dev_data->pretend.split_type = (u8)split_type;
                dev_data->pretend.split_id = split_id;
        }

        /* Read registers using GRC */
        qed_read_regs(p_hwfn, p_ptt, dump_buf, addr, len);

        return len;
}

/* Dumps GRC registers sequence header. Returns the dumped size in dwords.
 * The addr and len arguments are specified in dwords.
 */
static u32 qed_grc_dump_reg_entry_hdr(u32 *dump_buf,
                                      bool dump, u32 addr, u32 len)
{
        if (dump)
                *dump_buf = addr | (len << REG_DUMP_LEN_SHIFT);

        return 1;
}

/* Dumps GRC registers sequence. Returns the dumped size in dwords.
 * The addr and len arguments are specified in dwords.
 */
static u32 qed_grc_dump_reg_entry(struct qed_hwfn *p_hwfn,
                                  struct qed_ptt *p_ptt,
                                  u32 *dump_buf,
                                  bool dump, u32 addr, u32 len, bool wide_bus,
                                  enum init_split_types split_type, u8 split_id)
{
        u32 offset = 0;

        offset += qed_grc_dump_reg_entry_hdr(dump_buf, dump, addr, len);
        offset += qed_grc_dump_addr_range(p_hwfn,
                                          p_ptt,
                                          dump_buf + offset,
                                          dump, addr, len, wide_bus,
                                          split_type, split_id);

        return offset;
}

/* Dumps GRC registers sequence with skip cycle.
 * Returns the dumped size in dwords.
 * - addr:      start GRC address in dwords
 * - total_len: total no. of dwords to dump
 * - read_len:  no. consecutive dwords to read
 * - skip_len:  no. of dwords to skip (and fill with zeros)
 */
static u32 qed_grc_dump_reg_entry_skip(struct qed_hwfn *p_hwfn,
                                       struct qed_ptt *p_ptt,
                                       u32 *dump_buf,
                                       bool dump,
                                       u32 addr,
                                       u32 total_len,
                                       u32 read_len, u32 skip_len)
{
        u32 offset = 0, reg_offset = 0;

        offset += qed_grc_dump_reg_entry_hdr(dump_buf, dump, addr, total_len);

        if (!dump)
                return offset + total_len;

        while (reg_offset < total_len) {
                u32 curr_len = min_t(u32, read_len, total_len - reg_offset);

                offset += qed_grc_dump_addr_range(p_hwfn,
                                                  p_ptt,
                                                  dump_buf + offset,
                                                  dump,  addr, curr_len, false,
                                                  SPLIT_TYPE_NONE, 0);
                reg_offset += curr_len;
                addr += curr_len;

                if (reg_offset < total_len) {
                        curr_len = min_t(u32, skip_len, total_len - skip_len);
                        memset(dump_buf + offset, 0, DWORDS_TO_BYTES(curr_len));
                        offset += curr_len;
                        reg_offset += curr_len;
                        addr += curr_len;
                }
        }

        return offset;
}

/* Dumps GRC registers entries. Returns the dumped size in dwords. */
static u32 qed_grc_dump_regs_entries(struct qed_hwfn *p_hwfn,
                                     struct qed_ptt *p_ptt,
                                     struct dbg_array input_regs_arr,
                                     u32 *dump_buf,
                                     bool dump,
                                     enum init_split_types split_type,
                                     u8 split_id,
                                     bool block_enable[MAX_BLOCK_ID],
                                     u32 *num_dumped_reg_entries)
{
        u32 i, offset = 0, input_offset = 0;
        bool mode_match = true;

        *num_dumped_reg_entries = 0;

        while (input_offset < input_regs_arr.size_in_dwords) {
                const struct dbg_dump_cond_hdr *cond_hdr =
                    (const struct dbg_dump_cond_hdr *)
                    &input_regs_arr.ptr[input_offset++];
                u16 modes_buf_offset;
                bool eval_mode;

                /* Check mode/block */
                eval_mode = GET_FIELD(cond_hdr->mode.data,
                                      DBG_MODE_HDR_EVAL_MODE) > 0;
                if (eval_mode) {
                        modes_buf_offset =
                                GET_FIELD(cond_hdr->mode.data,
                                          DBG_MODE_HDR_MODES_BUF_OFFSET);
                        mode_match = qed_is_mode_match(p_hwfn,
                                                       &modes_buf_offset);
                }

                if (!mode_match || !block_enable[cond_hdr->block_id]) {
                        input_offset += cond_hdr->data_size;
                        continue;
                }

                for (i = 0; i < cond_hdr->data_size; i++, input_offset++) {
                        const struct dbg_dump_reg *reg =
                            (const struct dbg_dump_reg *)
                            &input_regs_arr.ptr[input_offset];
                        u32 addr, len;
                        bool wide_bus;

                        addr = GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS);
                        len = GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH);
                        wide_bus = GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS);
                        offset += qed_grc_dump_reg_entry(p_hwfn,
                                                         p_ptt,
                                                         dump_buf + offset,
                                                         dump,
                                                         addr,
                                                         len,
                                                         wide_bus,
                                                         split_type, split_id);
                        (*num_dumped_reg_entries)++;
                }
        }

        return offset;
}

/* Dumps GRC registers entries. Returns the dumped size in dwords. */
static u32 qed_grc_dump_split_data(struct qed_hwfn *p_hwfn,
                                   struct qed_ptt *p_ptt,
                                   struct dbg_array input_regs_arr,
                                   u32 *dump_buf,
                                   bool dump,
                                   bool block_enable[MAX_BLOCK_ID],
                                   enum init_split_types split_type,
                                   u8 split_id,
                                   const char *param_name,
                                   const char *param_val)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        enum init_split_types hdr_split_type = split_type;
        u32 num_dumped_reg_entries, offset;
        u8 hdr_split_id = split_id;

        /* In PORT_PF split type, print a port split header */
        if (split_type == SPLIT_TYPE_PORT_PF) {
                hdr_split_type = SPLIT_TYPE_PORT;
                hdr_split_id = split_id / dev_data->num_pfs_per_port;
        }

        /* Calculate register dump header size (and skip it for now) */
        offset = qed_grc_dump_regs_hdr(dump_buf,
                                       false,
                                       0,
                                       hdr_split_type,
                                       hdr_split_id, param_name, param_val);

        /* Dump registers */
        offset += qed_grc_dump_regs_entries(p_hwfn,
                                            p_ptt,
                                            input_regs_arr,
                                            dump_buf + offset,
                                            dump,
                                            split_type,
                                            split_id,
                                            block_enable,
                                            &num_dumped_reg_entries);

        /* Write register dump header */
        if (dump && num_dumped_reg_entries > 0)
                qed_grc_dump_regs_hdr(dump_buf,
                                      dump,
                                      num_dumped_reg_entries,
                                      hdr_split_type,
                                      hdr_split_id, param_name, param_val);

        return num_dumped_reg_entries > 0 ? offset : 0;
}

/* Dumps registers according to the input registers array. Returns the dumped
 * size in dwords.
 */
static u32 qed_grc_dump_registers(struct qed_hwfn *p_hwfn,
                                  struct qed_ptt *p_ptt,
                                  u32 *dump_buf,
                                  bool dump,
                                  bool block_enable[MAX_BLOCK_ID],
                                  const char *param_name, const char *param_val)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u32 offset = 0, input_offset = 0;
        u16 fid;
        while (input_offset <
               s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].size_in_dwords) {
                const struct dbg_dump_split_hdr *split_hdr;
                struct dbg_array curr_input_regs_arr;
                enum init_split_types split_type;
                u16 split_count = 0;
                u32 split_data_size;
                u8 split_id;

                split_hdr =
                        (const struct dbg_dump_split_hdr *)
                        &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset++];
                split_type =
                        GET_FIELD(split_hdr->hdr,
                                  DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
                split_data_size =
                        GET_FIELD(split_hdr->hdr,
                                  DBG_DUMP_SPLIT_HDR_DATA_SIZE);
                curr_input_regs_arr.ptr =
                        &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset];
                curr_input_regs_arr.size_in_dwords = split_data_size;

                switch (split_type) {
                case SPLIT_TYPE_NONE:
                        split_count = 1;
                        break;
                case SPLIT_TYPE_PORT:
                        split_count = dev_data->num_ports;
                        break;
                case SPLIT_TYPE_PF:
                case SPLIT_TYPE_PORT_PF:
                        split_count = dev_data->num_ports *
                            dev_data->num_pfs_per_port;
                        break;
                case SPLIT_TYPE_VF:
                        split_count = dev_data->num_vfs;
                        break;
                default:
                        return 0;
                }

                for (split_id = 0; split_id < split_count; split_id++)
                        offset += qed_grc_dump_split_data(p_hwfn, p_ptt,
                                                          curr_input_regs_arr,
                                                          dump_buf + offset,
                                                          dump, block_enable,
                                                          split_type,
                                                          split_id,
                                                          param_name,
                                                          param_val);

                input_offset += split_data_size;
        }

        /* Cancel pretends (pretend to original PF) */
        if (dump) {
                fid = p_hwfn->rel_pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT;
                qed_fid_pretend(p_hwfn, p_ptt, fid);
                dev_data->pretend.split_type = SPLIT_TYPE_NONE;
                dev_data->pretend.split_id = 0;
        }

        return offset;
}

/* Dump reset registers. Returns the dumped size in dwords. */
static u32 qed_grc_dump_reset_regs(struct qed_hwfn *p_hwfn,
                                   struct qed_ptt *p_ptt,
                                   u32 *dump_buf, bool dump)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u32 i, offset = 0, num_regs = 0;

        /* Calculate header size */
        offset += qed_grc_dump_regs_hdr(dump_buf,
                                        false, 0,
                                        SPLIT_TYPE_NONE, 0, NULL, NULL);

        /* Write reset registers */
        for (i = 0; i < MAX_DBG_RESET_REGS; i++) {
                if (!s_reset_regs_defs[i].exists[dev_data->chip_id])
                        continue;

                offset += qed_grc_dump_reg_entry(p_hwfn,
                                                 p_ptt,
                                                 dump_buf + offset,
                                                 dump,
                                                 BYTES_TO_DWORDS
                                                 (s_reset_regs_defs[i].addr), 1,
                                                 false, SPLIT_TYPE_NONE, 0);
                num_regs++;
        }

        /* Write header */
        if (dump)
                qed_grc_dump_regs_hdr(dump_buf,
                                      true, num_regs, SPLIT_TYPE_NONE,
                                      0, NULL, NULL);

        return offset;
}

/* Dump registers that are modified during GRC Dump and therefore must be
 * dumped first. Returns the dumped size in dwords.
 */
static u32 qed_grc_dump_modified_regs(struct qed_hwfn *p_hwfn,
                                      struct qed_ptt *p_ptt,
                                      u32 *dump_buf, bool dump)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u32 block_id, offset = 0, num_reg_entries = 0;
        const struct dbg_attn_reg *attn_reg_arr;
        u8 storm_id, reg_idx, num_attn_regs;

        /* Calculate header size */
        offset += qed_grc_dump_regs_hdr(dump_buf,
                                        false, 0, SPLIT_TYPE_NONE,
                                        0, NULL, NULL);

        /* Write parity registers */
        for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
                if (dev_data->block_in_reset[block_id] && dump)
                        continue;

                attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id,
                                                       ATTN_TYPE_PARITY,
                                                       &num_attn_regs);

                for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) {
                        const struct dbg_attn_reg *reg_data =
                                &attn_reg_arr[reg_idx];
                        u16 modes_buf_offset;
                        bool eval_mode;
                        u32 addr;

                        /* Check mode */
                        eval_mode = GET_FIELD(reg_data->mode.data,
                                              DBG_MODE_HDR_EVAL_MODE) > 0;
                        modes_buf_offset =
                                GET_FIELD(reg_data->mode.data,
                                          DBG_MODE_HDR_MODES_BUF_OFFSET);
                        if (eval_mode &&
                            !qed_is_mode_match(p_hwfn, &modes_buf_offset))
                                continue;

                        /* Mode match: read & dump registers */
                        addr = reg_data->mask_address;
                        offset += qed_grc_dump_reg_entry(p_hwfn,
                                                         p_ptt,
                                                         dump_buf + offset,
                                                         dump,
                                                         addr,
                                                         1, false,
                                                         SPLIT_TYPE_NONE, 0);
                        addr = GET_FIELD(reg_data->data,
                                         DBG_ATTN_REG_STS_ADDRESS);
                        offset += qed_grc_dump_reg_entry(p_hwfn,
                                                         p_ptt,
                                                         dump_buf + offset,
                                                         dump,
                                                         addr,
                                                         1, false,
                                                         SPLIT_TYPE_NONE, 0);
                        num_reg_entries += 2;
                }
        }

        /* Write Storm stall status registers */
        for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
                struct storm_defs *storm = &s_storm_defs[storm_id];
                u32 addr;

                if (dev_data->block_in_reset[storm->block_id] && dump)
                        continue;

                addr =
                    BYTES_TO_DWORDS(s_storm_defs[storm_id].sem_fast_mem_addr +
                                    SEM_FAST_REG_STALLED);
                offset += qed_grc_dump_reg_entry(p_hwfn,
                                                 p_ptt,
                                                 dump_buf + offset,
                                                 dump,
                                                 addr,
                                                 1,
                                                 false, SPLIT_TYPE_NONE, 0);
                num_reg_entries++;
        }

        /* Write header */
        if (dump)
                qed_grc_dump_regs_hdr(dump_buf,
                                      true,
                                      num_reg_entries, SPLIT_TYPE_NONE,
                                      0, NULL, NULL);

        return offset;
}

/* Dumps registers that can't be represented in the debug arrays */
static u32 qed_grc_dump_special_regs(struct qed_hwfn *p_hwfn,
                                     struct qed_ptt *p_ptt,
                                     u32 *dump_buf, bool dump)
{
        u32 offset = 0, addr;

        offset += qed_grc_dump_regs_hdr(dump_buf,
                                        dump, 2, SPLIT_TYPE_NONE, 0,
                                        NULL, NULL);

        /* Dump R/TDIF_REG_DEBUG_ERROR_INFO_SIZE (every 8'th register should be
         * skipped).
         */
        addr = BYTES_TO_DWORDS(RDIF_REG_DEBUG_ERROR_INFO);
        offset += qed_grc_dump_reg_entry_skip(p_hwfn,
                                              p_ptt,
                                              dump_buf + offset,
                                              dump,
                                              addr,
                                              RDIF_REG_DEBUG_ERROR_INFO_SIZE,
                                              7,
                                              1);
        addr = BYTES_TO_DWORDS(TDIF_REG_DEBUG_ERROR_INFO);
        offset +=
            qed_grc_dump_reg_entry_skip(p_hwfn,
                                        p_ptt,
                                        dump_buf + offset,
                                        dump,
                                        addr,
                                        TDIF_REG_DEBUG_ERROR_INFO_SIZE,
                                        7,
                                        1);

        return offset;
}

/* Dumps a GRC memory header (section and params). Returns the dumped size in
 * dwords. The following parameters are dumped:
 * - name:         dumped only if it's not NULL.
 * - addr:         in dwords, dumped only if name is NULL.
 * - len:          in dwords, always dumped.
 * - width:        dumped if it's not zero.
 * - packed:       dumped only if it's not false.
 * - mem_group:    always dumped.
 * - is_storm:     true only if the memory is related to a Storm.
 * - storm_letter: valid only if is_storm is true.
 *
 */
static u32 qed_grc_dump_mem_hdr(struct qed_hwfn *p_hwfn,
                                u32 *dump_buf,
                                bool dump,
                                const char *name,
                                u32 addr,
                                u32 len,
                                u32 bit_width,
                                bool packed,
                                const char *mem_group,
                                bool is_storm, char storm_letter)
{
        u8 num_params = 3;
        u32 offset = 0;
        char buf[64];

        if (!len)
                DP_NOTICE(p_hwfn,
                          "Unexpected GRC Dump error: dumped memory size must be non-zero\n");

        if (bit_width)
                num_params++;
        if (packed)
                num_params++;

        /* Dump section header */
        offset += qed_dump_section_hdr(dump_buf + offset,
                                       dump, "grc_mem", num_params);

        if (name) {
                /* Dump name */
                if (is_storm) {
                        strcpy(buf, "?STORM_");
                        buf[0] = storm_letter;
                        strcpy(buf + strlen(buf), name);
                } else {
                        strcpy(buf, name);
                }

                offset += qed_dump_str_param(dump_buf + offset,
                                             dump, "name", buf);
        } else {
                /* Dump address */
                u32 addr_in_bytes = DWORDS_TO_BYTES(addr);

                offset += qed_dump_num_param(dump_buf + offset,
                                             dump, "addr", addr_in_bytes);
        }

        /* Dump len */
        offset += qed_dump_num_param(dump_buf + offset, dump, "len", len);

        /* Dump bit width */
        if (bit_width)
                offset += qed_dump_num_param(dump_buf + offset,
                                             dump, "width", bit_width);

        /* Dump packed */
        if (packed)
                offset += qed_dump_num_param(dump_buf + offset,
                                             dump, "packed", 1);

        /* Dump reg type */
        if (is_storm) {
                strcpy(buf, "?STORM_");
                buf[0] = storm_letter;
                strcpy(buf + strlen(buf), mem_group);
        } else {
                strcpy(buf, mem_group);
        }

        offset += qed_dump_str_param(dump_buf + offset, dump, "type", buf);

        return offset;
}

/* Dumps a single GRC memory. If name is NULL, the memory is stored by address.
 * Returns the dumped size in dwords.
 * The addr and len arguments are specified in dwords.
 */
static u32 qed_grc_dump_mem(struct qed_hwfn *p_hwfn,
                            struct qed_ptt *p_ptt,
                            u32 *dump_buf,
                            bool dump,
                            const char *name,
                            u32 addr,
                            u32 len,
                            bool wide_bus,
                            u32 bit_width,
                            bool packed,
                            const char *mem_group,
                            bool is_storm, char storm_letter)
{
        u32 offset = 0;

        offset += qed_grc_dump_mem_hdr(p_hwfn,
                                       dump_buf + offset,
                                       dump,
                                       name,
                                       addr,
                                       len,
                                       bit_width,
                                       packed,
                                       mem_group, is_storm, storm_letter);
        offset += qed_grc_dump_addr_range(p_hwfn,
                                          p_ptt,
                                          dump_buf + offset,
                                          dump, addr, len, wide_bus,
                                          SPLIT_TYPE_NONE, 0);

        return offset;
}

/* Dumps GRC memories entries. Returns the dumped size in dwords. */
static u32 qed_grc_dump_mem_entries(struct qed_hwfn *p_hwfn,
                                    struct qed_ptt *p_ptt,
                                    struct dbg_array input_mems_arr,
                                    u32 *dump_buf, bool dump)
{
        u32 i, offset = 0, input_offset = 0;
        bool mode_match = true;

        while (input_offset < input_mems_arr.size_in_dwords) {
                const struct dbg_dump_cond_hdr *cond_hdr;
                u16 modes_buf_offset;
                u32 num_entries;
                bool eval_mode;

                cond_hdr = (const struct dbg_dump_cond_hdr *)
                           &input_mems_arr.ptr[input_offset++];
                num_entries = cond_hdr->data_size / MEM_DUMP_ENTRY_SIZE_DWORDS;

                /* Check required mode */
                eval_mode = GET_FIELD(cond_hdr->mode.data,
                                      DBG_MODE_HDR_EVAL_MODE) > 0;
                if (eval_mode) {
                        modes_buf_offset =
                                GET_FIELD(cond_hdr->mode.data,
                                          DBG_MODE_HDR_MODES_BUF_OFFSET);
                        mode_match = qed_is_mode_match(p_hwfn,
                                                       &modes_buf_offset);
                }

                if (!mode_match) {
                        input_offset += cond_hdr->data_size;
                        continue;
                }

                for (i = 0; i < num_entries;
                     i++, input_offset += MEM_DUMP_ENTRY_SIZE_DWORDS) {
                        const struct dbg_dump_mem *mem =
                                (const struct dbg_dump_mem *)
                                &input_mems_arr.ptr[input_offset];
                        u8 mem_group_id = GET_FIELD(mem->dword0,
                                                    DBG_DUMP_MEM_MEM_GROUP_ID);
                        bool is_storm = false, mem_wide_bus;
                        enum dbg_grc_params grc_param;
                        char storm_letter = 'a';
                        enum block_id block_id;
                        u32 mem_addr, mem_len;

                        if (mem_group_id >= MEM_GROUPS_NUM) {
                                DP_NOTICE(p_hwfn, "Invalid mem_group_id\n");
                                return 0;
                        }

                        block_id = (enum block_id)cond_hdr->block_id;
                        if (!qed_grc_is_mem_included(p_hwfn,
                                                     block_id,
                                                     mem_group_id))
                                continue;

                        mem_addr = GET_FIELD(mem->dword0, DBG_DUMP_MEM_ADDRESS);
                        mem_len = GET_FIELD(mem->dword1, DBG_DUMP_MEM_LENGTH);
                        mem_wide_bus = GET_FIELD(mem->dword1,
                                                 DBG_DUMP_MEM_WIDE_BUS);

                        /* Update memory length for CCFC/TCFC memories
                         * according to number of LCIDs/LTIDs.
                         */
                        if (mem_group_id == MEM_GROUP_CONN_CFC_MEM) {
                                if (mem_len % MAX_LCIDS) {
                                        DP_NOTICE(p_hwfn,
                                                  "Invalid CCFC connection memory size\n");
                                        return 0;
                                }

                                grc_param = DBG_GRC_PARAM_NUM_LCIDS;
                                mem_len = qed_grc_get_param(p_hwfn, grc_param) *
                                          (mem_len / MAX_LCIDS);
                        } else if (mem_group_id == MEM_GROUP_TASK_CFC_MEM) {
                                if (mem_len % MAX_LTIDS) {
                                        DP_NOTICE(p_hwfn,
                                                  "Invalid TCFC task memory size\n");
                                        return 0;
                                }

                                grc_param = DBG_GRC_PARAM_NUM_LTIDS;
                                mem_len = qed_grc_get_param(p_hwfn, grc_param) *
                                          (mem_len / MAX_LTIDS);
                        }

                        /* If memory is associated with Storm, update Storm
                         * details.
                         */
                        if (s_block_defs
                            [cond_hdr->block_id]->associated_to_storm) {
                                is_storm = true;
                                storm_letter =
                                    s_storm_defs[s_block_defs
                                                 [cond_hdr->block_id]->
                                                 storm_id].letter;
                        }

                        /* Dump memory */
                        offset += qed_grc_dump_mem(p_hwfn,
                                                p_ptt,
                                                dump_buf + offset,
                                                dump,
                                                NULL,
                                                mem_addr,
                                                mem_len,
                                                mem_wide_bus,
                                                0,
                                                false,
                                                s_mem_group_names[mem_group_id],
                                                is_storm,
                                                storm_letter);
                }
        }

        return offset;
}

/* Dumps GRC memories according to the input array dump_mem.
 * Returns the dumped size in dwords.
 */
static u32 qed_grc_dump_memories(struct qed_hwfn *p_hwfn,
                                 struct qed_ptt *p_ptt,
                                 u32 *dump_buf, bool dump)
{
        u32 offset = 0, input_offset = 0;

        while (input_offset <
               s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].size_in_dwords) {
                const struct dbg_dump_split_hdr *split_hdr;
                struct dbg_array curr_input_mems_arr;
                enum init_split_types split_type;
                u32 split_data_size;

                split_hdr = (const struct dbg_dump_split_hdr *)
                        &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset++];
                split_type =
                        GET_FIELD(split_hdr->hdr,
                                  DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
                split_data_size =
                        GET_FIELD(split_hdr->hdr,
                                  DBG_DUMP_SPLIT_HDR_DATA_SIZE);
                curr_input_mems_arr.ptr =
                        &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset];
                curr_input_mems_arr.size_in_dwords = split_data_size;

                if (split_type == SPLIT_TYPE_NONE)
                        offset += qed_grc_dump_mem_entries(p_hwfn,
                                                           p_ptt,
                                                           curr_input_mems_arr,
                                                           dump_buf + offset,
                                                           dump);
                else
                        DP_NOTICE(p_hwfn,
                                  "Dumping split memories is currently not supported\n");

                input_offset += split_data_size;
        }

        return offset;
}

/* Dumps GRC context data for the specified Storm.
 * Returns the dumped size in dwords.
 * The lid_size argument is specified in quad-regs.
 */
static u32 qed_grc_dump_ctx_data(struct qed_hwfn *p_hwfn,
                                 struct qed_ptt *p_ptt,
                                 u32 *dump_buf,
                                 bool dump,
                                 const char *name,
                                 u32 num_lids,
                                 u32 lid_size,
                                 u32 rd_reg_addr,
                                 u8 storm_id)
{
        struct storm_defs *storm = &s_storm_defs[storm_id];
        u32 i, lid, total_size, offset = 0;

        if (!lid_size)
                return 0;

        lid_size *= BYTES_IN_DWORD;
        total_size = num_lids * lid_size;

        offset += qed_grc_dump_mem_hdr(p_hwfn,
                                       dump_buf + offset,
                                       dump,
                                       name,
                                       0,
                                       total_size,
                                       lid_size * 32,
                                       false, name, true, storm->letter);

        if (!dump)
                return offset + total_size;

        /* Dump context data */
        for (lid = 0; lid < num_lids; lid++) {
                for (i = 0; i < lid_size; i++, offset++) {
                        qed_wr(p_hwfn,
                               p_ptt, storm->cm_ctx_wr_addr, (i << 9) | lid);
                        *(dump_buf + offset) = qed_rd(p_hwfn,
                                                      p_ptt, rd_reg_addr);
                }
        }

        return offset;
}

/* Dumps GRC contexts. Returns the dumped size in dwords. */
static u32 qed_grc_dump_ctx(struct qed_hwfn *p_hwfn,
                            struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
{
        enum dbg_grc_params grc_param;
        u32 offset = 0;
        u8 storm_id;

        for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
                struct storm_defs *storm = &s_storm_defs[storm_id];

                if (!qed_grc_is_storm_included(p_hwfn,
                                               (enum dbg_storms)storm_id))
                        continue;

                /* Dump Conn AG context size */
                grc_param = DBG_GRC_PARAM_NUM_LCIDS;
                offset +=
                        qed_grc_dump_ctx_data(p_hwfn,
                                              p_ptt,
                                              dump_buf + offset,
                                              dump,
                                              "CONN_AG_CTX",
                                              qed_grc_get_param(p_hwfn,
                                                                grc_param),
                                              storm->cm_conn_ag_ctx_lid_size,
                                              storm->cm_conn_ag_ctx_rd_addr,
                                              storm_id);

                /* Dump Conn ST context size */
                grc_param = DBG_GRC_PARAM_NUM_LCIDS;
                offset +=
                        qed_grc_dump_ctx_data(p_hwfn,
                                              p_ptt,
                                              dump_buf + offset,
                                              dump,
                                              "CONN_ST_CTX",
                                              qed_grc_get_param(p_hwfn,
                                                                grc_param),
                                              storm->cm_conn_st_ctx_lid_size,
                                              storm->cm_conn_st_ctx_rd_addr,
                                              storm_id);

                /* Dump Task AG context size */
                grc_param = DBG_GRC_PARAM_NUM_LTIDS;
                offset +=
                        qed_grc_dump_ctx_data(p_hwfn,
                                              p_ptt,
                                              dump_buf + offset,
                                              dump,
                                              "TASK_AG_CTX",
                                              qed_grc_get_param(p_hwfn,
                                                                grc_param),
                                              storm->cm_task_ag_ctx_lid_size,
                                              storm->cm_task_ag_ctx_rd_addr,
                                              storm_id);

                /* Dump Task ST context size */
                grc_param = DBG_GRC_PARAM_NUM_LTIDS;
                offset +=
                        qed_grc_dump_ctx_data(p_hwfn,
                                              p_ptt,
                                              dump_buf + offset,
                                              dump,
                                              "TASK_ST_CTX",
                                              qed_grc_get_param(p_hwfn,
                                                                grc_param),
                                              storm->cm_task_st_ctx_lid_size,
                                              storm->cm_task_st_ctx_rd_addr,
                                              storm_id);
        }

        return offset;
}

/* Dumps GRC IORs data. Returns the dumped size in dwords. */
static u32 qed_grc_dump_iors(struct qed_hwfn *p_hwfn,
                             struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
{
        char buf[10] = "IOR_SET_?";
        u32 addr, offset = 0;
        u8 storm_id, set_id;

        for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
                struct storm_defs *storm = &s_storm_defs[storm_id];

                if (!qed_grc_is_storm_included(p_hwfn,
                                               (enum dbg_storms)storm_id))
                        continue;

                for (set_id = 0; set_id < NUM_IOR_SETS; set_id++) {
                        addr = BYTES_TO_DWORDS(storm->sem_fast_mem_addr +
                                               SEM_FAST_REG_STORM_REG_FILE) +
                               IOR_SET_OFFSET(set_id);
                        if (strlen(buf) > 0)
                                buf[strlen(buf) - 1] = '0' + set_id;
                        offset += qed_grc_dump_mem(p_hwfn,
                                                   p_ptt,
                                                   dump_buf + offset,
                                                   dump,
                                                   buf,
                                                   addr,
                                                   IORS_PER_SET,
                                                   false,
                                                   32,
                                                   false,
                                                   "ior",
                                                   true,
                                                   storm->letter);
                }
        }

        return offset;
}

/* Dump VFC CAM. Returns the dumped size in dwords. */
static u32 qed_grc_dump_vfc_cam(struct qed_hwfn *p_hwfn,
                                struct qed_ptt *p_ptt,
                                u32 *dump_buf, bool dump, u8 storm_id)
{
        u32 total_size = VFC_CAM_NUM_ROWS * VFC_CAM_RESP_DWORDS;
        struct storm_defs *storm = &s_storm_defs[storm_id];
        u32 cam_addr[VFC_CAM_ADDR_DWORDS] = { 0 };
        u32 cam_cmd[VFC_CAM_CMD_DWORDS] = { 0 };
        u32 row, i, offset = 0;

        offset += qed_grc_dump_mem_hdr(p_hwfn,
                                       dump_buf + offset,
                                       dump,
                                       "vfc_cam",
                                       0,
                                       total_size,
                                       256,
                                       false, "vfc_cam", true, storm->letter);

        if (!dump)
                return offset + total_size;

        /* Prepare CAM address */
        SET_VAR_FIELD(cam_addr, VFC_CAM_ADDR, OP, VFC_OPCODE_CAM_RD);

        for (row = 0; row < VFC_CAM_NUM_ROWS;
             row++, offset += VFC_CAM_RESP_DWORDS) {
                /* Write VFC CAM command */
                SET_VAR_FIELD(cam_cmd, VFC_CAM_CMD, ROW, row);
                ARR_REG_WR(p_hwfn,
                           p_ptt,
                           storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR,
                           cam_cmd, VFC_CAM_CMD_DWORDS);

                /* Write VFC CAM address */
                ARR_REG_WR(p_hwfn,
                           p_ptt,
                           storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR,
                           cam_addr, VFC_CAM_ADDR_DWORDS);

                /* Read VFC CAM read response */
                ARR_REG_RD(p_hwfn,
                           p_ptt,
                           storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD,
                           dump_buf + offset, VFC_CAM_RESP_DWORDS);
        }

        return offset;
}

/* Dump VFC RAM. Returns the dumped size in dwords. */
static u32 qed_grc_dump_vfc_ram(struct qed_hwfn *p_hwfn,
                                struct qed_ptt *p_ptt,
                                u32 *dump_buf,
                                bool dump,
                                u8 storm_id, struct vfc_ram_defs *ram_defs)
{
        u32 total_size = ram_defs->num_rows * VFC_RAM_RESP_DWORDS;
        struct storm_defs *storm = &s_storm_defs[storm_id];
        u32 ram_addr[VFC_RAM_ADDR_DWORDS] = { 0 };
        u32 ram_cmd[VFC_RAM_CMD_DWORDS] = { 0 };
        u32 row, i, offset = 0;

        offset += qed_grc_dump_mem_hdr(p_hwfn,
                                       dump_buf + offset,
                                       dump,
                                       ram_defs->mem_name,
                                       0,
                                       total_size,
                                       256,
                                       false,
                                       ram_defs->type_name,
                                       true, storm->letter);

        /* Prepare RAM address */
        SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD);

        if (!dump)
                return offset + total_size;

        for (row = ram_defs->base_row;
             row < ram_defs->base_row + ram_defs->num_rows;
             row++, offset += VFC_RAM_RESP_DWORDS) {
                /* Write VFC RAM command */
                ARR_REG_WR(p_hwfn,
                           p_ptt,
                           storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR,
                           ram_cmd, VFC_RAM_CMD_DWORDS);

                /* Write VFC RAM address */
                SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, ROW, row);
                ARR_REG_WR(p_hwfn,
                           p_ptt,
                           storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR,
                           ram_addr, VFC_RAM_ADDR_DWORDS);

                /* Read VFC RAM read response */
                ARR_REG_RD(p_hwfn,
                           p_ptt,
                           storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD,
                           dump_buf + offset, VFC_RAM_RESP_DWORDS);
        }

        return offset;
}

/* Dumps GRC VFC data. Returns the dumped size in dwords. */
static u32 qed_grc_dump_vfc(struct qed_hwfn *p_hwfn,
                            struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u8 storm_id, i;
        u32 offset = 0;

        for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
                if (!qed_grc_is_storm_included(p_hwfn,
                                               (enum dbg_storms)storm_id) ||
                    !s_storm_defs[storm_id].has_vfc ||
                    (storm_id == DBG_PSTORM_ID && dev_data->platform_id !=
                     PLATFORM_ASIC))
                        continue;

                /* Read CAM */
                offset += qed_grc_dump_vfc_cam(p_hwfn,
                                               p_ptt,
                                               dump_buf + offset,
                                               dump, storm_id);

                /* Read RAM */
                for (i = 0; i < NUM_VFC_RAM_TYPES; i++)
                        offset += qed_grc_dump_vfc_ram(p_hwfn,
                                                       p_ptt,
                                                       dump_buf + offset,
                                                       dump,
                                                       storm_id,
                                                       &s_vfc_ram_defs[i]);
        }

        return offset;
}

/* Dumps GRC RSS data. Returns the dumped size in dwords. */
static u32 qed_grc_dump_rss(struct qed_hwfn *p_hwfn,
                            struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u32 offset = 0;
        u8 rss_mem_id;

        for (rss_mem_id = 0; rss_mem_id < NUM_RSS_MEM_TYPES; rss_mem_id++) {
                u32 rss_addr, num_entries, total_dwords;
                struct rss_mem_defs *rss_defs;
                u32 addr, num_dwords_to_read;
                bool packed;

                rss_defs = &s_rss_mem_defs[rss_mem_id];
                rss_addr = rss_defs->addr;
                num_entries = rss_defs->num_entries[dev_data->chip_id];
                total_dwords = (num_entries * rss_defs->entry_width) / 32;
                packed = (rss_defs->entry_width == 16);

                offset += qed_grc_dump_mem_hdr(p_hwfn,
                                               dump_buf + offset,
                                               dump,
                                               rss_defs->mem_name,
                                               0,
                                               total_dwords,
                                               rss_defs->entry_width,
                                               packed,
                                               rss_defs->type_name, false, 0);

                /* Dump RSS data */
                if (!dump) {
                        offset += total_dwords;
                        continue;
                }

                addr = BYTES_TO_DWORDS(RSS_REG_RSS_RAM_DATA);
                while (total_dwords) {
                        num_dwords_to_read = min_t(u32,
                                                   RSS_REG_RSS_RAM_DATA_SIZE,
                                                   total_dwords);
                        qed_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_ADDR, rss_addr);
                        offset += qed_grc_dump_addr_range(p_hwfn,
                                                          p_ptt,
                                                          dump_buf + offset,
                                                          dump,
                                                          addr,
                                                          num_dwords_to_read,
                                                          false,
                                                          SPLIT_TYPE_NONE, 0);
                        total_dwords -= num_dwords_to_read;
                        rss_addr++;
                }
        }

        return offset;
}

/* Dumps GRC Big RAM. Returns the dumped size in dwords. */
static u32 qed_grc_dump_big_ram(struct qed_hwfn *p_hwfn,
                                struct qed_ptt *p_ptt,
                                u32 *dump_buf, bool dump, u8 big_ram_id)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u32 block_size, ram_size, offset = 0, reg_val, i;
        char mem_name[12] = "???_BIG_RAM";
        char type_name[8] = "???_RAM";
        struct big_ram_defs *big_ram;

        big_ram = &s_big_ram_defs[big_ram_id];
        ram_size = big_ram->ram_size[dev_data->chip_id];

        reg_val = qed_rd(p_hwfn, p_ptt, big_ram->is_256b_reg_addr);
        block_size = reg_val &
                     BIT(big_ram->is_256b_bit_offset[dev_data->chip_id]) ? 256
                                                                         : 128;

        strncpy(type_name, big_ram->instance_name, BIG_RAM_NAME_LEN);
        strncpy(mem_name, big_ram->instance_name, BIG_RAM_NAME_LEN);

        /* Dump memory header */
        offset += qed_grc_dump_mem_hdr(p_hwfn,
                                       dump_buf + offset,
                                       dump,
                                       mem_name,
                                       0,
                                       ram_size,
                                       block_size * 8,
                                       false, type_name, false, 0);

        /* Read and dump Big RAM data */
        if (!dump)
                return offset + ram_size;

        /* Dump Big RAM */
        for (i = 0; i < DIV_ROUND_UP(ram_size, BRB_REG_BIG_RAM_DATA_SIZE);
             i++) {
                u32 addr, len;

                qed_wr(p_hwfn, p_ptt, big_ram->addr_reg_addr, i);
                addr = BYTES_TO_DWORDS(big_ram->data_reg_addr);
                len = BRB_REG_BIG_RAM_DATA_SIZE;
                offset += qed_grc_dump_addr_range(p_hwfn,
                                                  p_ptt,
                                                  dump_buf + offset,
                                                  dump,
                                                  addr,
                                                  len,
                                                  false, SPLIT_TYPE_NONE, 0);
        }

        return offset;
}

static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn,
                            struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
{
        bool block_enable[MAX_BLOCK_ID] = { 0 };
        u32 offset = 0, addr;
        bool halted = false;

        /* Halt MCP */
        if (dump && !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) {
                halted = !qed_mcp_halt(p_hwfn, p_ptt);
                if (!halted)
                        DP_NOTICE(p_hwfn, "MCP halt failed!\n");
        }

        /* Dump MCP scratchpad */
        offset += qed_grc_dump_mem(p_hwfn,
                                   p_ptt,
                                   dump_buf + offset,
                                   dump,
                                   NULL,
                                   BYTES_TO_DWORDS(MCP_REG_SCRATCH),
                                   MCP_REG_SCRATCH_SIZE_BB_K2,
                                   false, 0, false, "MCP", false, 0);

        /* Dump MCP cpu_reg_file */
        offset += qed_grc_dump_mem(p_hwfn,
                                   p_ptt,
                                   dump_buf + offset,
                                   dump,
                                   NULL,
                                   BYTES_TO_DWORDS(MCP_REG_CPU_REG_FILE),
                                   MCP_REG_CPU_REG_FILE_SIZE,
                                   false, 0, false, "MCP", false, 0);

        /* Dump MCP registers */
        block_enable[BLOCK_MCP] = true;
        offset += qed_grc_dump_registers(p_hwfn,
                                         p_ptt,
                                         dump_buf + offset,
                                         dump, block_enable, "block", "MCP");

        /* Dump required non-MCP registers */
        offset += qed_grc_dump_regs_hdr(dump_buf + offset,
                                        dump, 1, SPLIT_TYPE_NONE, 0,
                                        "block", "MCP");
        addr = BYTES_TO_DWORDS(MISC_REG_SHARED_MEM_ADDR);
        offset += qed_grc_dump_reg_entry(p_hwfn,
                                         p_ptt,
                                         dump_buf + offset,
                                         dump,
                                         addr,
                                         1,
                                         false, SPLIT_TYPE_NONE, 0);

        /* Release MCP */
        if (halted && qed_mcp_resume(p_hwfn, p_ptt))
                DP_NOTICE(p_hwfn, "Failed to resume MCP after halt!\n");

        return offset;
}

/* Dumps the tbus indirect memory for all PHYs. */
static u32 qed_grc_dump_phy(struct qed_hwfn *p_hwfn,
                            struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
{
        u32 offset = 0, tbus_lo_offset, tbus_hi_offset;
        char mem_name[32];
        u8 phy_id;

        for (phy_id = 0; phy_id < ARRAY_SIZE(s_phy_defs); phy_id++) {
                u32 addr_lo_addr, addr_hi_addr, data_lo_addr, data_hi_addr;
                struct phy_defs *phy_defs;
                u8 *bytes_buf;

                phy_defs = &s_phy_defs[phy_id];
                addr_lo_addr = phy_defs->base_addr +
                               phy_defs->tbus_addr_lo_addr;
                addr_hi_addr = phy_defs->base_addr +
                               phy_defs->tbus_addr_hi_addr;
                data_lo_addr = phy_defs->base_addr +
                               phy_defs->tbus_data_lo_addr;
                data_hi_addr = phy_defs->base_addr +
                               phy_defs->tbus_data_hi_addr;

                if (snprintf(mem_name, sizeof(mem_name), "tbus_%s",
                             phy_defs->phy_name) < 0)
                        DP_NOTICE(p_hwfn,
                                  "Unexpected debug error: invalid PHY memory name\n");

                offset += qed_grc_dump_mem_hdr(p_hwfn,
                                               dump_buf + offset,
                                               dump,
                                               mem_name,
                                               0,
                                               PHY_DUMP_SIZE_DWORDS,
                                               16, true, mem_name, false, 0);

                if (!dump) {
                        offset += PHY_DUMP_SIZE_DWORDS;
                        continue;
                }

                bytes_buf = (u8 *)(dump_buf + offset);
                for (tbus_hi_offset = 0;
                     tbus_hi_offset < (NUM_PHY_TBUS_ADDRESSES >> 8);
                     tbus_hi_offset++) {
                        qed_wr(p_hwfn, p_ptt, addr_hi_addr, tbus_hi_offset);
                        for (tbus_lo_offset = 0; tbus_lo_offset < 256;
                             tbus_lo_offset++) {
                                qed_wr(p_hwfn,
                                       p_ptt, addr_lo_addr, tbus_lo_offset);
                                *(bytes_buf++) = (u8)qed_rd(p_hwfn,
                                                            p_ptt,
                                                            data_lo_addr);
                                *(bytes_buf++) = (u8)qed_rd(p_hwfn,
                                                            p_ptt,
                                                            data_hi_addr);
                        }
                }

                offset += PHY_DUMP_SIZE_DWORDS;
        }

        return offset;
}

static void qed_config_dbg_line(struct qed_hwfn *p_hwfn,
                                struct qed_ptt *p_ptt,
                                enum block_id block_id,
                                u8 line_id,
                                u8 enable_mask,
                                u8 right_shift,
                                u8 force_valid_mask, u8 force_frame_mask)
{
        struct block_defs *block = s_block_defs[block_id];

        qed_wr(p_hwfn, p_ptt, block->dbg_select_addr, line_id);
        qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, enable_mask);
        qed_wr(p_hwfn, p_ptt, block->dbg_shift_addr, right_shift);
        qed_wr(p_hwfn, p_ptt, block->dbg_force_valid_addr, force_valid_mask);
        qed_wr(p_hwfn, p_ptt, block->dbg_force_frame_addr, force_frame_mask);
}

/* Dumps Static Debug data. Returns the dumped size in dwords. */
static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn,
                                     struct qed_ptt *p_ptt,
                                     u32 *dump_buf, bool dump)
{
        struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
        u32 block_id, line_id, offset = 0;

        /* Don't dump static debug if a debug bus recording is in progress */
        if (dump && qed_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON))
                return 0;

        if (dump) {
                /* Disable all blocks debug output */
                for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
                        struct block_defs *block = s_block_defs[block_id];

                        if (block->dbg_client_id[dev_data->chip_id] !=
                            MAX_DBG_BUS_CLIENTS)
                                qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr,
                                       0);
                }

                qed_bus_reset_dbg_block(p_hwfn, p_ptt);
                qed_bus_set_framing_mode(p_hwfn,
                                         p_ptt, DBG_BUS_FRAME_MODE_8HW_0ST);
                qed_wr(p_hwfn,
                       p_ptt, DBG_REG_DEBUG_TARGET, DBG_BUS_TARGET_ID_INT_BUF);
                qed_wr(p_hwfn, p_ptt, DBG_REG_FULL_MODE, 1);
                qed_bus_enable_dbg_block(p_hwfn, p_ptt, true);
        }

        /* Dump all static debug lines for each relevant block */
        for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
                struct block_defs *block = s_block_defs[block_id];
                struct dbg_bus_block *block_desc;
                u32 block_dwords, addr, len;
                u8 dbg_client_id;

                if (block->dbg_client_id[dev_data->chip_id] ==
                    MAX_DBG_BUS_CLIENTS)
                        continue;

                block_desc = get_dbg_bus_block_desc(p_hwfn,
                                                    (enum block_id)block_id);
                block_dwords = NUM_DBG_LINES(block_desc) *
                               STATIC_DEBUG_LINE_DWORDS;

                /* Dump static section params */
                offset += qed_grc_dump_mem_hdr(p_hwfn,
                                               dump_buf + offset,
                                               dump,
                                               block->name,
                                               0,
                                               block_dwords,
                                               32, false, "STATIC", false, 0);

                if (!dump) {
                        offset += block_dwords;
                        continue;
                }

                /* If all lines are invalid - dump zeros */
                if (dev_data->block_in_reset[block_id]) {
                        memset(dump_buf + offset, 0,
                               DWORDS_TO_BYTES(block_dwords));
                        offset += block_dwords;
                        continue;
                }

                /* Enable block's client */
                dbg_client_id = block->dbg_client_id[dev_data->chip_id];
                qed_bus_enable_clients(p_hwfn,
                                       p_ptt,
                                       BIT(dbg_client_id));

                addr = BYTES_TO_DWORDS(DBG_REG_CALENDAR_OUT_DATA);
                len = STATIC_DEBUG_LINE_DWORDS;
                for (line_id = 0; line_id < (u32)NUM_DBG_LINES(block_desc);
                     line_id++) {
                        /* Configure debug line ID */
                        qed_config_dbg_line(p_hwfn,
                                            p_ptt,
                                            (enum block_id)block_id,
                                            (u8)line_id, 0xf, 0, 0, 0);

                        /* Read debug line info */
                        offset += qed_grc_dump_addr_range(p_hwfn,
                                                          p_ptt,
                                                          dump_buf + offset,
                                                          dump,
                                                          addr,
                                                          len,
                                                          true, SPLIT_TYPE_NONE,
                                                          0);
                }

                /* Disable block's client and debug output */
                qed_bus_enable_clients(p_hwfn, p_ptt, 0);
                qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0);
        }

        if (dump) {
                qed_bus_enable_dbg_block(p_hwfn, p_ptt, false);
                qed_bus_enable_clients(p_hwfn, p_ptt, 0);
        }

        return offset;
}

/* Performs GRC Dump to the specified buffer.
 * Returns the dumped size in dwords.
 */
static enum dbg_status qed_grc_dump(struct qed_hwfn *p_hwfn,
                                    struct qed_ptt *p_ptt,
                                    u32 *dump_buf,
                                    bool dump, u32 *num_dumped_dwords)
{