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12#ifndef __il_3945_h__
13#define __il_3945_h__
14
15#include <linux/pci.h>
16#include <linux/kernel.h>
17#include <net/ieee80211_radiotap.h>
18
19
20extern const struct pci_device_id il3945_hw_card_ids[];
21
22#include "common.h"
23
24extern const struct il_ops il3945_ops;
25
26
27#define IL3945_UCODE_API_MAX 2
28
29
30#define IL3945_UCODE_API_MIN 1
31
32#define IL3945_FW_PRE "iwlwifi-3945-"
33#define _IL3945_MODULE_FIRMWARE(api) IL3945_FW_PRE #api ".ucode"
34#define IL3945_MODULE_FIRMWARE(api) _IL3945_MODULE_FIRMWARE(api)
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46
47#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
48
49
50extern struct il_mod_params il3945_mod_params;
51
52struct il3945_rate_scale_data {
53 u64 data;
54 s32 success_counter;
55 s32 success_ratio;
56 s32 counter;
57 s32 average_tpt;
58 unsigned long stamp;
59};
60
61struct il3945_rs_sta {
62 spinlock_t lock;
63 struct il_priv *il;
64 s32 *expected_tpt;
65 unsigned long last_partial_flush;
66 unsigned long last_flush;
67 u32 flush_time;
68 u32 last_tx_packets;
69 u32 tx_packets;
70 u8 tgg;
71 u8 flush_pending;
72 u8 start_rate;
73 struct timer_list rate_scale_flush;
74 struct il3945_rate_scale_data win[RATE_COUNT_3945];
75
76
77 int last_txrate_idx;
78};
79
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82
83
84struct il3945_sta_priv {
85 struct il_station_priv_common common;
86 struct il3945_rs_sta rs_sta;
87};
88
89enum il3945_antenna {
90 IL_ANTENNA_DIVERSITY,
91 IL_ANTENNA_MAIN,
92 IL_ANTENNA_AUX
93};
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102
103#define DEFAULT_RTS_THRESHOLD 2347U
104#define MIN_RTS_THRESHOLD 0U
105#define MAX_RTS_THRESHOLD 2347U
106#define MAX_MSDU_SIZE 2304U
107#define MAX_MPDU_SIZE 2346U
108#define DEFAULT_BEACON_INTERVAL 100U
109#define DEFAULT_SHORT_RETRY_LIMIT 7U
110#define DEFAULT_LONG_RETRY_LIMIT 4U
111
112#define IL_TX_FIFO_AC0 0
113#define IL_TX_FIFO_AC1 1
114#define IL_TX_FIFO_AC2 2
115#define IL_TX_FIFO_AC3 3
116#define IL_TX_FIFO_HCCA_1 5
117#define IL_TX_FIFO_HCCA_2 6
118#define IL_TX_FIFO_NONE 7
119
120#define IEEE80211_DATA_LEN 2304
121#define IEEE80211_4ADDR_LEN 30
122#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
123#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
124
125struct il3945_frame {
126 union {
127 struct ieee80211_hdr frame;
128 struct il3945_tx_beacon_cmd beacon;
129 u8 raw[IEEE80211_FRAME_LEN];
130 u8 cmd[360];
131 } u;
132 struct list_head list;
133};
134
135#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
136#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
137#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
138
139#define IL_SUPPORTED_RATES_IE_LEN 8
140
141#define SCAN_INTERVAL 100
142
143#define MAX_TID_COUNT 9
144
145#define IL_INVALID_RATE 0xFF
146#define IL_INVALID_VALUE -1
147
148#define STA_PS_STATUS_WAKE 0
149#define STA_PS_STATUS_SLEEP 1
150
151struct il3945_ibss_seq {
152 u8 mac[ETH_ALEN];
153 u16 seq_num;
154 u16 frag_num;
155 unsigned long packet_time;
156 struct list_head list;
157};
158
159#define IL_RX_HDR(x) ((struct il3945_rx_frame_hdr *)(\
160 x->u.rx_frame.stats.payload + \
161 x->u.rx_frame.stats.phy_count))
162#define IL_RX_END(x) ((struct il3945_rx_frame_end *)(\
163 IL_RX_HDR(x)->payload + \
164 le16_to_cpu(IL_RX_HDR(x)->len)))
165#define IL_RX_STATS(x) (&x->u.rx_frame.stats)
166#define IL_RX_DATA(x) (IL_RX_HDR(x)->payload)
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173
174int il3945_calc_db_from_ratio(int sig_ratio);
175void il3945_rx_replenish(void *data);
176void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
177unsigned int il3945_fill_beacon_frame(struct il_priv *il,
178 struct ieee80211_hdr *hdr, int left);
179int il3945_dump_nic_event_log(struct il_priv *il, bool full_log, char **buf,
180 bool display);
181void il3945_dump_nic_error_log(struct il_priv *il);
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198
199void il3945_hw_handler_setup(struct il_priv *il);
200void il3945_hw_setup_deferred_work(struct il_priv *il);
201void il3945_hw_cancel_deferred_work(struct il_priv *il);
202int il3945_hw_rxq_stop(struct il_priv *il);
203int il3945_hw_set_hw_params(struct il_priv *il);
204int il3945_hw_nic_init(struct il_priv *il);
205int il3945_hw_nic_stop_master(struct il_priv *il);
206void il3945_hw_txq_ctx_free(struct il_priv *il);
207void il3945_hw_txq_ctx_stop(struct il_priv *il);
208int il3945_hw_nic_reset(struct il_priv *il);
209int il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
210 dma_addr_t addr, u16 len, u8 reset, u8 pad);
211void il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
212int il3945_hw_get_temperature(struct il_priv *il);
213int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
214unsigned int il3945_hw_get_beacon_cmd(struct il_priv *il,
215 struct il3945_frame *frame, u8 rate);
216void il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
217 struct ieee80211_tx_info *info,
218 struct ieee80211_hdr *hdr, int sta_id);
219int il3945_hw_reg_send_txpower(struct il_priv *il);
220int il3945_hw_reg_set_txpower(struct il_priv *il, s8 power);
221void il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb);
222void il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb);
223void il3945_disable_events(struct il_priv *il);
224int il4965_get_temperature(const struct il_priv *il);
225void il3945_post_associate(struct il_priv *il);
226void il3945_config_ap(struct il_priv *il);
227
228int il3945_commit_rxon(struct il_priv *il);
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238u8 il3945_hw_find_station(struct il_priv *il, const u8 *bssid);
239
240__le32 il3945_get_antenna_flags(const struct il_priv *il);
241int il3945_init_hw_rate_table(struct il_priv *il);
242void il3945_reg_txpower_periodic(struct il_priv *il);
243int il3945_txpower_set_from_eeprom(struct il_priv *il);
244
245int il3945_rs_next_rate(struct il_priv *il, int rate);
246
247
248int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
249void il3945_post_scan(struct il_priv *il);
250
251
252extern const struct il3945_rate_info il3945_rates[RATE_COUNT_3945];
253
254
255#define IL39_RSSI_OFFSET 95
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259
260#define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)
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273struct il3945_eeprom_txpower_sample {
274 u8 gain_idx;
275 s8 power;
276 u16 v_det;
277} __packed;
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287struct il3945_eeprom_txpower_group {
288 struct il3945_eeprom_txpower_sample samples[5];
289 s32 a, b, c, d, e;
290
291 s32 Fa, Fb, Fc, Fd, Fe;
292
293 s8 saturation_power;
294
295 u8 group_channel;
296 s16 temperature;
297
298} __packed;
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306struct il3945_eeprom_temperature_corr {
307 u32 Ta;
308 u32 Tb;
309 u32 Tc;
310 u32 Td;
311 u32 Te;
312} __packed;
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316
317struct il3945_eeprom {
318 u8 reserved0[16];
319 u16 device_id;
320 u8 reserved1[2];
321 u16 pmc;
322 u8 reserved2[20];
323 u8 mac_address[6];
324 u8 reserved3[58];
325 u16 board_revision;
326 u8 reserved4[11];
327 u8 board_pba_number[9];
328 u8 reserved5[8];
329 u16 version;
330 u8 sku_cap;
331 u8 leds_mode;
332 u16 oem_mode;
333 u16 wowlan_mode;
334 u16 leds_time_interval;
335 u8 leds_off_time;
336 u8 leds_on_time;
337 u8 almgor_m_version;
338 u8 antenna_switch_type;
339 u8 reserved6[42];
340 u8 sku_id[4];
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353 u16 band_1_count;
354 struct il_eeprom_channel band_1_channels[14];
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361 u16 band_2_count;
362 struct il_eeprom_channel band_2_channels[13];
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368 u16 band_3_count;
369 struct il_eeprom_channel band_3_channels[12];
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375 u16 band_4_count;
376 struct il_eeprom_channel band_4_channels[11];
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382 u16 band_5_count;
383 struct il_eeprom_channel band_5_channels[6];
384
385 u8 reserved9[194];
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390#define IL_NUM_TX_CALIB_GROUPS 5
391 struct il3945_eeprom_txpower_group groups[IL_NUM_TX_CALIB_GROUPS];
392
393 struct il3945_eeprom_temperature_corr corrections;
394 u8 reserved16[172];
395} __packed;
396
397#define IL3945_EEPROM_IMG_SIZE 1024
398
399
400
401#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40)
402#define PCI_CFG_REV_ID_BIT_RTP (0x80)
403
404
405#define IL39_NUM_QUEUES 5
406#define IL39_CMD_QUEUE_NUM 4
407
408#define IL_DEFAULT_TX_RETRY 15
409
410
411
412#define RFD_SIZE 4
413#define NUM_TFD_CHUNKS 4
414
415#define TFD_CTL_COUNT_SET(n) (n << 24)
416#define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7)
417#define TFD_CTL_PAD_SET(n) (n << 28)
418#define TFD_CTL_PAD_GET(ctl) (ctl >> 28)
419
420
421
422#define IL39_RTC_INST_LOWER_BOUND (0x000000)
423#define IL39_RTC_INST_UPPER_BOUND (0x014000)
424
425#define IL39_RTC_DATA_LOWER_BOUND (0x800000)
426#define IL39_RTC_DATA_UPPER_BOUND (0x808000)
427
428#define IL39_RTC_INST_SIZE (IL39_RTC_INST_UPPER_BOUND - \
429 IL39_RTC_INST_LOWER_BOUND)
430#define IL39_RTC_DATA_SIZE (IL39_RTC_DATA_UPPER_BOUND - \
431 IL39_RTC_DATA_LOWER_BOUND)
432
433#define IL39_MAX_INST_SIZE IL39_RTC_INST_SIZE
434#define IL39_MAX_DATA_SIZE IL39_RTC_DATA_SIZE
435
436
437#define IL39_MAX_BSM_SIZE IL39_RTC_INST_SIZE
438
439static inline int
440il3945_hw_valid_rtc_data_addr(u32 addr)
441{
442 return (addr >= IL39_RTC_DATA_LOWER_BOUND &&
443 addr < IL39_RTC_DATA_UPPER_BOUND);
444}
445
446
447
448struct il3945_shared {
449 __le32 tx_base_ptr[8];
450} __packed;
451
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459
460#define FH39_MEM_LOWER_BOUND (0x0800)
461#define FH39_MEM_UPPER_BOUND (0x1000)
462
463#define FH39_CBCC_TBL (FH39_MEM_LOWER_BOUND + 0x140)
464#define FH39_TFDB_TBL (FH39_MEM_LOWER_BOUND + 0x180)
465#define FH39_RCSR_TBL (FH39_MEM_LOWER_BOUND + 0x400)
466#define FH39_RSSR_TBL (FH39_MEM_LOWER_BOUND + 0x4c0)
467#define FH39_TCSR_TBL (FH39_MEM_LOWER_BOUND + 0x500)
468#define FH39_TSSR_TBL (FH39_MEM_LOWER_BOUND + 0x680)
469
470
471#define FH39_TFDB(_ch, buf) (FH39_TFDB_TBL + \
472 ((_ch) * 2 + (buf)) * 0x28)
473#define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch) (FH39_TFDB_TBL + 0x50 * (_ch))
474
475
476#define FH39_CBCC(_ch) (FH39_CBCC_TBL + (_ch) * 0x8)
477#define FH39_CBCC_CTRL(_ch) (FH39_CBCC(_ch) + 0x00)
478#define FH39_CBCC_BASE(_ch) (FH39_CBCC(_ch) + 0x04)
479
480
481#define FH39_RCSR(_ch) (FH39_RCSR_TBL + (_ch) * 0x40)
482#define FH39_RCSR_CONFIG(_ch) (FH39_RCSR(_ch) + 0x00)
483#define FH39_RCSR_RBD_BASE(_ch) (FH39_RCSR(_ch) + 0x04)
484#define FH39_RCSR_WPTR(_ch) (FH39_RCSR(_ch) + 0x20)
485#define FH39_RCSR_RPTR_ADDR(_ch) (FH39_RCSR(_ch) + 0x24)
486
487#define FH39_RSCSR_CHNL0_WPTR (FH39_RCSR_WPTR(0))
488
489
490#define FH39_RSSR_CTRL (FH39_RSSR_TBL + 0x000)
491#define FH39_RSSR_STATUS (FH39_RSSR_TBL + 0x004)
492
493
494#define FH39_TCSR(_ch) (FH39_TCSR_TBL + (_ch) * 0x20)
495#define FH39_TCSR_CONFIG(_ch) (FH39_TCSR(_ch) + 0x00)
496#define FH39_TCSR_CREDIT(_ch) (FH39_TCSR(_ch) + 0x04)
497#define FH39_TCSR_BUFF_STTS(_ch) (FH39_TCSR(_ch) + 0x08)
498
499
500#define FH39_TSSR_CBB_BASE (FH39_TSSR_TBL + 0x000)
501#define FH39_TSSR_MSG_CONFIG (FH39_TSSR_TBL + 0x008)
502#define FH39_TSSR_TX_STATUS (FH39_TSSR_TBL + 0x010)
503
504
505
506#define FH39_SRVC_CHNL (6)
507
508#define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
509#define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
510
511#define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
512
513#define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
514
515#define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
516
517#define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
518
519#define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
520
521#define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
522
523#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
524#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
525
526#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
527#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
528
529#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
530
531#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
532
533#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
534#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
535
536#define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
537
538#define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
539
540#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
541#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
542
543#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
544
545#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
546#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
547
548#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
549#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
550
551#define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24)
552#define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) (BIT(_ch) << 16)
553
554#define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \
555 (FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \
556 FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch))
557
558#define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
559
560struct il3945_tfd_tb {
561 __le32 addr;
562 __le32 len;
563} __packed;
564
565struct il3945_tfd {
566 __le32 control_flags;
567 struct il3945_tfd_tb tbs[4];
568 u8 __pad[28];
569} __packed;
570
571#ifdef CONFIG_IWLEGACY_DEBUGFS
572extern const struct il_debugfs_ops il3945_debugfs_ops;
573#endif
574
575#endif
576