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6#include <linux/delay.h>
7#include "mt76x2.h"
8#include "eeprom.h"
9#include "mcu.h"
10
11static void
12mt76x2_mac_pbf_init(struct mt76x02_dev *dev)
13{
14 u32 val;
15
16 val = MT_PBF_SYS_CTRL_MCU_RESET |
17 MT_PBF_SYS_CTRL_DMA_RESET |
18 MT_PBF_SYS_CTRL_MAC_RESET |
19 MT_PBF_SYS_CTRL_PBF_RESET |
20 MT_PBF_SYS_CTRL_ASY_RESET;
21
22 mt76_set(dev, MT_PBF_SYS_CTRL, val);
23 mt76_clear(dev, MT_PBF_SYS_CTRL, val);
24
25 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
26 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
27}
28
29static void
30mt76x2_fixup_xtal(struct mt76x02_dev *dev)
31{
32 u16 eep_val;
33 s8 offset = 0;
34
35 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
36
37 offset = eep_val & 0x7f;
38 if ((eep_val & 0xff) == 0xff)
39 offset = 0;
40 else if (eep_val & 0x80)
41 offset = 0 - offset;
42
43 eep_val >>= 8;
44 if (eep_val == 0x00 || eep_val == 0xff) {
45 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
46 eep_val &= 0xff;
47
48 if (eep_val == 0x00 || eep_val == 0xff)
49 eep_val = 0x14;
50 }
51
52 eep_val &= 0x7f;
53 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
54 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
55
56 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
57 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
58 case 0:
59 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
60 break;
61 case 1:
62 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
63 break;
64 default:
65 break;
66 }
67}
68
69int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard)
70{
71 const u8 *macaddr = dev->mt76.macaddr;
72 u32 val;
73 int i, k;
74
75 if (!mt76x02_wait_for_mac(&dev->mt76))
76 return -ETIMEDOUT;
77
78 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
79
80 val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
81 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
82 MT_WPDMA_GLO_CFG_RX_DMA_EN |
83 MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
84 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
85 val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
86
87 mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
88
89 mt76x2_mac_pbf_init(dev);
90 mt76_write_mac_initvals(dev);
91 mt76x2_fixup_xtal(dev);
92
93 mt76_clear(dev, MT_MAC_SYS_CTRL,
94 MT_MAC_SYS_CTRL_RESET_CSR |
95 MT_MAC_SYS_CTRL_RESET_BBP);
96
97 if (is_mt7612(dev))
98 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
99
100 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
101 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
102
103 mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
104 mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
105 usleep_range(5000, 10000);
106 mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
107
108 mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
109 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
110
111 mt76x02_mac_setaddr(dev, macaddr);
112 mt76x02e_init_beacon_config(dev);
113 if (!hard)
114 return 0;
115
116 for (i = 0; i < 256 / 32; i++)
117 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);
118
119 for (i = 0; i < 256; i++) {
120 mt76x02_mac_wcid_setup(dev, i, 0, NULL);
121 mt76_wr(dev, MT_WCID_TX_RATE(i), 0);
122 mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0);
123 }
124
125 for (i = 0; i < MT_MAX_VIFS; i++)
126 mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL);
127
128 for (i = 0; i < 16; i++)
129 for (k = 0; k < 4; k++)
130 mt76x02_mac_shared_key_setup(dev, i, k, NULL);
131
132 for (i = 0; i < 16; i++)
133 mt76_rr(dev, MT_TX_STAT_FIFO);
134
135 mt76_wr(dev, MT_CH_TIME_CFG,
136 MT_CH_TIME_CFG_TIMER_EN |
137 MT_CH_TIME_CFG_TX_AS_BUSY |
138 MT_CH_TIME_CFG_RX_AS_BUSY |
139 MT_CH_TIME_CFG_NAV_AS_BUSY |
140 MT_CH_TIME_CFG_EIFS_AS_BUSY |
141 MT_CH_CCA_RC_EN |
142 FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
143
144 mt76x02_set_tx_ackto(dev);
145
146 return 0;
147}
148
149int mt76x2_mac_start(struct mt76x02_dev *dev)
150{
151 int i;
152
153 for (i = 0; i < 16; i++)
154 mt76_rr(dev, MT_TX_AGG_CNT(i));
155
156 for (i = 0; i < 16; i++)
157 mt76_rr(dev, MT_TX_STAT_FIFO);
158
159 memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats));
160 mt76x02_mac_start(dev);
161
162 return 0;
163}
164
165static void
166mt76x2_power_on_rf_patch(struct mt76x02_dev *dev)
167{
168 mt76_set(dev, 0x10130, BIT(0) | BIT(16));
169 udelay(1);
170
171 mt76_clear(dev, 0x1001c, 0xff);
172 mt76_set(dev, 0x1001c, 0x30);
173
174 mt76_wr(dev, 0x10014, 0x484f);
175 udelay(1);
176
177 mt76_set(dev, 0x10130, BIT(17));
178 udelay(125);
179
180 mt76_clear(dev, 0x10130, BIT(16));
181 udelay(50);
182
183 mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
184}
185
186static void
187mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit)
188{
189 int shift = unit ? 8 : 0;
190
191
192 mt76_set(dev, 0x10130, BIT(0) << shift);
193 udelay(10);
194
195
196 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
197 udelay(10);
198
199
200 mt76_clear(dev, 0x10130, BIT(2) << shift);
201 udelay(10);
202
203 mt76x2_power_on_rf_patch(dev);
204
205 mt76_set(dev, 0x530, 0xf);
206}
207
208static void
209mt76x2_power_on(struct mt76x02_dev *dev)
210{
211 u32 val;
212
213
214 mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
215
216 val = MT_WLAN_MTC_CTRL_STATE_UP |
217 MT_WLAN_MTC_CTRL_PWR_ACK |
218 MT_WLAN_MTC_CTRL_PWR_ACK_S;
219
220 mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
221
222 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
223 udelay(10);
224
225 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
226 udelay(10);
227
228 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
229 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
230
231
232 mt76_clear(dev, 0x11204, BIT(3));
233
234
235 mt76_set(dev, 0x10080, BIT(0));
236
237
238 mt76_clear(dev, 0x10064, BIT(18));
239
240 mt76x2_power_on_rf(dev, 0);
241 mt76x2_power_on_rf(dev, 1);
242}
243
244static int mt76x2_init_hardware(struct mt76x02_dev *dev)
245{
246 int ret;
247
248 mt76x02_dma_disable(dev);
249 mt76x2_reset_wlan(dev, true);
250 mt76x2_power_on(dev);
251
252 ret = mt76x2_eeprom_init(dev);
253 if (ret)
254 return ret;
255
256 ret = mt76x2_mac_reset(dev, true);
257 if (ret)
258 return ret;
259
260 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
261
262 ret = mt76x02_dma_init(dev);
263 if (ret)
264 return ret;
265
266 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
267 ret = mt76x2_mac_start(dev);
268 if (ret)
269 return ret;
270
271 ret = mt76x2_mcu_init(dev);
272 if (ret)
273 return ret;
274
275 mt76x2_mac_stop(dev, false);
276
277 return 0;
278}
279
280void mt76x2_stop_hardware(struct mt76x02_dev *dev)
281{
282 cancel_delayed_work_sync(&dev->cal_work);
283 cancel_delayed_work_sync(&dev->mt76.mac_work);
284 cancel_delayed_work_sync(&dev->wdt_work);
285 mt76x02_mcu_set_radio_state(dev, false);
286 mt76x2_mac_stop(dev, false);
287}
288
289void mt76x2_cleanup(struct mt76x02_dev *dev)
290{
291 tasklet_disable(&dev->dfs_pd.dfs_tasklet);
292 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
293 mt76x2_stop_hardware(dev);
294 mt76x02_dma_cleanup(dev);
295 mt76x02_mcu_cleanup(dev);
296}
297
298int mt76x2_register_device(struct mt76x02_dev *dev)
299{
300 int ret;
301
302 INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate);
303
304 mt76x02_init_device(dev);
305
306 ret = mt76x2_init_hardware(dev);
307 if (ret)
308 return ret;
309
310 mt76x02_config_mac_addr_list(dev);
311
312 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates,
313 ARRAY_SIZE(mt76x02_rates));
314 if (ret)
315 goto fail;
316
317 mt76x02_init_debugfs(dev);
318 mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband);
319 mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband);
320
321 return 0;
322
323fail:
324 mt76x2_stop_hardware(dev);
325 return ret;
326}
327
328
