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15#define dev_fmt(fmt) "pciehp: " fmt
16
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/jiffies.h>
20#include <linux/kthread.h>
21#include <linux/pci.h>
22#include <linux/pm_runtime.h>
23#include <linux/interrupt.h>
24#include <linux/slab.h>
25
26#include "../pci.h"
27#include "pciehp.h"
28
29static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
30{
31 return ctrl->pcie->port;
32}
33
34static irqreturn_t pciehp_isr(int irq, void *dev_id);
35static irqreturn_t pciehp_ist(int irq, void *dev_id);
36static int pciehp_poll(void *data);
37
38static inline int pciehp_request_irq(struct controller *ctrl)
39{
40 int retval, irq = ctrl->pcie->irq;
41
42 if (pciehp_poll_mode) {
43 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
44 "pciehp_poll-%s",
45 slot_name(ctrl));
46 return PTR_ERR_OR_ZERO(ctrl->poll_thread);
47 }
48
49
50 retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
51 IRQF_SHARED, "pciehp", ctrl);
52 if (retval)
53 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
54 irq);
55 return retval;
56}
57
58static inline void pciehp_free_irq(struct controller *ctrl)
59{
60 if (pciehp_poll_mode)
61 kthread_stop(ctrl->poll_thread);
62 else
63 free_irq(ctrl->pcie->irq, ctrl);
64}
65
66static int pcie_poll_cmd(struct controller *ctrl, int timeout)
67{
68 struct pci_dev *pdev = ctrl_dev(ctrl);
69 u16 slot_status;
70
71 while (true) {
72 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
73 if (slot_status == (u16) ~0) {
74 ctrl_info(ctrl, "%s: no response from device\n",
75 __func__);
76 return 0;
77 }
78
79 if (slot_status & PCI_EXP_SLTSTA_CC) {
80 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
81 PCI_EXP_SLTSTA_CC);
82 return 1;
83 }
84 if (timeout < 0)
85 break;
86 msleep(10);
87 timeout -= 10;
88 }
89 return 0;
90}
91
92static void pcie_wait_cmd(struct controller *ctrl)
93{
94 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
95 unsigned long duration = msecs_to_jiffies(msecs);
96 unsigned long cmd_timeout = ctrl->cmd_started + duration;
97 unsigned long now, timeout;
98 int rc;
99
100
101
102
103
104 if (NO_CMD_CMPL(ctrl))
105 return;
106
107 if (!ctrl->cmd_busy)
108 return;
109
110
111
112
113
114 now = jiffies;
115 if (time_before_eq(cmd_timeout, now))
116 timeout = 1;
117 else
118 timeout = cmd_timeout - now;
119
120 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
121 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
122 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
123 else
124 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
125
126 if (!rc)
127 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
128 ctrl->slot_ctrl,
129 jiffies_to_msecs(jiffies - ctrl->cmd_started));
130}
131
132#define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \
133 PCI_EXP_SLTCTL_PIC | \
134 PCI_EXP_SLTCTL_AIC | \
135 PCI_EXP_SLTCTL_EIC)
136
137static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
138 u16 mask, bool wait)
139{
140 struct pci_dev *pdev = ctrl_dev(ctrl);
141 u16 slot_ctrl_orig, slot_ctrl;
142
143 mutex_lock(&ctrl->ctrl_lock);
144
145
146
147
148 pcie_wait_cmd(ctrl);
149
150 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
151 if (slot_ctrl == (u16) ~0) {
152 ctrl_info(ctrl, "%s: no response from device\n", __func__);
153 goto out;
154 }
155
156 slot_ctrl_orig = slot_ctrl;
157 slot_ctrl &= ~mask;
158 slot_ctrl |= (cmd & mask);
159 ctrl->cmd_busy = 1;
160 smp_mb();
161 ctrl->slot_ctrl = slot_ctrl;
162 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
163 ctrl->cmd_started = jiffies;
164
165
166
167
168
169
170
171
172 if (pdev->broken_cmd_compl &&
173 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
174 ctrl->cmd_busy = 0;
175
176
177
178
179
180 if (wait)
181 pcie_wait_cmd(ctrl);
182
183out:
184 mutex_unlock(&ctrl->ctrl_lock);
185}
186
187
188
189
190
191
192
193static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
194{
195 pcie_do_write_cmd(ctrl, cmd, mask, true);
196}
197
198
199static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
200{
201 pcie_do_write_cmd(ctrl, cmd, mask, false);
202}
203
204bool pciehp_check_link_active(struct controller *ctrl)
205{
206 struct pci_dev *pdev = ctrl_dev(ctrl);
207 u16 lnk_status;
208 bool ret;
209
210 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
211 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
212
213 if (ret)
214 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
215
216 return ret;
217}
218
219static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
220{
221 u32 l;
222 int count = 0;
223 int delay = 1000, step = 20;
224 bool found = false;
225
226 do {
227 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
228 count++;
229
230 if (found)
231 break;
232
233 msleep(step);
234 delay -= step;
235 } while (delay > 0);
236
237 if (count > 1)
238 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
239 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
240 PCI_FUNC(devfn), count, step, l);
241
242 return found;
243}
244
245int pciehp_check_link_status(struct controller *ctrl)
246{
247 struct pci_dev *pdev = ctrl_dev(ctrl);
248 bool found;
249 u16 lnk_status;
250
251 if (!pcie_wait_for_link(pdev, true))
252 return -1;
253
254 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
255 PCI_DEVFN(0, 0));
256
257
258 if (found)
259 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
260 &ctrl->pending_events);
261
262 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
263 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
264 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
265 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
266 ctrl_err(ctrl, "link training error: status %#06x\n",
267 lnk_status);
268 return -1;
269 }
270
271 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
272
273 if (!found)
274 return -1;
275
276 return 0;
277}
278
279static int __pciehp_link_set(struct controller *ctrl, bool enable)
280{
281 struct pci_dev *pdev = ctrl_dev(ctrl);
282 u16 lnk_ctrl;
283
284 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
285
286 if (enable)
287 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
288 else
289 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
290
291 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
292 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
293 return 0;
294}
295
296static int pciehp_link_enable(struct controller *ctrl)
297{
298 return __pciehp_link_set(ctrl, true);
299}
300
301int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
302 u8 *status)
303{
304 struct controller *ctrl = to_ctrl(hotplug_slot);
305 struct pci_dev *pdev = ctrl_dev(ctrl);
306 u16 slot_ctrl;
307
308 pci_config_pm_runtime_get(pdev);
309 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
310 pci_config_pm_runtime_put(pdev);
311 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
312 return 0;
313}
314
315int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
316{
317 struct controller *ctrl = to_ctrl(hotplug_slot);
318 struct pci_dev *pdev = ctrl_dev(ctrl);
319 u16 slot_ctrl;
320
321 pci_config_pm_runtime_get(pdev);
322 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
323 pci_config_pm_runtime_put(pdev);
324 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
325 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
326
327 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
328 case PCI_EXP_SLTCTL_ATTN_IND_ON:
329 *status = 1;
330 break;
331 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
332 *status = 2;
333 break;
334 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
335 *status = 0;
336 break;
337 default:
338 *status = 0xFF;
339 break;
340 }
341
342 return 0;
343}
344
345void pciehp_get_power_status(struct controller *ctrl, u8 *status)
346{
347 struct pci_dev *pdev = ctrl_dev(ctrl);
348 u16 slot_ctrl;
349
350 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
351 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
352 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
353
354 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
355 case PCI_EXP_SLTCTL_PWR_ON:
356 *status = 1;
357 break;
358 case PCI_EXP_SLTCTL_PWR_OFF:
359 *status = 0;
360 break;
361 default:
362 *status = 0xFF;
363 break;
364 }
365}
366
367void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
368{
369 struct pci_dev *pdev = ctrl_dev(ctrl);
370 u16 slot_status;
371
372 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
373 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
374}
375
376bool pciehp_card_present(struct controller *ctrl)
377{
378 struct pci_dev *pdev = ctrl_dev(ctrl);
379 u16 slot_status;
380
381 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
382 return slot_status & PCI_EXP_SLTSTA_PDS;
383}
384
385
386
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388
389
390
391
392
393
394bool pciehp_card_present_or_link_active(struct controller *ctrl)
395{
396 return pciehp_card_present(ctrl) || pciehp_check_link_active(ctrl);
397}
398
399int pciehp_query_power_fault(struct controller *ctrl)
400{
401 struct pci_dev *pdev = ctrl_dev(ctrl);
402 u16 slot_status;
403
404 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
405 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
406}
407
408int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
409 u8 status)
410{
411 struct controller *ctrl = to_ctrl(hotplug_slot);
412 struct pci_dev *pdev = ctrl_dev(ctrl);
413
414 pci_config_pm_runtime_get(pdev);
415 pcie_write_cmd_nowait(ctrl, status << 6,
416 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
417 pci_config_pm_runtime_put(pdev);
418 return 0;
419}
420
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431
432
433
434
435
436void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
437{
438 u16 cmd = 0, mask = 0;
439
440 if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
441 cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
442 mask |= PCI_EXP_SLTCTL_PIC;
443 }
444
445 if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
446 cmd |= (attn & PCI_EXP_SLTCTL_AIC);
447 mask |= PCI_EXP_SLTCTL_AIC;
448 }
449
450 if (cmd) {
451 pcie_write_cmd_nowait(ctrl, cmd, mask);
452 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
453 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
454 }
455}
456
457int pciehp_power_on_slot(struct controller *ctrl)
458{
459 struct pci_dev *pdev = ctrl_dev(ctrl);
460 u16 slot_status;
461 int retval;
462
463
464 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
465 if (slot_status & PCI_EXP_SLTSTA_PFD)
466 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
467 PCI_EXP_SLTSTA_PFD);
468 ctrl->power_fault_detected = 0;
469
470 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
471 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
472 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
473 PCI_EXP_SLTCTL_PWR_ON);
474
475 retval = pciehp_link_enable(ctrl);
476 if (retval)
477 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
478
479 return retval;
480}
481
482void pciehp_power_off_slot(struct controller *ctrl)
483{
484 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
485 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
486 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
487 PCI_EXP_SLTCTL_PWR_OFF);
488}
489
490static irqreturn_t pciehp_isr(int irq, void *dev_id)
491{
492 struct controller *ctrl = (struct controller *)dev_id;
493 struct pci_dev *pdev = ctrl_dev(ctrl);
494 struct device *parent = pdev->dev.parent;
495 u16 status, events;
496
497
498
499
500
501 if (pdev->current_state == PCI_D3cold ||
502 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
503 return IRQ_NONE;
504
505
506
507
508
509
510 if (parent) {
511 pm_runtime_get_noresume(parent);
512 if (!pm_runtime_active(parent)) {
513 pm_runtime_put(parent);
514 disable_irq_nosync(irq);
515 atomic_or(RERUN_ISR, &ctrl->pending_events);
516 return IRQ_WAKE_THREAD;
517 }
518 }
519
520 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
521 if (status == (u16) ~0) {
522 ctrl_info(ctrl, "%s: no response from device\n", __func__);
523 if (parent)
524 pm_runtime_put(parent);
525 return IRQ_NONE;
526 }
527
528
529
530
531
532 events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
533 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
534 PCI_EXP_SLTSTA_DLLSC);
535
536
537
538
539
540 if (ctrl->power_fault_detected)
541 events &= ~PCI_EXP_SLTSTA_PFD;
542
543 if (!events) {
544 if (parent)
545 pm_runtime_put(parent);
546 return IRQ_NONE;
547 }
548
549 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
550 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
551 if (parent)
552 pm_runtime_put(parent);
553
554
555
556
557
558 if (events & PCI_EXP_SLTSTA_CC) {
559 ctrl->cmd_busy = 0;
560 smp_mb();
561 wake_up(&ctrl->queue);
562
563 if (events == PCI_EXP_SLTSTA_CC)
564 return IRQ_HANDLED;
565
566 events &= ~PCI_EXP_SLTSTA_CC;
567 }
568
569 if (pdev->ignore_hotplug) {
570 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
571 return IRQ_HANDLED;
572 }
573
574
575 atomic_or(events, &ctrl->pending_events);
576 return IRQ_WAKE_THREAD;
577}
578
579static irqreturn_t pciehp_ist(int irq, void *dev_id)
580{
581 struct controller *ctrl = (struct controller *)dev_id;
582 struct pci_dev *pdev = ctrl_dev(ctrl);
583 irqreturn_t ret;
584 u32 events;
585
586 pci_config_pm_runtime_get(pdev);
587
588
589 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
590 ret = pciehp_isr(irq, dev_id);
591 enable_irq(irq);
592 if (ret != IRQ_WAKE_THREAD) {
593 pci_config_pm_runtime_put(pdev);
594 return ret;
595 }
596 }
597
598 synchronize_hardirq(irq);
599 events = atomic_xchg(&ctrl->pending_events, 0);
600 if (!events) {
601 pci_config_pm_runtime_put(pdev);
602 return IRQ_NONE;
603 }
604
605
606 if (events & PCI_EXP_SLTSTA_ABP) {
607 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
608 slot_name(ctrl));
609 pciehp_handle_button_press(ctrl);
610 }
611
612
613 if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
614 ctrl->power_fault_detected = 1;
615 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
616 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
617 PCI_EXP_SLTCTL_ATTN_IND_ON);
618 }
619
620
621
622
623
624 down_read(&ctrl->reset_lock);
625 if (events & DISABLE_SLOT)
626 pciehp_handle_disable_request(ctrl);
627 else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
628 pciehp_handle_presence_or_link_change(ctrl, events);
629 up_read(&ctrl->reset_lock);
630
631 pci_config_pm_runtime_put(pdev);
632 wake_up(&ctrl->requester);
633 return IRQ_HANDLED;
634}
635
636static int pciehp_poll(void *data)
637{
638 struct controller *ctrl = data;
639
640 schedule_timeout_idle(10 * HZ);
641
642 while (!kthread_should_stop()) {
643
644 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
645 atomic_read(&ctrl->pending_events))
646 pciehp_ist(IRQ_NOTCONNECTED, ctrl);
647
648 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
649 pciehp_poll_time = 2;
650
651 schedule_timeout_idle(pciehp_poll_time * HZ);
652 }
653
654 return 0;
655}
656
657static void pcie_enable_notification(struct controller *ctrl)
658{
659 u16 cmd, mask;
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677 cmd = PCI_EXP_SLTCTL_DLLSCE;
678 if (ATTN_BUTTN(ctrl))
679 cmd |= PCI_EXP_SLTCTL_ABPE;
680 else
681 cmd |= PCI_EXP_SLTCTL_PDCE;
682 if (!pciehp_poll_mode)
683 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
684
685 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
686 PCI_EXP_SLTCTL_PFDE |
687 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
688 PCI_EXP_SLTCTL_DLLSCE);
689
690 pcie_write_cmd_nowait(ctrl, cmd, mask);
691 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
692 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
693}
694
695static void pcie_disable_notification(struct controller *ctrl)
696{
697 u16 mask;
698
699 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
700 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
701 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
702 PCI_EXP_SLTCTL_DLLSCE);
703 pcie_write_cmd(ctrl, 0, mask);
704 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
705 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
706}
707
708void pcie_clear_hotplug_events(struct controller *ctrl)
709{
710 pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
711 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
712}
713
714void pcie_enable_interrupt(struct controller *ctrl)
715{
716 u16 mask;
717
718 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
719 pcie_write_cmd(ctrl, mask, mask);
720}
721
722void pcie_disable_interrupt(struct controller *ctrl)
723{
724 u16 mask;
725
726
727
728
729
730
731
732
733 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
734 pcie_write_cmd(ctrl, 0, mask);
735}
736
737
738
739
740
741
742
743
744
745int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe)
746{
747 struct controller *ctrl = to_ctrl(hotplug_slot);
748 struct pci_dev *pdev = ctrl_dev(ctrl);
749 u16 stat_mask = 0, ctrl_mask = 0;
750 int rc;
751
752 if (probe)
753 return 0;
754
755 down_write(&ctrl->reset_lock);
756
757 if (!ATTN_BUTTN(ctrl)) {
758 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
759 stat_mask |= PCI_EXP_SLTSTA_PDC;
760 }
761 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
762 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
763
764 pcie_write_cmd(ctrl, 0, ctrl_mask);
765 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
766 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
767
768 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
769
770 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
771 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
772 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
773 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
774
775 up_write(&ctrl->reset_lock);
776 return rc;
777}
778
779int pcie_init_notification(struct controller *ctrl)
780{
781 if (pciehp_request_irq(ctrl))
782 return -1;
783 pcie_enable_notification(ctrl);
784 ctrl->notification_enabled = 1;
785 return 0;
786}
787
788void pcie_shutdown_notification(struct controller *ctrl)
789{
790 if (ctrl->notification_enabled) {
791 pcie_disable_notification(ctrl);
792 pciehp_free_irq(ctrl);
793 ctrl->notification_enabled = 0;
794 }
795}
796
797static inline void dbg_ctrl(struct controller *ctrl)
798{
799 struct pci_dev *pdev = ctrl->pcie->port;
800 u16 reg16;
801
802 ctrl_dbg(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
803 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
804 ctrl_dbg(ctrl, "Slot Status : 0x%04x\n", reg16);
805 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
806 ctrl_dbg(ctrl, "Slot Control : 0x%04x\n", reg16);
807}
808
809#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
810
811struct controller *pcie_init(struct pcie_device *dev)
812{
813 struct controller *ctrl;
814 u32 slot_cap, link_cap;
815 u8 poweron;
816 struct pci_dev *pdev = dev->port;
817 struct pci_bus *subordinate = pdev->subordinate;
818
819 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
820 if (!ctrl)
821 return NULL;
822
823 ctrl->pcie = dev;
824 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
825
826 if (pdev->hotplug_user_indicators)
827 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
828
829
830
831
832
833 if (pdev->is_thunderbolt)
834 slot_cap |= PCI_EXP_SLTCAP_NCCS;
835
836 ctrl->slot_cap = slot_cap;
837 mutex_init(&ctrl->ctrl_lock);
838 mutex_init(&ctrl->state_lock);
839 init_rwsem(&ctrl->reset_lock);
840 init_waitqueue_head(&ctrl->requester);
841 init_waitqueue_head(&ctrl->queue);
842 INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
843 dbg_ctrl(ctrl);
844
845 down_read(&pci_bus_sem);
846 ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
847 up_read(&pci_bus_sem);
848
849
850 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
851
852
853 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
854 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
855 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
856 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
857
858 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n",
859 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
860 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
861 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
862 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
863 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
864 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
865 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
866 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
867 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
868 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
869 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
870 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
871
872
873
874
875
876 if (POWER_CTRL(ctrl)) {
877 pciehp_get_power_status(ctrl, &poweron);
878 if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
879 pcie_disable_notification(ctrl);
880 pciehp_power_off_slot(ctrl);
881 }
882 }
883
884 return ctrl;
885}
886
887void pciehp_release_ctrl(struct controller *ctrl)
888{
889 cancel_delayed_work_sync(&ctrl->button_work);
890 kfree(ctrl);
891}
892
893static void quirk_cmd_compl(struct pci_dev *pdev)
894{
895 u32 slot_cap;
896
897 if (pci_is_pcie(pdev)) {
898 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
899 if (slot_cap & PCI_EXP_SLTCAP_HPC &&
900 !(slot_cap & PCI_EXP_SLTCAP_NCCS))
901 pdev->broken_cmd_compl = 1;
902 }
903}
904DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
905 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
906DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
907 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
908DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
909 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
910DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
911 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
912