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7#include "qla_def.h"
8#include <linux/delay.h>
9#include <linux/ktime.h>
10#include <linux/pci.h>
11#include <linux/ratelimit.h>
12#include <linux/vmalloc.h>
13#include <scsi/scsi_tcq.h>
14#include <linux/utsname.h>
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38static int
39qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
40
41{
42 int rval;
43 unsigned long flags = 0;
44 device_reg_t *reg;
45 uint8_t abort_active;
46 uint8_t io_lock_on;
47 uint16_t command = 0;
48 uint32_t *iptr;
49 uint32_t __iomem *optr;
50 uint32_t cnt;
51 uint32_t mboxes;
52 unsigned long wait_time;
53 struct qla_hw_data *ha = vha->hw;
54 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
55
56 if (ha->pdev->error_state > pci_channel_io_frozen) {
57 ql_log(ql_log_warn, vha, 0x115c,
58 "error_state is greater than pci_channel_io_frozen, "
59 "exiting.\n");
60 return QLA_FUNCTION_TIMEOUT;
61 }
62
63 if (vha->device_flags & DFLG_DEV_FAILED) {
64 ql_log(ql_log_warn, vha, 0x115f,
65 "Device in failed state, exiting.\n");
66 return QLA_FUNCTION_TIMEOUT;
67 }
68
69 reg = ha->iobase;
70 io_lock_on = base_vha->flags.init_done;
71
72 rval = QLA_SUCCESS;
73 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
74
75 if (ha->flags.pci_channel_io_perm_failure) {
76 ql_log(ql_log_warn, vha, 0x1175,
77 "Perm failure on EEH timeout MBX, exiting.\n");
78 return QLA_FUNCTION_TIMEOUT;
79 }
80
81 if (ha->flags.isp82xx_fw_hung) {
82
83 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
84 ql_log(ql_log_warn, vha, 0x1176,
85 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
86 rval = QLA_FUNCTION_FAILED;
87 goto premature_exit;
88 }
89
90
91
92
93
94
95 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
96
97 ql_log(ql_log_warn, vha, 0x1177,
98 "Cmd access timeout, cmd=0x%x, Exiting.\n",
99 mcp->mb[0]);
100 return QLA_FUNCTION_TIMEOUT;
101 }
102
103 ha->flags.mbox_busy = 1;
104
105 ha->mcp32 = mcp;
106
107 ql_dbg(ql_dbg_mbx, vha, 0x1178,
108 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
109
110 spin_lock_irqsave(&ha->hardware_lock, flags);
111
112
113 optr = (uint32_t __iomem *)®->ispfx00.mailbox0;
114
115 iptr = mcp->mb;
116 command = mcp->mb[0];
117 mboxes = mcp->out_mb;
118
119 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
120 if (mboxes & BIT_0)
121 WRT_REG_DWORD(optr, *iptr);
122
123 mboxes >>= 1;
124 optr++;
125 iptr++;
126 }
127
128
129 ha->flags.mbox_int = 0;
130 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
131
132 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
133 (uint8_t *)mcp->mb, 16);
134 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
135 ((uint8_t *)mcp->mb + 0x10), 16);
136 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
137 ((uint8_t *)mcp->mb + 0x20), 8);
138
139
140 ql_dbg(ql_dbg_mbx, vha, 0x1179,
141 "Going to unlock irq & waiting for interrupts. "
142 "jiffies=%lx.\n", jiffies);
143
144
145 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
146 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
147
148 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
149 spin_unlock_irqrestore(&ha->hardware_lock, flags);
150
151 WARN_ON_ONCE(wait_for_completion_timeout(&ha->mbx_intr_comp,
152 mcp->tov * HZ) != 0);
153 } else {
154 ql_dbg(ql_dbg_mbx, vha, 0x112c,
155 "Cmd=%x Polling Mode.\n", command);
156
157 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
158 spin_unlock_irqrestore(&ha->hardware_lock, flags);
159
160 wait_time = jiffies + mcp->tov * HZ;
161 while (!ha->flags.mbox_int) {
162 if (time_after(jiffies, wait_time))
163 break;
164
165
166 qla2x00_poll(ha->rsp_q_map[0]);
167
168 if (!ha->flags.mbox_int &&
169 !(IS_QLA2200(ha) &&
170 command == MBC_LOAD_RISC_RAM_EXTENDED))
171 usleep_range(10000, 11000);
172 }
173 ql_dbg(ql_dbg_mbx, vha, 0x112d,
174 "Waited %d sec.\n",
175 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
176 }
177
178
179 if (ha->flags.mbox_int) {
180 uint32_t *iptr2;
181
182 ql_dbg(ql_dbg_mbx, vha, 0x112e,
183 "Cmd=%x completed.\n", command);
184
185
186 ha->flags.mbox_int = 0;
187 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
188
189 if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
190 rval = QLA_FUNCTION_FAILED;
191
192
193 iptr2 = mcp->mb;
194 iptr = (uint32_t *)&ha->mailbox_out32[0];
195 mboxes = mcp->in_mb;
196 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
197 if (mboxes & BIT_0)
198 *iptr2 = *iptr;
199
200 mboxes >>= 1;
201 iptr2++;
202 iptr++;
203 }
204 } else {
205
206 rval = QLA_FUNCTION_TIMEOUT;
207 }
208
209 ha->flags.mbox_busy = 0;
210
211
212 ha->mcp32 = NULL;
213
214 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
215 ql_dbg(ql_dbg_mbx, vha, 0x113a,
216 "checking for additional resp interrupt.\n");
217
218
219 qla2x00_poll(ha->rsp_q_map[0]);
220 }
221
222 if (rval == QLA_FUNCTION_TIMEOUT &&
223 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
224 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
225 ha->flags.eeh_busy) {
226
227 ql_dbg(ql_dbg_mbx, vha, 0x115d,
228 "Timeout, schedule isp_abort_needed.\n");
229
230 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
231 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
232 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
233
234 ql_log(ql_log_info, base_vha, 0x115e,
235 "Mailbox cmd timeout occurred, cmd=0x%x, "
236 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
237 "abort.\n", command, mcp->mb[0],
238 ha->flags.eeh_busy);
239 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
240 qla2xxx_wake_dpc(vha);
241 }
242 } else if (!abort_active) {
243
244 ql_dbg(ql_dbg_mbx, vha, 0x1160,
245 "Timeout, calling abort_isp.\n");
246
247 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
248 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
249 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
250
251 ql_log(ql_log_info, base_vha, 0x1161,
252 "Mailbox cmd timeout occurred, cmd=0x%x, "
253 "mb[0]=0x%x. Scheduling ISP abort ",
254 command, mcp->mb[0]);
255
256 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
257 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
258 if (ha->isp_ops->abort_isp(vha)) {
259
260 set_bit(ISP_ABORT_NEEDED,
261 &vha->dpc_flags);
262 }
263 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
264 ql_dbg(ql_dbg_mbx, vha, 0x1162,
265 "Finished abort_isp.\n");
266 }
267 }
268 }
269
270premature_exit:
271
272 complete(&ha->mbx_cmd_comp);
273
274 if (rval) {
275 ql_log(ql_log_warn, base_vha, 0x1163,
276 "**** Failed=%x mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
277 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
278 command);
279 } else {
280 ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
281 }
282
283 return rval;
284}
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297
298
299int
300qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
301{
302 int rval;
303 struct mbx_cmd_32 mc;
304 struct mbx_cmd_32 *mcp = &mc;
305
306 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
307 "Entered %s.\n", __func__);
308
309 mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
310 mcp->out_mb = MBX_0;
311 mcp->in_mb = MBX_0;
312 if (tmo)
313 mcp->tov = tmo;
314 else
315 mcp->tov = MBX_TOV_SECONDS;
316 mcp->flags = 0;
317 rval = qlafx00_mailbox_command(vha, mcp);
318
319 if (rval != QLA_SUCCESS) {
320 ql_dbg(ql_dbg_mbx, vha, 0x1167,
321 "Failed=%x.\n", rval);
322 } else {
323 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
324 "Done %s.\n", __func__);
325 }
326
327 return rval;
328}
329
330
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341
342
343
344
345static int
346qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
347{
348 int rval;
349 struct mbx_cmd_32 mc;
350 struct mbx_cmd_32 *mcp = &mc;
351
352 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
353 "Entered %s.\n", __func__);
354
355 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
356 mcp->out_mb = MBX_0;
357 mcp->in_mb = MBX_1|MBX_0;
358 mcp->tov = MBX_TOV_SECONDS;
359 mcp->flags = 0;
360 rval = qlafx00_mailbox_command(vha, mcp);
361
362
363 states[0] = mcp->mb[1];
364
365 if (rval != QLA_SUCCESS) {
366 ql_dbg(ql_dbg_mbx, vha, 0x116a,
367 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
368 } else {
369 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
370 "Done %s.\n", __func__);
371 }
372 return rval;
373}
374
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389
390
391
392int
393qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
394{
395 int rval;
396 struct mbx_cmd_32 mc;
397 struct mbx_cmd_32 *mcp = &mc;
398 struct qla_hw_data *ha = vha->hw;
399
400 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
401 "Entered %s.\n", __func__);
402
403 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
404
405 mcp->mb[1] = 0;
406 mcp->mb[2] = MSD(ha->init_cb_dma);
407 mcp->mb[3] = LSD(ha->init_cb_dma);
408
409 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
410 mcp->in_mb = MBX_0;
411 mcp->buf_size = size;
412 mcp->flags = MBX_DMA_OUT;
413 mcp->tov = MBX_TOV_SECONDS;
414 rval = qlafx00_mailbox_command(vha, mcp);
415
416 if (rval != QLA_SUCCESS) {
417 ql_dbg(ql_dbg_mbx, vha, 0x116d,
418 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
419 } else {
420 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
421 "Done %s.\n", __func__);
422 }
423 return rval;
424}
425
426
427
428
429static int
430qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
431{
432 int rval;
433 struct mbx_cmd_32 mc;
434 struct mbx_cmd_32 *mcp = &mc;
435
436 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
437 "Entered %s.\n", __func__);
438
439
440 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
441 mcp->mb[1] = 0xAAAA;
442 mcp->mb[2] = 0x5555;
443 mcp->mb[3] = 0xAA55;
444 mcp->mb[4] = 0x55AA;
445 mcp->mb[5] = 0xA5A5;
446 mcp->mb[6] = 0x5A5A;
447 mcp->mb[7] = 0x2525;
448 mcp->mb[8] = 0xBBBB;
449 mcp->mb[9] = 0x6666;
450 mcp->mb[10] = 0xBB66;
451 mcp->mb[11] = 0x66BB;
452 mcp->mb[12] = 0xB6B6;
453 mcp->mb[13] = 0x6B6B;
454 mcp->mb[14] = 0x3636;
455 mcp->mb[15] = 0xCCCC;
456
457
458 mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
459 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
460 mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
461 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
462 mcp->buf_size = 0;
463 mcp->flags = MBX_DMA_OUT;
464 mcp->tov = MBX_TOV_SECONDS;
465 rval = qlafx00_mailbox_command(vha, mcp);
466 if (rval == QLA_SUCCESS) {
467 if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
468 mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
469 rval = QLA_FUNCTION_FAILED;
470 if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
471 mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
472 rval = QLA_FUNCTION_FAILED;
473 if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
474 mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
475 rval = QLA_FUNCTION_FAILED;
476 if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
477 mcp->mb[31] != 0xCCCC)
478 rval = QLA_FUNCTION_FAILED;
479 }
480
481 if (rval != QLA_SUCCESS) {
482 ql_dbg(ql_dbg_mbx, vha, 0x1170,
483 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
484 } else {
485 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
486 "Done %s.\n", __func__);
487 }
488 return rval;
489}
490
491
492
493
494
495
496
497int
498qlafx00_pci_config(scsi_qla_host_t *vha)
499{
500 uint16_t w;
501 struct qla_hw_data *ha = vha->hw;
502
503 pci_set_master(ha->pdev);
504 pci_try_set_mwi(ha->pdev);
505
506 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
507 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
508 w &= ~PCI_COMMAND_INTX_DISABLE;
509 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
510
511
512 if (pci_is_pcie(ha->pdev))
513 pcie_set_readrq(ha->pdev, 2048);
514
515 ha->chip_revision = ha->pdev->revision;
516
517 return QLA_SUCCESS;
518}
519
520
521
522
523
524
525static inline void
526qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
527{
528 unsigned long flags = 0;
529 struct qla_hw_data *ha = vha->hw;
530 int i, core;
531 uint32_t cnt;
532 uint32_t reg_val;
533
534 spin_lock_irqsave(&ha->hardware_lock, flags);
535
536 QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
537 QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
538
539
540 QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
541 QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
542 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
543 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
544
545
546 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
547 reg_val &= ~(1<<12);
548 QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
549
550 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
551 reg_val &= ~(1<<12);
552 QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
553
554 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
555 reg_val &= ~(1<<12);
556 QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
557
558 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
559 reg_val &= ~(1<<12);
560 QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
561
562 for (i = 0; i < 100000; i++) {
563 if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
564 (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
565 break;
566 udelay(100);
567 }
568
569
570 for (i = 0; i < 4; i++) {
571 QLAFX00_SET_HBA_SOC_REG(ha,
572 (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
573 QLAFX00_SET_HBA_SOC_REG(ha,
574 (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
575 }
576
577
578 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
579
580
581 QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
582 QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
583
584
585 for (i = 0; i < 5; i++) {
586 QLAFX00_SET_HBA_SOC_REG(ha,
587 (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
588 }
589
590
591 for (i = 0; i < 115; i++) {
592 QLAFX00_SET_HBA_SOC_REG(ha,
593 (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
594 }
595
596
597 for (core = 0; core < 4; core++)
598 for (i = 0; i < 8; i++)
599 QLAFX00_SET_HBA_SOC_REG(ha,
600 (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
601
602
603 for (core = 0; core < 4; core++)
604 QLAFX00_SET_HBA_SOC_REG(ha,
605 (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
606
607
608 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
609 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
610
611
612 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
613
614
615 QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
616
617 spin_unlock_irqrestore(&ha->hardware_lock, flags);
618
619
620 for (cnt = 10; cnt; cnt--) {
621 msleep(1000);
622 barrier();
623 }
624}
625
626
627
628
629
630
631
632int
633qlafx00_soft_reset(scsi_qla_host_t *vha)
634{
635 struct qla_hw_data *ha = vha->hw;
636 int rval = QLA_FUNCTION_FAILED;
637
638 if (unlikely(pci_channel_offline(ha->pdev) &&
639 ha->flags.pci_channel_io_perm_failure))
640 return rval;
641
642 ha->isp_ops->disable_intrs(ha);
643 qlafx00_soc_cpu_reset(vha);
644
645 return QLA_SUCCESS;
646}
647
648
649
650
651
652
653
654int
655qlafx00_chip_diag(scsi_qla_host_t *vha)
656{
657 int rval = 0;
658 struct qla_hw_data *ha = vha->hw;
659 struct req_que *req = ha->req_q_map[0];
660
661 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
662
663 rval = qlafx00_mbx_reg_test(vha);
664 if (rval) {
665 ql_log(ql_log_warn, vha, 0x1165,
666 "Failed mailbox send register test\n");
667 } else {
668
669 rval = QLA_SUCCESS;
670 }
671 return rval;
672}
673
674void
675qlafx00_config_rings(struct scsi_qla_host *vha)
676{
677 struct qla_hw_data *ha = vha->hw;
678 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
679
680 WRT_REG_DWORD(®->req_q_in, 0);
681 WRT_REG_DWORD(®->req_q_out, 0);
682
683 WRT_REG_DWORD(®->rsp_q_in, 0);
684 WRT_REG_DWORD(®->rsp_q_out, 0);
685
686
687 RD_REG_DWORD(®->rsp_q_out);
688}
689
690char *
691qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
692{
693 struct qla_hw_data *ha = vha->hw;
694
695 if (pci_is_pcie(ha->pdev))
696 strlcpy(str, "PCIe iSA", str_len);
697 return str;
698}
699
700char *
701qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
702{
703 struct qla_hw_data *ha = vha->hw;
704
705 snprintf(str, size, "%s", ha->mr.fw_version);
706 return str;
707}
708
709void
710qlafx00_enable_intrs(struct qla_hw_data *ha)
711{
712 unsigned long flags = 0;
713
714 spin_lock_irqsave(&ha->hardware_lock, flags);
715 ha->interrupts_on = 1;
716 QLAFX00_ENABLE_ICNTRL_REG(ha);
717 spin_unlock_irqrestore(&ha->hardware_lock, flags);
718}
719
720void
721qlafx00_disable_intrs(struct qla_hw_data *ha)
722{
723 unsigned long flags = 0;
724
725 spin_lock_irqsave(&ha->hardware_lock, flags);
726 ha->interrupts_on = 0;
727 QLAFX00_DISABLE_ICNTRL_REG(ha);
728 spin_unlock_irqrestore(&ha->hardware_lock, flags);
729}
730
731int
732qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
733{
734 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
735}
736
737int
738qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
739{
740 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
741}
742
743int
744qlafx00_loop_reset(scsi_qla_host_t *vha)
745{
746 int ret;
747 struct fc_port *fcport;
748 struct qla_hw_data *ha = vha->hw;
749
750 if (ql2xtargetreset) {
751 list_for_each_entry(fcport, &vha->vp_fcports, list) {
752 if (fcport->port_type != FCT_TARGET)
753 continue;
754
755 ret = ha->isp_ops->target_reset(fcport, 0, 0);
756 if (ret != QLA_SUCCESS) {
757 ql_dbg(ql_dbg_taskm, vha, 0x803d,
758 "Bus Reset failed: Reset=%d "
759 "d_id=%x.\n", ret, fcport->d_id.b24);
760 }
761 }
762 }
763 return QLA_SUCCESS;
764}
765
766int
767qlafx00_iospace_config(struct qla_hw_data *ha)
768{
769 if (pci_request_selected_regions(ha->pdev, ha->bars,
770 QLA2XXX_DRIVER_NAME)) {
771 ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
772 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
773 pci_name(ha->pdev));
774 goto iospace_error_exit;
775 }
776
777
778 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
779 ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
780 "Invalid pci I/O region size (%s).\n",
781 pci_name(ha->pdev));
782 goto iospace_error_exit;
783 }
784 if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
785 ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
786 "Invalid PCI mem BAR0 region size (%s), aborting\n",
787 pci_name(ha->pdev));
788 goto iospace_error_exit;
789 }
790
791 ha->cregbase =
792 ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
793 if (!ha->cregbase) {
794 ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
795 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
796 goto iospace_error_exit;
797 }
798
799 if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
800 ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
801 "region #2 not an MMIO resource (%s), aborting\n",
802 pci_name(ha->pdev));
803 goto iospace_error_exit;
804 }
805 if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
806 ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
807 "Invalid PCI mem BAR2 region size (%s), aborting\n",
808 pci_name(ha->pdev));
809 goto iospace_error_exit;
810 }
811
812 ha->iobase =
813 ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
814 if (!ha->iobase) {
815 ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
816 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
817 goto iospace_error_exit;
818 }
819
820
821 ha->max_req_queues = ha->max_rsp_queues = 1;
822
823 ql_log_pci(ql_log_info, ha->pdev, 0x012c,
824 "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
825 ha->bars, ha->cregbase, ha->iobase);
826
827 return 0;
828
829iospace_error_exit:
830 return -ENOMEM;
831}
832
833static void
834qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
835{
836 struct qla_hw_data *ha = vha->hw;
837 struct req_que *req = ha->req_q_map[0];
838 struct rsp_que *rsp = ha->rsp_q_map[0];
839
840 req->length_fx00 = req->length;
841 req->ring_fx00 = req->ring;
842 req->dma_fx00 = req->dma;
843
844 rsp->length_fx00 = rsp->length;
845 rsp->ring_fx00 = rsp->ring;
846 rsp->dma_fx00 = rsp->dma;
847
848 ql_dbg(ql_dbg_init, vha, 0x012d,
849 "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
850 "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
851 req->length_fx00, (u64)req->dma_fx00);
852
853 ql_dbg(ql_dbg_init, vha, 0x012e,
854 "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
855 "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
856 rsp->length_fx00, (u64)rsp->dma_fx00);
857}
858
859static int
860qlafx00_config_queues(struct scsi_qla_host *vha)
861{
862 struct qla_hw_data *ha = vha->hw;
863 struct req_que *req = ha->req_q_map[0];
864 struct rsp_que *rsp = ha->rsp_q_map[0];
865 dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
866
867 req->length = ha->req_que_len;
868 req->ring = (void __force *)ha->iobase + ha->req_que_off;
869 req->dma = bar2_hdl + ha->req_que_off;
870 if ((!req->ring) || (req->length == 0)) {
871 ql_log_pci(ql_log_info, ha->pdev, 0x012f,
872 "Unable to allocate memory for req_ring\n");
873 return QLA_FUNCTION_FAILED;
874 }
875
876 ql_dbg(ql_dbg_init, vha, 0x0130,
877 "req: %p req_ring pointer %p req len 0x%x "
878 "req off 0x%x\n, req->dma: 0x%llx",
879 req, req->ring, req->length,
880 ha->req_que_off, (u64)req->dma);
881
882 rsp->length = ha->rsp_que_len;
883 rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off;
884 rsp->dma = bar2_hdl + ha->rsp_que_off;
885 if ((!rsp->ring) || (rsp->length == 0)) {
886 ql_log_pci(ql_log_info, ha->pdev, 0x0131,
887 "Unable to allocate memory for rsp_ring\n");
888 return QLA_FUNCTION_FAILED;
889 }
890
891 ql_dbg(ql_dbg_init, vha, 0x0132,
892 "rsp: %p rsp_ring pointer %p rsp len 0x%x "
893 "rsp off 0x%x, rsp->dma: 0x%llx\n",
894 rsp, rsp->ring, rsp->length,
895 ha->rsp_que_off, (u64)rsp->dma);
896
897 return QLA_SUCCESS;
898}
899
900static int
901qlafx00_init_fw_ready(scsi_qla_host_t *vha)
902{
903 int rval = 0;
904 unsigned long wtime;
905 uint16_t wait_time;
906 struct qla_hw_data *ha = vha->hw;
907 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
908 uint32_t aenmbx, aenmbx7 = 0;
909 uint32_t pseudo_aen;
910 uint32_t state[5];
911 bool done = false;
912
913
914 wait_time = 30;
915
916 pseudo_aen = RD_REG_DWORD(®->pseudoaen);
917 if (pseudo_aen == 1) {
918 aenmbx7 = RD_REG_DWORD(®->initval7);
919 ha->mbx_intr_code = MSW(aenmbx7);
920 ha->rqstq_intr_code = LSW(aenmbx7);
921 rval = qlafx00_driver_shutdown(vha, 10);
922 if (rval != QLA_SUCCESS)
923 qlafx00_soft_reset(vha);
924 }
925
926
927 wtime = jiffies + (wait_time * HZ);
928 do {
929 aenmbx = RD_REG_DWORD(®->aenmailbox0);
930 barrier();
931 ql_dbg(ql_dbg_mbx, vha, 0x0133,
932 "aenmbx: 0x%x\n", aenmbx);
933
934 switch (aenmbx) {
935 case MBA_FW_NOT_STARTED:
936 case MBA_FW_STARTING:
937 break;
938
939 case MBA_SYSTEM_ERR:
940 case MBA_REQ_TRANSFER_ERR:
941 case MBA_RSP_TRANSFER_ERR:
942 case MBA_FW_INIT_FAILURE:
943 qlafx00_soft_reset(vha);
944 break;
945
946 case MBA_FW_RESTART_CMPLT:
947
948 aenmbx7 = RD_REG_DWORD(®->aenmailbox7);
949 ha->mbx_intr_code = MSW(aenmbx7);
950 ha->rqstq_intr_code = LSW(aenmbx7);
951 ha->req_que_off = RD_REG_DWORD(®->aenmailbox1);
952 ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3);
953 ha->req_que_len = RD_REG_DWORD(®->aenmailbox5);
954 ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6);
955 WRT_REG_DWORD(®->aenmailbox0, 0);
956 RD_REG_DWORD_RELAXED(®->aenmailbox0);
957 ql_dbg(ql_dbg_init, vha, 0x0134,
958 "f/w returned mbx_intr_code: 0x%x, "
959 "rqstq_intr_code: 0x%x\n",
960 ha->mbx_intr_code, ha->rqstq_intr_code);
961 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
962 rval = QLA_SUCCESS;
963 done = true;
964 break;
965
966 default:
967 if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
968 break;
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986 aenmbx7 = RD_REG_DWORD(®->initval7);
987 ha->mbx_intr_code = MSW(aenmbx7);
988 ha->rqstq_intr_code = LSW(aenmbx7);
989 ha->req_que_off = RD_REG_DWORD(®->initval1);
990 ha->rsp_que_off = RD_REG_DWORD(®->initval3);
991 ha->req_que_len = RD_REG_DWORD(®->initval5);
992 ha->rsp_que_len = RD_REG_DWORD(®->initval6);
993 ql_dbg(ql_dbg_init, vha, 0x0135,
994 "f/w returned mbx_intr_code: 0x%x, "
995 "rqstq_intr_code: 0x%x\n",
996 ha->mbx_intr_code, ha->rqstq_intr_code);
997 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
998
999
1000 rval = qlafx00_get_firmware_state(vha, state);
1001 if (rval != QLA_SUCCESS) {
1002
1003 break;
1004 }
1005
1006 if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
1007
1008
1009
1010 rval = QLA_SUCCESS;
1011 done = true;
1012 break;
1013 }
1014
1015
1016
1017
1018
1019 ql_dbg(ql_dbg_init, vha, 0x0136,
1020 "Sending Driver shutdown fw_state 0x%x\n",
1021 state[0]);
1022
1023 rval = qlafx00_driver_shutdown(vha, 10);
1024 if (rval != QLA_SUCCESS) {
1025 rval = QLA_FUNCTION_FAILED;
1026 break;
1027 }
1028 msleep(500);
1029
1030 wtime = jiffies + (wait_time * HZ);
1031 break;
1032 }
1033
1034 if (!done) {
1035 if (time_after_eq(jiffies, wtime)) {
1036 ql_dbg(ql_dbg_init, vha, 0x0137,
1037 "Init f/w failed: aen[7]: 0x%x\n",
1038 RD_REG_DWORD(®->aenmailbox7));
1039 rval = QLA_FUNCTION_FAILED;
1040 done = true;
1041 break;
1042 }
1043
1044 msleep(500);
1045 }
1046 } while (!done);
1047
1048 if (rval)
1049 ql_dbg(ql_dbg_init, vha, 0x0138,
1050 "%s **** FAILED ****.\n", __func__);
1051 else
1052 ql_dbg(ql_dbg_init, vha, 0x0139,
1053 "%s **** SUCCESS ****.\n", __func__);
1054
1055 return rval;
1056}
1057
1058
1059
1060
1061
1062
1063
1064int
1065qlafx00_fw_ready(scsi_qla_host_t *vha)
1066{
1067 int rval;
1068 unsigned long wtime;
1069 uint16_t wait_time;
1070 uint32_t state[5];
1071
1072 rval = QLA_SUCCESS;
1073
1074 wait_time = 10;
1075
1076
1077 wtime = jiffies + (wait_time * HZ);
1078
1079
1080 if (!vha->flags.init_done)
1081 ql_dbg(ql_dbg_init, vha, 0x013a,
1082 "Waiting for init to complete...\n");
1083
1084 do {
1085 rval = qlafx00_get_firmware_state(vha, state);
1086
1087 if (rval == QLA_SUCCESS) {
1088 if (state[0] == FSTATE_FX00_INITIALIZED) {
1089 ql_dbg(ql_dbg_init, vha, 0x013b,
1090 "fw_state=%x\n", state[0]);
1091 rval = QLA_SUCCESS;
1092 break;
1093 }
1094 }
1095 rval = QLA_FUNCTION_FAILED;
1096
1097 if (time_after_eq(jiffies, wtime))
1098 break;
1099
1100
1101 msleep(500);
1102
1103 ql_dbg(ql_dbg_init, vha, 0x013c,
1104 "fw_state=%x curr time=%lx.\n", state[0], jiffies);
1105 } while (1);
1106
1107
1108 if (rval)
1109 ql_dbg(ql_dbg_init, vha, 0x013d,
1110 "Firmware ready **** FAILED ****.\n");
1111 else
1112 ql_dbg(ql_dbg_init, vha, 0x013e,
1113 "Firmware ready **** SUCCESS ****.\n");
1114
1115 return rval;
1116}
1117
1118static int
1119qlafx00_find_all_targets(scsi_qla_host_t *vha,
1120 struct list_head *new_fcports)
1121{
1122 int rval;
1123 uint16_t tgt_id;
1124 fc_port_t *fcport, *new_fcport;
1125 int found;
1126 struct qla_hw_data *ha = vha->hw;
1127
1128 rval = QLA_SUCCESS;
1129
1130 if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1131 return QLA_FUNCTION_FAILED;
1132
1133 if ((atomic_read(&vha->loop_down_timer) ||
1134 STATE_TRANSITION(vha))) {
1135 atomic_set(&vha->loop_down_timer, 0);
1136 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1137 return QLA_FUNCTION_FAILED;
1138 }
1139
1140 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
1141 "Listing Target bit map...\n");
1142 ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha, 0x2089,
1143 ha->gid_list, 32);
1144
1145
1146 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1147 if (new_fcport == NULL)
1148 return QLA_MEMORY_ALLOC_FAILED;
1149
1150 for_each_set_bit(tgt_id, (void *)ha->gid_list,
1151 QLAFX00_TGT_NODE_LIST_SIZE) {
1152
1153
1154 new_fcport->tgt_id = tgt_id;
1155 rval = qlafx00_fx_disc(vha, new_fcport,
1156 FXDISC_GET_TGT_NODE_INFO);
1157 if (rval != QLA_SUCCESS) {
1158 ql_log(ql_log_warn, vha, 0x208a,
1159 "Target info scan failed -- assuming zero-entry "
1160 "result...\n");
1161 continue;
1162 }
1163
1164
1165 found = 0;
1166 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1167 if (memcmp(new_fcport->port_name,
1168 fcport->port_name, WWN_SIZE))
1169 continue;
1170
1171 found++;
1172
1173
1174
1175
1176
1177 if (fcport->tgt_id == new_fcport->tgt_id &&
1178 atomic_read(&fcport->state) == FCS_ONLINE)
1179 break;
1180
1181
1182
1183
1184 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
1185 "TGT-ID Change(%s): Present tgt id: "
1186 "0x%x state: 0x%x "
1187 "wwnn = %llx wwpn = %llx.\n",
1188 __func__, fcport->tgt_id,
1189 atomic_read(&fcport->state),
1190 (unsigned long long)wwn_to_u64(fcport->node_name),
1191 (unsigned long long)wwn_to_u64(fcport->port_name));
1192
1193 ql_log(ql_log_info, vha, 0x208c,
1194 "TGT-ID Announce(%s): Discovered tgt "
1195 "id 0x%x wwnn = %llx "
1196 "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
1197 (unsigned long long)
1198 wwn_to_u64(new_fcport->node_name),
1199 (unsigned long long)
1200 wwn_to_u64(new_fcport->port_name));
1201
1202 if (atomic_read(&fcport->state) != FCS_ONLINE) {
1203 fcport->old_tgt_id = fcport->tgt_id;
1204 fcport->tgt_id = new_fcport->tgt_id;
1205 ql_log(ql_log_info, vha, 0x208d,
1206 "TGT-ID: New fcport Added: %p\n", fcport);
1207 qla2x00_update_fcport(vha, fcport);
1208 } else {
1209 ql_log(ql_log_info, vha, 0x208e,
1210 " Existing TGT-ID %x did not get "
1211 " offline event from firmware.\n",
1212 fcport->old_tgt_id);
1213 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1214 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1215 kfree(new_fcport);
1216 return rval;
1217 }
1218 break;
1219 }
1220
1221 if (found)
1222 continue;
1223
1224
1225 list_add_tail(&new_fcport->list, new_fcports);
1226
1227
1228 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1229 if (new_fcport == NULL)
1230 return QLA_MEMORY_ALLOC_FAILED;
1231 }
1232
1233 kfree(new_fcport);
1234 return rval;
1235}
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248static int
1249qlafx00_configure_all_targets(scsi_qla_host_t *vha)
1250{
1251 int rval;
1252 fc_port_t *fcport, *rmptemp;
1253 LIST_HEAD(new_fcports);
1254
1255 rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1256 FXDISC_GET_TGT_NODE_LIST);
1257 if (rval != QLA_SUCCESS) {
1258 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1259 return rval;
1260 }
1261
1262 rval = qlafx00_find_all_targets(vha, &new_fcports);
1263 if (rval != QLA_SUCCESS) {
1264 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1265 return rval;
1266 }
1267
1268
1269
1270
1271 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1272 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1273 break;
1274
1275 if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
1276 if (fcport->port_type != FCT_INITIATOR)
1277 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1278 }
1279 }
1280
1281
1282
1283
1284 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1285 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1286 break;
1287
1288 qla2x00_update_fcport(vha, fcport);
1289 list_move_tail(&fcport->list, &vha->vp_fcports);
1290 ql_log(ql_log_info, vha, 0x208f,
1291 "Attach new target id 0x%x wwnn = %llx "
1292 "wwpn = %llx.\n",
1293 fcport->tgt_id,
1294 (unsigned long long)wwn_to_u64(fcport->node_name),
1295 (unsigned long long)wwn_to_u64(fcport->port_name));
1296 }
1297
1298
1299 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1300 list_del(&fcport->list);
1301 kfree(fcport);
1302 }
1303
1304 return rval;
1305}
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319int
1320qlafx00_configure_devices(scsi_qla_host_t *vha)
1321{
1322 int rval;
1323 unsigned long flags;
1324
1325 rval = QLA_SUCCESS;
1326
1327 flags = vha->dpc_flags;
1328
1329 ql_dbg(ql_dbg_disc, vha, 0x2090,
1330 "Configure devices -- dpc flags =0x%lx\n", flags);
1331
1332 rval = qlafx00_configure_all_targets(vha);
1333
1334 if (rval == QLA_SUCCESS) {
1335 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1336 rval = QLA_FUNCTION_FAILED;
1337 } else {
1338 atomic_set(&vha->loop_state, LOOP_READY);
1339 ql_log(ql_log_info, vha, 0x2091,
1340 "Device Ready\n");
1341 }
1342 }
1343
1344 if (rval) {
1345 ql_dbg(ql_dbg_disc, vha, 0x2092,
1346 "%s *** FAILED ***.\n", __func__);
1347 } else {
1348 ql_dbg(ql_dbg_disc, vha, 0x2093,
1349 "%s: exiting normally.\n", __func__);
1350 }
1351 return rval;
1352}
1353
1354static void
1355qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
1356{
1357 struct qla_hw_data *ha = vha->hw;
1358 fc_port_t *fcport;
1359
1360 vha->flags.online = 0;
1361 ha->mr.fw_hbt_en = 0;
1362
1363 if (!critemp) {
1364 ha->flags.chip_reset_done = 0;
1365 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1366 vha->qla_stats.total_isp_aborts++;
1367 ql_log(ql_log_info, vha, 0x013f,
1368 "Performing ISP error recovery - ha = %p.\n", ha);
1369 ha->isp_ops->reset_chip(vha);
1370 }
1371
1372 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
1373 atomic_set(&vha->loop_state, LOOP_DOWN);
1374 atomic_set(&vha->loop_down_timer,
1375 QLAFX00_LOOP_DOWN_TIME);
1376 } else {
1377 if (!atomic_read(&vha->loop_down_timer))
1378 atomic_set(&vha->loop_down_timer,
1379 QLAFX00_LOOP_DOWN_TIME);
1380 }
1381
1382
1383 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1384 fcport->flags = 0;
1385 if (atomic_read(&fcport->state) == FCS_ONLINE)
1386 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1387 }
1388
1389 if (!ha->flags.eeh_busy) {
1390 if (critemp) {
1391 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
1392 } else {
1393
1394 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
1395 }
1396 }
1397
1398 qla2x00_free_irqs(vha);
1399 if (critemp)
1400 set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
1401 else
1402 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1403
1404
1405 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1406
1407 ql_log(ql_log_info, vha, 0x0140,
1408 "%s Done done - ha=%p.\n", __func__, ha);
1409}
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420void
1421qlafx00_init_response_q_entries(struct rsp_que *rsp)
1422{
1423 uint16_t cnt;
1424 response_t *pkt;
1425
1426 rsp->ring_ptr = rsp->ring;
1427 rsp->ring_index = 0;
1428 rsp->status_srb = NULL;
1429 pkt = rsp->ring_ptr;
1430 for (cnt = 0; cnt < rsp->length; cnt++) {
1431 pkt->signature = RESPONSE_PROCESSED;
1432 WRT_REG_DWORD((void __force __iomem *)&pkt->signature,
1433 RESPONSE_PROCESSED);
1434 pkt++;
1435 }
1436}
1437
1438int
1439qlafx00_rescan_isp(scsi_qla_host_t *vha)
1440{
1441 uint32_t status = QLA_FUNCTION_FAILED;
1442 struct qla_hw_data *ha = vha->hw;
1443 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1444 uint32_t aenmbx7;
1445
1446 qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
1447
1448 aenmbx7 = RD_REG_DWORD(®->aenmailbox7);
1449 ha->mbx_intr_code = MSW(aenmbx7);
1450 ha->rqstq_intr_code = LSW(aenmbx7);
1451 ha->req_que_off = RD_REG_DWORD(®->aenmailbox1);
1452 ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3);
1453 ha->req_que_len = RD_REG_DWORD(®->aenmailbox5);
1454 ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6);
1455
1456 ql_dbg(ql_dbg_disc, vha, 0x2094,
1457 "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
1458 " Req que offset 0x%x Rsp que offset 0x%x\n",
1459 ha->mbx_intr_code, ha->rqstq_intr_code,
1460 ha->req_que_off, ha->rsp_que_len);
1461
1462
1463 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1464
1465 status = qla2x00_init_rings(vha);
1466 if (!status) {
1467 vha->flags.online = 1;
1468
1469
1470 if ((vha->device_flags & DFLG_NO_CABLE))
1471 status = 0;
1472
1473 if (qlafx00_fx_disc(vha,
1474 &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
1475 ql_dbg(ql_dbg_disc, vha, 0x2095,
1476 "failed to register host info\n");
1477 }
1478 scsi_unblock_requests(vha->host);
1479 return status;
1480}
1481
1482void
1483qlafx00_timer_routine(scsi_qla_host_t *vha)
1484{
1485 struct qla_hw_data *ha = vha->hw;
1486 uint32_t fw_heart_beat;
1487 uint32_t aenmbx0;
1488 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1489 uint32_t tempc;
1490
1491
1492 if (ha->mr.fw_hbt_cnt)
1493 ha->mr.fw_hbt_cnt--;
1494 else {
1495 if ((!ha->flags.mr_reset_hdlr_active) &&
1496 (!test_bit(UNLOADING, &vha->dpc_flags)) &&
1497 (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
1498 (ha->mr.fw_hbt_en)) {
1499 fw_heart_beat = RD_REG_DWORD(®->fwheartbeat);
1500 if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
1501 ha->mr.old_fw_hbt_cnt = fw_heart_beat;
1502 ha->mr.fw_hbt_miss_cnt = 0;
1503 } else {
1504 ha->mr.fw_hbt_miss_cnt++;
1505 if (ha->mr.fw_hbt_miss_cnt ==
1506 QLAFX00_HEARTBEAT_MISS_CNT) {
1507 set_bit(ISP_ABORT_NEEDED,
1508 &vha->dpc_flags);
1509 qla2xxx_wake_dpc(vha);
1510 ha->mr.fw_hbt_miss_cnt = 0;
1511 }
1512 }
1513 }
1514 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
1515 }
1516
1517 if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
1518
1519 aenmbx0 = RD_REG_DWORD(®->aenmailbox0);
1520 if (ha->mr.fw_reset_timer_exp) {
1521 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1522 qla2xxx_wake_dpc(vha);
1523 ha->mr.fw_reset_timer_exp = 0;
1524 } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
1525
1526 set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
1527 clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1528 qla2xxx_wake_dpc(vha);
1529 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1530 } else if ((aenmbx0 == MBA_FW_STARTING) &&
1531 (!ha->mr.fw_hbt_en)) {
1532 ha->mr.fw_hbt_en = 1;
1533 } else if (!ha->mr.fw_reset_timer_tick) {
1534 if (aenmbx0 == ha->mr.old_aenmbx0_state)
1535 ha->mr.fw_reset_timer_exp = 1;
1536 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1537 } else if (aenmbx0 == 0xFFFFFFFF) {
1538 uint32_t data0, data1;
1539
1540 data0 = QLAFX00_RD_REG(ha,
1541 QLAFX00_BAR1_BASE_ADDR_REG);
1542 data1 = QLAFX00_RD_REG(ha,
1543 QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
1544
1545 data0 &= 0xffff0000;
1546 data1 &= 0x0000ffff;
1547
1548 QLAFX00_WR_REG(ha,
1549 QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
1550 (data0 | data1));
1551 } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
1552 ha->mr.fw_reset_timer_tick =
1553 QLAFX00_MAX_RESET_INTERVAL;
1554 } else if (aenmbx0 == MBA_FW_RESET_FCT) {
1555 ha->mr.fw_reset_timer_tick =
1556 QLAFX00_MAX_RESET_INTERVAL;
1557 }
1558 if (ha->mr.old_aenmbx0_state != aenmbx0) {
1559 ha->mr.old_aenmbx0_state = aenmbx0;
1560 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1561 }
1562 ha->mr.fw_reset_timer_tick--;
1563 }
1564 if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
1565
1566
1567
1568
1569 if (ha->mr.fw_critemp_timer_tick == 0) {
1570 tempc = QLAFX00_GET_TEMPERATURE(ha);
1571 ql_dbg(ql_dbg_timer, vha, 0x6012,
1572 "ISPFx00(%s): Critical temp timer, "
1573 "current SOC temperature: %d\n",
1574 __func__, tempc);
1575 if (tempc < ha->mr.critical_temperature) {
1576 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1577 clear_bit(FX00_CRITEMP_RECOVERY,
1578 &vha->dpc_flags);
1579 qla2xxx_wake_dpc(vha);
1580 }
1581 ha->mr.fw_critemp_timer_tick =
1582 QLAFX00_CRITEMP_INTERVAL;
1583 } else {
1584 ha->mr.fw_critemp_timer_tick--;
1585 }
1586 }
1587 if (ha->mr.host_info_resend) {
1588
1589
1590
1591
1592 if (ha->mr.hinfo_resend_timer_tick == 0) {
1593 ha->mr.host_info_resend = false;
1594 set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
1595 ha->mr.hinfo_resend_timer_tick =
1596 QLAFX00_HINFO_RESEND_INTERVAL;
1597 qla2xxx_wake_dpc(vha);
1598 } else {
1599 ha->mr.hinfo_resend_timer_tick--;
1600 }
1601 }
1602
1603}
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615int
1616qlafx00_reset_initialize(scsi_qla_host_t *vha)
1617{
1618 struct qla_hw_data *ha = vha->hw;
1619
1620 if (vha->device_flags & DFLG_DEV_FAILED) {
1621 ql_dbg(ql_dbg_init, vha, 0x0142,
1622 "Device in failed state\n");
1623 return QLA_SUCCESS;
1624 }
1625
1626 ha->flags.mr_reset_hdlr_active = 1;
1627
1628 if (vha->flags.online) {
1629 scsi_block_requests(vha->host);
1630 qlafx00_abort_isp_cleanup(vha, false);
1631 }
1632
1633 ql_log(ql_log_info, vha, 0x0143,
1634 "(%s): succeeded.\n", __func__);
1635 ha->flags.mr_reset_hdlr_active = 0;
1636 return QLA_SUCCESS;
1637}
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649int
1650qlafx00_abort_isp(scsi_qla_host_t *vha)
1651{
1652 struct qla_hw_data *ha = vha->hw;
1653
1654 if (vha->flags.online) {
1655 if (unlikely(pci_channel_offline(ha->pdev) &&
1656 ha->flags.pci_channel_io_perm_failure)) {
1657 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1658 return QLA_SUCCESS;
1659 }
1660
1661 scsi_block_requests(vha->host);
1662 qlafx00_abort_isp_cleanup(vha, false);
1663 } else {
1664 scsi_block_requests(vha->host);
1665 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1666 vha->qla_stats.total_isp_aborts++;
1667 ha->isp_ops->reset_chip(vha);
1668 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1669
1670 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1671 }
1672
1673 ql_log(ql_log_info, vha, 0x0145,
1674 "(%s): succeeded.\n", __func__);
1675
1676 return QLA_SUCCESS;
1677}
1678
1679static inline fc_port_t*
1680qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
1681{
1682 fc_port_t *fcport;
1683
1684
1685 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1686 if (fcport->tgt_id == tgt_id) {
1687 ql_dbg(ql_dbg_async, vha, 0x5072,
1688 "Matching fcport(%p) found with TGT-ID: 0x%x "
1689 "and Remote TGT_ID: 0x%x\n",
1690 fcport, fcport->tgt_id, tgt_id);
1691 return fcport;
1692 }
1693 }
1694 return NULL;
1695}
1696
1697static void
1698qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
1699{
1700 fc_port_t *fcport;
1701
1702 ql_log(ql_log_info, vha, 0x5073,
1703 "Detach TGT-ID: 0x%x\n", tgt_id);
1704
1705 fcport = qlafx00_get_fcport(vha, tgt_id);
1706 if (!fcport)
1707 return;
1708
1709 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1710
1711 return;
1712}
1713
1714int
1715qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
1716{
1717 int rval = 0;
1718 uint32_t aen_code, aen_data;
1719
1720 aen_code = FCH_EVT_VENDOR_UNIQUE;
1721 aen_data = evt->u.aenfx.evtcode;
1722
1723 switch (evt->u.aenfx.evtcode) {
1724 case QLAFX00_MBA_PORT_UPDATE:
1725 if (evt->u.aenfx.mbx[1] == 0) {
1726 if (evt->u.aenfx.mbx[2] == 1) {
1727 if (!vha->flags.fw_tgt_reported)
1728 vha->flags.fw_tgt_reported = 1;
1729 atomic_set(&vha->loop_down_timer, 0);
1730 atomic_set(&vha->loop_state, LOOP_UP);
1731 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1732 qla2xxx_wake_dpc(vha);
1733 } else if (evt->u.aenfx.mbx[2] == 2) {
1734 qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
1735 }
1736 } else if (evt->u.aenfx.mbx[1] == 0xffff) {
1737 if (evt->u.aenfx.mbx[2] == 1) {
1738 if (!vha->flags.fw_tgt_reported)
1739 vha->flags.fw_tgt_reported = 1;
1740 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1741 } else if (evt->u.aenfx.mbx[2] == 2) {
1742 vha->device_flags |= DFLG_NO_CABLE;
1743 qla2x00_mark_all_devices_lost(vha, 1);
1744 }
1745 }
1746 break;
1747 case QLAFX00_MBA_LINK_UP:
1748 aen_code = FCH_EVT_LINKUP;
1749 aen_data = 0;
1750 break;
1751 case QLAFX00_MBA_LINK_DOWN:
1752 aen_code = FCH_EVT_LINKDOWN;
1753 aen_data = 0;
1754 break;
1755 case QLAFX00_MBA_TEMP_CRIT:
1756 ql_log(ql_log_info, vha, 0x5082,
1757 "Process critical temperature event "
1758 "aenmb[0]: %x\n",
1759 evt->u.aenfx.evtcode);
1760 scsi_block_requests(vha->host);
1761 qlafx00_abort_isp_cleanup(vha, true);
1762 scsi_unblock_requests(vha->host);
1763 break;
1764 }
1765
1766 fc_host_post_event(vha->host, fc_get_event_number(),
1767 aen_code, aen_data);
1768
1769 return rval;
1770}
1771
1772static void
1773qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
1774{
1775 u64 port_name = 0, node_name = 0;
1776
1777 port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
1778 node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
1779
1780 fc_host_node_name(vha->host) = node_name;
1781 fc_host_port_name(vha->host) = port_name;
1782 if (!pinfo->port_type)
1783 vha->hw->current_topology = ISP_CFG_F;
1784 if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
1785 atomic_set(&vha->loop_state, LOOP_READY);
1786 else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
1787 atomic_set(&vha->loop_state, LOOP_DOWN);
1788 vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
1789}
1790
1791static void
1792qla2x00_fxdisc_iocb_timeout(void *data)
1793{
1794 srb_t *sp = data;
1795 struct srb_iocb *lio = &sp->u.iocb_cmd;
1796
1797 complete(&lio->u.fxiocb.fxiocb_comp);
1798}
1799
1800static void qla2x00_fxdisc_sp_done(srb_t *sp, int res)
1801{
1802 struct srb_iocb *lio = &sp->u.iocb_cmd;
1803
1804 complete(&lio->u.fxiocb.fxiocb_comp);
1805}
1806
1807int
1808qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
1809{
1810 srb_t *sp;
1811 struct srb_iocb *fdisc;
1812 int rval = QLA_FUNCTION_FAILED;
1813 struct qla_hw_data *ha = vha->hw;
1814 struct host_system_info *phost_info;
1815 struct register_host_info *preg_hsi;
1816 struct new_utsname *p_sysid = NULL;
1817
1818 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1819 if (!sp)
1820 goto done;
1821
1822 sp->type = SRB_FXIOCB_DCMD;
1823 sp->name = "fxdisc";
1824
1825 fdisc = &sp->u.iocb_cmd;
1826 fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
1827 qla2x00_init_timer(sp, FXDISC_TIMEOUT);
1828
1829 switch (fx_type) {
1830 case FXDISC_GET_CONFIG_INFO:
1831 fdisc->u.fxiocb.flags =
1832 SRB_FXDISC_RESP_DMA_VALID;
1833 fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
1834 break;
1835 case FXDISC_GET_PORT_INFO:
1836 fdisc->u.fxiocb.flags =
1837 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1838 fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
1839 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
1840 break;
1841 case FXDISC_GET_TGT_NODE_INFO:
1842 fdisc->u.fxiocb.flags =
1843 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1844 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
1845 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
1846 break;
1847 case FXDISC_GET_TGT_NODE_LIST:
1848 fdisc->u.fxiocb.flags =
1849 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1850 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
1851 break;
1852 case FXDISC_REG_HOST_INFO:
1853 fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
1854 fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
1855 p_sysid = utsname();
1856 if (!p_sysid) {
1857 ql_log(ql_log_warn, vha, 0x303c,
1858 "Not able to get the system information\n");
1859 goto done_free_sp;
1860 }
1861 break;
1862 case FXDISC_ABORT_IOCTL:
1863 default:
1864 break;
1865 }
1866
1867 if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
1868 fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
1869 fdisc->u.fxiocb.req_len,
1870 &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
1871 if (!fdisc->u.fxiocb.req_addr)
1872 goto done_free_sp;
1873
1874 if (fx_type == FXDISC_REG_HOST_INFO) {
1875 preg_hsi = (struct register_host_info *)
1876 fdisc->u.fxiocb.req_addr;
1877 phost_info = &preg_hsi->hsi;
1878 memset(preg_hsi, 0, sizeof(struct register_host_info));
1879 phost_info->os_type = OS_TYPE_LINUX;
1880 strlcpy(phost_info->sysname, p_sysid->sysname,
1881 sizeof(phost_info->sysname));
1882 strlcpy(phost_info->nodename, p_sysid->nodename,
1883 sizeof(phost_info->nodename));
1884 if (!strcmp(phost_info->nodename, "(none)"))
1885 ha->mr.host_info_resend = true;
1886 strlcpy(phost_info->release, p_sysid->release,
1887 sizeof(phost_info->release));
1888 strlcpy(phost_info->version, p_sysid->version,
1889 sizeof(phost_info->version));
1890 strlcpy(phost_info->machine, p_sysid->machine,
1891 sizeof(phost_info->machine));
1892 strlcpy(phost_info->domainname, p_sysid->domainname,
1893 sizeof(phost_info->domainname));
1894 strlcpy(phost_info->hostdriver, QLA2XXX_VERSION,
1895 sizeof(phost_info->hostdriver));
1896 preg_hsi->utc = (uint64_t)ktime_get_real_seconds();
1897 ql_dbg(ql_dbg_init, vha, 0x0149,
1898 "ISP%04X: Host registration with firmware\n",
1899 ha->pdev->device);
1900 ql_dbg(ql_dbg_init, vha, 0x014a,
1901 "os_type = '%d', sysname = '%s', nodname = '%s'\n",
1902 phost_info->os_type,
1903 phost_info->sysname,
1904 phost_info->nodename);
1905 ql_dbg(ql_dbg_init, vha, 0x014b,
1906 "release = '%s', version = '%s'\n",
1907 phost_info->release,
1908 phost_info->version);
1909 ql_dbg(ql_dbg_init, vha, 0x014c,
1910 "machine = '%s' "
1911 "domainname = '%s', hostdriver = '%s'\n",
1912 phost_info->machine,
1913 phost_info->domainname,
1914 phost_info->hostdriver);
1915 ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
1916 phost_info, sizeof(*phost_info));
1917 }
1918 }
1919
1920 if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
1921 fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
1922 fdisc->u.fxiocb.rsp_len,
1923 &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
1924 if (!fdisc->u.fxiocb.rsp_addr)
1925 goto done_unmap_req;
1926 }
1927
1928 fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
1929 sp->done = qla2x00_fxdisc_sp_done;
1930
1931 rval = qla2x00_start_sp(sp);
1932 if (rval != QLA_SUCCESS)
1933 goto done_unmap_dma;
1934
1935 wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
1936
1937 if (fx_type == FXDISC_GET_CONFIG_INFO) {
1938 struct config_info_data *pinfo =
1939 (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
1940 strlcpy(vha->hw->model_number, pinfo->model_num,
1941 ARRAY_SIZE(vha->hw->model_number));
1942 strlcpy(vha->hw->model_desc, pinfo->model_description,
1943 ARRAY_SIZE(vha->hw->model_desc));
1944 memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
1945 sizeof(vha->hw->mr.symbolic_name));
1946 memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
1947 sizeof(vha->hw->mr.serial_num));
1948 memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
1949 sizeof(vha->hw->mr.hw_version));
1950 memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
1951 sizeof(vha->hw->mr.fw_version));
1952 strim(vha->hw->mr.fw_version);
1953 memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
1954 sizeof(vha->hw->mr.uboot_version));
1955 memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
1956 sizeof(vha->hw->mr.fru_serial_num));
1957 vha->hw->mr.critical_temperature =
1958 (pinfo->nominal_temp_value) ?
1959 pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
1960 ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
1961 QLAFX00_EXTENDED_IO_EN_MASK) != 0;
1962 } else if (fx_type == FXDISC_GET_PORT_INFO) {
1963 struct port_info_data *pinfo =
1964 (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
1965 memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
1966 memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
1967 vha->d_id.b.domain = pinfo->port_id[0];
1968 vha->d_id.b.area = pinfo->port_id[1];
1969 vha->d_id.b.al_pa = pinfo->port_id[2];
1970 qlafx00_update_host_attr(vha, pinfo);
1971 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
1972 pinfo, 16);
1973 } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
1974 struct qlafx00_tgt_node_info *pinfo =
1975 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1976 memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
1977 memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
1978 fcport->port_type = FCT_TARGET;
1979 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
1980 pinfo, 16);
1981 } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
1982 struct qlafx00_tgt_node_info *pinfo =
1983 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1984 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
1985 pinfo, 16);
1986 memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
1987 } else if (fx_type == FXDISC_ABORT_IOCTL)
1988 fdisc->u.fxiocb.result =
1989 (fdisc->u.fxiocb.result ==
1990 cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
1991 cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
1992
1993 rval = le32_to_cpu(fdisc->u.fxiocb.result);
1994
1995done_unmap_dma:
1996 if (fdisc->u.fxiocb.rsp_addr)
1997 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
1998 fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
1999
2000done_unmap_req:
2001 if (fdisc->u.fxiocb.req_addr)
2002 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
2003 fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
2004done_free_sp:
2005 sp->free(sp);
2006done:
2007 return rval;
2008}
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020int
2021qlafx00_initialize_adapter(scsi_qla_host_t *vha)
2022{
2023 int rval;
2024 struct qla_hw_data *ha = vha->hw;
2025 uint32_t tempc;
2026
2027
2028 vha->flags.online = 0;
2029 ha->flags.chip_reset_done = 0;
2030 vha->flags.reset_active = 0;
2031 ha->flags.pci_channel_io_perm_failure = 0;
2032 ha->flags.eeh_busy = 0;
2033 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2034 atomic_set(&vha->loop_state, LOOP_DOWN);
2035 vha->device_flags = DFLG_NO_CABLE;
2036 vha->dpc_flags = 0;
2037 vha->flags.management_server_logged_in = 0;
2038 ha->isp_abort_cnt = 0;
2039 ha->beacon_blink_led = 0;
2040
2041 set_bit(0, ha->req_qid_map);
2042 set_bit(0, ha->rsp_qid_map);
2043
2044 ql_dbg(ql_dbg_init, vha, 0x0147,
2045 "Configuring PCI space...\n");
2046
2047 rval = ha->isp_ops->pci_config(vha);
2048 if (rval) {
2049 ql_log(ql_log_warn, vha, 0x0148,
2050 "Unable to configure PCI space.\n");
2051 return rval;
2052 }
2053
2054 rval = qlafx00_init_fw_ready(vha);
2055 if (rval != QLA_SUCCESS)
2056 return rval;
2057
2058 qlafx00_save_queue_ptrs(vha);
2059
2060 rval = qlafx00_config_queues(vha);
2061 if (rval != QLA_SUCCESS)
2062 return rval;
2063
2064
2065
2066
2067
2068 rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
2069 if (rval != QLA_SUCCESS)
2070 return rval;
2071
2072 rval = qla2x00_init_rings(vha);
2073 ha->flags.chip_reset_done = 1;
2074
2075 tempc = QLAFX00_GET_TEMPERATURE(ha);
2076 ql_dbg(ql_dbg_init, vha, 0x0152,
2077 "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
2078 __func__, tempc);
2079
2080 return rval;
2081}
2082
2083uint32_t
2084qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
2085 char *buf)
2086{
2087 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
2088 int rval = QLA_FUNCTION_FAILED;
2089 uint32_t state[1];
2090
2091 if (qla2x00_reset_active(vha))
2092 ql_log(ql_log_warn, vha, 0x70ce,
2093 "ISP reset active.\n");
2094 else if (!vha->hw->flags.eeh_busy) {
2095 rval = qlafx00_get_firmware_state(vha, state);
2096 }
2097 if (rval != QLA_SUCCESS)
2098 memset(state, -1, sizeof(state));
2099
2100 return state[0];
2101}
2102
2103void
2104qlafx00_get_host_speed(struct Scsi_Host *shost)
2105{
2106 struct qla_hw_data *ha = ((struct scsi_qla_host *)
2107 (shost_priv(shost)))->hw;
2108 u32 speed = FC_PORTSPEED_UNKNOWN;
2109
2110 switch (ha->link_data_rate) {
2111 case QLAFX00_PORT_SPEED_2G:
2112 speed = FC_PORTSPEED_2GBIT;
2113 break;
2114 case QLAFX00_PORT_SPEED_4G:
2115 speed = FC_PORTSPEED_4GBIT;
2116 break;
2117 case QLAFX00_PORT_SPEED_8G:
2118 speed = FC_PORTSPEED_8GBIT;
2119 break;
2120 case QLAFX00_PORT_SPEED_10G:
2121 speed = FC_PORTSPEED_10GBIT;
2122 break;
2123 }
2124 fc_host_speed(shost) = speed;
2125}
2126
2127
2128
2129static inline void
2130qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
2131 uint32_t sense_len, struct rsp_que *rsp, int res)
2132{
2133 struct scsi_qla_host *vha = sp->vha;
2134 struct scsi_cmnd *cp = GET_CMD_SP(sp);
2135 uint32_t track_sense_len;
2136
2137 SET_FW_SENSE_LEN(sp, sense_len);
2138
2139 if (sense_len >= SCSI_SENSE_BUFFERSIZE)
2140 sense_len = SCSI_SENSE_BUFFERSIZE;
2141
2142 SET_CMD_SENSE_LEN(sp, sense_len);
2143 SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
2144 track_sense_len = sense_len;
2145
2146 if (sense_len > par_sense_len)
2147 sense_len = par_sense_len;
2148
2149 memcpy(cp->sense_buffer, sense_data, sense_len);
2150
2151 SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
2152
2153 SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
2154 track_sense_len -= sense_len;
2155 SET_CMD_SENSE_LEN(sp, track_sense_len);
2156
2157 ql_dbg(ql_dbg_io, vha, 0x304d,
2158 "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
2159 sense_len, par_sense_len, track_sense_len);
2160 if (GET_FW_SENSE_LEN(sp) > 0) {
2161 rsp->status_srb = sp;
2162 cp->result = res;
2163 }
2164
2165 if (sense_len) {
2166 ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
2167 "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
2168 sp->vha->host_no, cp->device->id, cp->device->lun,
2169 cp);
2170 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
2171 cp->sense_buffer, sense_len);
2172 }
2173}
2174
2175static void
2176qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2177 struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
2178 __le16 sstatus, __le16 cpstatus)
2179{
2180 struct srb_iocb *tmf;
2181
2182 tmf = &sp->u.iocb_cmd;
2183 if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
2184 (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
2185 cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
2186 tmf->u.tmf.comp_status = cpstatus;
2187 sp->done(sp, 0);
2188}
2189
2190static void
2191qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2192 struct abort_iocb_entry_fx00 *pkt)
2193{
2194 const char func[] = "ABT_IOCB";
2195 srb_t *sp;
2196 struct srb_iocb *abt;
2197
2198 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2199 if (!sp)
2200 return;
2201
2202 abt = &sp->u.iocb_cmd;
2203 abt->u.abt.comp_status = pkt->tgt_id_sts;
2204 sp->done(sp, 0);
2205}
2206
2207static void
2208qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
2209 struct ioctl_iocb_entry_fx00 *pkt)
2210{
2211 const char func[] = "IOSB_IOCB";
2212 srb_t *sp;
2213 struct bsg_job *bsg_job;
2214 struct fc_bsg_reply *bsg_reply;
2215 struct srb_iocb *iocb_job;
2216 int res = 0;
2217 struct qla_mt_iocb_rsp_fx00 fstatus;
2218 uint8_t *fw_sts_ptr;
2219
2220 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2221 if (!sp)
2222 return;
2223
2224 if (sp->type == SRB_FXIOCB_DCMD) {
2225 iocb_job = &sp->u.iocb_cmd;
2226 iocb_job->u.fxiocb.seq_number = pkt->seq_no;
2227 iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
2228 iocb_job->u.fxiocb.result = pkt->status;
2229 if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
2230 iocb_job->u.fxiocb.req_data =
2231 pkt->dataword_r;
2232 } else {
2233 bsg_job = sp->u.bsg_job;
2234 bsg_reply = bsg_job->reply;
2235
2236 memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
2237
2238 fstatus.reserved_1 = pkt->reserved_0;
2239 fstatus.func_type = pkt->comp_func_num;
2240 fstatus.ioctl_flags = pkt->fw_iotcl_flags;
2241 fstatus.ioctl_data = pkt->dataword_r;
2242 fstatus.adapid = pkt->adapid;
2243 fstatus.reserved_2 = pkt->dataword_r_extra;
2244 fstatus.res_count = pkt->residuallen;
2245 fstatus.status = pkt->status;
2246 fstatus.seq_number = pkt->seq_no;
2247 memcpy(fstatus.reserved_3,
2248 pkt->reserved_2, 20 * sizeof(uint8_t));
2249
2250 fw_sts_ptr = bsg_job->reply + sizeof(struct fc_bsg_reply);
2251
2252 memcpy(fw_sts_ptr, &fstatus, sizeof(fstatus));
2253 bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
2254 sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
2255
2256 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2257 sp->vha, 0x5080, pkt, sizeof(*pkt));
2258
2259 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2260 sp->vha, 0x5074,
2261 fw_sts_ptr, sizeof(fstatus));
2262
2263 res = bsg_reply->result = DID_OK << 16;
2264 bsg_reply->reply_payload_rcv_len =
2265 bsg_job->reply_payload.payload_len;
2266 }
2267 sp->done(sp, res);
2268}
2269
2270
2271
2272
2273
2274
2275
2276static void
2277qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
2278{
2279 srb_t *sp;
2280 fc_port_t *fcport;
2281 struct scsi_cmnd *cp;
2282 struct sts_entry_fx00 *sts;
2283 __le16 comp_status;
2284 __le16 scsi_status;
2285 __le16 lscsi_status;
2286 int32_t resid;
2287 uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
2288 fw_resid_len;
2289 uint8_t *rsp_info = NULL, *sense_data = NULL;
2290 struct qla_hw_data *ha = vha->hw;
2291 uint32_t hindex, handle;
2292 uint16_t que;
2293 struct req_que *req;
2294 int logit = 1;
2295 int res = 0;
2296
2297 sts = (struct sts_entry_fx00 *) pkt;
2298
2299 comp_status = sts->comp_status;
2300 scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
2301 hindex = sts->handle;
2302 handle = LSW(hindex);
2303
2304 que = MSW(hindex);
2305 req = ha->req_q_map[que];
2306
2307
2308 if (handle < req->num_outstanding_cmds)
2309 sp = req->outstanding_cmds[handle];
2310 else
2311 sp = NULL;
2312
2313 if (sp == NULL) {
2314 ql_dbg(ql_dbg_io, vha, 0x3034,
2315 "Invalid status handle (0x%x).\n", handle);
2316
2317 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2318 qla2xxx_wake_dpc(vha);
2319 return;
2320 }
2321
2322 if (sp->type == SRB_TM_CMD) {
2323 req->outstanding_cmds[handle] = NULL;
2324 qlafx00_tm_iocb_entry(vha, req, pkt, sp,
2325 scsi_status, comp_status);
2326 return;
2327 }
2328
2329
2330 if (comp_status == CS_COMPLETE && scsi_status == 0) {
2331 qla2x00_process_completed_request(vha, req, handle);
2332 return;
2333 }
2334
2335 req->outstanding_cmds[handle] = NULL;
2336 cp = GET_CMD_SP(sp);
2337 if (cp == NULL) {
2338 ql_dbg(ql_dbg_io, vha, 0x3048,
2339 "Command already returned (0x%x/%p).\n",
2340 handle, sp);
2341
2342 return;
2343 }
2344
2345 lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
2346
2347 fcport = sp->fcport;
2348
2349 sense_len = par_sense_len = rsp_info_len = resid_len =
2350 fw_resid_len = 0;
2351 if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
2352 sense_len = sts->sense_len;
2353 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2354 | (uint16_t)SS_RESIDUAL_OVER)))
2355 resid_len = le32_to_cpu(sts->residual_len);
2356 if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
2357 fw_resid_len = le32_to_cpu(sts->residual_len);
2358 rsp_info = sense_data = sts->data;
2359 par_sense_len = sizeof(sts->data);
2360
2361
2362 if (comp_status == CS_COMPLETE &&
2363 scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
2364 comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
2365
2366
2367
2368
2369 switch (le16_to_cpu(comp_status)) {
2370 case CS_COMPLETE:
2371 case CS_QUEUE_FULL:
2372 if (scsi_status == 0) {
2373 res = DID_OK << 16;
2374 break;
2375 }
2376 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2377 | (uint16_t)SS_RESIDUAL_OVER))) {
2378 resid = resid_len;
2379 scsi_set_resid(cp, resid);
2380
2381 if (!lscsi_status &&
2382 ((unsigned)(scsi_bufflen(cp) - resid) <
2383 cp->underflow)) {
2384 ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
2385 "Mid-layer underflow "
2386 "detected (0x%x of 0x%x bytes).\n",
2387 resid, scsi_bufflen(cp));
2388
2389 res = DID_ERROR << 16;
2390 break;
2391 }
2392 }
2393 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2394
2395 if (lscsi_status ==
2396 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2397 ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
2398 "QUEUE FULL detected.\n");
2399 break;
2400 }
2401 logit = 0;
2402 if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2403 break;
2404
2405 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2406 if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2407 break;
2408
2409 qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
2410 rsp, res);
2411 break;
2412
2413 case CS_DATA_UNDERRUN:
2414
2415 if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2416 resid = fw_resid_len;
2417 else
2418 resid = resid_len;
2419 scsi_set_resid(cp, resid);
2420 if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
2421 if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2422 && fw_resid_len != resid_len) {
2423 ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
2424 "Dropped frame(s) detected "
2425 "(0x%x of 0x%x bytes).\n",
2426 resid, scsi_bufflen(cp));
2427
2428 res = DID_ERROR << 16 |
2429 le16_to_cpu(lscsi_status);
2430 goto check_scsi_status;
2431 }
2432
2433 if (!lscsi_status &&
2434 ((unsigned)(scsi_bufflen(cp) - resid) <
2435 cp->underflow)) {
2436 ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
2437 "Mid-layer underflow "
2438 "detected (0x%x of 0x%x bytes, "
2439 "cp->underflow: 0x%x).\n",
2440 resid, scsi_bufflen(cp), cp->underflow);
2441
2442 res = DID_ERROR << 16;
2443 break;
2444 }
2445 } else if (lscsi_status !=
2446 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
2447 lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
2448
2449
2450
2451
2452
2453 ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
2454 "Dropped frame(s) detected (0x%x "
2455 "of 0x%x bytes).\n", resid,
2456 scsi_bufflen(cp));
2457
2458 res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
2459 goto check_scsi_status;
2460 } else {
2461 ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
2462 "scsi_status: 0x%x, lscsi_status: 0x%x\n",
2463 scsi_status, lscsi_status);
2464 }
2465
2466 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2467 logit = 0;
2468
2469check_scsi_status:
2470
2471
2472
2473
2474 if (lscsi_status != 0) {
2475 if (lscsi_status ==
2476 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2477 ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
2478 "QUEUE FULL detected.\n");
2479 logit = 1;
2480 break;
2481 }
2482 if (lscsi_status !=
2483 cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2484 break;
2485
2486 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2487 if (!(scsi_status &
2488 cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2489 break;
2490
2491 qlafx00_handle_sense(sp, sense_data, par_sense_len,
2492 sense_len, rsp, res);
2493 }
2494 break;
2495
2496 case CS_PORT_LOGGED_OUT:
2497 case CS_PORT_CONFIG_CHG:
2498 case CS_PORT_BUSY:
2499 case CS_INCOMPLETE:
2500 case CS_PORT_UNAVAILABLE:
2501 case CS_TIMEOUT:
2502 case CS_RESET:
2503
2504
2505
2506
2507
2508
2509 res = DID_TRANSPORT_DISRUPTED << 16;
2510
2511 ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
2512 "Port down status: port-state=0x%x.\n",
2513 atomic_read(&fcport->state));
2514
2515 if (atomic_read(&fcport->state) == FCS_ONLINE)
2516 qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
2517 break;
2518
2519 case CS_ABORTED:
2520 res = DID_RESET << 16;
2521 break;
2522
2523 default:
2524 res = DID_ERROR << 16;
2525 break;
2526 }
2527
2528 if (logit)
2529 ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
2530 "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
2531 "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
2532 "rsp_info=%p resid=0x%x fw_resid=0x%x sense_len=0x%x, "
2533 "par_sense_len=0x%x, rsp_info_len=0x%x\n",
2534 comp_status, scsi_status, res, vha->host_no,
2535 cp->device->id, cp->device->lun, fcport->tgt_id,
2536 lscsi_status, cp->cmnd, scsi_bufflen(cp),
2537 rsp_info, resid_len, fw_resid_len, sense_len,
2538 par_sense_len, rsp_info_len);
2539
2540 if (rsp->status_srb == NULL)
2541 sp->done(sp, res);
2542 else
2543 WARN_ON_ONCE(true);
2544}
2545
2546
2547
2548
2549
2550
2551
2552
2553static void
2554qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
2555{
2556 uint8_t sense_sz = 0;
2557 struct qla_hw_data *ha = rsp->hw;
2558 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
2559 srb_t *sp = rsp->status_srb;
2560 struct scsi_cmnd *cp;
2561 uint32_t sense_len;
2562 uint8_t *sense_ptr;
2563
2564 if (!sp) {
2565 ql_dbg(ql_dbg_io, vha, 0x3037,
2566 "no SP, sp = %p\n", sp);
2567 return;
2568 }
2569
2570 if (!GET_FW_SENSE_LEN(sp)) {
2571 ql_dbg(ql_dbg_io, vha, 0x304b,
2572 "no fw sense data, sp = %p\n", sp);
2573 return;
2574 }
2575 cp = GET_CMD_SP(sp);
2576 if (cp == NULL) {
2577 ql_log(ql_log_warn, vha, 0x303b,
2578 "cmd is NULL: already returned to OS (sp=%p).\n", sp);
2579
2580 rsp->status_srb = NULL;
2581 return;
2582 }
2583
2584 if (!GET_CMD_SENSE_LEN(sp)) {
2585 ql_dbg(ql_dbg_io, vha, 0x304c,
2586 "no sense data, sp = %p\n", sp);
2587 } else {
2588 sense_len = GET_CMD_SENSE_LEN(sp);
2589 sense_ptr = GET_CMD_SENSE_PTR(sp);
2590 ql_dbg(ql_dbg_io, vha, 0x304f,
2591 "sp=%p sense_len=0x%x sense_ptr=%p.\n",
2592 sp, sense_len, sense_ptr);
2593
2594 if (sense_len > sizeof(pkt->data))
2595 sense_sz = sizeof(pkt->data);
2596 else
2597 sense_sz = sense_len;
2598
2599
2600 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
2601 pkt, sizeof(*pkt));
2602 memcpy(sense_ptr, pkt->data, sense_sz);
2603 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
2604 sense_ptr, sense_sz);
2605
2606 sense_len -= sense_sz;
2607 sense_ptr += sense_sz;
2608
2609 SET_CMD_SENSE_PTR(sp, sense_ptr);
2610 SET_CMD_SENSE_LEN(sp, sense_len);
2611 }
2612 sense_len = GET_FW_SENSE_LEN(sp);
2613 sense_len = (sense_len > sizeof(pkt->data)) ?
2614 (sense_len - sizeof(pkt->data)) : 0;
2615 SET_FW_SENSE_LEN(sp, sense_len);
2616
2617
2618 if (sense_len == 0) {
2619 rsp->status_srb = NULL;
2620 sp->done(sp, cp->result);
2621 } else {
2622 WARN_ON_ONCE(true);
2623 }
2624}
2625
2626
2627
2628
2629
2630
2631
2632static void
2633qlafx00_multistatus_entry(struct scsi_qla_host *vha,
2634 struct rsp_que *rsp, void *pkt)
2635{
2636 srb_t *sp;
2637 struct multi_sts_entry_fx00 *stsmfx;
2638 struct qla_hw_data *ha = vha->hw;
2639 uint32_t handle, hindex, handle_count, i;
2640 uint16_t que;
2641 struct req_que *req;
2642 __le32 *handle_ptr;
2643
2644 stsmfx = (struct multi_sts_entry_fx00 *) pkt;
2645
2646 handle_count = stsmfx->handle_count;
2647
2648 if (handle_count > MAX_HANDLE_COUNT) {
2649 ql_dbg(ql_dbg_io, vha, 0x3035,
2650 "Invalid handle count (0x%x).\n", handle_count);
2651 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2652 qla2xxx_wake_dpc(vha);
2653 return;
2654 }
2655
2656 handle_ptr = &stsmfx->handles[0];
2657
2658 for (i = 0; i < handle_count; i++) {
2659 hindex = le32_to_cpu(*handle_ptr);
2660 handle = LSW(hindex);
2661 que = MSW(hindex);
2662 req = ha->req_q_map[que];
2663
2664
2665 if (handle < req->num_outstanding_cmds)
2666 sp = req->outstanding_cmds[handle];
2667 else
2668 sp = NULL;
2669
2670 if (sp == NULL) {
2671 ql_dbg(ql_dbg_io, vha, 0x3044,
2672 "Invalid status handle (0x%x).\n", handle);
2673 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2674 qla2xxx_wake_dpc(vha);
2675 return;
2676 }
2677 qla2x00_process_completed_request(vha, req, handle);
2678 handle_ptr++;
2679 }
2680}
2681
2682
2683
2684
2685
2686
2687
2688static void
2689qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
2690 struct sts_entry_fx00 *pkt)
2691{
2692 srb_t *sp;
2693 struct qla_hw_data *ha = vha->hw;
2694 const char func[] = "ERROR-IOCB";
2695 uint16_t que = 0;
2696 struct req_que *req = NULL;
2697 int res = DID_ERROR << 16;
2698
2699 req = ha->req_q_map[que];
2700
2701 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2702 if (sp) {
2703 sp->done(sp, res);
2704 return;
2705 }
2706
2707 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2708 qla2xxx_wake_dpc(vha);
2709}
2710
2711
2712
2713
2714
2715
2716static void
2717qlafx00_process_response_queue(struct scsi_qla_host *vha,
2718 struct rsp_que *rsp)
2719{
2720 struct sts_entry_fx00 *pkt;
2721 response_t *lptr;
2722 uint16_t lreq_q_in = 0;
2723 uint16_t lreq_q_out = 0;
2724
2725 lreq_q_in = RD_REG_DWORD(rsp->rsp_q_in);
2726 lreq_q_out = rsp->ring_index;
2727
2728 while (lreq_q_in != lreq_q_out) {
2729 lptr = rsp->ring_ptr;
2730 memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
2731 sizeof(rsp->rsp_pkt));
2732 pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
2733
2734 rsp->ring_index++;
2735 lreq_q_out++;
2736 if (rsp->ring_index == rsp->length) {
2737 lreq_q_out = 0;
2738 rsp->ring_index = 0;
2739 rsp->ring_ptr = rsp->ring;
2740 } else {
2741 rsp->ring_ptr++;
2742 }
2743
2744 if (pkt->entry_status != 0 &&
2745 pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
2746 ql_dbg(ql_dbg_async, vha, 0x507f,
2747 "type of error status in response: 0x%x\n",
2748 pkt->entry_status);
2749 qlafx00_error_entry(vha, rsp,
2750 (struct sts_entry_fx00 *)pkt);
2751 continue;
2752 }
2753
2754 switch (pkt->entry_type) {
2755 case STATUS_TYPE_FX00:
2756 qlafx00_status_entry(vha, rsp, pkt);
2757 break;
2758
2759 case STATUS_CONT_TYPE_FX00:
2760 qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
2761 break;
2762
2763 case MULTI_STATUS_TYPE_FX00:
2764 qlafx00_multistatus_entry(vha, rsp, pkt);
2765 break;
2766
2767 case ABORT_IOCB_TYPE_FX00:
2768 qlafx00_abort_iocb_entry(vha, rsp->req,
2769 (struct abort_iocb_entry_fx00 *)pkt);
2770 break;
2771
2772 case IOCTL_IOSB_TYPE_FX00:
2773 qlafx00_ioctl_iosb_entry(vha, rsp->req,
2774 (struct ioctl_iocb_entry_fx00 *)pkt);
2775 break;
2776 default:
2777
2778 ql_dbg(ql_dbg_async, vha, 0x5081,
2779 "Received unknown response pkt type %x "
2780 "entry status=%x.\n",
2781 pkt->entry_type, pkt->entry_status);
2782 break;
2783 }
2784 }
2785
2786
2787 WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
2788}
2789
2790
2791
2792
2793
2794static void
2795qlafx00_async_event(scsi_qla_host_t *vha)
2796{
2797 struct qla_hw_data *ha = vha->hw;
2798 struct device_reg_fx00 __iomem *reg;
2799 int data_size = 1;
2800
2801 reg = &ha->iobase->ispfx00;
2802
2803 switch (ha->aenmb[0]) {
2804 case QLAFX00_MBA_SYSTEM_ERR:
2805 ql_log(ql_log_warn, vha, 0x5079,
2806 "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
2807 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2808 break;
2809
2810 case QLAFX00_MBA_SHUTDOWN_RQSTD:
2811 ql_dbg(ql_dbg_async, vha, 0x5076,
2812 "Asynchronous FW shutdown requested.\n");
2813 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2814 qla2xxx_wake_dpc(vha);
2815 break;
2816
2817 case QLAFX00_MBA_PORT_UPDATE:
2818 ha->aenmb[1] = RD_REG_DWORD(®->aenmailbox1);
2819 ha->aenmb[2] = RD_REG_DWORD(®->aenmailbox2);
2820 ha->aenmb[3] = RD_REG_DWORD(®->aenmailbox3);
2821 ql_dbg(ql_dbg_async, vha, 0x5077,
2822 "Asynchronous port Update received "
2823 "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
2824 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
2825 data_size = 4;
2826 break;
2827
2828 case QLAFX00_MBA_TEMP_OVER:
2829 ql_log(ql_log_info, vha, 0x5085,
2830 "Asynchronous over temperature event received "
2831 "aenmb[0]: %x\n",
2832 ha->aenmb[0]);
2833 break;
2834
2835 case QLAFX00_MBA_TEMP_NORM:
2836 ql_log(ql_log_info, vha, 0x5086,
2837 "Asynchronous normal temperature event received "
2838 "aenmb[0]: %x\n",
2839 ha->aenmb[0]);
2840 break;
2841
2842 case QLAFX00_MBA_TEMP_CRIT:
2843 ql_log(ql_log_info, vha, 0x5083,
2844 "Asynchronous critical temperature event received "
2845 "aenmb[0]: %x\n",
2846 ha->aenmb[0]);
2847 break;
2848
2849 default:
2850 ha->aenmb[1] = RD_REG_WORD(®->aenmailbox1);
2851 ha->aenmb[2] = RD_REG_WORD(®->aenmailbox2);
2852 ha->aenmb[3] = RD_REG_WORD(®->aenmailbox3);
2853 ha->aenmb[4] = RD_REG_WORD(®->aenmailbox4);
2854 ha->aenmb[5] = RD_REG_WORD(®->aenmailbox5);
2855 ha->aenmb[6] = RD_REG_WORD(®->aenmailbox6);
2856 ha->aenmb[7] = RD_REG_WORD(®->aenmailbox7);
2857 ql_dbg(ql_dbg_async, vha, 0x5078,
2858 "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
2859 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
2860 ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
2861 break;
2862 }
2863 qlafx00_post_aenfx_work(vha, ha->aenmb[0],
2864 (uint32_t *)ha->aenmb, data_size);
2865}
2866
2867
2868
2869
2870
2871
2872static void
2873qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
2874{
2875 uint16_t cnt;
2876 uint32_t __iomem *wptr;
2877 struct qla_hw_data *ha = vha->hw;
2878 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
2879
2880 if (!ha->mcp32)
2881 ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
2882
2883
2884 ha->flags.mbox_int = 1;
2885 ha->mailbox_out32[0] = mb0;
2886 wptr = (uint32_t __iomem *)®->mailbox17;
2887
2888 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2889 ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr);
2890 wptr++;
2891 }
2892}
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903irqreturn_t
2904qlafx00_intr_handler(int irq, void *dev_id)
2905{
2906 scsi_qla_host_t *vha;
2907 struct qla_hw_data *ha;
2908 struct device_reg_fx00 __iomem *reg;
2909 int status;
2910 unsigned long iter;
2911 uint32_t stat;
2912 uint32_t mb[8];
2913 struct rsp_que *rsp;
2914 unsigned long flags;
2915 uint32_t clr_intr = 0;
2916 uint32_t intr_stat = 0;
2917
2918 rsp = (struct rsp_que *) dev_id;
2919 if (!rsp) {
2920 ql_log(ql_log_info, NULL, 0x507d,
2921 "%s: NULL response queue pointer.\n", __func__);
2922 return IRQ_NONE;
2923 }
2924
2925 ha = rsp->hw;
2926 reg = &ha->iobase->ispfx00;
2927 status = 0;
2928
2929 if (unlikely(pci_channel_offline(ha->pdev)))
2930 return IRQ_HANDLED;
2931
2932 spin_lock_irqsave(&ha->hardware_lock, flags);
2933 vha = pci_get_drvdata(ha->pdev);
2934 for (iter = 50; iter--; clr_intr = 0) {
2935 stat = QLAFX00_RD_INTR_REG(ha);
2936 if (qla2x00_check_reg32_for_disconnect(vha, stat))
2937 break;
2938 intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
2939 if (!intr_stat)
2940 break;
2941
2942 if (stat & QLAFX00_INTR_MB_CMPLT) {
2943 mb[0] = RD_REG_WORD(®->mailbox16);
2944 qlafx00_mbx_completion(vha, mb[0]);
2945 status |= MBX_INTERRUPT;
2946 clr_intr |= QLAFX00_INTR_MB_CMPLT;
2947 }
2948 if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
2949 ha->aenmb[0] = RD_REG_WORD(®->aenmailbox0);
2950 qlafx00_async_event(vha);
2951 clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
2952 }
2953 if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
2954 qlafx00_process_response_queue(vha, rsp);
2955 clr_intr |= QLAFX00_INTR_RSP_CMPLT;
2956 }
2957
2958 QLAFX00_CLR_INTR_REG(ha, clr_intr);
2959 QLAFX00_RD_INTR_REG(ha);
2960 }
2961
2962 qla2x00_handle_mbx_completion(ha, status);
2963 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2964
2965 return IRQ_HANDLED;
2966}
2967
2968
2969
2970static inline cont_a64_entry_t *
2971qlafx00_prep_cont_type1_iocb(struct req_que *req,
2972 cont_a64_entry_t *lcont_pkt)
2973{
2974 cont_a64_entry_t *cont_pkt;
2975
2976
2977 req->ring_index++;
2978 if (req->ring_index == req->length) {
2979 req->ring_index = 0;
2980 req->ring_ptr = req->ring;
2981 } else {
2982 req->ring_ptr++;
2983 }
2984
2985 cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
2986
2987
2988 lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
2989
2990 return cont_pkt;
2991}
2992
2993static inline void
2994qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
2995 uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
2996{
2997 uint16_t avail_dsds;
2998 struct dsd64 *cur_dsd;
2999 scsi_qla_host_t *vha;
3000 struct scsi_cmnd *cmd;
3001 struct scatterlist *sg;
3002 int i, cont;
3003 struct req_que *req;
3004 cont_a64_entry_t lcont_pkt;
3005 cont_a64_entry_t *cont_pkt;
3006
3007 vha = sp->vha;
3008 req = vha->req;
3009
3010 cmd = GET_CMD_SP(sp);
3011 cont = 0;
3012 cont_pkt = NULL;
3013
3014
3015 lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
3016
3017
3018 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
3019 lcmd_pkt->byte_count = cpu_to_le32(0);
3020 return;
3021 }
3022
3023
3024 if (cmd->sc_data_direction == DMA_TO_DEVICE) {
3025 lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
3026 vha->qla_stats.output_bytes += scsi_bufflen(cmd);
3027 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
3028 lcmd_pkt->cntrl_flags = TMF_READ_DATA;
3029 vha->qla_stats.input_bytes += scsi_bufflen(cmd);
3030 }
3031
3032
3033 avail_dsds = 1;
3034 cur_dsd = &lcmd_pkt->dsd;
3035
3036
3037 scsi_for_each_sg(cmd, sg, tot_dsds, i) {
3038
3039 if (avail_dsds == 0) {
3040
3041
3042
3043
3044 memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
3045 cont_pkt =
3046 qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
3047 cur_dsd = lcont_pkt.dsd;
3048 avail_dsds = 5;
3049 cont = 1;
3050 }
3051
3052 append_dsd64(&cur_dsd, sg);
3053 avail_dsds--;
3054 if (avail_dsds == 0 && cont == 1) {
3055 cont = 0;
3056 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3057 sizeof(lcont_pkt));
3058 }
3059
3060 }
3061 if (avail_dsds != 0 && cont == 1) {
3062 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3063 sizeof(lcont_pkt));
3064 }
3065}
3066
3067
3068
3069
3070
3071
3072
3073int
3074qlafx00_start_scsi(srb_t *sp)
3075{
3076 int nseg;
3077 unsigned long flags;
3078 uint32_t handle;
3079 uint16_t cnt;
3080 uint16_t req_cnt;
3081 uint16_t tot_dsds;
3082 struct req_que *req = NULL;
3083 struct rsp_que *rsp = NULL;
3084 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
3085 struct scsi_qla_host *vha = sp->vha;
3086 struct qla_hw_data *ha = vha->hw;
3087 struct cmd_type_7_fx00 *cmd_pkt;
3088 struct cmd_type_7_fx00 lcmd_pkt;
3089 struct scsi_lun llun;
3090
3091
3092 rsp = ha->rsp_q_map[0];
3093 req = vha->req;
3094
3095
3096 tot_dsds = 0;
3097
3098
3099 spin_lock_irqsave(&ha->hardware_lock, flags);
3100
3101 handle = qla2xxx_get_next_handle(req);
3102 if (handle == 0)
3103 goto queuing_error;
3104
3105
3106 if (scsi_sg_count(cmd)) {
3107 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
3108 scsi_sg_count(cmd), cmd->sc_data_direction);
3109 if (unlikely(!nseg))
3110 goto queuing_error;
3111 } else
3112 nseg = 0;
3113
3114 tot_dsds = nseg;
3115 req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
3116 if (req->cnt < (req_cnt + 2)) {
3117 cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
3118
3119 if (req->ring_index < cnt)
3120 req->cnt = cnt - req->ring_index;
3121 else
3122 req->cnt = req->length -
3123 (req->ring_index - cnt);
3124 if (req->cnt < (req_cnt + 2))
3125 goto queuing_error;
3126 }
3127
3128
3129 req->current_outstanding_cmd = handle;
3130 req->outstanding_cmds[handle] = sp;
3131 sp->handle = handle;
3132 cmd->host_scribble = (unsigned char *)(unsigned long)handle;
3133 req->cnt -= req_cnt;
3134
3135 cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
3136
3137 memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
3138
3139 lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
3140 lcmd_pkt.reserved_0 = 0;
3141 lcmd_pkt.port_path_ctrl = 0;
3142 lcmd_pkt.reserved_1 = 0;
3143 lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
3144 lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
3145
3146 int_to_scsilun(cmd->device->lun, &llun);
3147 host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
3148 sizeof(lcmd_pkt.lun));
3149
3150
3151 host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
3152 lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
3153
3154
3155 qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
3156
3157
3158 lcmd_pkt.entry_count = (uint8_t)req_cnt;
3159
3160
3161 lcmd_pkt.entry_status = (uint8_t) rsp->id;
3162
3163 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
3164 cmd->cmnd, cmd->cmd_len);
3165 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
3166 &lcmd_pkt, sizeof(lcmd_pkt));
3167
3168 memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
3169 wmb();
3170
3171
3172 req->ring_index++;
3173 if (req->ring_index == req->length) {
3174 req->ring_index = 0;
3175 req->ring_ptr = req->ring;
3176 } else
3177 req->ring_ptr++;
3178
3179 sp->flags |= SRB_DMA_VALID;
3180
3181
3182 WRT_REG_DWORD(req->req_q_in, req->ring_index);
3183 QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
3184
3185 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3186 return QLA_SUCCESS;
3187
3188queuing_error:
3189 if (tot_dsds)
3190 scsi_dma_unmap(cmd);
3191
3192 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3193
3194 return QLA_FUNCTION_FAILED;
3195}
3196
3197void
3198qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
3199{
3200 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3201 scsi_qla_host_t *vha = sp->vha;
3202 struct req_que *req = vha->req;
3203 struct tsk_mgmt_entry_fx00 tm_iocb;
3204 struct scsi_lun llun;
3205
3206 memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
3207 tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
3208 tm_iocb.entry_count = 1;
3209 tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
3210 tm_iocb.reserved_0 = 0;
3211 tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
3212 tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
3213 if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
3214 int_to_scsilun(fxio->u.tmf.lun, &llun);
3215 host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
3216 sizeof(struct scsi_lun));
3217 }
3218
3219 memcpy((void *)ptm_iocb, &tm_iocb,
3220 sizeof(struct tsk_mgmt_entry_fx00));
3221 wmb();
3222}
3223
3224void
3225qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
3226{
3227 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3228 scsi_qla_host_t *vha = sp->vha;
3229 struct req_que *req = vha->req;
3230 struct abort_iocb_entry_fx00 abt_iocb;
3231
3232 memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
3233 abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
3234 abt_iocb.entry_count = 1;
3235 abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
3236 abt_iocb.abort_handle =
3237 cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
3238 abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
3239 abt_iocb.req_que_no = cpu_to_le16(req->id);
3240
3241 memcpy((void *)pabt_iocb, &abt_iocb,
3242 sizeof(struct abort_iocb_entry_fx00));
3243 wmb();
3244}
3245
3246void
3247qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
3248{
3249 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3250 struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
3251 struct bsg_job *bsg_job;
3252 struct fc_bsg_request *bsg_request;
3253 struct fxdisc_entry_fx00 fx_iocb;
3254 uint8_t entry_cnt = 1;
3255
3256 memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
3257 fx_iocb.entry_type = FX00_IOCB_TYPE;
3258 fx_iocb.handle = cpu_to_le32(sp->handle);
3259 fx_iocb.entry_count = entry_cnt;
3260
3261 if (sp->type == SRB_FXIOCB_DCMD) {
3262 fx_iocb.func_num =
3263 sp->u.iocb_cmd.u.fxiocb.req_func_type;
3264 fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
3265 fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
3266 fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
3267 fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
3268 fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
3269
3270 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
3271 fx_iocb.req_dsdcnt = cpu_to_le16(1);
3272 fx_iocb.req_xfrcnt =
3273 cpu_to_le16(fxio->u.fxiocb.req_len);
3274 put_unaligned_le64(fxio->u.fxiocb.req_dma_handle,
3275 &fx_iocb.dseg_rq.address);
3276 fx_iocb.dseg_rq.length =
3277 cpu_to_le32(fxio->u.fxiocb.req_len);
3278 }
3279
3280 if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
3281 fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
3282 fx_iocb.rsp_xfrcnt =
3283 cpu_to_le16(fxio->u.fxiocb.rsp_len);
3284 put_unaligned_le64(fxio->u.fxiocb.rsp_dma_handle,
3285 &fx_iocb.dseg_rsp.address);
3286 fx_iocb.dseg_rsp.length =
3287 cpu_to_le32(fxio->u.fxiocb.rsp_len);
3288 }
3289
3290 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
3291 fx_iocb.dataword = fxio->u.fxiocb.req_data;
3292 }
3293 fx_iocb.flags = fxio->u.fxiocb.flags;
3294 } else {
3295 struct scatterlist *sg;
3296
3297 bsg_job = sp->u.bsg_job;
3298 bsg_request = bsg_job->request;
3299 piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
3300 &bsg_request->rqst_data.h_vendor.vendor_cmd[1];
3301
3302 fx_iocb.func_num = piocb_rqst->func_type;
3303 fx_iocb.adapid = piocb_rqst->adapid;
3304 fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
3305 fx_iocb.reserved_0 = piocb_rqst->reserved_0;
3306 fx_iocb.reserved_1 = piocb_rqst->reserved_1;
3307 fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
3308 fx_iocb.dataword = piocb_rqst->dataword;
3309 fx_iocb.req_xfrcnt = piocb_rqst->req_len;
3310 fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
3311
3312 if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
3313 int avail_dsds, tot_dsds;
3314 cont_a64_entry_t lcont_pkt;
3315 cont_a64_entry_t *cont_pkt = NULL;
3316 struct dsd64 *cur_dsd;
3317 int index = 0, cont = 0;
3318
3319 fx_iocb.req_dsdcnt =
3320 cpu_to_le16(bsg_job->request_payload.sg_cnt);
3321 tot_dsds =
3322 bsg_job->request_payload.sg_cnt;
3323 cur_dsd = &fx_iocb.dseg_rq;
3324 avail_dsds = 1;
3325 for_each_sg(bsg_job->request_payload.sg_list, sg,
3326 tot_dsds, index) {
3327
3328 if (avail_dsds == 0) {
3329
3330
3331
3332
3333 memset(&lcont_pkt, 0,
3334 REQUEST_ENTRY_SIZE);
3335 cont_pkt =
3336 qlafx00_prep_cont_type1_iocb(
3337 sp->vha->req, &lcont_pkt);
3338 cur_dsd = lcont_pkt.dsd;
3339 avail_dsds = 5;
3340 cont = 1;
3341 entry_cnt++;
3342 }
3343
3344 append_dsd64(&cur_dsd, sg);
3345 avail_dsds--;
3346
3347 if (avail_dsds == 0 && cont == 1) {
3348 cont = 0;
3349 memcpy_toio(
3350 (void __iomem *)cont_pkt,
3351 &lcont_pkt, REQUEST_ENTRY_SIZE);
3352 ql_dump_buffer(
3353 ql_dbg_user + ql_dbg_verbose,
3354 sp->vha, 0x3042,
3355 (uint8_t *)&lcont_pkt,
3356 REQUEST_ENTRY_SIZE);
3357 }
3358 }
3359 if (avail_dsds != 0 && cont == 1) {
3360 memcpy_toio((void __iomem *)cont_pkt,
3361 &lcont_pkt, REQUEST_ENTRY_SIZE);
3362 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3363 sp->vha, 0x3043,
3364 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3365 }
3366 }
3367
3368 if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
3369 int avail_dsds, tot_dsds;
3370 cont_a64_entry_t lcont_pkt;
3371 cont_a64_entry_t *cont_pkt = NULL;
3372 struct dsd64 *cur_dsd;
3373 int index = 0, cont = 0;
3374
3375 fx_iocb.rsp_dsdcnt =
3376 cpu_to_le16(bsg_job->reply_payload.sg_cnt);
3377 tot_dsds = bsg_job->reply_payload.sg_cnt;
3378 cur_dsd = &fx_iocb.dseg_rsp;
3379 avail_dsds = 1;
3380
3381 for_each_sg(bsg_job->reply_payload.sg_list, sg,
3382 tot_dsds, index) {
3383
3384 if (avail_dsds == 0) {
3385
3386
3387
3388
3389 memset(&lcont_pkt, 0,
3390 REQUEST_ENTRY_SIZE);
3391 cont_pkt =
3392 qlafx00_prep_cont_type1_iocb(
3393 sp->vha->req, &lcont_pkt);
3394 cur_dsd = lcont_pkt.dsd;
3395 avail_dsds = 5;
3396 cont = 1;
3397 entry_cnt++;
3398 }
3399
3400 append_dsd64(&cur_dsd, sg);
3401 avail_dsds--;
3402
3403 if (avail_dsds == 0 && cont == 1) {
3404 cont = 0;
3405 memcpy_toio((void __iomem *)cont_pkt,
3406 &lcont_pkt,
3407 REQUEST_ENTRY_SIZE);
3408 ql_dump_buffer(
3409 ql_dbg_user + ql_dbg_verbose,
3410 sp->vha, 0x3045,
3411 (uint8_t *)&lcont_pkt,
3412 REQUEST_ENTRY_SIZE);
3413 }
3414 }
3415 if (avail_dsds != 0 && cont == 1) {
3416 memcpy_toio((void __iomem *)cont_pkt,
3417 &lcont_pkt, REQUEST_ENTRY_SIZE);
3418 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3419 sp->vha, 0x3046,
3420 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3421 }
3422 }
3423
3424 if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
3425 fx_iocb.dataword = piocb_rqst->dataword;
3426 fx_iocb.flags = piocb_rqst->flags;
3427 fx_iocb.entry_count = entry_cnt;
3428 }
3429
3430 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3431 sp->vha, 0x3047, &fx_iocb, sizeof(fx_iocb));
3432
3433 memcpy_toio((void __iomem *)pfxiocb, &fx_iocb, sizeof(fx_iocb));
3434 wmb();
3435}
3436
