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33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/if_ether.h>
37#include <linux/pci.h>
38#include <linux/completion.h>
39#include <linux/radix-tree.h>
40#include <linux/cpu_rmap.h>
41#include <linux/crash_dump.h>
42
43#include <linux/refcount.h>
44
45#include <linux/timecounter.h>
46
47#define DEFAULT_UAR_PAGE_SHIFT 12
48
49#define MAX_MSIX_P_PORT 17
50#define MAX_MSIX 64
51#define MIN_MSIX_P_PORT 5
52#define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
53 (dev_cap).num_ports * MIN_MSIX_P_PORT)
54
55#define MLX4_MAX_100M_UNITS_VAL 255
56
57
58
59
60#define MLX4_RATELIMIT_100M_UNITS 3
61#define MLX4_RATELIMIT_1G_UNITS 4
62#define MLX4_RATELIMIT_DEFAULT 0x00ff
63
64#define MLX4_ROCE_MAX_GIDS 128
65#define MLX4_ROCE_PF_GIDS 16
66
67enum {
68 MLX4_FLAG_MSI_X = 1 << 0,
69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
70 MLX4_FLAG_MASTER = 1 << 2,
71 MLX4_FLAG_SLAVE = 1 << 3,
72 MLX4_FLAG_SRIOV = 1 << 4,
73 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
74 MLX4_FLAG_BONDED = 1 << 7,
75 MLX4_FLAG_SECURE_HOST = 1 << 8,
76};
77
78enum {
79 MLX4_PORT_CAP_IS_SM = 1 << 1,
80 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
81};
82
83enum {
84 MLX4_MAX_PORTS = 2,
85 MLX4_MAX_PORT_PKEYS = 128,
86 MLX4_MAX_PORT_GIDS = 128
87};
88
89
90
91
92
93#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
94#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
95
96enum {
97 MLX4_BOARD_ID_LEN = 64
98};
99
100enum {
101 MLX4_MAX_NUM_PF = 16,
102 MLX4_MAX_NUM_VF = 126,
103 MLX4_MAX_NUM_VF_P_PORT = 64,
104 MLX4_MFUNC_MAX = 128,
105 MLX4_MAX_EQ_NUM = 1024,
106 MLX4_MFUNC_EQ_NUM = 4,
107 MLX4_MFUNC_MAX_EQES = 8,
108 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
109};
110
111
112
113
114
115
116
117
118enum {
119 MLX4_STEERING_MODE_A0,
120 MLX4_STEERING_MODE_B0,
121 MLX4_STEERING_MODE_DEVICE_MANAGED
122};
123
124enum {
125 MLX4_STEERING_DMFS_A0_DEFAULT,
126 MLX4_STEERING_DMFS_A0_DYNAMIC,
127 MLX4_STEERING_DMFS_A0_STATIC,
128 MLX4_STEERING_DMFS_A0_DISABLE,
129 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
130};
131
132static inline const char *mlx4_steering_mode_str(int steering_mode)
133{
134 switch (steering_mode) {
135 case MLX4_STEERING_MODE_A0:
136 return "A0 steering";
137
138 case MLX4_STEERING_MODE_B0:
139 return "B0 steering";
140
141 case MLX4_STEERING_MODE_DEVICE_MANAGED:
142 return "Device managed flow steering";
143
144 default:
145 return "Unrecognize steering mode";
146 }
147}
148
149enum {
150 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
151 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
152};
153
154enum {
155 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
156 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
157 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
158 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
159 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
160 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
161 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
162 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
163 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
164 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
165 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
166 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
167 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
168 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
169 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
170 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
171 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
172 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
173 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
174 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
175 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
176 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
177 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
178 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
179 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
180 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
181 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
182 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
183 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
184 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
185 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
186};
187
188enum {
189 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
190 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
191 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
192 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
193 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
194 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
195 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
196 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
197 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
198 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
199 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
200 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
201 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
202 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
203 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
204 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
205 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
206 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
207 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
208 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
209 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
210 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
211 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
212 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
213 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
214 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
215 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
216 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
217 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
218 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
219 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
220 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
221 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
222 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
223 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34,
224 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35,
225 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36,
226 MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37,
227 MLX4_DEV_CAP_FLAG2_USER_MAC_EN = 1ULL << 38,
228 MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1ULL << 39,
229 MLX4_DEV_CAP_FLAG2_SW_CQ_INIT = 1ULL << 40,
230};
231
232enum {
233 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
234 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
235};
236
237enum {
238 MLX4_VF_CAP_FLAG_RESET = 1 << 0
239};
240
241
242
243
244
245
246
247
248
249enum {
250 MLX4_RESERVE_A0_QP = 1 << 6,
251 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
252};
253
254enum {
255 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
256 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
257 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
258 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
259};
260
261enum {
262 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
263 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
264 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
265};
266
267
268#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
269
270enum {
271 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
272 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
273 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
274 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
275 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
276 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
277 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
278 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
279 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
280};
281
282enum {
283 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
284 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
285};
286
287enum mlx4_event {
288 MLX4_EVENT_TYPE_COMP = 0x00,
289 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
290 MLX4_EVENT_TYPE_COMM_EST = 0x02,
291 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
292 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
293 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
294 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
295 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
296 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
297 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
298 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
299 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
300 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
301 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
302 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
303 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
304 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
305 MLX4_EVENT_TYPE_CMD = 0x0a,
306 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
307 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
308 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
309 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
310 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
311 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
312 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
313 MLX4_EVENT_TYPE_NONE = 0xff,
314};
315
316enum {
317 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
318 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
319};
320
321enum {
322 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
323 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
324};
325
326enum {
327 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
328};
329
330enum slave_port_state {
331 SLAVE_PORT_DOWN = 0,
332 SLAVE_PENDING_UP,
333 SLAVE_PORT_UP,
334};
335
336enum slave_port_gen_event {
337 SLAVE_PORT_GEN_EVENT_DOWN = 0,
338 SLAVE_PORT_GEN_EVENT_UP,
339 SLAVE_PORT_GEN_EVENT_NONE,
340};
341
342enum slave_port_state_event {
343 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
344 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
345 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
346 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
347};
348
349enum {
350 MLX4_PERM_LOCAL_READ = 1 << 10,
351 MLX4_PERM_LOCAL_WRITE = 1 << 11,
352 MLX4_PERM_REMOTE_READ = 1 << 12,
353 MLX4_PERM_REMOTE_WRITE = 1 << 13,
354 MLX4_PERM_ATOMIC = 1 << 14,
355 MLX4_PERM_BIND_MW = 1 << 15,
356 MLX4_PERM_MASK = 0xFC00
357};
358
359enum {
360 MLX4_OPCODE_NOP = 0x00,
361 MLX4_OPCODE_SEND_INVAL = 0x01,
362 MLX4_OPCODE_RDMA_WRITE = 0x08,
363 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
364 MLX4_OPCODE_SEND = 0x0a,
365 MLX4_OPCODE_SEND_IMM = 0x0b,
366 MLX4_OPCODE_LSO = 0x0e,
367 MLX4_OPCODE_RDMA_READ = 0x10,
368 MLX4_OPCODE_ATOMIC_CS = 0x11,
369 MLX4_OPCODE_ATOMIC_FA = 0x12,
370 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
371 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
372 MLX4_OPCODE_BIND_MW = 0x18,
373 MLX4_OPCODE_FMR = 0x19,
374 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
375 MLX4_OPCODE_CONFIG_CMD = 0x1f,
376
377 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
378 MLX4_RECV_OPCODE_SEND = 0x01,
379 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
380 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
381
382 MLX4_CQE_OPCODE_ERROR = 0x1e,
383 MLX4_CQE_OPCODE_RESIZE = 0x16,
384};
385
386enum {
387 MLX4_STAT_RATE_OFFSET = 5
388};
389
390enum mlx4_protocol {
391 MLX4_PROT_IB_IPV6 = 0,
392 MLX4_PROT_ETH,
393 MLX4_PROT_IB_IPV4,
394 MLX4_PROT_FCOE
395};
396
397enum {
398 MLX4_MTT_FLAG_PRESENT = 1
399};
400
401enum mlx4_qp_region {
402 MLX4_QP_REGION_FW = 0,
403 MLX4_QP_REGION_RSS_RAW_ETH,
404 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
405 MLX4_QP_REGION_ETH_ADDR,
406 MLX4_QP_REGION_FC_ADDR,
407 MLX4_QP_REGION_FC_EXCH,
408 MLX4_NUM_QP_REGION
409};
410
411enum mlx4_port_type {
412 MLX4_PORT_TYPE_NONE = 0,
413 MLX4_PORT_TYPE_IB = 1,
414 MLX4_PORT_TYPE_ETH = 2,
415 MLX4_PORT_TYPE_AUTO = 3
416};
417
418enum mlx4_special_vlan_idx {
419 MLX4_NO_VLAN_IDX = 0,
420 MLX4_VLAN_MISS_IDX,
421 MLX4_VLAN_REGULAR
422};
423
424enum mlx4_steer_type {
425 MLX4_MC_STEER = 0,
426 MLX4_UC_STEER,
427 MLX4_NUM_STEERS
428};
429
430enum mlx4_resource_usage {
431 MLX4_RES_USAGE_NONE,
432 MLX4_RES_USAGE_DRIVER,
433 MLX4_RES_USAGE_USER_VERBS,
434};
435
436enum {
437 MLX4_NUM_FEXCH = 64 * 1024,
438};
439
440enum {
441 MLX4_MAX_FAST_REG_PAGES = 511,
442};
443
444enum {
445
446
447
448
449
450
451
452 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
453};
454
455enum {
456 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
457 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
458 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
459 MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17,
460};
461
462
463enum {
464 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
465 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
466 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
467 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
468 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
469};
470
471union sl2vl_tbl_to_u64 {
472 u8 sl8[8];
473 u64 sl64;
474};
475
476enum {
477 MLX4_DEVICE_STATE_UP = 1 << 0,
478 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
479};
480
481enum {
482 MLX4_INTERFACE_STATE_UP = 1 << 0,
483 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
484 MLX4_INTERFACE_STATE_NOWAIT = 1 << 2,
485};
486
487#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
488 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
489
490enum mlx4_module_id {
491 MLX4_MODULE_ID_SFP = 0x3,
492 MLX4_MODULE_ID_QSFP = 0xC,
493 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
494 MLX4_MODULE_ID_QSFP28 = 0x11,
495};
496
497enum {
498 MLX4_QP_RATE_LIMIT_NONE = 0,
499 MLX4_QP_RATE_LIMIT_KBS = 1,
500 MLX4_QP_RATE_LIMIT_MBS = 2,
501 MLX4_QP_RATE_LIMIT_GBS = 3
502};
503
504struct mlx4_rate_limit_caps {
505 u16 num_rates;
506 u8 min_unit;
507 u16 min_val;
508 u8 max_unit;
509 u16 max_val;
510};
511
512static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
513{
514 return (major << 32) | (minor << 16) | subminor;
515}
516
517struct mlx4_phys_caps {
518 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
519 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
520 u32 num_phys_eqs;
521 u32 base_sqpn;
522 u32 base_proxy_sqpn;
523 u32 base_tunnel_sqpn;
524};
525
526struct mlx4_spec_qps {
527 u32 qp0_qkey;
528 u32 qp0_proxy;
529 u32 qp0_tunnel;
530 u32 qp1_proxy;
531 u32 qp1_tunnel;
532};
533
534struct mlx4_caps {
535 u64 fw_ver;
536 u32 function;
537 int num_ports;
538 int vl_cap[MLX4_MAX_PORTS + 1];
539 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
540 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
541 u64 def_mac[MLX4_MAX_PORTS + 1];
542 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
543 int gid_table_len[MLX4_MAX_PORTS + 1];
544 int pkey_table_len[MLX4_MAX_PORTS + 1];
545 int trans_type[MLX4_MAX_PORTS + 1];
546 int vendor_oui[MLX4_MAX_PORTS + 1];
547 int wavelength[MLX4_MAX_PORTS + 1];
548 u64 trans_code[MLX4_MAX_PORTS + 1];
549 int local_ca_ack_delay;
550 int num_uars;
551 u32 uar_page_size;
552 int bf_reg_size;
553 int bf_regs_per_page;
554 int max_sq_sg;
555 int max_rq_sg;
556 int num_qps;
557 int max_wqes;
558 int max_sq_desc_sz;
559 int max_rq_desc_sz;
560 int max_qp_init_rdma;
561 int max_qp_dest_rdma;
562 int max_tc_eth;
563 struct mlx4_spec_qps *spec_qps;
564 int num_srqs;
565 int max_srq_wqes;
566 int max_srq_sge;
567 int reserved_srqs;
568 int num_cqs;
569 int max_cqes;
570 int reserved_cqs;
571 int num_sys_eqs;
572 int num_eqs;
573 int reserved_eqs;
574 int num_comp_vectors;
575 int num_mpts;
576 int max_fmr_maps;
577 int num_mtts;
578 int fmr_reserved_mtts;
579 int reserved_mtts;
580 int reserved_mrws;
581 int reserved_uars;
582 int num_mgms;
583 int num_amgms;
584 int reserved_mcgs;
585 int num_qp_per_mgm;
586 int steering_mode;
587 int dmfs_high_steer_mode;
588 int fs_log_max_ucast_qp_range_size;
589 int num_pds;
590 int reserved_pds;
591 int max_xrcds;
592 int reserved_xrcds;
593 int mtt_entry_sz;
594 u32 max_msg_sz;
595 u32 page_size_cap;
596 u64 flags;
597 u64 flags2;
598 u32 bmme_flags;
599 u32 reserved_lkey;
600 u16 stat_rate_support;
601 u8 port_width_cap[MLX4_MAX_PORTS + 1];
602 int max_gso_sz;
603 int max_rss_tbl_sz;
604 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
605 int reserved_qps;
606 int reserved_qps_base[MLX4_NUM_QP_REGION];
607 int log_num_macs;
608 int log_num_vlans;
609 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
610 u8 supported_type[MLX4_MAX_PORTS + 1];
611 u8 suggested_type[MLX4_MAX_PORTS + 1];
612 u8 default_sense[MLX4_MAX_PORTS + 1];
613 u32 port_mask[MLX4_MAX_PORTS + 1];
614 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
615 u32 max_counters;
616 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
617 u16 sqp_demux;
618 u32 eqe_size;
619 u32 cqe_size;
620 u8 eqe_factor;
621 u32 userspace_caps;
622 u32 function_caps;
623 u16 hca_core_clock;
624 u64 phys_port_id[MLX4_MAX_PORTS + 1];
625 int tunnel_offload_mode;
626 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
627 u8 phv_bit[MLX4_MAX_PORTS + 1];
628 u8 alloc_res_qp_mask;
629 u32 dmfs_high_rate_qpn_base;
630 u32 dmfs_high_rate_qpn_range;
631 u32 vf_caps;
632 bool wol_port[MLX4_MAX_PORTS + 1];
633 struct mlx4_rate_limit_caps rl_caps;
634 u32 health_buffer_addrs;
635};
636
637struct mlx4_buf_list {
638 void *buf;
639 dma_addr_t map;
640};
641
642struct mlx4_buf {
643 struct mlx4_buf_list direct;
644 struct mlx4_buf_list *page_list;
645 int nbufs;
646 int npages;
647 int page_shift;
648};
649
650struct mlx4_mtt {
651 u32 offset;
652 int order;
653 int page_shift;
654};
655
656enum {
657 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
658};
659
660struct mlx4_db_pgdir {
661 struct list_head list;
662 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
663 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
664 unsigned long *bits[2];
665 __be32 *db_page;
666 dma_addr_t db_dma;
667};
668
669struct mlx4_ib_user_db_page;
670
671struct mlx4_db {
672 __be32 *db;
673 union {
674 struct mlx4_db_pgdir *pgdir;
675 struct mlx4_ib_user_db_page *user_page;
676 } u;
677 dma_addr_t dma;
678 int index;
679 int order;
680};
681
682struct mlx4_hwq_resources {
683 struct mlx4_db db;
684 struct mlx4_mtt mtt;
685 struct mlx4_buf buf;
686};
687
688struct mlx4_mr {
689 struct mlx4_mtt mtt;
690 u64 iova;
691 u64 size;
692 u32 key;
693 u32 pd;
694 u32 access;
695 int enabled;
696};
697
698enum mlx4_mw_type {
699 MLX4_MW_TYPE_1 = 1,
700 MLX4_MW_TYPE_2 = 2,
701};
702
703struct mlx4_mw {
704 u32 key;
705 u32 pd;
706 enum mlx4_mw_type type;
707 int enabled;
708};
709
710struct mlx4_fmr {
711 struct mlx4_mr mr;
712 struct mlx4_mpt_entry *mpt;
713 __be64 *mtts;
714 dma_addr_t dma_handle;
715 int max_pages;
716 int max_maps;
717 int maps;
718 u8 page_shift;
719};
720
721struct mlx4_uar {
722 unsigned long pfn;
723 int index;
724 struct list_head bf_list;
725 unsigned free_bf_bmap;
726 void __iomem *map;
727 void __iomem *bf_map;
728};
729
730struct mlx4_bf {
731 unsigned int offset;
732 int buf_size;
733 struct mlx4_uar *uar;
734 void __iomem *reg;
735};
736
737struct mlx4_cq {
738 void (*comp) (struct mlx4_cq *);
739 void (*event) (struct mlx4_cq *, enum mlx4_event);
740
741 struct mlx4_uar *uar;
742
743 u32 cons_index;
744
745 u16 irq;
746 __be32 *set_ci_db;
747 __be32 *arm_db;
748 int arm_sn;
749
750 int cqn;
751 unsigned vector;
752
753 refcount_t refcount;
754 struct completion free;
755 struct {
756 struct list_head list;
757 void (*comp)(struct mlx4_cq *);
758 void *priv;
759 } tasklet_ctx;
760 int reset_notify_added;
761 struct list_head reset_notify;
762 u8 usage;
763};
764
765struct mlx4_qp {
766 void (*event) (struct mlx4_qp *, enum mlx4_event);
767
768 int qpn;
769
770 refcount_t refcount;
771 struct completion free;
772 u8 usage;
773};
774
775struct mlx4_srq {
776 void (*event) (struct mlx4_srq *, enum mlx4_event);
777
778 int srqn;
779 int max;
780 int max_gs;
781 int wqe_shift;
782
783 refcount_t refcount;
784 struct completion free;
785};
786
787struct mlx4_av {
788 __be32 port_pd;
789 u8 reserved1;
790 u8 g_slid;
791 __be16 dlid;
792 u8 reserved2;
793 u8 gid_index;
794 u8 stat_rate;
795 u8 hop_limit;
796 __be32 sl_tclass_flowlabel;
797 u8 dgid[16];
798};
799
800struct mlx4_eth_av {
801 __be32 port_pd;
802 u8 reserved1;
803 u8 smac_idx;
804 u16 reserved2;
805 u8 reserved3;
806 u8 gid_index;
807 u8 stat_rate;
808 u8 hop_limit;
809 __be32 sl_tclass_flowlabel;
810 u8 dgid[16];
811 u8 s_mac[6];
812 u8 reserved4[2];
813 __be16 vlan;
814 u8 mac[ETH_ALEN];
815};
816
817union mlx4_ext_av {
818 struct mlx4_av ib;
819 struct mlx4_eth_av eth;
820};
821
822
823#define ASSIGN_32BIT_COUNTER(counter, value) do { \
824 if ((value) > U32_MAX) \
825 counter = cpu_to_be32(U32_MAX); \
826 else \
827 counter = cpu_to_be32(value); \
828} while (0)
829
830struct mlx4_counter {
831 u8 reserved1[3];
832 u8 counter_mode;
833 __be32 num_ifc;
834 u32 reserved2[2];
835 __be64 rx_frames;
836 __be64 rx_bytes;
837 __be64 tx_frames;
838 __be64 tx_bytes;
839};
840
841struct mlx4_quotas {
842 int qp;
843 int cq;
844 int srq;
845 int mpt;
846 int mtt;
847 int counter;
848 int xrcd;
849};
850
851struct mlx4_vf_dev {
852 u8 min_port;
853 u8 n_ports;
854};
855
856struct mlx4_fw_crdump {
857 bool snapshot_enable;
858 struct devlink_region *region_crspace;
859 struct devlink_region *region_fw_health;
860};
861
862enum mlx4_pci_status {
863 MLX4_PCI_STATUS_DISABLED,
864 MLX4_PCI_STATUS_ENABLED,
865};
866
867struct mlx4_dev_persistent {
868 struct pci_dev *pdev;
869 struct mlx4_dev *dev;
870 int nvfs[MLX4_MAX_PORTS + 1];
871 int num_vfs;
872 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
873 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
874 struct work_struct catas_work;
875 struct workqueue_struct *catas_wq;
876 struct mutex device_state_mutex;
877 u8 state;
878 struct mutex interface_state_mutex;
879 u8 interface_state;
880 struct mutex pci_status_mutex;
881 enum mlx4_pci_status pci_status;
882 struct mlx4_fw_crdump crdump;
883};
884
885struct mlx4_dev {
886 struct mlx4_dev_persistent *persist;
887 unsigned long flags;
888 unsigned long num_slaves;
889 struct mlx4_caps caps;
890 struct mlx4_phys_caps phys_caps;
891 struct mlx4_quotas quotas;
892 struct radix_tree_root qp_table_tree;
893 u8 rev_id;
894 u8 port_random_macs;
895 char board_id[MLX4_BOARD_ID_LEN];
896 int numa_node;
897 int oper_log_mgm_entry_size;
898 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
899 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
900 struct mlx4_vf_dev *dev_vfs;
901 u8 uar_page_shift;
902};
903
904struct mlx4_clock_params {
905 u64 offset;
906 u8 bar;
907 u8 size;
908};
909
910struct mlx4_eqe {
911 u8 reserved1;
912 u8 type;
913 u8 reserved2;
914 u8 subtype;
915 union {
916 u32 raw[6];
917 struct {
918 __be32 cqn;
919 } __packed comp;
920 struct {
921 u16 reserved1;
922 __be16 token;
923 u32 reserved2;
924 u8 reserved3[3];
925 u8 status;
926 __be64 out_param;
927 } __packed cmd;
928 struct {
929 __be32 qpn;
930 } __packed qp;
931 struct {
932 __be32 srqn;
933 } __packed srq;
934 struct {
935 __be32 cqn;
936 u32 reserved1;
937 u8 reserved2[3];
938 u8 syndrome;
939 } __packed cq_err;
940 struct {
941 u32 reserved1[2];
942 __be32 port;
943 } __packed port_change;
944 struct {
945 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
946 u32 reserved;
947 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
948 } __packed comm_channel_arm;
949 struct {
950 u8 port;
951 u8 reserved[3];
952 __be64 mac;
953 } __packed mac_update;
954 struct {
955 __be32 slave_id;
956 } __packed flr_event;
957 struct {
958 __be16 current_temperature;
959 __be16 warning_threshold;
960 } __packed warming;
961 struct {
962 u8 reserved[3];
963 u8 port;
964 union {
965 struct {
966 __be16 mstr_sm_lid;
967 __be16 port_lid;
968 __be32 changed_attr;
969 u8 reserved[3];
970 u8 mstr_sm_sl;
971 __be64 gid_prefix;
972 } __packed port_info;
973 struct {
974 __be32 block_ptr;
975 __be32 tbl_entries_mask;
976 } __packed tbl_change_info;
977 struct {
978 u8 sl2vl_table[8];
979 } __packed sl2vl_tbl_change_info;
980 } params;
981 } __packed port_mgmt_change;
982 struct {
983 u8 reserved[3];
984 u8 port;
985 u32 reserved1[5];
986 } __packed bad_cable;
987 } event;
988 u8 slave_id;
989 u8 reserved3[2];
990 u8 owner;
991} __packed;
992
993struct mlx4_init_port_param {
994 int set_guid0;
995 int set_node_guid;
996 int set_si_guid;
997 u16 mtu;
998 int port_width_cap;
999 u16 vl_cap;
1000 u16 max_gid;
1001 u16 max_pkey;
1002 u64 guid0;
1003 u64 node_guid;
1004 u64 si_guid;
1005};
1006
1007#define MAD_IFC_DATA_SZ 192
1008
1009struct mlx4_mad_ifc {
1010 u8 base_version;
1011 u8 mgmt_class;
1012 u8 class_version;
1013 u8 method;
1014 __be16 status;
1015 __be16 class_specific;
1016 __be64 tid;
1017 __be16 attr_id;
1018 __be16 resv;
1019 __be32 attr_mod;
1020 __be64 mkey;
1021 __be16 dr_slid;
1022 __be16 dr_dlid;
1023 u8 reserved[28];
1024 u8 data[MAD_IFC_DATA_SZ];
1025} __packed;
1026
1027#define mlx4_foreach_port(port, dev, type) \
1028 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1029 if ((type) == (dev)->caps.port_mask[(port)])
1030
1031#define mlx4_foreach_ib_transport_port(port, dev) \
1032 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1033 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
1034 ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH))
1035
1036#define MLX4_INVALID_SLAVE_ID 0xFF
1037#define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
1038
1039void handle_port_mgmt_change_event(struct work_struct *work);
1040
1041static inline int mlx4_master_func_num(struct mlx4_dev *dev)
1042{
1043 return dev->caps.function;
1044}
1045
1046static inline int mlx4_is_master(struct mlx4_dev *dev)
1047{
1048 return dev->flags & MLX4_FLAG_MASTER;
1049}
1050
1051static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1052{
1053 return dev->phys_caps.base_sqpn + 8 +
1054 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1055}
1056
1057static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1058{
1059 return (qpn < dev->phys_caps.base_sqpn + 8 +
1060 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1061 qpn >= dev->phys_caps.base_sqpn) ||
1062 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1063}
1064
1065static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1066{
1067 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1068
1069 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1070 return 1;
1071
1072 return 0;
1073}
1074
1075static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1076{
1077 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1078}
1079
1080static inline int mlx4_is_slave(struct mlx4_dev *dev)
1081{
1082 return dev->flags & MLX4_FLAG_SLAVE;
1083}
1084
1085static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1086{
1087 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1088}
1089
1090int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1091 struct mlx4_buf *buf);
1092void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1093static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1094{
1095 if (buf->nbufs == 1)
1096 return buf->direct.buf + offset;
1097 else
1098 return buf->page_list[offset >> PAGE_SHIFT].buf +
1099 (offset & (PAGE_SIZE - 1));
1100}
1101
1102int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1103void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1104int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1105void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1106
1107int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1108void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1109int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1110void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1111
1112int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1113 struct mlx4_mtt *mtt);
1114void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1115u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1116
1117int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1118 int npages, int page_shift, struct mlx4_mr *mr);
1119int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1120int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1121int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1122 struct mlx4_mw *mw);
1123void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1124int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1125int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1126 int start_index, int npages, u64 *page_list);
1127int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1128 struct mlx4_buf *buf);
1129
1130int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
1131void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1132
1133int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1134 int size);
1135void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1136 int size);
1137
1138int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1139 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1140 unsigned int vector, int collapsed, int timestamp_en,
1141 void *buf_addr, bool user_cq);
1142void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1143int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1144 int *base, u8 flags, u8 usage);
1145void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1146
1147int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
1148void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1149
1150int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1151 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1152void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1153int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1154int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1155
1156int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1157int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1158
1159int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1160 int block_mcast_loopback, enum mlx4_protocol prot);
1161int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1162 enum mlx4_protocol prot);
1163int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1164 u8 port, int block_mcast_loopback,
1165 enum mlx4_protocol protocol, u64 *reg_id);
1166int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1167 enum mlx4_protocol protocol, u64 reg_id);
1168
1169enum {
1170 MLX4_DOMAIN_UVERBS = 0x1000,
1171 MLX4_DOMAIN_ETHTOOL = 0x2000,
1172 MLX4_DOMAIN_RFS = 0x3000,
1173 MLX4_DOMAIN_NIC = 0x5000,
1174};
1175
1176enum mlx4_net_trans_rule_id {
1177 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1178 MLX4_NET_TRANS_RULE_ID_IB,
1179 MLX4_NET_TRANS_RULE_ID_IPV6,
1180 MLX4_NET_TRANS_RULE_ID_IPV4,
1181 MLX4_NET_TRANS_RULE_ID_TCP,
1182 MLX4_NET_TRANS_RULE_ID_UDP,
1183 MLX4_NET_TRANS_RULE_ID_VXLAN,
1184 MLX4_NET_TRANS_RULE_NUM,
1185};
1186
1187extern const u16 __sw_id_hw[];
1188
1189static inline int map_hw_to_sw_id(u16 header_id)
1190{
1191
1192 int i;
1193 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1194 if (header_id == __sw_id_hw[i])
1195 return i;
1196 }
1197 return -EINVAL;
1198}
1199
1200enum mlx4_net_trans_promisc_mode {
1201 MLX4_FS_REGULAR = 1,
1202 MLX4_FS_ALL_DEFAULT,
1203 MLX4_FS_MC_DEFAULT,
1204 MLX4_FS_MIRROR_RX_PORT,
1205 MLX4_FS_MIRROR_SX_PORT,
1206 MLX4_FS_UC_SNIFFER,
1207 MLX4_FS_MC_SNIFFER,
1208 MLX4_FS_MODE_NUM,
1209};
1210
1211struct mlx4_spec_eth {
1212 u8 dst_mac[ETH_ALEN];
1213 u8 dst_mac_msk[ETH_ALEN];
1214 u8 src_mac[ETH_ALEN];
1215 u8 src_mac_msk[ETH_ALEN];
1216 u8 ether_type_enable;
1217 __be16 ether_type;
1218 __be16 vlan_id_msk;
1219 __be16 vlan_id;
1220};
1221
1222struct mlx4_spec_tcp_udp {
1223 __be16 dst_port;
1224 __be16 dst_port_msk;
1225 __be16 src_port;
1226 __be16 src_port_msk;
1227};
1228
1229struct mlx4_spec_ipv4 {
1230 __be32 dst_ip;
1231 __be32 dst_ip_msk;
1232 __be32 src_ip;
1233 __be32 src_ip_msk;
1234};
1235
1236struct mlx4_spec_ib {
1237 __be32 l3_qpn;
1238 __be32 qpn_msk;
1239 u8 dst_gid[16];
1240 u8 dst_gid_msk[16];
1241};
1242
1243struct mlx4_spec_vxlan {
1244 __be32 vni;
1245 __be32 vni_mask;
1246
1247};
1248
1249struct mlx4_spec_list {
1250 struct list_head list;
1251 enum mlx4_net_trans_rule_id id;
1252 union {
1253 struct mlx4_spec_eth eth;
1254 struct mlx4_spec_ib ib;
1255 struct mlx4_spec_ipv4 ipv4;
1256 struct mlx4_spec_tcp_udp tcp_udp;
1257 struct mlx4_spec_vxlan vxlan;
1258 };
1259};
1260
1261enum mlx4_net_trans_hw_rule_queue {
1262 MLX4_NET_TRANS_Q_FIFO,
1263 MLX4_NET_TRANS_Q_LIFO,
1264};
1265
1266struct mlx4_net_trans_rule {
1267 struct list_head list;
1268 enum mlx4_net_trans_hw_rule_queue queue_mode;
1269 bool exclusive;
1270 bool allow_loopback;
1271 enum mlx4_net_trans_promisc_mode promisc_mode;
1272 u8 port;
1273 u16 priority;
1274 u32 qpn;
1275};
1276
1277struct mlx4_net_trans_rule_hw_ctrl {
1278 __be16 prio;
1279 u8 type;
1280 u8 flags;
1281 u8 rsvd1;
1282 u8 funcid;
1283 u8 vep;
1284 u8 port;
1285 __be32 qpn;
1286 __be32 rsvd2;
1287};
1288
1289struct mlx4_net_trans_rule_hw_ib {
1290 u8 size;
1291 u8 rsvd1;
1292 __be16 id;
1293 u32 rsvd2;
1294 __be32 l3_qpn;
1295 __be32 qpn_mask;
1296 u8 dst_gid[16];
1297 u8 dst_gid_msk[16];
1298} __packed;
1299
1300struct mlx4_net_trans_rule_hw_eth {
1301 u8 size;
1302 u8 rsvd;
1303 __be16 id;
1304 u8 rsvd1[6];
1305 u8 dst_mac[6];
1306 u16 rsvd2;
1307 u8 dst_mac_msk[6];
1308 u16 rsvd3;
1309 u8 src_mac[6];
1310 u16 rsvd4;
1311 u8 src_mac_msk[6];
1312 u8 rsvd5;
1313 u8 ether_type_enable;
1314 __be16 ether_type;
1315 __be16 vlan_tag_msk;
1316 __be16 vlan_tag;
1317} __packed;
1318
1319struct mlx4_net_trans_rule_hw_tcp_udp {
1320 u8 size;
1321 u8 rsvd;
1322 __be16 id;
1323 __be16 rsvd1[3];
1324 __be16 dst_port;
1325 __be16 rsvd2;
1326 __be16 dst_port_msk;
1327 __be16 rsvd3;
1328 __be16 src_port;
1329 __be16 rsvd4;
1330 __be16 src_port_msk;
1331} __packed;
1332
1333struct mlx4_net_trans_rule_hw_ipv4 {
1334 u8 size;
1335 u8 rsvd;
1336 __be16 id;
1337 __be32 rsvd1;
1338 __be32 dst_ip;
1339 __be32 dst_ip_msk;
1340 __be32 src_ip;
1341 __be32 src_ip_msk;
1342} __packed;
1343
1344struct mlx4_net_trans_rule_hw_vxlan {
1345 u8 size;
1346 u8 rsvd;
1347 __be16 id;
1348 __be32 rsvd1;
1349 __be32 vni;
1350 __be32 vni_mask;
1351} __packed;
1352
1353struct _rule_hw {
1354 union {
1355 struct {
1356 u8 size;
1357 u8 rsvd;
1358 __be16 id;
1359 };
1360 struct mlx4_net_trans_rule_hw_eth eth;
1361 struct mlx4_net_trans_rule_hw_ib ib;
1362 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1363 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1364 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1365 };
1366};
1367
1368enum {
1369 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1370 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1371 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1372 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1373 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1374};
1375
1376enum {
1377 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
1378};
1379
1380int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1381 enum mlx4_net_trans_promisc_mode mode);
1382int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1383 enum mlx4_net_trans_promisc_mode mode);
1384int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1385int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1386int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1387int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1388int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1389
1390int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1391void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1392int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1393int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1394int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1395 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1396int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac);
1397int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu);
1398int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1399 u8 promisc);
1400int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1401int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1402 u8 ignore_fcs_value);
1403int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1404int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1405int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1406int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port,
1407 bool *vlan_offload_disabled);
1408void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
1409 struct _rule_hw *eth_header);
1410int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1411int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1412int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1413void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1414
1415int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1416 int npages, u64 iova, u32 *lkey, u32 *rkey);
1417int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1418 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1419int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1420void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1421 u32 *lkey, u32 *rkey);
1422int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1423int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1424int mlx4_test_interrupt(struct mlx4_dev *dev, int vector);
1425int mlx4_test_async(struct mlx4_dev *dev);
1426int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
1427 const u32 offset[], u32 value[],
1428 size_t array_len, u8 port);
1429u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1430bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1431struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1432int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1433void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1434
1435int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1436int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1437
1438int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1439int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1440int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1441
1442int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage);
1443void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1444int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1445
1446void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1447 int port);
1448__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1449void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1450int mlx4_flow_attach(struct mlx4_dev *dev,
1451 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1452int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1453int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1454 enum mlx4_net_trans_promisc_mode flow_type);
1455int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1456 enum mlx4_net_trans_rule_id id);
1457int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1458
1459int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1460 int port, int qpn, u16 prio, u64 *reg_id);
1461
1462void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1463 int i, int val);
1464
1465int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1466
1467int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1468int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1469int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1470int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1471int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1472enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1473int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1474
1475void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1476__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1477
1478int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1479 int *slave_id);
1480int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1481 u8 *gid);
1482
1483int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1484 u32 max_range_qpn);
1485
1486u64 mlx4_read_clock(struct mlx4_dev *dev);
1487
1488struct mlx4_active_ports {
1489 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1490};
1491
1492struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1493
1494
1495
1496
1497int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1498
1499struct mlx4_slaves_pport {
1500 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1501};
1502
1503struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1504 int port);
1505
1506
1507
1508struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1509 struct mlx4_dev *dev,
1510 const struct mlx4_active_ports *crit_ports);
1511
1512
1513int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1514
1515int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1516
1517int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1518int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1519int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1520int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1521int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1522int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1523int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1524 int enable);
1525int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1526 struct mlx4_mpt_entry ***mpt_entry);
1527int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1528 struct mlx4_mpt_entry **mpt_entry);
1529int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1530 u32 pdn);
1531int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1532 struct mlx4_mpt_entry *mpt_entry,
1533 u32 access);
1534void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1535 struct mlx4_mpt_entry **mpt_entry);
1536void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1537int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1538 u64 iova, u64 size, int npages,
1539 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1540
1541int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1542 u16 offset, u16 size, u8 *data);
1543int mlx4_max_tc(struct mlx4_dev *dev);
1544
1545
1546static inline bool mlx4_low_memory_profile(void)
1547{
1548 return is_kdump_kernel();
1549}
1550
1551
1552enum mlx4_access_reg_method {
1553 MLX4_ACCESS_REG_QUERY = 0x1,
1554 MLX4_ACCESS_REG_WRITE = 0x2,
1555};
1556
1557
1558enum mlx4_ptys_proto {
1559 MLX4_PTYS_IB = 1<<0,
1560 MLX4_PTYS_EN = 1<<2,
1561};
1562
1563enum mlx4_ptys_flags {
1564 MLX4_PTYS_AN_DISABLE_CAP = 1 << 5,
1565 MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6,
1566};
1567
1568struct mlx4_ptys_reg {
1569 u8 flags;
1570 u8 local_port;
1571 u8 resrvd2;
1572 u8 proto_mask;
1573 __be32 resrvd3[2];
1574 __be32 eth_proto_cap;
1575 __be16 ib_width_cap;
1576 __be16 ib_speed_cap;
1577 __be32 resrvd4;
1578 __be32 eth_proto_admin;
1579 __be16 ib_width_admin;
1580 __be16 ib_speed_admin;
1581 __be32 resrvd5;
1582 __be32 eth_proto_oper;
1583 __be16 ib_width_oper;
1584 __be16 ib_speed_oper;
1585 __be32 resrvd6;
1586 __be32 eth_proto_lp_adv;
1587} __packed;
1588
1589int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1590 enum mlx4_access_reg_method method,
1591 struct mlx4_ptys_reg *ptys_reg);
1592
1593int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1594 struct mlx4_clock_params *params);
1595
1596static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
1597{
1598 return (index << (PAGE_SHIFT - dev->uar_page_shift));
1599}
1600
1601static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
1602{
1603
1604 return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
1605}
1606#endif
1607
