1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * mt8183-reg.h -- Mediatek 8183 audio driver reg definition 4 * 5 * Copyright (c) 2018 MediaTek Inc. 6 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 */ 8 9#ifndef _MT8183_REG_H_ 10#define _MT8183_REG_H_ 11 12#define AUDIO_TOP_CON0 0x0000 13#define AUDIO_TOP_CON1 0x0004 14#define AUDIO_TOP_CON3 0x000c 15#define AFE_DAC_CON0 0x0010 16#define AFE_DAC_CON1 0x0014 17#define AFE_I2S_CON 0x0018 18#define AFE_DAIBT_CON0 0x001c 19#define AFE_CONN0 0x0020 20#define AFE_CONN1 0x0024 21#define AFE_CONN2 0x0028 22#define AFE_CONN3 0x002c 23#define AFE_CONN4 0x0030 24#define AFE_I2S_CON1 0x0034 25#define AFE_I2S_CON2 0x0038 26#define AFE_MRGIF_CON 0x003c 27#define AFE_DL1_BASE 0x0040 28#define AFE_DL1_CUR 0x0044 29#define AFE_DL1_END 0x0048 30#define AFE_I2S_CON3 0x004c 31#define AFE_DL2_BASE 0x0050 32#define AFE_DL2_CUR 0x0054 33#define AFE_DL2_END 0x0058 34#define AFE_CONN5 0x005c 35#define AFE_CONN_24BIT 0x006c 36#define AFE_AWB_BASE 0x0070 37#define AFE_AWB_END 0x0078 38#define AFE_AWB_CUR 0x007c 39#define AFE_VUL_BASE 0x0080 40#define AFE_VUL_END 0x0088 41#define AFE_VUL_CUR 0x008c 42#define AFE_CONN6 0x00bc 43#define AFE_MEMIF_MSB 0x00cc 44#define AFE_MEMIF_MON0 0x00d0 45#define AFE_MEMIF_MON1 0x00d4 46#define AFE_MEMIF_MON2 0x00d8 47#define AFE_MEMIF_MON3 0x00dc 48#define AFE_MEMIF_MON4 0x00e0 49#define AFE_MEMIF_MON5 0x00e4 50#define AFE_MEMIF_MON6 0x00e8 51#define AFE_MEMIF_MON7 0x00ec 52#define AFE_MEMIF_MON8 0x00f0 53#define AFE_MEMIF_MON9 0x00f4 54#define AFE_ADDA_DL_SRC2_CON0 0x0108 55#define AFE_ADDA_DL_SRC2_CON1 0x010c 56#define AFE_ADDA_UL_SRC_CON0 0x0114 57#define AFE_ADDA_UL_SRC_CON1 0x0118 58#define AFE_ADDA_TOP_CON0 0x0120 59#define AFE_ADDA_UL_DL_CON0 0x0124 60#define AFE_ADDA_SRC_DEBUG 0x012c 61#define AFE_ADDA_SRC_DEBUG_MON0 0x0130 62#define AFE_ADDA_SRC_DEBUG_MON1 0x0134 63#define AFE_ADDA_UL_SRC_MON0 0x0148 64#define AFE_ADDA_UL_SRC_MON1 0x014c 65#define AFE_SIDETONE_DEBUG 0x01d0 66#define AFE_SIDETONE_MON 0x01d4 67#define AFE_SINEGEN_CON2 0x01dc 68#define AFE_SIDETONE_CON0 0x01e0 69#define AFE_SIDETONE_COEFF 0x01e4 70#define AFE_SIDETONE_CON1 0x01e8 71#define AFE_SIDETONE_GAIN 0x01ec 72#define AFE_SINEGEN_CON0 0x01f0 73#define AFE_TOP_CON0 0x0200 74#define AFE_BUS_CFG 0x0240 75#define AFE_BUS_MON0 0x0244 76#define AFE_ADDA_PREDIS_CON0 0x0260 77#define AFE_ADDA_PREDIS_CON1 0x0264 78#define AFE_MRGIF_MON0 0x0270 79#define AFE_MRGIF_MON1 0x0274 80#define AFE_MRGIF_MON2 0x0278 81#define AFE_I2S_MON 0x027c 82#define AFE_ADDA_IIR_COEF_02_01 0x0290 83#define AFE_ADDA_IIR_COEF_04_03 0x0294 84#define AFE_ADDA_IIR_COEF_06_05 0x0298 85#define AFE_ADDA_IIR_COEF_08_07 0x029c 86#define AFE_ADDA_IIR_COEF_10_09 0x02a0 87#define AFE_DAC_CON2 0x02e0 88#define AFE_IRQ_MCU_CON1 0x02e4 89#define AFE_IRQ_MCU_CON2 0x02e8 90#define AFE_DAC_MON 0x02ec 91#define AFE_VUL2_BASE 0x02f0 92#define AFE_VUL2_END 0x02f8 93#define AFE_VUL2_CUR 0x02fc 94#define AFE_IRQ_MCU_CNT0 0x0300 95#define AFE_IRQ_MCU_CNT6 0x0304 96#define AFE_IRQ_MCU_CNT8 0x0308 97#define AFE_IRQ_MCU_EN1 0x030c 98#define AFE_IRQ0_MCU_CNT_MON 0x0310 99#define AFE_IRQ6_MCU_CNT_MON 0x0314 100#define AFE_MOD_DAI_BASE 0x0330 101#define AFE_MOD_DAI_END 0x0338 102#define AFE_MOD_DAI_CUR 0x033c 103#define AFE_VUL_D2_BASE 0x0350 104#define AFE_VUL_D2_END 0x0358 105#define AFE_VUL_D2_CUR 0x035c 106#define AFE_DL3_BASE 0x0360 107#define AFE_DL3_CUR 0x0364 108#define AFE_DL3_END 0x0368 109#define AFE_HDMI_OUT_CON0 0x0370 110#define AFE_HDMI_OUT_BASE 0x0374 111#define AFE_HDMI_OUT_CUR 0x0378 112#define AFE_HDMI_OUT_END 0x037c 113#define AFE_HDMI_CONN0 0x0390 114#define AFE_IRQ3_MCU_CNT_MON 0x0398 115#define AFE_IRQ4_MCU_CNT_MON 0x039c 116#define AFE_IRQ_MCU_CON0 0x03a0 117#define AFE_IRQ_MCU_STATUS 0x03a4 118#define AFE_IRQ_MCU_CLR 0x03a8 119#define AFE_IRQ_MCU_CNT1 0x03ac 120#define AFE_IRQ_MCU_CNT2 0x03b0 121#define AFE_IRQ_MCU_EN 0x03b4 122#define AFE_IRQ_MCU_MON2 0x03b8 123#define AFE_IRQ_MCU_CNT5 0x03bc 124#define AFE_IRQ1_MCU_CNT_MON 0x03c0 125#define AFE_IRQ2_MCU_CNT_MON 0x03c4 126#define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8 127#define AFE_IRQ5_MCU_CNT_MON 0x03cc 128#define AFE_MEMIF_MINLEN 0x03d0 129#define AFE_MEMIF_MAXLEN 0x03d4 130#define AFE_MEMIF_PBUF_SIZE 0x03d8 131#define AFE_IRQ_MCU_CNT7 0x03dc 132#define AFE_IRQ7_MCU_CNT_MON 0x03e0 133#define AFE_IRQ_MCU_CNT3 0x03e4 134#define AFE_IRQ_MCU_CNT4 0x03e8 135#define AFE_IRQ_MCU_CNT11 0x03ec 136#define AFE_APLL1_TUNER_CFG 0x03f0 137#define AFE_APLL2_TUNER_CFG 0x03f4 138#define AFE_MEMIF_HD_MODE 0x03f8 139#define AFE_MEMIF_HDALIGN 0x03fc 140#define AFE_CONN33 0x0408 141#define AFE_IRQ_MCU_CNT12 0x040c 142#define AFE_GAIN1_CON0 0x0410 143#define AFE_GAIN1_CON1 0x0414 144#define AFE_GAIN1_CON2 0x0418 145#define AFE_GAIN1_CON3 0x041c 146#define AFE_CONN7 0x0420 147#define AFE_GAIN1_CUR 0x0424 148#define AFE_GAIN2_CON0 0x0428 149#define AFE_GAIN2_CON1 0x042c 150#define AFE_GAIN2_CON2 0x0430 151#define AFE_GAIN2_CON3 0x0434 152#define AFE_CONN8 0x0438 153#define AFE_GAIN2_CUR 0x043c 154#define AFE_CONN9 0x0440 155#define AFE_CONN10 0x0444 156#define AFE_CONN11 0x0448 157#define AFE_CONN12 0x044c 158#define AFE_CONN13 0x0450 159#define AFE_CONN14 0x0454 160#define AFE_CONN15 0x0458 161#define AFE_CONN16 0x045c 162#define AFE_CONN17 0x0460 163#define AFE_CONN18 0x0464 164#define AFE_CONN19 0x0468 165#define AFE_CONN20 0x046c 166#define AFE_CONN21 0x0470 167#define AFE_CONN22 0x0474 168#define AFE_CONN23 0x0478 169#define AFE_CONN24 0x047c 170#define AFE_CONN_RS 0x0494 171#define AFE_CONN_DI 0x0498 172#define AFE_CONN25 0x04b0 173#define AFE_CONN26 0x04b4 174#define AFE_CONN27 0x04b8 175#define AFE_CONN28 0x04bc 176#define AFE_CONN29 0x04c0 177#define AFE_CONN30 0x04c4 178#define AFE_CONN31 0x04c8 179#define AFE_CONN32 0x04cc 180#define AFE_SRAM_DELSEL_CON0 0x04f0 181#define AFE_SRAM_DELSEL_CON2 0x04f8 182#define AFE_SRAM_DELSEL_CON3 0x04fc 183#define AFE_ASRC_2CH_CON12 0x0528 184#define AFE_ASRC_2CH_CON13 0x052c 185#define PCM_INTF_CON1 0x0530 186#define PCM_INTF_CON2 0x0538 187#define PCM2_INTF_CON 0x053c 188#define AFE_TDM_CON1 0x0548 189#define AFE_TDM_CON2 0x054c 190#define AFE_CONN34 0x0580 191#define FPGA_CFG0 0x05b0 192#define FPGA_CFG1 0x05b4 193#define FPGA_CFG2 0x05c0 194#define FPGA_CFG3 0x05c4 195#define AUDIO_TOP_DBG_CON 0x05c8 196#define AUDIO_TOP_DBG_MON0 0x05cc 197#define AUDIO_TOP_DBG_MON1 0x05d0 198#define AFE_IRQ8_MCU_CNT_MON 0x05e4 199#define AFE_IRQ11_MCU_CNT_MON 0x05e8 200#define AFE_IRQ12_MCU_CNT_MON 0x05ec 201#define AFE_GENERAL_REG0 0x0800 202#define AFE_GENERAL_REG1 0x0804 203#define AFE_GENERAL_REG2 0x0808 204#define AFE_GENERAL_REG3 0x080c 205#define AFE_GENERAL_REG4 0x0810 206#define AFE_GENERAL_REG5 0x0814 207#define AFE_GENERAL_REG6 0x0818 208#define AFE_GENERAL_REG7 0x081c 209#define AFE_GENERAL_REG8 0x0820 210#define AFE_GENERAL_REG9 0x0824 211#define AFE_GENERAL_REG10 0x0828 212#define AFE_GENERAL_REG11 0x082c 213#define AFE_GENERAL_REG12 0x0830 214#define AFE_GENERAL_REG13 0x0834 215#define AFE_GENERAL_REG14 0x0838 216#define AFE_GENERAL_REG15 0x083c 217#define AFE_CBIP_CFG0 0x0840 218#define AFE_CBIP_MON0 0x0844 219#define AFE_CBIP_SLV_MUX_MON0 0x0848 220#define AFE_CBIP_SLV_DECODER_MON0 0x084c 221#define AFE_CONN0_1 0x0900 222#define AFE_CONN1_1 0x0904 223#define AFE_CONN2_1 0x0908 224#define AFE_CONN3_1 0x090c 225#define AFE_CONN4_1 0x0910 226#define AFE_CONN5_1 0x0914 227#define AFE_CONN6_1 0x0918 228#define AFE_CONN7_1 0x091c 229#define AFE_CONN8_1 0x0920 230#define AFE_CONN9_1 0x0924 231#define AFE_CONN10_1 0x0928 232#define AFE_CONN11_1 0x092c 233#define AFE_CONN12_1 0x0930 234#define AFE_CONN13_1 0x0934 235#define AFE_CONN14_1 0x0938 236#define AFE_CONN15_1 0x093c 237#define AFE_CONN16_1 0x0940 238#define AFE_CONN17_1 0x0944 239#define AFE_CONN18_1 0x0948 240#define AFE_CONN19_1 0x094c 241#define AFE_CONN20_1 0x0950 242#define AFE_CONN21_1 0x0954 243#define AFE_CONN22_1 0x0958 244#define AFE_CONN23_1 0x095c 245#define AFE_CONN24_1 0x0960 246#define AFE_CONN25_1 0x0964 247#define AFE_CONN26_1 0x0968 248#define AFE_CONN27_1 0x096c 249#define AFE_CONN28_1 0x0970 250#define AFE_CONN29_1 0x0974 251#define AFE_CONN30_1 0x0978 252#define AFE_CONN31_1 0x097c 253#define AFE_CONN32_1 0x0980 254#define AFE_CONN33_1 0x0984 255#define AFE_CONN34_1 0x0988 256#define AFE_CONN_RS_1 0x098c 257#define AFE_CONN_DI_1 0x0990 258#define AFE_CONN_24BIT_1 0x0994 259#define AFE_CONN_REG 0x0998 260#define AFE_CONN35 0x09a0 261#define AFE_CONN36 0x09a4 262#define AFE_CONN37 0x09a8 263#define AFE_CONN38 0x09ac 264#define AFE_CONN35_1 0x09b0 265#define AFE_CONN36_1 0x09b4 266#define AFE_CONN37_1 0x09b8 267#define AFE_CONN38_1 0x09bc 268#define AFE_CONN39 0x09c0 269#define AFE_CONN40 0x09c4 270#define AFE_CONN41 0x09c8 271#define AFE_CONN42 0x09cc 272#define AFE_CONN39_1 0x09e0 273#define AFE_CONN40_1 0x09e4 274#define AFE_CONN41_1 0x09e8 275#define AFE_CONN42_1 0x09ec 276#define AFE_I2S_CON4 0x09f8 277#define AFE_ADDA6_TOP_CON0 0x0a80 278#define AFE_ADDA6_UL_SRC_CON0 0x0a84 279#define AFE_ADD6_UL_SRC_CON1 0x0a88 280#define AFE_ADDA6_SRC_DEBUG 0x0a8c 281#define AFE_ADDA6_SRC_DEBUG_MON0 0x0a90 282#define AFE_ADDA6_ULCF_CFG_02_01 0x0aa0 283#define AFE_ADDA6_ULCF_CFG_04_03 0x0aa4 284#define AFE_ADDA6_ULCF_CFG_06_05 0x0aa8 285#define AFE_ADDA6_ULCF_CFG_08_07 0x0aac 286#define AFE_ADDA6_ULCF_CFG_10_09 0x0ab0 287#define AFE_ADDA6_ULCF_CFG_12_11 0x0ab4 288#define AFE_ADDA6_ULCF_CFG_14_13 0x0ab8 289#define AFE_ADDA6_ULCF_CFG_16_15 0x0abc 290#define AFE_ADDA6_ULCF_CFG_18_17 0x0ac0 291#define AFE_ADDA6_ULCF_CFG_20_19 0x0ac4 292#define AFE_ADDA6_ULCF_CFG_22_21 0x0ac8 293#define AFE_ADDA6_ULCF_CFG_24_23 0x0acc 294#define AFE_ADDA6_ULCF_CFG_26_25 0x0ad0 295#define AFE_ADDA6_ULCF_CFG_28_27 0x0ad4 296#define AFE_ADDA6_ULCF_CFG_30_29 0x0ad8 297#define AFE_ADD6A_UL_SRC_MON0 0x0ae4 298#define AFE_ADDA6_UL_SRC_MON1 0x0ae8 299#define AFE_CONN43 0x0af8 300#define AFE_CONN43_1 0x0afc 301#define AFE_DL1_BASE_MSB 0x0b00 302#define AFE_DL1_CUR_MSB 0x0b04 303#define AFE_DL1_END_MSB 0x0b08 304#define AFE_DL2_BASE_MSB 0x0b10 305#define AFE_DL2_CUR_MSB 0x0b14 306#define AFE_DL2_END_MSB 0x0b18 307#define AFE_AWB_BASE_MSB 0x0b20 308#define AFE_AWB_END_MSB 0x0b28 309#define AFE_AWB_CUR_MSB 0x0b2c 310#define AFE_VUL_BASE_MSB 0x0b30 311#define AFE_VUL_END_MSB 0x0b38 312#define AFE_VUL_CUR_MSB 0x0b3c 313#define AFE_VUL2_BASE_MSB 0x0b50 314#define AFE_VUL2_END_MSB 0x0b58 315#define AFE_VUL2_CUR_MSB 0x0b5c 316#define AFE_MOD_DAI_BASE_MSB 0x0b60 317#define AFE_MOD_DAI_END_MSB 0x0b68 318#define AFE_MOD_DAI_CUR_MSB 0x0b6c 319#define AFE_VUL_D2_BASE_MSB 0x0b80 320#define AFE_VUL_D2_END_MSB 0x0b88 321#define AFE_VUL_D2_CUR_MSB 0x0b8c 322#define AFE_DL3_BASE_MSB 0x0b90 323#define AFE_DL3_CUR_MSB 0x0b94 324#define AFE_DL3_END_MSB 0x0b98 325#define AFE_HDMI_OUT_BASE_MSB 0x0ba4 326#define AFE_HDMI_OUT_CUR_MSB 0x0ba8 327#define AFE_HDMI_OUT_END_MSB 0x0bac 328#define AFE_AWB2_BASE 0x0bd0 329#define AFE_AWB2_END 0x0bd8 330#define AFE_AWB2_CUR 0x0bdc 331#define AFE_AWB2_BASE_MSB 0x0be0 332#define AFE_AWB2_END_MSB 0x0be8 333#define AFE_AWB2_CUR_MSB 0x0bec 334#define AFE_ADDA_DL_SDM_DCCOMP_CON 0x0c50 335#define AFE_ADDA_DL_SDM_TEST 0x0c54 336#define AFE_ADDA_DL_DC_COMP_CFG0 0x0c58 337#define AFE_ADDA_DL_DC_COMP_CFG1 0x0c5c 338#define AFE_ADDA_DL_SDM_FIFO_MON 0x0c60 339#define AFE_ADDA_DL_SRC_LCH_MON 0x0c64 340#define AFE_ADDA_DL_SRC_RCH_MON 0x0c68 341#define AFE_ADDA_DL_SDM_OUT_MON 0x0c6c 342#define AFE_CONNSYS_I2S_CON 0x0c78 343#define AFE_CONNSYS_I2S_MON 0x0c7c 344#define AFE_ASRC_2CH_CON0 0x0c80 345#define AFE_ASRC_2CH_CON1 0x0c84 346#define AFE_ASRC_2CH_CON2 0x0c88 347#define AFE_ASRC_2CH_CON3 0x0c8c 348#define AFE_ASRC_2CH_CON4 0x0c90 349#define AFE_ASRC_2CH_CON5 0x0c94 350#define AFE_ASRC_2CH_CON6 0x0c98 351#define AFE_ASRC_2CH_CON7 0x0c9c 352#define AFE_ASRC_2CH_CON8 0x0ca0 353#define AFE_ASRC_2CH_CON9 0x0ca4 354#define AFE_ASRC_2CH_CON10 0x0ca8 355#define AFE_ADDA6_IIR_COEF_02_01 0x0ce0 356#define AFE_ADDA6_IIR_COEF_04_03 0x0ce4 357#define AFE_ADDA6_IIR_COEF_06_05 0x0ce8 358#define AFE_ADDA6_IIR_COEF_08_07 0x0cec 359#define AFE_ADDA6_IIR_COEF_10_09 0x0cf0 360#define AFE_ADDA_PREDIS_CON2 0x0d40 361#define AFE_ADDA_PREDIS_CON3 0x0d44 362#define AFE_MEMIF_MON12 0x0d70 363#define AFE_MEMIF_MON13 0x0d74 364#define AFE_MEMIF_MON14 0x0d78 365#define AFE_MEMIF_MON15 0x0d7c 366#define AFE_MEMIF_MON16 0x0d80 367#define AFE_MEMIF_MON17 0x0d84 368#define AFE_MEMIF_MON18 0x0d88 369#define AFE_MEMIF_MON19 0x0d8c 370#define AFE_MEMIF_MON20 0x0d90 371#define AFE_MEMIF_MON21 0x0d94 372#define AFE_MEMIF_MON22 0x0d98 373#define AFE_MEMIF_MON23 0x0d9c 374#define AFE_MEMIF_MON24 0x0da0 375#define AFE_HD_ENGEN_ENABLE 0x0dd0 376#define AFE_ADDA_MTKAIF_CFG0 0x0e00 377#define AFE_ADDA_MTKAIF_TX_CFG1 0x0e14 378#define AFE_ADDA_MTKAIF_RX_CFG0 0x0e20 379#define AFE_ADDA_MTKAIF_RX_CFG1 0x0e24 380#define AFE_ADDA_MTKAIF_RX_CFG2 0x0e28 381#define AFE_ADDA_MTKAIF_MON0 0x0e34 382#define AFE_ADDA_MTKAIF_MON1 0x0e38 383#define AFE_AUD_PAD_TOP 0x0e40 384#define AFE_GENERAL1_ASRC_2CH_CON0 0x0e80 385#define AFE_GENERAL1_ASRC_2CH_CON1 0x0e84 386#define AFE_GENERAL1_ASRC_2CH_CON2 0x0e88 387#define AFE_GENERAL1_ASRC_2CH_CON3 0x0e8c 388#define AFE_GENERAL1_ASRC_2CH_CON4 0x0e90 389#define AFE_GENERAL1_ASRC_2CH_CON5 0x0e94 390#define AFE_GENERAL1_ASRC_2CH_CON6 0x0e98 391#define AFE_GENERAL1_ASRC_2CH_CON7 0x0e9c 392#define AFE_GENERAL1_ASRC_2CH_CON8 0x0ea0 393#define AFE_GENERAL1_ASRC_2CH_CON9 0x0ea4 394#define AFE_GENERAL1_ASRC_2CH_CON10 0x0ea8 395#define AFE_GENERAL1_ASRC_2CH_CON12 0x0eb0 396#define AFE_GENERAL1_ASRC_2CH_CON13 0x0eb4 397#define GENERAL_ASRC_MODE 0x0eb8 398#define GENERAL_ASRC_EN_ON 0x0ebc 399#define AFE_GENERAL2_ASRC_2CH_CON0 0x0f00 400#define AFE_GENERAL2_ASRC_2CH_CON1 0x0f04 401#define AFE_GENERAL2_ASRC_2CH_CON2 0x0f08 402#define AFE_GENERAL2_ASRC_2CH_CON3 0x0f0c 403#define AFE_GENERAL2_ASRC_2CH_CON4 0x0f10 404#define AFE_GENERAL2_ASRC_2CH_CON5 0x0f14 405#define AFE_GENERAL2_ASRC_2CH_CON6 0x0f18 406#define AFE_GENERAL2_ASRC_2CH_CON7 0x0f1c 407#define AFE_GENERAL2_ASRC_2CH_CON8 0x0f20 408#define AFE_GENERAL2_ASRC_2CH_CON9 0x0f24 409#define AFE_GENERAL2_ASRC_2CH_CON10 0x0f28 410#define AFE_GENERAL2_ASRC_2CH_CON12 0x0f30 411#define AFE_GENERAL2_ASRC_2CH_CON13 0x0f34 412 413#define AFE_MAX_REGISTER AFE_GENERAL2_ASRC_2CH_CON13 414#define AFE_IRQ_STATUS_BITS 0x1fff 415 416/* AUDIO_TOP_CON3 */ 417#define BCK_INVERSE_SFT 3 418#define BCK_INVERSE_MASK 0x1 419#define BCK_INVERSE_MASK_SFT (0x1 << 3) 420 421/* AFE_DAC_CON0 */ 422#define AWB2_ON_SFT 29 423#define AWB2_ON_MASK 0x1 424#define AWB2_ON_MASK_SFT (0x1 << 29) 425#define VUL2_ON_SFT 27 426#define VUL2_ON_MASK 0x1 427#define VUL2_ON_MASK_SFT (0x1 << 27) 428#define MOD_DAI_DUP_WR_SFT 26 429#define MOD_DAI_DUP_WR_MASK 0x1 430#define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26) 431#define VUL12_MODE_SFT 20 432#define VUL12_MODE_MASK 0xf 433#define VUL12_MODE_MASK_SFT (0xf << 20) 434#define VUL12_R_MONO_SFT 11 435#define VUL12_R_MONO_MASK 0x1 436#define VUL12_R_MONO_MASK_SFT (0x1 << 11) 437#define VUL12_MONO_SFT 10 438#define VUL12_MONO_MASK 0x1 439#define VUL12_MONO_MASK_SFT (0x1 << 10) 440#define VUL12_ON_SFT 9 441#define VUL12_ON_MASK 0x1 442#define VUL12_ON_MASK_SFT (0x1 << 9) 443#define MOD_DAI_ON_SFT 7 444#define MOD_DAI_ON_MASK 0x1 445#define MOD_DAI_ON_MASK_SFT (0x1 << 7) 446#define AWB_ON_SFT 6 447#define AWB_ON_MASK 0x1 448#define AWB_ON_MASK_SFT (0x1 << 6) 449#define DL3_ON_SFT 5 450#define DL3_ON_MASK 0x1 451#define DL3_ON_MASK_SFT (0x1 << 5) 452#define VUL_ON_SFT 3 453#define VUL_ON_MASK 0x1 454#define VUL_ON_MASK_SFT (0x1 << 3) 455#define DL2_ON_SFT 2 456#define DL2_ON_MASK 0x1 457#define DL2_ON_MASK_SFT (0x1 << 2) 458#define DL1_ON_SFT 1 459#define DL1_ON_MASK 0x1 460#define DL1_ON_MASK_SFT (0x1 << 1) 461#define AFE_ON_SFT 0 462#define AFE_ON_MASK 0x1 463#define AFE_ON_MASK_SFT (0x1 << 0) 464 465/* AFE_DAC_CON1 */ 466#define MOD_DAI_MODE_SFT 30 467#define MOD_DAI_MODE_MASK 0x3 468#define MOD_DAI_MODE_MASK_SFT (0x3 << 30) 469#define VUL_R_MONO_SFT 28 470#define VUL_R_MONO_MASK 0x1 471#define VUL_R_MONO_MASK_SFT (0x1 << 28) 472#define VUL_DATA_SFT 27 473#define VUL_DATA_MASK 0x1 474#define VUL_DATA_MASK_SFT (0x1 << 27) 475#define AWB_R_MONO_SFT 25 476#define AWB_R_MONO_MASK 0x1 477#define AWB_R_MONO_MASK_SFT (0x1 << 25) 478#define AWB_DATA_SFT 24 479#define AWB_DATA_MASK 0x1 480#define AWB_DATA_MASK_SFT (0x1 << 24) 481#define DL3_DATA_SFT 23 482#define DL3_DATA_MASK 0x1 483#define DL3_DATA_MASK_SFT (0x1 << 23) 484#define DL2_DATA_SFT 22 485#define DL2_DATA_MASK 0x1 486#define DL2_DATA_MASK_SFT (0x1 << 22) 487#define DL1_DATA_SFT 21 488#define DL1_DATA_MASK 0x1 489#define DL1_DATA_MASK_SFT (0x1 << 21) 490#define VUL_MODE_SFT 16 491#define VUL_MODE_MASK 0xf 492#define VUL_MODE_MASK_SFT (0xf << 16) 493#define AWB_MODE_SFT 12 494#define AWB_MODE_MASK 0xf 495#define AWB_MODE_MASK_SFT (0xf << 12) 496#define I2S_MODE_SFT 8 497#define I2S_MODE_MASK 0xf 498#define I2S_MODE_MASK_SFT (0xf << 8) 499#define DL2_MODE_SFT 4 500#define DL2_MODE_MASK 0xf 501#define DL2_MODE_MASK_SFT (0xf << 4) 502#define DL1_MODE_SFT 0 503#define DL1_MODE_MASK 0xf 504#define DL1_MODE_MASK_SFT (0xf << 0) 505 506/* AFE_DAC_CON2 */ 507#define AWB2_R_MONO_SFT 21 508#define AWB2_R_MONO_MASK 0x1 509#define AWB2_R_MONO_MASK_SFT (0x1 << 21) 510#define AWB2_DATA_SFT 20 511#define AWB2_DATA_MASK 0x1 512#define AWB2_DATA_MASK_SFT (0x1 << 20) 513#define AWB2_MODE_SFT 16 514#define AWB2_MODE_MASK 0xf 515#define AWB2_MODE_MASK_SFT (0xf << 16) 516#define DL3_MODE_SFT 8 517#define DL3_MODE_MASK 0xf 518#define DL3_MODE_MASK_SFT (0xf << 8) 519#define VUL2_MODE_SFT 4 520#define VUL2_MODE_MASK 0xf 521#define VUL2_MODE_MASK_SFT (0xf << 4) 522#define VUL2_R_MONO_SFT 1 523#define VUL2_R_MONO_MASK 0x1 524#define VUL2_R_MONO_MASK_SFT (0x1 << 1) 525#define VUL2_DATA_SFT 0 526#define VUL2_DATA_MASK 0x1 527#define VUL2_DATA_MASK_SFT (0x1 << 0) 528 529/* AFE_DAC_MON */ 530#define AFE_ON_RETM_SFT 0 531#define AFE_ON_RETM_MASK 0x1 532#define AFE_ON_RETM_MASK_SFT (0x1 << 0) 533 534/* AFE_I2S_CON */ 535#define BCK_NEG_EG_LATCH_SFT 30 536#define BCK_NEG_EG_LATCH_MASK 0x1 537#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30) 538#define BCK_INV_SFT 29 539#define BCK_INV_MASK 0x1 540#define BCK_INV_MASK_SFT (0x1 << 29) 541#define I2SIN_PAD_SEL_SFT 28 542#define I2SIN_PAD_SEL_MASK 0x1 543#define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28) 544#define I2S_LOOPBACK_SFT 20 545#define I2S_LOOPBACK_MASK 0x1 546#define I2S_LOOPBACK_MASK_SFT (0x1 << 20) 547#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17 548#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1 549#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17) 550#define I2S1_HD_EN_SFT 12 551#define I2S1_HD_EN_MASK 0x1 552#define I2S1_HD_EN_MASK_SFT (0x1 << 12) 553#define INV_PAD_CTRL_SFT 7 554#define INV_PAD_CTRL_MASK 0x1 555#define INV_PAD_CTRL_MASK_SFT (0x1 << 7) 556#define I2S_BYPSRC_SFT 6 557#define I2S_BYPSRC_MASK 0x1 558#define I2S_BYPSRC_MASK_SFT (0x1 << 6) 559#define INV_LRCK_SFT 5 560#define INV_LRCK_MASK 0x1 561#define INV_LRCK_MASK_SFT (0x1 << 5) 562#define I2S_FMT_SFT 3 563#define I2S_FMT_MASK 0x1 564#define I2S_FMT_MASK_SFT (0x1 << 3) 565#define I2S_SRC_SFT 2 566#define I2S_SRC_MASK 0x1 567#define I2S_SRC_MASK_SFT (0x1 << 2) 568#define I2S_WLEN_SFT 1 569#define I2S_WLEN_MASK 0x1 570#define I2S_WLEN_MASK_SFT (0x1 << 1) 571#define I2S_EN_SFT 0 572#define I2S_EN_MASK 0x1 573#define I2S_EN_MASK_SFT (0x1 << 0) 574 575/* AFE_I2S_CON1 */ 576#define I2S2_LR_SWAP_SFT 31 577#define I2S2_LR_SWAP_MASK 0x1 578#define I2S2_LR_SWAP_MASK_SFT (0x1 << 31) 579#define I2S2_SEL_O19_O20_SFT 18 580#define I2S2_SEL_O19_O20_MASK 0x1 581#define I2S2_SEL_O19_O20_MASK_SFT (0x1 << 18) 582#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17 583#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1 584#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17) 585#define I2S2_SEL_O03_O04_SFT 16 586#define I2S2_SEL_O03_O04_MASK 0x1 587#define I2S2_SEL_O03_O04_MASK_SFT (0x1 << 16) 588#define I2S2_32BIT_EN_SFT 13 589#define I2S2_32BIT_EN_MASK 0x1 590#define I2S2_32BIT_EN_MASK_SFT (0x1 << 13) 591#define I2S2_HD_EN_SFT 12 592#define I2S2_HD_EN_MASK 0x1 593#define I2S2_HD_EN_MASK_SFT (0x1 << 12) 594#define I2S2_OUT_MODE_SFT 8 595#define I2S2_OUT_MODE_MASK 0xf 596#define I2S2_OUT_MODE_MASK_SFT (0xf << 8) 597#define INV_LRCK_SFT 5 598#define INV_LRCK_MASK 0x1 599#define INV_LRCK_MASK_SFT (0x1 << 5) 600#define I2S2_FMT_SFT 3 601#define I2S2_FMT_MASK 0x1 602#define I2S2_FMT_MASK_SFT (0x1 << 3) 603#define I2S2_WLEN_SFT 1 604#define I2S2_WLEN_MASK 0x1 605#define I2S2_WLEN_MASK_SFT (0x1 << 1) 606#define I2S2_EN_SFT 0 607#define I2S2_EN_MASK 0x1 608#define I2S2_EN_MASK_SFT (0x1 << 0) 609 610/* AFE_I2S_CON2 */ 611#define I2S3_LR_SWAP_SFT 31 612#define I2S3_LR_SWAP_MASK 0x1 613#define I2S3_LR_SWAP_MASK_SFT (0x1 << 31) 614#define I2S3_UPDATE_WORD_SFT 24 615#define I2S3_UPDATE_WORD_MASK 0x1f 616#define I2S3_UPDATE_WORD_MASK_SFT (0x1f << 24) 617#define I2S3_BCK_INV_SFT 23 618#define I2S3_BCK_INV_MASK 0x1 619#define I2S3_BCK_INV_MASK_SFT (0x1 << 23) 620#define I2S3_FPGA_BIT_TEST_SFT 22 621#define I2S3_FPGA_BIT_TEST_MASK 0x1 622#define I2S3_FPGA_BIT_TEST_MASK_SFT (0x1 << 22) 623#define I2S3_FPGA_BIT_SFT 21 624#define I2S3_FPGA_BIT_MASK 0x1 625#define I2S3_FPGA_BIT_MASK_SFT (0x1 << 21) 626#define I2S3_LOOPBACK_SFT 20 627#define I2S3_LOOPBACK_MASK 0x1 628#define I2S3_LOOPBACK_MASK_SFT (0x1 << 20) 629#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17 630#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1 631#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17) 632#define I2S3_HD_EN_SFT 12 633#define I2S3_HD_EN_MASK 0x1 634#define I2S3_HD_EN_MASK_SFT (0x1 << 12) 635#define I2S3_OUT_MODE_SFT 8 636#define I2S3_OUT_MODE_MASK 0xf 637#define I2S3_OUT_MODE_MASK_SFT (0xf << 8) 638#define I2S3_FMT_SFT 3 639#define I2S3_FMT_MASK 0x1 640#define I2S3_FMT_MASK_SFT (0x1 << 3) 641#define I2S3_WLEN_SFT 1 642#define I2S3_WLEN_MASK 0x1 643#define I2S3_WLEN_MASK_SFT (0x1 << 1) 644#define I2S3_EN_SFT 0 645#define I2S3_EN_MASK 0x1 646#define I2S3_EN_MASK_SFT (0x1 << 0) 647 648/* AFE_I2S_CON3 */ 649#define I2S4_LR_SWAP_SFT 31 650#define I2S4_LR_SWAP_MASK 0x1 651#define I2S4_LR_SWAP_MASK_SFT (0x1 << 31) 652#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17 653#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1 654#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17) 655#define I2S4_32BIT_EN_SFT 13 656#define I2S4_32BIT_EN_MASK 0x1 657#define I2S4_32BIT_EN_MASK_SFT (0x1 << 13) 658#define I2S4_HD_EN_SFT 12 659#define I2S4_HD_EN_MASK 0x1 660#define I2S4_HD_EN_MASK_SFT (0x1 << 12) 661#define I2S4_OUT_MODE_SFT 8 662#define I2S4_OUT_MODE_MASK 0xf 663#define I2S4_OUT_MODE_MASK_SFT (0xf << 8) 664#define INV_LRCK_SFT 5 665#define INV_LRCK_MASK 0x1 666#define INV_LRCK_MASK_SFT (0x1 << 5) 667#define I2S4_FMT_SFT 3 668#define I2S4_FMT_MASK 0x1 669#define I2S4_FMT_MASK_SFT (0x1 << 3) 670#define I2S4_WLEN_SFT 1 671#define I2S4_WLEN_MASK 0x1 672#define I2S4_WLEN_MASK_SFT (0x1 << 1) 673#define I2S4_EN_SFT 0 674#define I2S4_EN_MASK 0x1 675#define I2S4_EN_MASK_SFT (0x1 << 0) 676 677/* AFE_I2S_CON4 */ 678#define I2S5_LR_SWAP_SFT 31 679#define I2S5_LR_SWAP_MASK 0x1 680#define I2S5_LR_SWAP_MASK_SFT (0x1 << 31) 681#define I2S_LOOPBACK_SFT 20 682#define I2S_LOOPBACK_MASK 0x1 683#define I2S_LOOPBACK_MASK_SFT (0x1 << 20) 684#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17 685#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1 686#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17) 687#define I2S5_32BIT_EN_SFT 13 688#define I2S5_32BIT_EN_MASK 0x1 689#define I2S5_32BIT_EN_MASK_SFT (0x1 << 13) 690#define I2S5_HD_EN_SFT 12 691#define I2S5_HD_EN_MASK 0x1 692#define I2S5_HD_EN_MASK_SFT (0x1 << 12) 693#define I2S5_OUT_MODE_SFT 8 694#define I2S5_OUT_MODE_MASK 0xf 695#define I2S5_OUT_MODE_MASK_SFT (0xf << 8) 696#define INV_LRCK_SFT 5 697#define INV_LRCK_MASK 0x1 698#define INV_LRCK_MASK_SFT (0x1 << 5) 699#define I2S5_FMT_SFT 3 700#define I2S5_FMT_MASK 0x1 701#define I2S5_FMT_MASK_SFT (0x1 << 3) 702#define I2S5_WLEN_SFT 1 703#define I2S5_WLEN_MASK 0x1 704#define I2S5_WLEN_MASK_SFT (0x1 << 1) 705#define I2S5_EN_SFT 0 706#define I2S5_EN_MASK 0x1 707#define I2S5_EN_MASK_SFT (0x1 << 0) 708 709/* AFE_GAIN1_CON0 */ 710#define GAIN1_SAMPLE_PER_STEP_SFT 8 711#define GAIN1_SAMPLE_PER_STEP_MASK 0xff 712#define GAIN1_SAMPLE_PER_STEP_MASK_SFT (0xff << 8) 713#define GAIN1_MODE_SFT 4 714#define GAIN1_MODE_MASK 0xf 715#define GAIN1_MODE_MASK_SFT (0xf << 4) 716#define GAIN1_ON_SFT 0 717#define GAIN1_ON_MASK 0x1 718#define GAIN1_ON_MASK_SFT (0x1 << 0) 719 720/* AFE_GAIN1_CON1 */ 721#define GAIN1_TARGET_SFT 0 722#define GAIN1_TARGET_MASK 0xfffff 723#define GAIN1_TARGET_MASK_SFT (0xfffff << 0) 724 725/* AFE_GAIN2_CON0 */ 726#define GAIN2_SAMPLE_PER_STEP_SFT 8 727#define GAIN2_SAMPLE_PER_STEP_MASK 0xff 728#define GAIN2_SAMPLE_PER_STEP_MASK_SFT (0xff << 8) 729#define GAIN2_MODE_SFT 4 730#define GAIN2_MODE_MASK 0xf 731#define GAIN2_MODE_MASK_SFT (0xf << 4) 732#define GAIN2_ON_SFT 0 733#define GAIN2_ON_MASK 0x1 734#define GAIN2_ON_MASK_SFT (0x1 << 0) 735 736/* AFE_GAIN2_CON1 */ 737#define GAIN2_TARGET_SFT 0 738#define GAIN2_TARGET_MASK 0xfffff 739#define GAIN2_TARGET_MASK_SFT (0xfffff << 0) 740 741/* AFE_GAIN1_CUR */ 742#define AFE_GAIN1_CUR_SFT 0 743#define AFE_GAIN1_CUR_MASK 0xfffff 744#define AFE_GAIN1_CUR_MASK_SFT (0xfffff << 0) 745 746/* AFE_GAIN2_CUR */ 747#define AFE_GAIN2_CUR_SFT 0 748#define AFE_GAIN2_CUR_MASK 0xfffff 749#define AFE_GAIN2_CUR_MASK_SFT (0xfffff << 0) 750 751/* AFE_MEMIF_HD_MODE */ 752#define AWB2_HD_SFT 28 753#define AWB2_HD_MASK 0x3 754#define AWB2_HD_MASK_SFT (0x3 << 28) 755#define HDMI_HD_SFT 20 756#define HDMI_HD_MASK 0x3 757#define HDMI_HD_MASK_SFT (0x3 << 20) 758#define MOD_DAI_HD_SFT 18 759#define MOD_DAI_HD_MASK 0x3 760#define MOD_DAI_HD_MASK_SFT (0x3 << 18) 761#define DAI_HD_SFT 16 762#define DAI_HD_MASK 0x3 763#define DAI_HD_MASK_SFT (0x3 << 16) 764#define VUL2_HD_SFT 14 765#define VUL2_HD_MASK 0x3 766#define VUL2_HD_MASK_SFT (0x3 << 14) 767#define VUL12_HD_SFT 12 768#define VUL12_HD_MASK 0x3 769#define VUL12_HD_MASK_SFT (0x3 << 12) 770#define VUL_HD_SFT 10 771#define VUL_HD_MASK 0x3 772#define VUL_HD_MASK_SFT (0x3 << 10) 773#define AWB_HD_SFT 8 774#define AWB_HD_MASK 0x3 775#define AWB_HD_MASK_SFT (0x3 << 8) 776#define DL3_HD_SFT 6 777#define DL3_HD_MASK 0x3 778#define DL3_HD_MASK_SFT (0x3 << 6) 779#define DL2_HD_SFT 4 780#define DL2_HD_MASK 0x3 781#define DL2_HD_MASK_SFT (0x3 << 4) 782#define DL1_HD_SFT 0 783#define DL1_HD_MASK 0x3 784#define DL1_HD_MASK_SFT (0x3 << 0) 785 786/* AFE_MEMIF_HDALIGN */ 787#define AWB2_NORMAL_MODE_SFT 30 788#define AWB2_NORMAL_MODE_MASK 0x1 789#define AWB2_NORMAL_MODE_MASK_SFT (0x1 << 30) 790#define HDMI_NORMAL_MODE_SFT 26 791#define HDMI_NORMAL_MODE_MASK 0x1 792#define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26) 793#define MOD_DAI_NORMAL_MODE_SFT 25 794#define MOD_DAI_NORMAL_MODE_MASK 0x1 795#define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25) 796#define DAI_NORMAL_MODE_SFT 24 797#define DAI_NORMAL_MODE_MASK 0x1 798#define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24) 799#define VUL2_NORMAL_MODE_SFT 23 800#define VUL2_NORMAL_MODE_MASK 0x1 801#define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 23) 802#define VUL12_NORMAL_MODE_SFT 22 803#define VUL12_NORMAL_MODE_MASK 0x1 804#define VUL12_NORMAL_MODE_MASK_SFT (0x1 << 22) 805#define VUL_NORMAL_MODE_SFT 21 806#define VUL_NORMAL_MODE_MASK 0x1 807#define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21) 808#define AWB_NORMAL_MODE_SFT 20 809#define AWB_NORMAL_MODE_MASK 0x1 810#define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20) 811#define DL3_NORMAL_MODE_SFT 19 812#define DL3_NORMAL_MODE_MASK 0x1 813#define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19) 814#define DL2_NORMAL_MODE_SFT 18 815#define DL2_NORMAL_MODE_MASK 0x1 816#define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18) 817#define DL1_NORMAL_MODE_SFT 16 818#define DL1_NORMAL_MODE_MASK 0x1 819#define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16) 820#define RESERVED1_SFT 15 821#define RESERVED1_MASK 0x1 822#define RESERVED1_MASK_SFT (0x1 << 15) 823#define AWB2_ALIGN_SFT 14 824#define AWB2_ALIGN_MASK 0x1 825#define AWB2_ALIGN_MASK_SFT (0x1 << 14) 826#define HDMI_HD_ALIGN_SFT 10 827#define HDMI_HD_ALIGN_MASK 0x1 828#define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10) 829#define MOD_DAI_HD_ALIGN_SFT 9 830#define MOD_DAI_HD_ALIGN_MASK 0x1 831#define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9) 832#define VUL2_HD_ALIGN_SFT 7 833#define VUL2_HD_ALIGN_MASK 0x1 834#define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7) 835#define VUL12_HD_ALIGN_SFT 6 836#define VUL12_HD_ALIGN_MASK 0x1 837#define VUL12_HD_ALIGN_MASK_SFT (0x1 << 6) 838#define VUL_HD_ALIGN_SFT 5 839#define VUL_HD_ALIGN_MASK 0x1 840#define VUL_HD_ALIGN_MASK_SFT (0x1 << 5) 841#define AWB_HD_ALIGN_SFT 4 842#define AWB_HD_ALIGN_MASK 0x1 843#define AWB_HD_ALIGN_MASK_SFT (0x1 << 4) 844#define DL3_HD_ALIGN_SFT 3 845#define DL3_HD_ALIGN_MASK 0x1 846#define DL3_HD_ALIGN_MASK_SFT (0x1 << 3) 847#define DL2_HD_ALIGN_SFT 2 848#define DL2_HD_ALIGN_MASK 0x1 849#define DL2_HD_ALIGN_MASK_SFT (0x1 << 2) 850#define DL1_HD_ALIGN_SFT 0 851#define DL1_HD_ALIGN_MASK 0x1 852#define DL1_HD_ALIGN_MASK_SFT (0x1 << 0) 853 854/* PCM_INTF_CON1 */ 855#define PCM_FIX_VALUE_SEL_SFT 31 856#define PCM_FIX_VALUE_SEL_MASK 0x1 857#define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31) 858#define PCM_BUFFER_LOOPBACK_SFT 30 859#define PCM_BUFFER_LOOPBACK_MASK 0x1 860#define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30) 861#define PCM_PARALLEL_LOOPBACK_SFT 29 862#define PCM_PARALLEL_LOOPBACK_MASK 0x1 863#define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29) 864#define PCM_SERIAL_LOOPBACK_SFT 28 865#define PCM_SERIAL_LOOPBACK_MASK 0x1 866#define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28) 867#define PCM_DAI_PCM_LOOPBACK_SFT 27 868#define PCM_DAI_PCM_LOOPBACK_MASK 0x1 869#define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27) 870#define PCM_I2S_PCM_LOOPBACK_SFT 26 871#define PCM_I2S_PCM_LOOPBACK_MASK 0x1 872#define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26) 873#define PCM_SYNC_DELSEL_SFT 25 874#define PCM_SYNC_DELSEL_MASK 0x1 875#define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25) 876#define PCM_TX_LR_SWAP_SFT 24 877#define PCM_TX_LR_SWAP_MASK 0x1 878#define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24) 879#define PCM_SYNC_OUT_INV_SFT 23 880#define PCM_SYNC_OUT_INV_MASK 0x1 881#define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23) 882#define PCM_BCLK_OUT_INV_SFT 22 883#define PCM_BCLK_OUT_INV_MASK 0x1 884#define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22) 885#define PCM_SYNC_IN_INV_SFT 21 886#define PCM_SYNC_IN_INV_MASK 0x1 887#define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21) 888#define PCM_BCLK_IN_INV_SFT 20 889#define PCM_BCLK_IN_INV_MASK 0x1 890#define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20) 891#define PCM_TX_LCH_RPT_SFT 19 892#define PCM_TX_LCH_RPT_MASK 0x1 893#define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19) 894#define PCM_VBT_16K_MODE_SFT 18 895#define PCM_VBT_16K_MODE_MASK 0x1 896#define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18) 897#define PCM_EXT_MODEM_SFT 17 898#define PCM_EXT_MODEM_MASK 0x1 899#define PCM_EXT_MODEM_MASK_SFT (0x1 << 17) 900#define PCM_24BIT_SFT 16 901#define PCM_24BIT_MASK 0x1 902#define PCM_24BIT_MASK_SFT (0x1 << 16) 903#define PCM_WLEN_SFT 14 904#define PCM_WLEN_MASK 0x3 905#define PCM_WLEN_MASK_SFT (0x3 << 14) 906#define PCM_SYNC_LENGTH_SFT 9 907#define PCM_SYNC_LENGTH_MASK 0x1f 908#define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9) 909#define PCM_SYNC_TYPE_SFT 8 910#define PCM_SYNC_TYPE_MASK 0x1 911#define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8) 912#define PCM_BT_MODE_SFT 7 913#define PCM_BT_MODE_MASK 0x1 914#define PCM_BT_MODE_MASK_SFT (0x1 << 7) 915#define PCM_BYP_ASRC_SFT 6 916#define PCM_BYP_ASRC_MASK 0x1 917#define PCM_BYP_ASRC_MASK_SFT (0x1 << 6) 918#define PCM_SLAVE_SFT 5 919#define PCM_SLAVE_MASK 0x1 920#define PCM_SLAVE_MASK_SFT (0x1 << 5) 921#define PCM_MODE_SFT 3 922#define PCM_MODE_MASK 0x3 923#define PCM_MODE_MASK_SFT (0x3 << 3) 924#define PCM_FMT_SFT 1 925#define PCM_FMT_MASK 0x3 926#define PCM_FMT_MASK_SFT (0x3 << 1) 927#define PCM_EN_SFT 0 928#define PCM_EN_MASK 0x1 929#define PCM_EN_MASK_SFT (0x1 << 0) 930 931/* PCM_INTF_CON2 */ 932#define PCM1_TX_FIFO_OV_SFT 31 933#define PCM1_TX_FIFO_OV_MASK 0x1 934#define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31) 935#define PCM1_RX_FIFO_OV_SFT 30 936#define PCM1_RX_FIFO_OV_MASK 0x1 937#define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30) 938#define PCM2_TX_FIFO_OV_SFT 29 939#define PCM2_TX_FIFO_OV_MASK 0x1 940#define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29) 941#define PCM2_RX_FIFO_OV_SFT 28 942#define PCM2_RX_FIFO_OV_MASK 0x1 943#define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28) 944#define PCM1_SYNC_GLITCH_SFT 27 945#define PCM1_SYNC_GLITCH_MASK 0x1 946#define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27) 947#define PCM2_SYNC_GLITCH_SFT 26 948#define PCM2_SYNC_GLITCH_MASK 0x1 949#define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26) 950#define TX3_RCH_DBG_MODE_SFT 17 951#define TX3_RCH_DBG_MODE_MASK 0x1 952#define TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17) 953#define PCM1_PCM2_LOOPBACK_SFT 16 954#define PCM1_PCM2_LOOPBACK_MASK 0x1 955#define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 16) 956#define DAI_PCM_LOOPBACK_CH_SFT 14 957#define DAI_PCM_LOOPBACK_CH_MASK 0x3 958#define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 14) 959#define I2S_PCM_LOOPBACK_CH_SFT 12 960#define I2S_PCM_LOOPBACK_CH_MASK 0x3 961#define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 12) 962#define TX_FIX_VALUE_SFT 0 963#define TX_FIX_VALUE_MASK 0xff 964#define TX_FIX_VALUE_MASK_SFT (0xff << 0) 965 966/* PCM2_INTF_CON */ 967#define PCM2_TX_FIX_VALUE_SFT 24 968#define PCM2_TX_FIX_VALUE_MASK 0xff 969#define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24) 970#define PCM2_FIX_VALUE_SEL_SFT 23 971#define PCM2_FIX_VALUE_SEL_MASK 0x1 972#define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23) 973#define PCM2_BUFFER_LOOPBACK_SFT 22 974#define PCM2_BUFFER_LOOPBACK_MASK 0x1 975#define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22) 976#define PCM2_PARALLEL_LOOPBACK_SFT 21 977#define PCM2_PARALLEL_LOOPBACK_MASK 0x1 978#define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21) 979#define PCM2_SERIAL_LOOPBACK_SFT 20 980#define PCM2_SERIAL_LOOPBACK_MASK 0x1 981#define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20) 982#define PCM2_DAI_PCM_LOOPBACK_SFT 19 983#define PCM2_DAI_PCM_LOOPBACK_MASK 0x1 984#define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19) 985#define PCM2_I2S_PCM_LOOPBACK_SFT 18 986#define PCM2_I2S_PCM_LOOPBACK_MASK 0x1 987#define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18) 988#define PCM2_SYNC_DELSEL_SFT 17 989#define PCM2_SYNC_DELSEL_MASK 0x1 990#define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17) 991#define PCM2_TX_LR_SWAP_SFT 16 992#define PCM2_TX_LR_SWAP_MASK 0x1 993#define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16) 994#define PCM2_SYNC_IN_INV_SFT 15 995#define PCM2_SYNC_IN_INV_MASK 0x1 996#define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15) 997#define PCM2_BCLK_IN_INV_SFT 14 998#define PCM2_BCLK_IN_INV_MASK 0x1 999#define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14) 1000#define PCM2_TX_LCH_RPT_SFT 13
1001#define PCM2_TX_LCH_RPT_MASK 0x1 1002#define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13) 1003#define PCM2_VBT_16K_MODE_SFT 12 1004#define PCM2_VBT_16K_MODE_MASK 0x1 1005#define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12) 1006#define PCM2_LOOPBACK_CH_SEL_SFT 10 1007#define PCM2_LOOPBACK_CH_SEL_MASK 0x3 1008#define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10) 1009#define PCM2_TX2_BT_MODE_SFT 8 1010#define PCM2_TX2_BT_MODE_MASK 0x1 1011#define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8) 1012#define PCM2_BT_MODE_SFT 7 1013#define PCM2_BT_MODE_MASK 0x1 1014#define PCM2_BT_MODE_MASK_SFT (0x1 << 7) 1015#define PCM2_AFIFO_SFT 6 1016#define PCM2_AFIFO_MASK 0x1 1017#define PCM2_AFIFO_MASK_SFT (0x1 << 6) 1018#define PCM2_WLEN_SFT 5 1019#define PCM2_WLEN_MASK 0x1 1020#define PCM2_WLEN_MASK_SFT (0x1 << 5) 1021#define PCM2_MODE_SFT 3 1022#define PCM2_MODE_MASK 0x3 1023#define PCM2_MODE_MASK_SFT (0x3 << 3) 1024#define PCM2_FMT_SFT 1 1025#define PCM2_FMT_MASK 0x3 1026#define PCM2_FMT_MASK_SFT (0x3 << 1) 1027#define PCM2_EN_SFT 0 1028#define PCM2_EN_MASK 0x1 1029#define PCM2_EN_MASK_SFT (0x1 << 0) 1030 1031/* AFE_ADDA_MTKAIF_CFG0 */ 1032#define MTKAIF_RXIF_CLKINV_ADC_SFT 31 1033#define MTKAIF_RXIF_CLKINV_ADC_MASK 0x1 1034#define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31) 1035#define MTKAIF_RXIF_BYPASS_SRC_SFT 17 1036#define MTKAIF_RXIF_BYPASS_SRC_MASK 0x1 1037#define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17) 1038#define MTKAIF_RXIF_PROTOCOL2_SFT 16 1039#define MTKAIF_RXIF_PROTOCOL2_MASK 0x1 1040#define MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16) 1041#define MTKAIF_TXIF_BYPASS_SRC_SFT 5 1042#define MTKAIF_TXIF_BYPASS_SRC_MASK 0x1 1043#define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5) 1044#define MTKAIF_TXIF_PROTOCOL2_SFT 4 1045#define MTKAIF_TXIF_PROTOCOL2_MASK 0x1 1046#define MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4) 1047#define MTKAIF_TXIF_8TO5_SFT 2 1048#define MTKAIF_TXIF_8TO5_MASK 0x1 1049#define MTKAIF_TXIF_8TO5_MASK_SFT (0x1 << 2) 1050#define MTKAIF_RXIF_8TO5_SFT 1 1051#define MTKAIF_RXIF_8TO5_MASK 0x1 1052#define MTKAIF_RXIF_8TO5_MASK_SFT (0x1 << 1) 1053#define MTKAIF_IF_LOOPBACK1_SFT 0 1054#define MTKAIF_IF_LOOPBACK1_MASK 0x1 1055#define MTKAIF_IF_LOOPBACK1_MASK_SFT (0x1 << 0) 1056 1057/* AFE_ADDA_MTKAIF_RX_CFG2 */ 1058#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 16 1059#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1 1060#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 16) 1061#define MTKAIF_RXIF_DELAY_CYCLE_SFT 12 1062#define MTKAIF_RXIF_DELAY_CYCLE_MASK 0xf 1063#define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12) 1064#define MTKAIF_RXIF_DELAY_DATA_SFT 8 1065#define MTKAIF_RXIF_DELAY_DATA_MASK 0x1 1066#define MTKAIF_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8) 1067#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4 1068#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7 1069#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4) 1070 1071/* AFE_ADDA_DL_SRC2_CON0 */ 1072#define DL_2_INPUT_MODE_CTL_SFT 28 1073#define DL_2_INPUT_MODE_CTL_MASK 0xf 1074#define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28) 1075#define DL_2_CH1_SATURATION_EN_CTL_SFT 27 1076#define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1 1077#define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27) 1078#define DL_2_CH2_SATURATION_EN_CTL_SFT 26 1079#define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1 1080#define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26) 1081#define DL_2_OUTPUT_SEL_CTL_SFT 24 1082#define DL_2_OUTPUT_SEL_CTL_MASK 0x3 1083#define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24) 1084#define DL_2_FADEIN_0START_EN_SFT 16 1085#define DL_2_FADEIN_0START_EN_MASK 0x3 1086#define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16) 1087#define DL_DISABLE_HW_CG_CTL_SFT 15 1088#define DL_DISABLE_HW_CG_CTL_MASK 0x1 1089#define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15) 1090#define C_DATA_EN_SEL_CTL_PRE_SFT 14 1091#define C_DATA_EN_SEL_CTL_PRE_MASK 0x1 1092#define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14) 1093#define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13 1094#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1 1095#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13) 1096#define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12 1097#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1 1098#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12) 1099#define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11 1100#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1 1101#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11) 1102#define DL2_ARAMPSP_CTL_PRE_SFT 9 1103#define DL2_ARAMPSP_CTL_PRE_MASK 0x3 1104#define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9) 1105#define DL_2_IIRMODE_CTL_PRE_SFT 6 1106#define DL_2_IIRMODE_CTL_PRE_MASK 0x7 1107#define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6) 1108#define DL_2_VOICE_MODE_CTL_PRE_SFT 5 1109#define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1 1110#define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5) 1111#define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4 1112#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1 1113#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4) 1114#define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3 1115#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1 1116#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3) 1117#define DL_2_IIR_ON_CTL_PRE_SFT 2 1118#define DL_2_IIR_ON_CTL_PRE_MASK 0x1 1119#define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2) 1120#define DL_2_GAIN_ON_CTL_PRE_SFT 1 1121#define DL_2_GAIN_ON_CTL_PRE_MASK 0x1 1122#define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1) 1123#define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0 1124#define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1 1125#define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0) 1126 1127/* AFE_ADDA_DL_SRC2_CON1 */ 1128#define DL_2_GAIN_CTL_PRE_SFT 16 1129#define DL_2_GAIN_CTL_PRE_MASK 0xffff 1130#define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16) 1131#define DL_2_GAIN_MODE_CTL_SFT 0 1132#define DL_2_GAIN_MODE_CTL_MASK 0x1 1133#define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0) 1134 1135/* AFE_ADDA_UL_SRC_CON0 */ 1136#define ULCF_CFG_EN_CTL_SFT 31 1137#define ULCF_CFG_EN_CTL_MASK 0x1 1138#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31) 1139#define UL_MODE_3P25M_CH2_CTL_SFT 22 1140#define UL_MODE_3P25M_CH2_CTL_MASK 0x1 1141#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22) 1142#define UL_MODE_3P25M_CH1_CTL_SFT 21 1143#define UL_MODE_3P25M_CH1_CTL_MASK 0x1 1144#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21) 1145#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17 1146#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7 1147#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17) 1148#define DMIC_LOW_POWER_MODE_CTL_SFT 14 1149#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3 1150#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14) 1151#define UL_DISABLE_HW_CG_CTL_SFT 12 1152#define UL_DISABLE_HW_CG_CTL_MASK 0x1 1153#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12) 1154#define UL_IIR_ON_TMP_CTL_SFT 10 1155#define UL_IIR_ON_TMP_CTL_MASK 0x1 1156#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10) 1157#define UL_IIRMODE_CTL_SFT 7 1158#define UL_IIRMODE_CTL_MASK 0x7 1159#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7) 1160#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 1161#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 1162#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) 1163#define UL_LOOP_BACK_MODE_CTL_SFT 2 1164#define UL_LOOP_BACK_MODE_CTL_MASK 0x1 1165#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) 1166#define UL_SDM_3_LEVEL_CTL_SFT 1 1167#define UL_SDM_3_LEVEL_CTL_MASK 0x1 1168#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) 1169#define UL_SRC_ON_TMP_CTL_SFT 0 1170#define UL_SRC_ON_TMP_CTL_MASK 0x1 1171#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) 1172 1173/* AFE_ADDA_UL_SRC_CON1 */ 1174#define C_DAC_EN_CTL_SFT 27 1175#define C_DAC_EN_CTL_MASK 0x1 1176#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27) 1177#define C_MUTE_SW_CTL_SFT 26 1178#define C_MUTE_SW_CTL_MASK 0x1 1179#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26) 1180#define ASDM_SRC_SEL_CTL_SFT 25 1181#define ASDM_SRC_SEL_CTL_MASK 0x1 1182#define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25) 1183#define C_AMP_DIV_CH2_CTL_SFT 21 1184#define C_AMP_DIV_CH2_CTL_MASK 0x7 1185#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21) 1186#define C_FREQ_DIV_CH2_CTL_SFT 16 1187#define C_FREQ_DIV_CH2_CTL_MASK 0x1f 1188#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16) 1189#define C_SINE_MODE_CH2_CTL_SFT 12 1190#define C_SINE_MODE_CH2_CTL_MASK 0xf 1191#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12) 1192#define C_AMP_DIV_CH1_CTL_SFT 9 1193#define C_AMP_DIV_CH1_CTL_MASK 0x7 1194#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9) 1195#define C_FREQ_DIV_CH1_CTL_SFT 4 1196#define C_FREQ_DIV_CH1_CTL_MASK 0x1f 1197#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4) 1198#define C_SINE_MODE_CH1_CTL_SFT 0 1199#define C_SINE_MODE_CH1_CTL_MASK 0xf 1200#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0) 1201 1202/* AFE_ADDA_TOP_CON0 */ 1203#define C_LOOP_BACK_MODE_CTL_SFT 12 1204#define C_LOOP_BACK_MODE_CTL_MASK 0xf 1205#define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12) 1206#define C_EXT_ADC_CTL_SFT 0 1207#define C_EXT_ADC_CTL_MASK 0x1 1208#define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0) 1209 1210/* AFE_ADDA_UL_DL_CON0 */ 1211#define AFE_ADDA6_UL_LR_SWAP_SFT 15 1212#define AFE_ADDA6_UL_LR_SWAP_MASK 0x1 1213#define AFE_ADDA6_UL_LR_SWAP_MASK_SFT (0x1 << 15) 1214#define AFE_ADDA6_CKDIV_RST_SFT 14 1215#define AFE_ADDA6_CKDIV_RST_MASK 0x1 1216#define AFE_ADDA6_CKDIV_RST_MASK_SFT (0x1 << 14) 1217#define AFE_ADDA6_FIFO_AUTO_RST_SFT 13 1218#define AFE_ADDA6_FIFO_AUTO_RST_MASK 0x1 1219#define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT (0x1 << 13) 1220#define UL_FIFO_DIGMIC_TESTIN_SFT 5 1221#define UL_FIFO_DIGMIC_TESTIN_MASK 0x3 1222#define UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 5) 1223#define UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 4 1224#define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1 1225#define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 4) 1226#define ADDA_AFE_ON_SFT 0 1227#define ADDA_AFE_ON_MASK 0x1 1228#define ADDA_AFE_ON_MASK_SFT (0x1 << 0) 1229 1230/* AFE_SIDETONE_CON0 */ 1231#define R_RDY_SFT 30 1232#define R_RDY_MASK 0x1 1233#define R_RDY_MASK_SFT (0x1 << 30) 1234#define W_RDY_SFT 29 1235#define W_RDY_MASK 0x1 1236#define W_RDY_MASK_SFT (0x1 << 29) 1237#define R_W_EN_SFT 25 1238#define R_W_EN_MASK 0x1 1239#define R_W_EN_MASK_SFT (0x1 << 25) 1240#define R_W_SEL_SFT 24 1241#define R_W_SEL_MASK 0x1 1242#define R_W_SEL_MASK_SFT (0x1 << 24) 1243#define SEL_CH2_SFT 23 1244#define SEL_CH2_MASK 0x1 1245#define SEL_CH2_MASK_SFT (0x1 << 23) 1246#define SIDE_TONE_COEFFICIENT_ADDR_SFT 16 1247#define SIDE_TONE_COEFFICIENT_ADDR_MASK 0x1f 1248#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT (0x1f << 16) 1249#define SIDE_TONE_COEFFICIENT_SFT 0 1250#define SIDE_TONE_COEFFICIENT_MASK 0xffff 1251#define SIDE_TONE_COEFFICIENT_MASK_SFT (0xffff << 0) 1252 1253/* AFE_SIDETONE_COEFF */ 1254#define SIDE_TONE_COEFF_SFT 0 1255#define SIDE_TONE_COEFF_MASK 0xffff 1256#define SIDE_TONE_COEFF_MASK_SFT (0xffff << 0) 1257 1258/* AFE_SIDETONE_CON1 */ 1259#define STF_BYPASS_MODE_SFT 31 1260#define STF_BYPASS_MODE_MASK 0x1 1261#define STF_BYPASS_MODE_MASK_SFT (0x1 << 31) 1262#define STF_BYPASS_MODE_O28_O29_SFT 30 1263#define STF_BYPASS_MODE_O28_O29_MASK 0x1 1264#define STF_BYPASS_MODE_O28_O29_MASK_SFT (0x1 << 30) 1265#define STF_BYPASS_MODE_I2S4_SFT 29 1266#define STF_BYPASS_MODE_I2S4_MASK 0x1 1267#define STF_BYPASS_MODE_I2S4_MASK_SFT (0x1 << 29) 1268#define STF_BYPASS_MODE_I2S5_SFT 28 1269#define STF_BYPASS_MODE_I2S5_MASK 0x1 1270#define STF_BYPASS_MODE_I2S5_MASK_SFT (0x1 << 28) 1271#define STF_INPUT_EN_SEL_SFT 13 1272#define STF_INPUT_EN_SEL_MASK 0x1 1273#define STF_INPUT_EN_SEL_MASK_SFT (0x1 << 13) 1274#define STF_SOURCE_FROM_O19O20_SFT 12 1275#define STF_SOURCE_FROM_O19O20_MASK 0x1 1276#define STF_SOURCE_FROM_O19O20_MASK_SFT (0x1 << 12) 1277#define SIDE_TONE_ON_SFT 8 1278#define SIDE_TONE_ON_MASK 0x1 1279#define SIDE_TONE_ON_MASK_SFT (0x1 << 8) 1280#define SIDE_TONE_HALF_TAP_NUM_SFT 0 1281#define SIDE_TONE_HALF_TAP_NUM_MASK 0x3f 1282#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT (0x3f << 0) 1283 1284/* AFE_SIDETONE_GAIN */ 1285#define POSITIVE_GAIN_SFT 16 1286#define POSITIVE_GAIN_MASK 0x7 1287#define POSITIVE_GAIN_MASK_SFT (0x7 << 16) 1288#define SIDE_TONE_GAIN_SFT 0 1289#define SIDE_TONE_GAIN_MASK 0xffff 1290#define SIDE_TONE_GAIN_MASK_SFT (0xffff << 0) 1291 1292/* AFE_ADDA_DL_SDM_DCCOMP_CON */ 1293#define AUD_DC_COMP_EN_SFT 8 1294#define AUD_DC_COMP_EN_MASK 0x1 1295#define AUD_DC_COMP_EN_MASK_SFT (0x1 << 8) 1296#define ATTGAIN_CTL_SFT 0 1297#define ATTGAIN_CTL_MASK 0x3f 1298#define ATTGAIN_CTL_MASK_SFT (0x3f << 0) 1299 1300/* AFE_SINEGEN_CON0 */ 1301#define DAC_EN_SFT 26 1302#define DAC_EN_MASK 0x1 1303#define DAC_EN_MASK_SFT (0x1 << 26) 1304#define MUTE_SW_CH2_SFT 25 1305#define MUTE_SW_CH2_MASK 0x1 1306#define MUTE_SW_CH2_MASK_SFT (0x1 << 25) 1307#define MUTE_SW_CH1_SFT 24 1308#define MUTE_SW_CH1_MASK 0x1 1309#define MUTE_SW_CH1_MASK_SFT (0x1 << 24) 1310#define SINE_MODE_CH2_SFT 20 1311#define SINE_MODE_CH2_MASK 0xf 1312#define SINE_MODE_CH2_MASK_SFT (0xf << 20) 1313#define AMP_DIV_CH2_SFT 17 1314#define AMP_DIV_CH2_MASK 0x7 1315#define AMP_DIV_CH2_MASK_SFT (0x7 << 17) 1316#define FREQ_DIV_CH2_SFT 12 1317#define FREQ_DIV_CH2_MASK 0x1f 1318#define FREQ_DIV_CH2_MASK_SFT (0x1f << 12) 1319#define SINE_MODE_CH1_SFT 8 1320#define SINE_MODE_CH1_MASK 0xf 1321#define SINE_MODE_CH1_MASK_SFT (0xf << 8) 1322#define AMP_DIV_CH1_SFT 5 1323#define AMP_DIV_CH1_MASK 0x7 1324#define AMP_DIV_CH1_MASK_SFT (0x7 << 5) 1325#define FREQ_DIV_CH1_SFT 0 1326#define FREQ_DIV_CH1_MASK 0x1f 1327#define FREQ_DIV_CH1_MASK_SFT (0x1f << 0) 1328 1329/* AFE_SINEGEN_CON2 */ 1330#define INNER_LOOP_BACK_MODE_SFT 0 1331#define INNER_LOOP_BACK_MODE_MASK 0x3f 1332#define INNER_LOOP_BACK_MODE_MASK_SFT (0x3f << 0) 1333 1334/* AFE_MEMIF_MINLEN */ 1335#define HDMI_MINLEN_SFT 24 1336#define HDMI_MINLEN_MASK 0xf 1337#define HDMI_MINLEN_MASK_SFT (0xf << 24) 1338#define DL3_MINLEN_SFT 12 1339#define DL3_MINLEN_MASK 0xf 1340#define DL3_MINLEN_MASK_SFT (0xf << 12) 1341#define DL2_MINLEN_SFT 8 1342#define DL2_MINLEN_MASK 0xf 1343#define DL2_MINLEN_MASK_SFT (0xf << 8) 1344#define DL1_DATA2_MINLEN_SFT 4 1345#define DL1_DATA2_MINLEN_MASK 0xf 1346#define DL1_DATA2_MINLEN_MASK_SFT (0xf << 4) 1347#define DL1_MINLEN_SFT 0 1348#define DL1_MINLEN_MASK 0xf 1349#define DL1_MINLEN_MASK_SFT (0xf << 0) 1350 1351/* AFE_MEMIF_MAXLEN */ 1352#define HDMI_MAXLEN_SFT 24 1353#define HDMI_MAXLEN_MASK 0xf 1354#define HDMI_MAXLEN_MASK_SFT (0xf << 24) 1355#define DL3_MAXLEN_SFT 8 1356#define DL3_MAXLEN_MASK 0xf 1357#define DL3_MAXLEN_MASK_SFT (0xf << 8) 1358#define DL2_MAXLEN_SFT 4 1359#define DL2_MAXLEN_MASK 0xf 1360#define DL2_MAXLEN_MASK_SFT (0xf << 4) 1361#define DL1_MAXLEN_SFT 0 1362#define DL1_MAXLEN_MASK 0x3 1363#define DL1_MAXLEN_MASK_SFT (0x3 << 0) 1364 1365/* AFE_MEMIF_PBUF_SIZE */ 1366#define VUL12_4CH_SFT 17 1367#define VUL12_4CH_MASK 0x1 1368#define VUL12_4CH_MASK_SFT (0x1 << 17) 1369#define DL3_PBUF_SIZE_SFT 10 1370#define DL3_PBUF_SIZE_MASK 0x3 1371#define DL3_PBUF_SIZE_MASK_SFT (0x3 << 10) 1372#define HDMI_PBUF_SIZE_SFT 4 1373#define HDMI_PBUF_SIZE_MASK 0x3 1374#define HDMI_PBUF_SIZE_MASK_SFT (0x3 << 4) 1375#define DL2_PBUF_SIZE_SFT 2 1376#define DL2_PBUF_SIZE_MASK 0x3 1377#define DL2_PBUF_SIZE_MASK_SFT (0x3 << 2) 1378#define DL1_PBUF_SIZE_SFT 0 1379#define DL1_PBUF_SIZE_MASK 0x3 1380#define DL1_PBUF_SIZE_MASK_SFT (0x3 << 0) 1381 1382/* AFE_HD_ENGEN_ENABLE */ 1383#define AFE_24M_ON_SFT 1 1384#define AFE_24M_ON_MASK 0x1 1385#define AFE_24M_ON_MASK_SFT (0x1 << 1) 1386#define AFE_22M_ON_SFT 0 1387#define AFE_22M_ON_MASK 0x1 1388#define AFE_22M_ON_MASK_SFT (0x1 << 0) 1389 1390/* AFE_IRQ_MCU_CON0 */ 1391#define IRQ12_MCU_ON_SFT 12 1392#define IRQ12_MCU_ON_MASK 0x1 1393#define IRQ12_MCU_ON_MASK_SFT (0x1 << 12) 1394#define IRQ11_MCU_ON_SFT 11 1395#define IRQ11_MCU_ON_MASK 0x1 1396#define IRQ11_MCU_ON_MASK_SFT (0x1 << 11) 1397#define IRQ10_MCU_ON_SFT 10 1398#define IRQ10_MCU_ON_MASK 0x1 1399#define IRQ10_MCU_ON_MASK_SFT (0x1 << 10) 1400#define IRQ9_MCU_ON_SFT 9 1401#define IRQ9_MCU_ON_MASK 0x1 1402#define IRQ9_MCU_ON_MASK_SFT (0x1 << 9) 1403#define IRQ8_MCU_ON_SFT 8 1404#define IRQ8_MCU_ON_MASK 0x1 1405#define IRQ8_MCU_ON_MASK_SFT (0x1 << 8) 1406#define IRQ7_MCU_ON_SFT 7 1407#define IRQ7_MCU_ON_MASK 0x1 1408#define IRQ7_MCU_ON_MASK_SFT (0x1 << 7) 1409#define IRQ6_MCU_ON_SFT 6 1410#define IRQ6_MCU_ON_MASK 0x1 1411#define IRQ6_MCU_ON_MASK_SFT (0x1 << 6) 1412#define IRQ5_MCU_ON_SFT 5 1413#define IRQ5_MCU_ON_MASK 0x1 1414#define IRQ5_MCU_ON_MASK_SFT (0x1 << 5) 1415#define IRQ4_MCU_ON_SFT 4 1416#define IRQ4_MCU_ON_MASK 0x1 1417#define IRQ4_MCU_ON_MASK_SFT (0x1 << 4) 1418#define IRQ3_MCU_ON_SFT 3 1419#define IRQ3_MCU_ON_MASK 0x1 1420#define IRQ3_MCU_ON_MASK_SFT (0x1 << 3) 1421#define IRQ2_MCU_ON_SFT 2 1422#define IRQ2_MCU_ON_MASK 0x1 1423#define IRQ2_MCU_ON_MASK_SFT (0x1 << 2) 1424#define IRQ1_MCU_ON_SFT 1 1425#define IRQ1_MCU_ON_MASK 0x1 1426#define IRQ1_MCU_ON_MASK_SFT (0x1 << 1) 1427#define IRQ0_MCU_ON_SFT 0 1428#define IRQ0_MCU_ON_MASK 0x1 1429#define IRQ0_MCU_ON_MASK_SFT (0x1 << 0) 1430 1431/* AFE_IRQ_MCU_CON1 */ 1432#define IRQ7_MCU_MODE_SFT 28 1433#define IRQ7_MCU_MODE_MASK 0xf 1434#define IRQ7_MCU_MODE_MASK_SFT (0xf << 28) 1435#define IRQ6_MCU_MODE_SFT 24 1436#define IRQ6_MCU_MODE_MASK 0xf 1437#define IRQ6_MCU_MODE_MASK_SFT (0xf << 24) 1438#define IRQ5_MCU_MODE_SFT 20 1439#define IRQ5_MCU_MODE_MASK 0xf 1440#define IRQ5_MCU_MODE_MASK_SFT (0xf << 20) 1441#define IRQ4_MCU_MODE_SFT 16 1442#define IRQ4_MCU_MODE_MASK 0xf 1443#define IRQ4_MCU_MODE_MASK_SFT (0xf << 16) 1444#define IRQ3_MCU_MODE_SFT 12 1445#define IRQ3_MCU_MODE_MASK 0xf 1446#define IRQ3_MCU_MODE_MASK_SFT (0xf << 12) 1447#define IRQ2_MCU_MODE_SFT 8 1448#define IRQ2_MCU_MODE_MASK 0xf 1449#define IRQ2_MCU_MODE_MASK_SFT (0xf << 8) 1450#define IRQ1_MCU_MODE_SFT 4 1451#define IRQ1_MCU_MODE_MASK 0xf 1452#define IRQ1_MCU_MODE_MASK_SFT (0xf << 4) 1453#define IRQ0_MCU_MODE_SFT 0 1454#define IRQ0_MCU_MODE_MASK 0xf 1455#define IRQ0_MCU_MODE_MASK_SFT (0xf << 0) 1456 1457/* AFE_IRQ_MCU_CON2 */ 1458#define IRQ12_MCU_MODE_SFT 4 1459#define IRQ12_MCU_MODE_MASK 0xf 1460#define IRQ12_MCU_MODE_MASK_SFT (0xf << 4) 1461#define IRQ11_MCU_MODE_SFT 0 1462#define IRQ11_MCU_MODE_MASK 0xf 1463#define IRQ11_MCU_MODE_MASK_SFT (0xf << 0) 1464 1465/* AFE_IRQ_MCU_CLR */ 1466#define IRQ12_MCU_MISS_CNT_CLR_SFT 28 1467#define IRQ12_MCU_MISS_CNT_CLR_MASK 0x1 1468#define IRQ12_MCU_MISS_CNT_CLR_MASK_SFT (0x1 << 28) 1469#define IRQ11_MCU_MISS_CNT_CLR_SFT 27 1470#define IRQ11_MCU_MISS_CNT_CLR_MASK 0x1 1471#define IRQ11_MCU_MISS_CNT_CLR_MASK_SFT (0x1 << 27) 1472#define IRQ10_MCU_MISS_CLR_SFT 26 1473#define IRQ10_MCU_MISS_CLR_MASK 0x1 1474#define IRQ10_MCU_MISS_CLR_MASK_SFT (0x1 << 26) 1475#define IRQ9_MCU_MISS_CLR_SFT 25 1476#define IRQ9_MCU_MISS_CLR_MASK 0x1 1477#define IRQ9_MCU_MISS_CLR_MASK_SFT (0x1 << 25) 1478#define IRQ8_MCU_MISS_CLR_SFT 24 1479#define IRQ8_MCU_MISS_CLR_MASK 0x1 1480#define IRQ8_MCU_MISS_CLR_MASK_SFT (0x1 << 24) 1481#define IRQ7_MCU_MISS_CLR_SFT 23 1482#define IRQ7_MCU_MISS_CLR_MASK 0x1 1483#define IRQ7_MCU_MISS_CLR_MASK_SFT (0x1 << 23) 1484#define IRQ6_MCU_MISS_CLR_SFT 22 1485#define IRQ6_MCU_MISS_CLR_MASK 0x1 1486#define IRQ6_MCU_MISS_CLR_MASK_SFT (0x1 << 22) 1487#define IRQ5_MCU_MISS_CLR_SFT 21 1488#define IRQ5_MCU_MISS_CLR_MASK 0x1 1489#define IRQ5_MCU_MISS_CLR_MASK_SFT (0x1 << 21) 1490#define IRQ4_MCU_MISS_CLR_SFT 20 1491#define IRQ4_MCU_MISS_CLR_MASK 0x1 1492#define IRQ4_MCU_MISS_CLR_MASK_SFT (0x1 << 20) 1493#define IRQ3_MCU_MISS_CLR_SFT 19 1494#define IRQ3_MCU_MISS_CLR_MASK 0x1 1495#define IRQ3_MCU_MISS_CLR_MASK_SFT (0x1 << 19) 1496#define IRQ2_MCU_MISS_CLR_SFT 18 1497#define IRQ2_MCU_MISS_CLR_MASK 0x1 1498#define IRQ2_MCU_MISS_CLR_MASK_SFT (0x1 << 18) 1499#define IRQ1_MCU_MISS_CLR_SFT 17 1500#define IRQ1_MCU_MISS_CLR_MASK 0x1 1501#define IRQ1_MCU_MISS_CLR_MASK_SFT (0x1 << 17) 1502#define IRQ0_MCU_MISS_CLR_SFT 16 1503#define IRQ0_MCU_MISS_CLR_MASK 0x1 1504#define IRQ0_MCU_MISS_CLR_MASK_SFT (0x1 << 16) 1505#define IRQ12_MCU_CLR_SFT 12 1506#define IRQ12_MCU_CLR_MASK 0x1 1507#define IRQ12_MCU_CLR_MASK_SFT (0x1 << 12) 1508#define IRQ11_MCU_CLR_SFT 11 1509#define IRQ11_MCU_CLR_MASK 0x1 1510#define IRQ11_MCU_CLR_MASK_SFT (0x1 << 11) 1511#define IRQ10_MCU_CLR_SFT 10 1512#define IRQ10_MCU_CLR_MASK 0x1 1513#define IRQ10_MCU_CLR_MASK_SFT (0x1 << 10) 1514#define IRQ9_MCU_CLR_SFT 9 1515#define IRQ9_MCU_CLR_MASK 0x1 1516#define IRQ9_MCU_CLR_MASK_SFT (0x1 << 9) 1517#define IRQ8_MCU_CLR_SFT 8 1518#define IRQ8_MCU_CLR_MASK 0x1 1519#define IRQ8_MCU_CLR_MASK_SFT (0x1 << 8) 1520#define IRQ7_MCU_CLR_SFT 7 1521#define IRQ7_MCU_CLR_MASK 0x1 1522#define IRQ7_MCU_CLR_MASK_SFT (0x1 << 7) 1523#define IRQ6_MCU_CLR_SFT 6 1524#define IRQ6_MCU_CLR_MASK 0x1 1525#define IRQ6_MCU_CLR_MASK_SFT (0x1 << 6) 1526#define IRQ5_MCU_CLR_SFT 5 1527#define IRQ5_MCU_CLR_MASK 0x1 1528#define IRQ5_MCU_CLR_MASK_SFT (0x1 << 5) 1529#define IRQ4_MCU_CLR_SFT 4 1530#define IRQ4_MCU_CLR_MASK 0x1 1531#define IRQ4_MCU_CLR_MASK_SFT (0x1 << 4) 1532#define IRQ3_MCU_CLR_SFT 3 1533#define IRQ3_MCU_CLR_MASK 0x1 1534#define IRQ3_MCU_CLR_MASK_SFT (0x1 << 3) 1535#define IRQ2_MCU_CLR_SFT 2 1536#define IRQ2_MCU_CLR_MASK 0x1 1537#define IRQ2_MCU_CLR_MASK_SFT (0x1 << 2) 1538#define IRQ1_MCU_CLR_SFT 1 1539#define IRQ1_MCU_CLR_MASK 0x1 1540#define IRQ1_MCU_CLR_MASK_SFT (0x1 << 1) 1541#define IRQ0_MCU_CLR_SFT 0 1542#define IRQ0_MCU_CLR_MASK 0x1 1543#define IRQ0_MCU_CLR_MASK_SFT (0x1 << 0) 1544 1545/* AFE_MEMIF_MSB */ 1546#define CPU_COMPACT_MODE_SFT 29 1547#define CPU_COMPACT_MODE_MASK 0x1 1548#define CPU_COMPACT_MODE_MASK_SFT (0x1 << 29) 1549#define CPU_HD_ALIGN_SFT 28 1550#define CPU_HD_ALIGN_MASK 0x1 1551#define CPU_HD_ALIGN_MASK_SFT (0x1 << 28) 1552#define AWB2_AXI_WR_SIGN_SFT 24 1553#define AWB2_AXI_WR_SIGN_MASK 0x1 1554#define AWB2_AXI_WR_SIGN_MASK_SFT (0x1 << 24) 1555#define VUL2_AXI_WR_SIGN_SFT 22 1556#define VUL2_AXI_WR_SIGN_MASK 0x1 1557#define VUL2_AXI_WR_SIGN_MASK_SFT (0x1 << 22) 1558#define VUL12_AXI_WR_SIGN_SFT 21 1559#define VUL12_AXI_WR_SIGN_MASK 0x1 1560#define VUL12_AXI_WR_SIGN_MASK_SFT (0x1 << 21) 1561#define VUL_AXI_WR_SIGN_SFT 20 1562#define VUL_AXI_WR_SIGN_MASK 0x1 1563#define VUL_AXI_WR_SIGN_MASK_SFT (0x1 << 20) 1564#define MOD_DAI_AXI_WR_SIGN_SFT 18 1565#define MOD_DAI_AXI_WR_SIGN_MASK 0x1 1566#define MOD_DAI_AXI_WR_SIGN_MASK_SFT (0x1 << 18) 1567#define AWB_MSTR_SIGN_SFT 17 1568#define AWB_MSTR_SIGN_MASK 0x1 1569#define AWB_MSTR_SIGN_MASK_SFT (0x1 << 17) 1570#define SYSRAM_SIGN_SFT 16 1571#define SYSRAM_SIGN_MASK 0x1 1572#define SYSRAM_SIGN_MASK_SFT (0x1 << 16) 1573 1574/* AFE_HDMI_CONN0 */ 1575#define HDMI_O_7_SFT 21 1576#define HDMI_O_7_MASK 0x7 1577#define HDMI_O_7_MASK_SFT (0x7 << 21) 1578#define HDMI_O_6_SFT 18 1579#define HDMI_O_6_MASK 0x7 1580#define HDMI_O_6_MASK_SFT (0x7 << 18) 1581#define HDMI_O_5_SFT 15 1582#define HDMI_O_5_MASK 0x7 1583#define HDMI_O_5_MASK_SFT (0x7 << 15) 1584#define HDMI_O_4_SFT 12 1585#define HDMI_O_4_MASK 0x7 1586#define HDMI_O_4_MASK_SFT (0x7 << 12) 1587#define HDMI_O_3_SFT 9 1588#define HDMI_O_3_MASK 0x7 1589#define HDMI_O_3_MASK_SFT (0x7 << 9) 1590#define HDMI_O_2_SFT 6 1591#define HDMI_O_2_MASK 0x7 1592#define HDMI_O_2_MASK_SFT (0x7 << 6) 1593#define HDMI_O_1_SFT 3 1594#define HDMI_O_1_MASK 0x7 1595#define HDMI_O_1_MASK_SFT (0x7 << 3) 1596#define HDMI_O_0_SFT 0 1597#define HDMI_O_0_MASK 0x7 1598#define HDMI_O_0_MASK_SFT (0x7 << 0) 1599 1600/* AFE_TDM_CON1 */ 1601#define TDM_EN_SFT 0 1602#define TDM_EN_MASK 0x1 1603#define TDM_EN_MASK_SFT (0x1 << 0) 1604#define LRCK_INVERSE_SFT 2 1605#define LRCK_INVERSE_MASK 0x1 1606#define LRCK_INVERSE_MASK_SFT (0x1 << 2) 1607#define DELAY_DATA_SFT 3 1608#define DELAY_DATA_MASK 0x1 1609#define DELAY_DATA_MASK_SFT (0x1 << 3) 1610#define LEFT_ALIGN_SFT 4 1611#define LEFT_ALIGN_MASK 0x1 1612#define LEFT_ALIGN_MASK_SFT (0x1 << 4) 1613#define WLEN_SFT 8 1614#define WLEN_MASK 0x3 1615#define WLEN_MASK_SFT (0x3 << 8) 1616#define CHANNEL_NUM_SFT 10 1617#define CHANNEL_NUM_MASK 0x3 1618#define CHANNEL_NUM_MASK_SFT (0x3 << 10) 1619#define CHANNEL_BCK_CYCLES_SFT 12 1620#define CHANNEL_BCK_CYCLES_MASK 0x3 1621#define CHANNEL_BCK_CYCLES_MASK_SFT (0x3 << 12) 1622#define DAC_BIT_NUM_SFT 16 1623#define DAC_BIT_NUM_MASK 0x1f 1624#define DAC_BIT_NUM_MASK_SFT (0x1f << 16) 1625#define LRCK_TDM_WIDTH_SFT 24 1626#define LRCK_TDM_WIDTH_MASK 0xff 1627#define LRCK_TDM_WIDTH_MASK_SFT (0xff << 24) 1628 1629/* AFE_TDM_CON2 */ 1630#define ST_CH_PAIR_SOUT0_SFT 0 1631#define ST_CH_PAIR_SOUT0_MASK 0x7 1632#define ST_CH_PAIR_SOUT0_MASK_SFT (0x7 << 0) 1633#define ST_CH_PAIR_SOUT1_SFT 4 1634#define ST_CH_PAIR_SOUT1_MASK 0x7 1635#define ST_CH_PAIR_SOUT1_MASK_SFT (0x7 << 4) 1636#define ST_CH_PAIR_SOUT2_SFT 8 1637#define ST_CH_PAIR_SOUT2_MASK 0x7 1638#define ST_CH_PAIR_SOUT2_MASK_SFT (0x7 << 8) 1639#define ST_CH_PAIR_SOUT3_SFT 12 1640#define ST_CH_PAIR_SOUT3_MASK 0x7 1641#define ST_CH_PAIR_SOUT3_MASK_SFT (0x7 << 12) 1642#define TDM_FIX_VALUE_SEL_SFT 16 1643#define TDM_FIX_VALUE_SEL_MASK 0x1 1644#define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16) 1645#define TDM_I2S_LOOPBACK_SFT 20 1646#define TDM_I2S_LOOPBACK_MASK 0x1 1647#define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20) 1648#define TDM_I2S_LOOPBACK_CH_SFT 21 1649#define TDM_I2S_LOOPBACK_CH_MASK 0x3 1650#define TDM_I2S_LOOPBACK_CH_MASK_SFT (0x3 << 21) 1651#define TDM_FIX_VALUE_SFT 24 1652#define TDM_FIX_VALUE_MASK 0xff 1653#define TDM_FIX_VALUE_MASK_SFT (0xff << 24) 1654 1655/* AFE_HDMI_OUT_CON0 */ 1656#define AFE_HDMI_OUT_ON_RETM_SFT 8 1657#define AFE_HDMI_OUT_ON_RETM_MASK 0x1 1658#define AFE_HDMI_OUT_ON_RETM_MASK_SFT (0x1 << 8) 1659#define AFE_HDMI_OUT_CH_NUM_SFT 4 1660#define AFE_HDMI_OUT_CH_NUM_MASK 0xf 1661#define AFE_HDMI_OUT_CH_NUM_MASK_SFT (0xf << 4) 1662#define AFE_HDMI_OUT_BIT_WIDTH_SFT 1 1663#define AFE_HDMI_OUT_BIT_WIDTH_MASK 0x1 1664#define AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT (0x1 << 1) 1665#define AFE_HDMI_OUT_ON_SFT 0 1666#define AFE_HDMI_OUT_ON_MASK 0x1 1667#define AFE_HDMI_OUT_ON_MASK_SFT (0x1 << 0) 1668#endif 1669